Timing trigger on single wire RFFE bus

Abstract

A receiving device, the receiving device comprising: a clock generator circuit configured to generate a base clock signal; a counter configured to count periods or edges of the base clock signal when a measurement pulse is received through the single wire serial bus during a first transaction performed through the single wire serial bus, the measurement pulse having a pulse duration defined by a number of clock periods of the transmitter clock signal; and a controller configured to adjust a count value of the counter using the correction value when the counter is timing the triggered actuation, the correction value represents a difference between a period or edge of the base clock signal counted while the measurement pulse is being received and a number of clock periods of the transmitter clock signal defining the pulse duration.

Description

Cross-reference to related applications

[0001] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 449,567, filed August 14, 2023, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0002] This disclosure relates generally to serial communication, and more specifically to the management of trigger timing in a receiver coupled to a communication bus that supports single-wire and two-wire peripheral devices. Background Technology

[0003] Mobile communication devices may include various components, including circuit boards, integrated circuit (IC) devices, and / or system-on-a-chip (SoC) devices. These components may include processing circuitry, user interface components, storage devices, and other peripheral components that communicate via a serial bus. The serial bus may operate according to standardized or proprietary protocols. In one example, according to inter-integrated circuit (I2C or I2C) protocols... 2 C) The I2C protocol is used to operate a two-wire multipoint serial bus, developed to connect low-speed peripheral devices to a processor. The I2C bus provides a Serial Data Line (SDA) carrying data signals and a Serial Clock Line (SCL) carrying clock signals. In another example, the Improved Internal Integrated Circuit (I3C) protocol, defined by the Mobile Industry Processor Interface (MIPI) consortium, derives certain implementation aspects from the I2C protocol, which includes separate clock and data lines. In yet another example, the RF Front-End (RFFE) interface, defined by the MIPI consortium, provides a communication interface for controlling various RF front-end devices, including power amplifiers (PAs), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, etc. These devices can be cascaded in a single IC device or provided in multiple IC devices. In mobile communication devices, multiple antennas and radio transceivers can support multiple concurrent RF links. In yet another example, the System Power Management Interface (SPMI), defined by the MIPI consortium, provides a hardware interface that can be implemented between the baseband or application processor and peripheral components for power management purposes within the device.

[0004] Replacing the parallel bus with a serial bus defined by MIPI reduces the number of physical general-purpose input / output (GPIO) pins required to support communication between multiple devices. However, as device complexity increases, the demand for GPIO pins also increases, and there is a need for a simpler bus architecture, including one that supports communication via a single GPIO pin as well as via a single wire. There is also a need for improved timing management techniques when clock signals are not transmitted via a dedicated line on the serial bus. Summary of the Invention

[0005] Certain aspects of this disclosure provide systems, apparatus, methods, and techniques related to managing timing for self-actuated triggering when single-wire and two-wire slave devices use a common data line of a serial bus. Certain aspects of this disclosure relate to using a locally generated clock signal to time the trigger actuation. Certain aspects of this disclosure relate to techniques for minimizing the effects of frequency mismatch between a receiving and transmitting device when single-wire and two-wire slave devices use a common data line of a serial bus.

[0006] In various aspects of this disclosure, a receiving device includes: a clock generator circuit configured to generate a basic clock signal; a counter configured to count a period or edge of the basic clock signal when a measurement pulse is received via the single-wire serial bus during a first transaction; and a controller configured to adjust the counter's count value using a correction value when the counter is timing a triggered actuation, the correction value representing the difference between the period or edge of the basic clock signal counted while the measurement pulse is being received and the number of clock cycles of a transmitter clock signal defining the pulse duration of the measurement pulse.

[0007] In various aspects of this disclosure, a method for timing a trigger in a receiving device includes: generating a basic clock signal; counting a period or edge of the basic clock signal using a counter of the receiving device while a measurement pulse is received via the single-wire serial bus during a first transaction; and adjusting the count value of the counter using a correction value while the counter is timing the actuation of the trigger, the correction value representing the difference between the period or edge of the basic clock signal counted while the measurement pulse is being received and the number of clock periods of a transmitter clock signal defining the pulse duration of the measurement pulse.

[0008] In various aspects of this disclosure, a system includes a host device coupled to a single-wire serial bus and a plurality of receiving devices coupled to the single-wire serial bus. Each of the plurality of receiving devices includes a clock generator circuit configured to generate a basic clock signal and a counter configured to count the period or edge of a corresponding basic clock signal. The host device is configured to: initiate a first transaction to be performed via the single-wire serial bus; send a broadcast command in the first transaction; send a measurement pulse in the first transaction after the broadcast command, the measurement pulse having a pulse duration defined by the number of clock periods of a transmitter clock signal used by the host device; and receive the measurement duration of the measurement pulse from each of the plurality of receiving devices. At least one receiving device is configured to measure the measurement pulse by using its counter to count the period or edge of its basic clock signal while the measurement pulse is being transmitted via the single-wire serial bus. At least one receiving device is further configured to adjust the count value of its counter using a correction value when the counter is timing a triggered actuation, the correction value representing the difference between the period or edge of the basic clock signal being counted while receiving the measurement pulse and the number of clock periods of the transmitter clock signal used by the host device.

[0009] In some respects, measurement pulses are received after the associated Manchester-encoded command is received via a single-wire serial bus. The Manchester-encoded command can be received in a datagram configured according to the Radio Frequency Front-End (RFFE) protocol. The transmitter clock signal is embedded in the Manchester-encoded command.

[0010] In one respect, the frequency of the basic clock signal is a multiple of the frequency of the transmitter clock signal.

[0011] In some respects, the controller in the receiving device is further configured to increment the counter value when the frequency of the basic clock signal is less than the frequency of the transmitter clock signal. The controller may be further configured to decrement the counter value when the frequency of the basic clock signal is greater than the frequency of the transmitter clock signal.

[0012] In some aspects, the receiving device includes a trigger shadow register configured by trigger information received in a second transaction via a single-wire serial bus. A counter can be configured with an initial count value using timing information received in the second transaction. The receiving device can be one of multiple receiving devices coupled to the single-wire serial bus. Each of the multiple receiving devices can be configured by trigger and timing information received in the second transaction. Each of the multiple receiving devices can be configured to initiate timing for the corresponding trigger actuation when the second transaction terminates.

[0013] In some respects, the controller in the receiving device is further configured to periodically adjust the counter's count value using a correction value when the counter is timing the triggered actuation. The controller in the receiving device can adjust the counter's count value periodically, determined by the frequency of the fundamental clock signal. Attached Figure Description

[0014] Figure 1 An example is illustrated of a device employing a data link between IC devices, which operates selectively according to one of a plurality of available standards.

[0015] Figure 2 A first example of an apparatus employing a data link that can be used to communicatively couple two or more devices is illustrated.

[0016] Figure 3 A second example of an apparatus is illustrated, which employs a data link that can be used to communicatively couple two or more devices, including various radio frequency front-end devices.

[0017] Figure 4 This includes timing diagrams illustrating the signaling sent to depict the boundaries of RFFE and SPMI datagrams.

[0018] Figure 5 An example is illustrated of a system in which a host device communicates with one or more single-line slave devices according to certain aspects disclosed herein.

[0019] Figure 6 Examples of single-wire serial interfaces that can be configured according to certain aspects of this disclosure are illustrated.

[0020] Figure 7 An example is illustrated of a system in which single-line slave devices and two-line slave devices coexist, according to certain aspects disclosed herein.

[0021] Figure 8 This illustrates certain characteristics of a single-line transaction according to certain aspects of this disclosure.

[0022] Figure 9 Examples of actuation triggered according to certain aspects disclosed herein are provided.

[0023] Figure 10 This illustrates the availability of timing information for slave devices coupled to a mixed-mode serial bus when both single-wire and two-wire slave devices are actively communicating via the mixed-mode serial bus.

[0024] Figure 11 This illustrates some aspects of timing in a slave device that is configured to use internal clock resources to manage self-actuated timing.

[0025] Figure 12This illustrates the relationship between the trigger window and the counted clock cycles when the internal basic clock signal is used for time-triggered actuation.

[0026] Figure 13 Examples of trigger timing circuits that can be configured according to certain aspects of this disclosure are illustrated.

[0027] Figure 14 An example is provided of a trigger slope correction factor for multiple slave devices according to certain aspects of this disclosure.

[0028] Figure 15 An application of the trigger slope correction factor calculated according to certain aspects of this disclosure is illustrated.

[0029] Figure 16 The communication of trigger configuration information according to certain aspects of this disclosure is illustrated.

[0030] Figure 17 An example of an apparatus employing processing circuitry adaptable to certain aspects disclosed herein is illustrated.

[0031] Figure 18 This is a flowchart illustrating a method for timing a trigger in a receiving device according to certain aspects disclosed herein.

[0032] Figure 19 Examples of specific hardware implementations of devices adapted to certain aspects disclosed herein are illustrated. Detailed Implementation

[0033] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only the configurations in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0034] Several aspects of the invention will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0035] Certain aspects of this disclosure relate to communication of digital signals comprising transitions between two or more signaling states. For the purposes of this description, the transition between two signaling states in a digital signal may be referred to as an edge. A transition from a low-voltage signaling state to a higher-voltage signaling state may be referred to as a positive edge, positive transition, rising edge, rising transition, or positive transition edge. A transition from a higher-voltage signaling state to a low-voltage signaling state may be referred to as a negative edge, negative transition, falling edge, falling transition, or negative transition edge.

[0036] Certain aspects of this disclosure relate to serial bus configurations in which multiple devices can communicate at various times. The described serial bus typically operates in a hierarchical manner, as one device controls communication during a transaction. The controlling device may be referred to as a master device, bus master, management device, or another term supported by a standard defining a protocol implemented by the controlling device. In some serial bus configurations, a single controlling device manages or controls communication during all transactions conducted via the serial bus. In other serial bus configurations, for each transaction conducted via the serial bus, multiple devices may operate as controlling devices, and one device may act as the controlling device. The controlling device may provide a common clock signal transmitted over a conventional two-wire serial bus. The controlling device may provide control signaling that identifies the type of transaction to be conducted over the conventional two-wire serial bus. During certain transactions, the controlling device may send commands to one or more receiving devices using address information provided in or with a command. The receiving device may be referred to as a client device, slave device, dependent device, peripheral device, or another term supported by a standard defining a protocol implemented by the controlling device. For the purposes of this disclosure, the controlling device will be referred to as a master device, and the associated receiving device will be referred to as a dependent device.

[0037] Devices comprising multiple SoCs and / or other IC devices typically employ a shared communication interface, which may include a serial bus or other data communication link to connect the processor to modems and other peripherals. The serial bus or other data communication link may operate according to multiple standards or protocols. For example, the serial bus may operate according to I2C, I3C, SPMI, and / or RFFE protocols, or another protocol that can be configured for half-duplex operation. The increased functionality and complexity of operating devices coupled to a serial bus, and the imposition of tighter timing constraints to support applications, peripherals, and sensors, can lead to greater demands on general-purpose input / output (GPIO) pin availability and communication link throughput.

[0038] Some aspects of this disclosure relate to techniques for communicating over a single-wire bus using Manchester encoding. A receive clock generated at the receiving device and used to sample the Manchester encoded signal can be resynchronized at each bit transmission interval, thereby eliminating the possibility of cumulative effects of transmission errors on the phase and frequency of the Manchester encoded signal or on the receive clock.

[0039] A system implemented according to certain aspects of this disclosure includes a host device coupled to a single-wire serial bus and a plurality of receiving devices coupled to the single-wire serial bus. Each of the plurality of receiving devices may have a clock generator circuit configured to generate a basic clock signal and a counter configured to count the period or edge of a corresponding basic clock signal. The host device may be configured to: initiate a first transaction to be performed via the single-wire serial bus; send a broadcast command in the first transaction; send a measurement pulse in the first transaction after the broadcast command, the measurement pulse having a pulse duration defined by the number of clock periods of a transmitter clock signal used by the host device; and receive the measurement duration of the measurement pulse from each of the plurality of receiving devices. At least one receiving device may be configured to measure the measurement pulse by using its counter to count the period or edge of its basic clock signal while the measurement pulse is being transmitted via the single-wire serial bus. At least one receiving device may be further configured to adjust the count value of its counter using a correction value when the counter is timing a triggered actuation, the correction value representing the difference between the period or edge of the basic clock signal being counted while receiving the measurement pulse and the number of clock periods of the transmitter clock signal used by the host device.

[0040] Some aspects disclosed herein provide alternatives to or complements to serial bus protocols, such as I2C, I3C, SPMI, and / or RFFE protocols. Some aspects are applicable to serial buses operating in half-duplex or full-duplex mode.

[0041] Example of a device using a serial data link According to certain aspects of this disclosure, serial data links can be used to interconnect electronic devices that are subcomponents of devices such as: cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similar functional devices.

[0042] Figure 1 An example of a device 100 that may employ a data communication bus is illustrated. Device 100 may include processing circuitry 102 having multiple circuits or devices 104, 106, and / or 108, which may be implemented in a SoC or one or more ASICs. In one example, device 100 may be a communication device, and processing circuitry 102 may include processing devices provided in ASIC 104, one or more peripheral devices 106, and a transceiver 108 enabling the device to communicate with a radio access network, a core access network, the Internet, and / or another network via antenna 124.

[0043] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuitry 116, and / or other logic circuitry or functions. Processing circuitry 102 may be controlled by an operating system that provides an application programming interface (API) layer, enabling one or more processors 112 to execute software modules residing in onboard memory 114 or other processor-readable storage device 122 provided on processing circuitry 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable storage device 122. ASIC 104 may access its onboard memory 114, processor-readable storage device 122, and / or storage devices external to processing circuitry 102. Onboard memory 114 and processor-readable storage device 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. Processing circuitry 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information for configuring and operating device 100 and / or processing circuitry 102. The local database may be implemented using registers, database modules, flash memory, magnetic media, EEPROM, floppy disks, or hard disks, etc. Processing circuitry 102 may also be operatively coupled to external devices such as antenna 124, display 126, operator controls such as switches or buttons 128, 130 and / or integrated or external keyboard 132, and other components. The user interface module may be configured to operate with display 126, external keyboard 132, etc., via a dedicated communication link or via one or more serial data interconnects.

[0044] Processing circuitry 102 may provide one or more buses 118a, 118b, 120 that enable communication between certain devices 104, 106, and / or 108. In one example, ASIC 104 may include bus interface circuitry 116, which includes a combination of circuitry, counters, timers, control logic units, and other configurable circuitry or modules. In one example, bus interface circuitry 116 may be configured to operate according to a communication specification or protocol. Processing circuitry 102 may include or control power management functions that configure and manage the operation of device 100.

[0045] Figure 2 A first example of an apparatus 200 employing a data link that can be used to communicatively couple two or more devices is illustrated. Here, apparatus 200 includes a plurality of devices 202 and 2220 to 2220 coupled to a two-wire serial bus 220. N Equipment 202 and 2220 to 222 N It can be implemented in one or more semiconductor IC devices, such as application processors, SoCs, or ASICs. In various specific implementations, devices 202 and 2220 to 222... N Some of the devices may include, support modems, signal processing devices, display drivers, cameras, user interfaces, sensors, sensor controllers, media players, transceivers, and / or other such components or devices, or operate as such. In some examples, one or more devices 2220 to 222 N It can be used to control, manage, or monitor sensor devices. Devices 202 and 2220 to 222 are connected via serial bus 220. N Communication between them is controlled by the host device 202. Some types of buses can support multiple host devices 202.

[0046] In one example, host device 202 may include interface controller 204 that manages access to the serial bus, configures dynamic addresses for slave devices, and / or generates clock signals 228 to be transmitted on clock line 218 of the serial bus 220. Host device 202 may include configuration register 206 or other storage device 224 and other control logic components 212 configured to process protocols and / or higher-level functions. Control logic component 212 may include processing circuitry such as a state machine, sequencer, signal processor, or general-purpose processor. Host device 202 includes transceiver 210 and line drivers / receivers 214a and 214b. Transceiver 210 may include receivers, transmitters, and common circuitry, where such common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in clock signal 228 provided by clock generation circuitry 208. Additional timing clocks 226 may be used by control logic component 212 and other functions, circuitry, or modules.

[0047] One or more devices 2220-222 N It can be configured to operate as a slave device. In some examples, a slave device may include circuitry and modules supporting a display, an image sensor, and / or circuitry and modules controlling and communicating with one or more sensors measuring environmental conditions. In one example, device 2220 configured to operate as a slave device may provide control functions, modules, or circuitry 232, including circuitry and modules for supporting a display, an image sensor, and / or controlling and communicating with one or more sensors measuring environmental conditions. In this example, device 2220 may include a configuration register 234 or other storage device 236, control logic unit 242, transceiver 240, and line drivers / receivers 244a and 244b. Control logic unit 242 may include processing circuitry, such as a state machine, sequencer, signal processor, or general-purpose processor. Transceiver 240 may include a receiver, a transmitter, and common circuitry, wherein these common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in clock signal 248 provided by clock generation and / or recovery circuitry 246. In some cases, clock signal 248 may be derived from a signal received from clock line 218. Other timing clocks 238 may be used by control logic unit 242 and other functions, circuits, or modules.

[0048] Serial bus 220 can operate according to RFFE, I2C, I3C, SPMI, or other protocols. Devices 202 and 2220-222 NAt least one of them can be configured to operate as both a master device and a slave device on serial bus 220. Devices 202 and 2220-222 N Two or more of these devices can be configured to operate as master devices on serial bus 220. The protocol selected to control the operation of serial bus 220 can define DC characteristics affecting certain signal levels associated with serial bus 220, and / or AC characteristics affecting certain timing aspects of signals transmitted on serial bus 220. In various examples, the two-wire serial bus 220 transmits data on data line 216 and a clock signal on clock line 218. In some cases, the data can be encoded in signaling states or in signaling state transitions between data line 216 and clock line 218.

[0049] Figure 3 A second example of an apparatus 300 employing a data link that can be used to communicatively couple two or more devices is illustrated. In this example, a chipset or device 302 employs multiple RFFE buses 330, 332, 334 to couple various RF front-end devices 318, 320, 322, 324, 326, 328. A modem 304 includes an RFFE interface 308 that couples the modem 304 to a first RFFE bus 330. The modem 304 can communicate with a baseband processor 306 and a radio frequency IC (RFIC 312) via one or more communication links 310, 336. The illustrated device 302 may be embodied in one or more of the following: mobile communication devices, mobile phones, mobile computing systems, laptops, tablet computing devices, media players, gaming devices, wearable computing devices and / or communication devices, electrical appliances, etc.

[0050] In various examples, device 302 may be implemented using one or more baseband processors 306, modems 304, RFICs 312, multiple communication links 310, 336, multiple RFFE buses 330, 332, 334, and / or other types of buses. Device 302 may include other processors, circuitry, modules, and may be configured for various operations and / or different functionalities. Figure 3In the illustrated example, the modem is coupled to the RF tuner 318 via its RFFE interface 308 and first RFFE bus 330. The RFIC 312 may include one or more RFFE interfaces 314, 316, a controller, a state machine, and / or a processor that configures and controls certain aspects of the RF front end. The RFIC 312 can communicate with the PA 320 and the power tracking module 322 via the first RFFE interface and the second RFFE bus 332 in its RFFE interface 314. The RFIC 312 can communicate with the switch 324 and one or more LNAs 326, 328 via the second RFFE interface and the third RFFE bus 334 in its RFFE interface 316.

[0051] Bus latency can affect the serial bus's ability to process high-priority, real-time, and / or other time-constrained messages. Low-latency messages, or messages requiring low bus latency, may involve sensor states, device-generated real-time events, and virtualized GPIO states. In one example, bus latency can be measured as the time elapsed between when a message becomes available for transmission and the delivery of that message, or in some cases, the start of its transmission. Other measurements of bus latency may be employed. Bus latency typically includes delays incurred when transmitting higher-priority messages, interrupt handling, the time required to terminate datagrams in progress on the serial bus, the time for sending commands that cause the bus to switch between transmit and receive modes, bus arbitration, and / or command transmission specified by the protocol.

[0052] In some examples, delay-sensitive messages may include coexistence messages. Sending coexistence messages in a multi-system platform prevents or reduces conflicts between certain device types, including, for example, switches 324, LNAs 326, 328, PAs 320, and other types of devices operating concurrently in a manner that may generate inter-device interference or potentially damage one or more devices. Devices that may interfere with each other can exchange coexistence management (CxM) messages to allow each device to signal impending actions that may cause interference or conflict. CxM messages can be used to manage the operation of shared components, including switches 324, LNAs 326, 328, PAs 320, and / or antennas.

[0053] Multipoint interfaces (such as RFFE, SPMI, I3C, etc.) can reduce the number of physical input / output (I / O) pins used for communication between multiple devices. Protocols supporting communication over multipoint serial buses define datagram structures for sending command, control, and data payloads. Certain common features are defined for the datagram structures of different protocols, including addressing for selecting devices to receive or send data, clock generation and management, interrupt handling, and device priority. In this disclosure, examples of the RFFE protocol may be used to illustrate certain aspects disclosed herein. However, the concepts disclosed herein are applicable to other serial bus protocols and standards.

[0054] Figure 4 Timing diagrams 400 and 420 illustrate signaling transmitted to delineate the boundaries of datagrams sent according to the RFFE protocol. Timing diagrams 400 and 420 show the relative timing of signals transmitted on a two-wire serial bus, which provides a clock signal on SCLK 402 and facilitates data exchange via SDATA 404. The first timing diagram 400 illustrates the timing of a sequence start condition (SSC 408), which is transmitted to signal the start of a transaction, such as the transmission of datagram 410. SSC 408 is transmitted when the serial bus is in idle state 406. In idle state 406, SCLK 402 is driven at full strength by the master device, while slave devices coupled to the serial bus present high impedance to SCLK 402. SCLK 402 is held in a low signaling state (here, zero volts) by the master device. In idle state 406, SDATA 404 is weakly driven by the host device or held in a weakly driven low signaling state 412 using a hold circuit or a weak pull-down circuit. For example, the hold circuit or weak pull-down circuit can maintain the signaling state of SDATA 404 when the host device has put its line driver into a high-impedance state, and when no other device is driving SDATA 404. The weakly driven low signaling state 412 can be easily overcome by another line driver capable of driving SDATA 404 at full strength.

[0055] In the master-driven SSC 408, the master device begins transmitting SSC 408 at a first time point 414, at which time the master device begins driving SDATA 404, which is initially in a low signaling state, at full strength. The master device then provides pulse 416 on SDATA 404 while continuing to drive SCLK 402 to a low signaling state. Pulse 416 has a duration of at least one cycle of the clock signal provided on SCLK 402 during the transmission of datagram 410. At a second time point 418, the master device begins transmitting clock pulses on SCLK 402, thereby providing a clock signal for controlling or indicating the timing of datagram 410 transmitted on SDATA 404.

[0056] For example, second timing diagram 420 illustrates the timing of a bus stop cycle (BPC 424) that can be sent to signal the termination of datagram 422. BPC 424 is sent by providing a falling edge 428 on SDATA 404 when SCLK 402 is in a high signaling state 430. By protocol, transitions on SDATA 404 are permitted only during the transmission of datagram 422 when the clock signal is in a low signaling state, and the falling edge 428 occurring when SCLK 402 is in a high signaling state 430 is interpreted as control signaling (i.e., BPC 424). The falling edge 428 is provided by the master device driving SDATA 404 low at full strength. The master device then drives SCLK 402 low and continues to drive SCLK 402 at full strength through subsequent bus idle intervals 426, 436. After driving SCLK 402 low, the host device initiates a bus idle interval 436 at time 432 when it puts its line driver into a high-impedance state. When no other device is driving SDATA 404, SDATA 404 remains in a weakly driven low signaling state 434. BPC 424 is terminated, and the serial bus enters a bus idle interval 426 until the next datagram is ready to be transmitted.

[0057] The various examples provided herein depict examples of a single-wire serial bus in which data and commands are configured according to the RFFE protocol. However, these concepts are not limited to the RFFE protocol, and various aspects of this disclosure are equally applicable to I2C, I3C, SPI, SPMI, and other standard-defined or proprietary protocols. The single wire of the single-wire serial bus serves as a data line for bidirectional transmission of control and data signaling. According to certain aspects of this disclosure, timing for communication between single-wire slave devices coupled to the serial bus can be embedded in data transmission, and control signaling can be provided to synchronize clock signals at the transmitter and receiver.

[0058] Figure 5 Examples are illustrated of a host device 502 and one or more single-line slave devices 5041 to 504 according to certain aspects disclosed herein. N The communication system 500. The host device 502 may be located in an RFIC, modem, application processor, or other type of device. The host device 502 may be adapted to communicate with single-line slave devices 5041 to 504. N Data is exchanged on this single line, referred to as SDATA line 506 in the illustrated system 500. The data is encoded in a signal transmitted via SDATA line 506, wherein the signal includes embedded clock information that can be used by a receiving device to decode the data from the signal.

[0059] Master device 502 and single-line slave devices 5041 to 504 N This typically includes the corresponding protocol controllers 508, 5101 to 510. N Protocol controllers 508, 5101-510 N This may include a processor, controller, state machine, or other logic circuit configured to support one or more protocols. The protocol controller 508 in the host device 502 may be further configured to manage communication via the SDATA line 506. In some cases, the protocol controller 508 performs some of the functions of the host device. In some specific implementations, the protocol controller 508 in the host device 502 may be used to configure single-wire slave devices 5041 to 504. N One or more of them. The host device 502 can identify single-line slave devices 5041 to 504 as the designated recipients of data to be sent via the SDATA line 506. N The configuration allows the protocol controller 508 to be configured for use with receiver single-wire slave devices 5041 to 504. N The data encoding is to be sent via SDATA line 506 and addressed to single-wire slave devices 5041 to 504. N The signal.

[0060] The host device 502 may include a transmit clock generator 512, which can be used to define the timing of transmissions made via the SDATA line 506. Single-wire slave devices 5041 to 504 N Each of them includes local clock generation circuits 5141 to 514. N It provides corresponding protocol controllers 5101 to 510. N Timing. Local clock generation circuits 5141 to 514. N The synchronization pulse sent by the host device 502 after the SSC can be used, or by the host device 502 or single-line slave devices 5041 to 504 after online turnaround. N Synchronization is achieved by sending a synchronization pulse from one of the circuits. According to certain aspects of this disclosure, local clock generation circuits 5141 to 514... N Synchronization can be achieved using transitions in the Manchester-encoded command and data payloads transmitted via SDATA line 506. Local clock generation circuits 5141 to 514. N This may include a ring oscillator or a delay-locked loop. In some specific implementations, the local clock generation circuit 5141-514 N It may include an injection-locked oscillator that responds to synchronization pulses and / or transitions in the transmission of Manchester-encoded command and data payloads.

[0061] Holder circuit 516 may be coupled to SDATA line 506 to facilitate line turnaround, in-band interruption requests, or arbitration processes according to certain aspects disclosed herein. In one example, holder circuit 516 may be configured as a positive feedback circuit that drives SDATA line 506 through a high-impedance output and receives feedback from SDATA line 506 through a low-impedance input. Holder circuit 516 may be configured to maintain the signaling state or voltage of the last assertion on SDATA line 506. Holder circuit 516 may be in host device 502 or single-wire slave devices 5041 to 504. N The active line driver in one of them is easily overcome.

[0062] Figure 6 An example of a single-wire serial interface 600 that can be configured according to certain aspects of this disclosure is illustrated. In this example, a host device 502 and a single-wire slave device 504 are illustrated. N (See Figure 5 The host device 502 includes a protocol controller 602. The protocol controller 602 can be implemented using a processor, microcontroller, or finite state machine, and can be used to control the transmit and receive functions of the host device 502. The protocol controller 602 may include or be coupled to a signal generation circuit 604, which generates signals that couple the host device 502 to one or more slave devices 504. N The synchronization signal and SSC signal are transmitted on the SDATA line 620. The signal generation circuit 604 can be configured to generate different types of SSCs to initiate arbitration, initiate data transmission, or abandon arbitration. The signal generation circuit 604 can be configured to generate a synchronization pulse, which is used to enable the slave device 504. N The clock signal generated at the location is synchronized with the transmission clock signal generated in the host device 502.

[0063] Protocol controller 602 can be configured to selectively activate Manchester encoder 606 and Manchester decoder 608 based on the operating mode of single-wire serial interface 600. Manchester decoder 608 can extract data and clock information from signals received from SDATA line 620. Protocol controller 602 can be further configured to format datagrams for transmission via SDATA line 620. Protocol controller 602 can be further configured to generate commands to be transmitted via SDATA line 620.

[0064] In the illustrated example, single-line slave device 504 N This includes a protocol controller 622. The protocol controller 622 can be implemented using a processor, microcontroller, or finite state machine, and can be used to control a single-wire slave device 504. NThe protocol controller 622 may include or be coupled to a signal generation circuit 624, which is in the single-wire slave device 504. N A synchronization pulse to be transmitted is generated during transmission via SDATA line 620. Protocol controller 622 can be further configured to cause signal generation circuit 624 to drive SDATA line 620 to initiate SSC during an in-band interrupt, and can be further configured to cause signal generation circuit 624 to drive SDATA line during arbitration. The synchronization pulse generated by signal generation circuit 604 can be configured to synchronize the clock signal generated at master device 502 with that at slave device 504. N The transmitted clock signal generated in the process is synchronized.

[0065] Protocol controller 622 can be configured to selectively activate Manchester encoder 626 and Manchester decoder 628 based on the operating mode of single-wire serial interface 600. Manchester decoder 628 can extract data and clock information from signals received from SDATA line 620. Protocol controller 622 can be further configured to format datagrams for transmission via SDATA line 620. Protocol controller 622 can be further configured to decompose datagrams and / or respond to commands received from SDATA line 620.

[0066] Protocol controller 602 can be configured to manage and control the operation of line driver 612 and line receiver 610. Protocol controller 622 can be configured to manage and control the operation of line driver 632 and line receiver 630. When inactive or deactivated, line drivers 612, 632 may present a high impedance to SDATA line 620. For example, when single-line slave device 504... N When configured or intended to send data or control signals via SDATA line 620, the output of line driver 612 in host device 502 can present high impedance to SDATA line 620. While host device 502 is driving SDATA line 620, single-line slave device 504... N The output of the line driver 632 is typically in a high impedance state.

[0067] A hold circuit 640 coupled to SDATA line 620 facilitates line turnaround, in-band interrupt requests, and arbitration processes in a bidirectional single-wire serial bus. Maintaining the state of SDATA line 620 is typically desired when all devices are in high-impedance mode, during line turnaround, or during arbitration. Line turnaround occurs when master device 502 transitions from transmitting to receiving or from receiving to transmitting. During arbitration, when single-wire slave device 504... NWhen the host device 502 has a transmit option and the line driver in the host device 502 can present a high impedance to the SDATA line 620 to avoid contention, the host device 502 can enter a high impedance mode. A hold circuit 640 can be used to maintain the state of the SDATA line 620. In one example, the hold circuit 640 can be configured as a positive feedback circuit that drives the SDATA line 620 through a high impedance output and receives feedback from the SDATA line 620 through a low impedance input. The hold circuit 640 can be configured to maintain the last asserted voltage on the SDATA line 620. The hold circuit 640 can be controlled by both the host device 502 and the single-line slave device 504. N The line drivers 612 and 632 in the middle can be easily overcome.

[0068] Based on certain aspects disclosed herein, one or more protocols can be used to control the operation of a mixed-mode serial bus coupled to concurrent two-wire slave devices and single-wire slave devices. Protocols disclosed herein for configuring, managing, and controlling single-wire transmissions over a serial bus can coexist with, be based on, and / or be compatible with protocols for configuring, managing, and controlling two-wire transmissions over a serial bus.

[0069] Figure 7 A system 700 according to certain aspects disclosed herein is illustrated, in which single-line slave devices 7041-704 are provided. M and dual-line slave equipment 7061-706 N They can coexist, and the master device 702 can coexist with single-line slave devices 7041-704. M and dual-line slave equipment 7061-706 N The two communicate with each other. The host device 702 can be located in an RFIC, modem, application processor, or another type of device. The host device 702 is coupled to one or more slave devices 7041-704 via at least an SDATA line 710 of a two-wire serial bus 708 that also has an SCLK line 712. M 7061-706 N Data can be encoded in a data signal transmitted via SDATA line 710, and in two-wire communication mode, the receiver can extract the data using a clock signal transmitted via SCLK line 712. In the illustrated example, serial bus 708 operates according to the RFFE protocol. In other examples, serial bus 708 may operate according to another protocol (such as the I3C protocol, SPMI protocol, etc.). In the illustrated example, each single-wire slave device 7041-704 M and each dual-line slave device 7061-706N Coupled to SDATA line 710. Single-wire slave device 7041-704 M Adapted for single-wire communication mode, while dual-wire slave devices 7061-706 N It is also coupled to the SCLK line 712 to receive the clock signal used in two-wire communication mode.

[0070] The host device 702 may include a protocol controller 714, which may be implemented using processing circuitry having a processor, controller, state machine, or other logic components. The protocol controller 714 may be configured to support one or more protocols that can be used to manage the operation of the serial bus 708. In some implementations, the protocol controller 714 may be operable to configure one or more slave devices 7041-704. M 7061-706 N Protocol controller 714 can determine slave devices 7041-704 that are designated recipients of data to be transmitted via serial bus 708. M 7061-706 N The configuration allows for the corresponding encoding of data into signals to be transmitted via the SDATA line 710. In some cases, this applies to single-wire slave devices 7041-704. M and dual-line slave equipment 7061-706 N The combined broadcast message can be transmitted twice, once in single-wire communication mode and once in two-wire communication mode. Protocol controller 714 can additionally determine whether and / or when to send a clock signal via SCLK line 712. In some implementations, when data is sent to one or more single-wire slave devices 7041-704 in single-wire communication mode... M At that time, the clock signal is suppressed.

[0071] Based on certain aspects disclosed herein, the host device 702 can initiate a transaction on single-line slave devices 7041-704. M With dual-line slave equipment 7061-706 N The choice is made between these options. The master device 702 can use different Sequence Start Conditions (SSCs) to precede single-line and dual-line transactions. In some specific implementations, single-line slave devices 7041-704... M and / or dual-line slave equipment 7061-706 N Some interface features can be configurable. For example, single-wire slave devices 7041-704 coupled to the serial bus 708. M and / or dual-line slave equipment 7061-706 NThe specified bus capacitor can be matched when driving the SDATA line 710 based on the configurable register settings defined for the capacitor specified on the SDATA line 710. Otherwise, the specified bus capacitor can be hardwired in the single-wire slave devices 7041-704. M and / or dual-line slave equipment 7061-706 N middle.

[0072] In some implementations, a programmable sequence of synchronization pulses transmitted after the SSC or other frame start signaling can be used as an edge-sensitive phase synchronization trigger at the receiver. In one example, the synchronization pulses are transmitted before the transmission of data bits (including after a line turnaround event when the receiving device becomes the transmitting device). In other implementations, the first synchronization pulse transmitted can be used as frame start signaling. In some implementations, each synchronization pulse is transmitted in a single clock cycle.

[0073] Interface state transitions can be detected and used to disable or enable the oscillator in the receive clock generation circuitry. For example, the oscillator can be enabled upon detection of an SSC or other frame start signaling, and disabled upon detection of a BPC or other frame end signaling, thereby saving energy by avoiding the need for a constantly on, free-running oscillator. When the single-wire serial bus is controlled by a protocol derived from the RFFE protocol, an SSC indicates the start of a frame.

[0074] Triggers provide a mechanism for RF front-end control and can be used to coordinate the activities of different front-end components. For example, triggers can be used for various purposes, including beam steering or beamforming, gain setting, antenna path multiplexer control, etc. In some devices, triggers can be configured, activated, and / or actuated via a serial bus operating according to the RFFE protocol. In some conventional systems, the Bus Owner Master (BoM) can send commands that include trigger configuration and actions associated with the configured trigger, such that receiving the command causes the trigger to be actuated or otherwise activated or applied. Triggers configured by commands are referred to as self-actuated triggers.

[0075] Advances in RF technology and the introduction of additional capabilities in communication equipment have increased pressure on latency. For example, the deployment of radio access technologies such as 5G New Radio as defined by the 3rd Generation Partnership Project (3GPP) and the 802.11ax WLAN standard as defined by the IEEE 802.11 Working Group may require a 50% reduction in latency at conventional bus clock frequencies, increasing the complexity of the RFFE bus architecture and the likelihood of traffic congestion on the bus. RFFE bus congestion and timing bottlenecks are expected to exacerbate coexistence problems. For example, in cases of complex RFFE bus timing, increased bus activity may increase bus contention issues. In these scenarios, it is possible to prevent the Board of Management (BoM) from being triggered at the exact time required for slave devices to meet RF protocol timing.

[0076] In some systems, delayed triggering can be used to avoid bus congestion and timing bottlenecks, and to ensure timely trigger actuation. The Board of Management (BoM) can configure one or more triggers and corresponding timers that control the actual timing of the configured triggers. For example, the BoM can define the action associated with a configured trigger and can activate one or more counters or timers that define the time at which the trigger can be actuated. Actuating the trigger causes or initiates the action associated with it. The counters or timers can define the actuation time as the number of clock cycles in the clock signal sent by the BoM to control timing on the serial bus.

[0077] Figure 8 Examples of certain aspects of this disclosure can be illustrated by means of... Figure 7 The serial bus 708 illustrated here transmits the start of a two-wire transaction 800 and the start of a single-wire transaction 820. The two-wire transaction 800 and the single-wire transaction 820 can be formatted according to the RFFE protocol.

[0078] Two-wire transaction 800 begins with an SSC 808 of duration consistent with the RFFE protocol. The serial bus 708 is initially idle, with both the SDATA line 802 and the SCLK line 804 in a low signaling state. The host device 702 can initiate two-wire transaction 800 by sending two bits of SSC 808. The bit duration, or the transmission time per data bit, can be determined by the frequency of the internal clock signal used by the host device 702. The internal clock can be selected to control the bit rate of the serial bus 708 during data transmission. SSC 808 comprises a pulse transmitted on the SDATA line 802 while the SCLK line 804 remains low. This pulse consists of a high bit followed by a low bit. Following SSC 808 may be a slave address, which can be part of the command and data information 810. In normal RFFE operation, the command and data information 810 includes the slave address [SA3:SA0]. Information can be captured from the SDATA line 802 based on the timing of the clock pulses in the transmit clock signal 812 provided on the SCLK line 804. No clock pulses are provided during the transmission of the SSC 808, and the receiving device recognizes the transition of signaling state indication control signaling on the SDATA line 802 when the SCLK line 804 is held low.

[0079] Various aspects of the SSC 808 are defined by the RFFE protocol, including the duration of the high and low portions of the SSC 808. The rise time of the preamble transition (T...) R ) and the fall time of the pulse termination transition (T F The frequency of the clock signal transmitted on the SCLK line 804 is also defined by the protocol. Limitations on the frequency of the clock signal transmitted on the SCLK line 804 can be defined by design, application, and / or by the RFFE specification and protocol. The protocol controller 714 can be configured to transmit a modified SSC indicating when to communicate with single-wire slave devices 7041-704. M Perform transactions. In some examples, the protocol controller 714 can send an extended-length SSC to single-wire slave devices 7041-704. M The target communication and / or indication transaction will be conducted in single-wire communication mode. An extended-length SSC can have a duration greater than the duration of the SSC pulse for two-wire operation as defined by the RFFE specification. In some specific implementations, the protocol controller 714 can send a shortened SSC to single-wire slave devices 7041-704. M As a target for communication, the shortened SSC includes a pulse with a duration shorter than the duration of the SSC pulse provided according to the RFFE specification. In some cases, the protocol controller 714 may send an SSC with a modified rise time and / or fall time to single-wire slave devices 7041-704.M Communicate as a target.

[0080] The illustrated single-line transaction 820 provides the ability to use devices 7041-704 configured as single-line slaves. M An example of an extended duration SSC 822 for a target. Serial bus 708 is initially idle, with both SDATA line 802 and SCLK line 804 in a low signaling state. The single-wire nature of transaction 820 is indicated by a pulse timing signature in SSC 822. In the illustrated example, the pulse timing signature corresponds to a pulse duration in SSC 822 that is three times the pulse duration of SSC 808 sent to initiate two-wire transaction 800. In other examples, the pulse duration in SSC 822 may be some other multiple of the pulse duration of SSC 808 sent to initiate two-wire transaction 800.

[0081] The pulse duration in SSC 808 and 828 can be used in single-wire slave devices 7041-704. M and dual-line slave equipment 7061-706 N An internal clock signal 806 is provided to measure or determine the duration of the pulses in SSCs 808 and 828, since no clock pulses are provided on SCLK line 804 during the transmission of SSCs 808 or 828. The illustrated internal clock signal 806 is an oversampled signal whose frequency is four times the frequency of the transmit clock signal 812 sent on SCLK line 804 during a two-line transaction 800. In one example, the frequency of transmit clock signal 812 is 52 MHz. The internal clock signal 806 is needed to measure the duration of the pulses in SSCs 808 and 828 because no clock pulses are provided on SCLK line 804 during the transmission of SSCs 808 or 828.

[0082] The host device 702 initiates a single-wire transaction 820 by sending an extended-duration SSC 822. The pulse in the extended-duration SSC 822 consists of three high bits followed by one low bit. Following the extended-duration SSC 822 is a synchronization mode 824, which includes bits that can be used to synchronize the phase of the internal clock signal 806 with the edges of the data signal transmitted via the SDATA line 802. After the synchronization mode 824 has been sent, command and data information 826 is transmitted by the host device 702 in a Manchester-encoded data signal. The command and payload data in the single-wire transaction 820 can be sampled or captured based on the timing of the synchronized internal clock signal 806.

[0083] According to certain aspects of this disclosure, when a slave single-wire device is timing trigger actuation, the slave single-wire device can overcome the lack of a reference clock for trigger timing when coupled to a serial bus used for two-wire communication.

[0084] Figure 9 This is a block diagram illustrating an example of a trigger-actuation circuit 900 that can be configured to configure, activate, and actuate. In the illustrated example, configuration information is received as multiple data bytes 902, which can be stored in a trigger shadow register 904. The trigger shadow register 904 can be written to during configuration transactions via a serial bus that operates according to the RFFE protocol. For example, a timer or counter in a control circuit configured based on information provided by the BoM can be used to forward the contents of the trigger shadow register 904 to a target for configuration.

[0085] Trigger activation logic unit 906 can be configured to transmit the contents of trigger shadow register 904 to the corresponding target device in response to a received trigger command or trigger actuation signal 910 provided by control circuitry. Trigger elements 908 may include switches 324, LNAs 326, 328, PAs 320, and other types of devices operating concurrently in the RF front end. In one example, the BoM can be configured with masking or gating logic to determine which trigger elements 908 should receive data from trigger shadow register 904 during actuation initiated by trigger actuation signal 910. In another example, masking or gating logic can determine which trigger elements 908 should receive data from trigger shadow register 904 during actuation initiated by the corresponding trigger actuation signal 910.

[0086] Certain aspects disclosed herein provide mechanisms that enable the Board of Management (BoM) to configure triggers with reliable delayed actuation in two-wire and single-wire slave devices coupled to a mixed-mode serial bus. The trigger can be configured before a defined actuation time, and the slave device can wait for a defined period of time before actuating the trigger. In one example, the BoM can transmit the trigger ahead of time and when bus traffic conditions permit. The slave device may include configurable counters or timers that provide the trigger actuation signal 910 based on timing provided by clock information transmitted by the BoM via the serial bus. The clock information can be transmitted to the two-wire slave device via a dedicated clock line. The clock information can be provided to the single-wire slave device as equivalent clock ticks, which are encoded by continuously transmitting data or commands via the lines of the serial bus coupled to the single-wire slave device, thereby enabling the single-wire slave device to maintain a synchronous local clock that can be used to time the trigger actuation.

[0087] Figure 10This is a timing diagram 1000 illustrating the availability of timing information for slave devices coupled to a mixed-mode serial bus when both single-wire and two-wire slave devices are actively communicating via the mixed-mode serial bus. The single-wire and two-wire slave devices are coupled to a common data line (SDATA 1002). The two-wire slave device is coupled to a dedicated clock line (SCLK 1004), which provides timing information (clock pulse 1020) for sending and receiving data and commands via SDATA 1002 during two-wire transactions 1008. The single-wire slave device generates an internal clock signal, which may be referred to as a local oscillator (LO) clock signal, and can be used to generate a receive clock signal (single-wire RxClock 1006) that is synchronized with transitions in the Manchester-encoded signal sent via SDATA 1002 during single-wire transactions 1012.

[0088] The BoM can configure counters or other timing devices in single-wire and / or two-wire slave devices to actuate triggers at corresponding desired time points. In the nominal operating system, triggers can be configured to be actuated at the same time point or in a tightly scheduled sequence.

[0089] In one example, the nominal operating system may only support two-wire slave devices, in which trigger timing can be derived from the clock signal sent via SCLK 1004. The BoM sends clock pulses simultaneously with the transmission of datagrams in two-wire transaction 1008. For the purpose of trigger timing via a serial bus limited to two-wire use, the BoM can send clock pulses 1022, 1024, and 1026 when SDATA 1002 is idle. Two-wire slave devices can add clock pulses during idle periods 1016 of SCLK 1004, which correspond to the transmission of two-wire SSC 1010.

[0090] Other systems include single-wire and two-wire slave devices coupled to the mixed-mode serial bus. When performing a single-wire transaction 1012 via the mixed-mode serial bus, the clock signal transmitted via SCLK 1004 can be suppressed. SCLK 1004 is suppressed to prevent two-wire slave devices from recognizing or responding to single-wire SSC 1014 and potentially similar single-wire signaling. Two-wire slave devices coupled to the mixed-mode serial bus typically cannot know the number of clock pulses lost when the clock signal is suppressed during single-wire transaction 1012.

[0091] In another example, the nominal operating system may include a system that only supports single-wire slave devices, in which trigger timing can be derived from the single-wire RxClock 1006. The single-wire slave device can generate the single-wire RxClock 1006 while transmitting a datagram in single-wire transaction 1012. For the purpose of trigger timing via a serial bus limited to single-wire use, the BoM can transmit a stream of empty or unaddressed data when SDATA 1002 is idle. The single-wire slave device can add or interpolate clock pulses during the period corresponding to the transmission of single-wire SSC 1014. When performing a two-wire transaction 1008 via a mixed-mode serial bus, the single-wire slave device cannot synchronize its single-wire RxClock 1006. The accuracy of trigger timing may be significantly degraded by the loss of clock information that occurs when the BoM does not transmit Manchester-encoded data.

[0092] Slave devices configured according to certain aspects of this disclosure can provide improved trigger timing accuracy by calibrating the slave device using timing information associated with one or more internal clock signals. Single-wire slave devices configured according to certain aspects of this disclosure can use an internal basic clock signal to generate a receive clock signal synchronized with a BoM transmitter clock signal used to encode Manchester-encoded signals transmitted via SDATA 1002. In some embodiments, the basic clock signal is generated by a local oscillator and its frequency is four times the frequency of the BoM transmitter clock signal, and can provide the resolution required to calibrate the receive clock signal or compensate for the frequency difference observed between the receive clock signal and the BoM transmitter clock signal. Certain aspects of this disclosure also apply to two-wire slave devices, including those using a basic clock signal or those that can generate a basic clock signal at a frequency that is a multiple of the frequency of the BoM transmitter clock signal. In some cases, a BoM coupled to a mixed-mode serial bus can be configured with self-actuated triggering for any or all single-wire slave devices coupled to the mixed-mode serial bus, and then with corresponding self-actuated triggering for two-wire slave devices coupled to the mixed-mode serial bus. In these cases, the BoM can suppress single-wire communication until all triggers have been actuated, and can send clock signals for use by two-wire slave devices when the mixed-mode serial bus is idle.

[0093] Figure 11 This illustrates certain aspects of timing in a slave device configured to use internal clock resources to manage self-actuated timing. The slave device may be coupled to a mixed-mode serial bus and may include some combination of single-wire and two-wire slave devices.

[0094] The first illustration depicts a timeline 1100 for configuring and actuating triggers across multiple slave devices. The concepts disclosed herein are equally applicable to managing and implementing self-actuated triggering across multiple slave devices or a single slave device. In one example, a group of slave devices may be configured to actuate corresponding triggers in a timing sequence that can separate trigger actuation over several clock cycles or hundreds of clock cycles. In some examples, slave devices may be configured with trigger information associated with multiple triggers to be actuated by the slave devices in a timing sequence that can separate trigger actuation over several clock cycles or up to hundreds of clock cycles. For the purposes of this description, it will be assumed that each slave device in the slave device group is configured with a self-actuated trigger by the BoM.

[0095] Self-actuated triggering can be configured asynchronously. See also: Figure 9 For example, the trigger shadow register 904 in each slave device can be written in any order 1102. Timing information provided to each slave device can be used to load a counter with a value corresponding to the number of cycles of the transmitter clock signal used by the BoM to control communication via the mixed-mode serial bus. In some embodiments, the timing information indicates when a count should be initiated by the counter. According to certain aspects of this disclosure, a slave device can be configured to initiate a count by the counter after successfully receiving the timing information or after a transaction including the timing information has terminated. In some embodiments, a slave device is configured to initiate a count by the counter after receiving a broadcast or directed command via the mixed-mode serial bus. In the illustrated example, after all self-actuated triggers have been configured and predefined count initiation conditions have been indicated, the counters in all slave devices are started and count 1104.

[0096] After a counter in a slave device reaches its target, a trigger is activated in each slave device. In one example, the counter can be loaded with a count value and can be decremented until it reaches the target value of zero. In another example, the count value is stored in a register and compared with the output of a counter that was initially cleared and configured to increment. In the latter example, when the counter's output corresponds to the value stored in the register, the comparator can indicate that the counter has reached its target.

[0097] The triggers are actuated within a time period referred to herein as trigger window 1110. In one example, trigger window 1110 is limited to a maximum duration of 0.25 microseconds (0.25µs). Self-actuated triggers can be configured according to a synchronization sequence, whereby the order and time interval of the triggers are defined by the configuration. In the illustrated example, two triggers 1112 and 1114 are configured to actuate concurrently, and four trigger actuation points are defined within trigger window 1110.

[0098] The example illustrated in timeline 1100 pertains to a nominal execution system in which a local oscillator in a slave device generates a fundamental clock signal at a nominal frequency, which is a multiple of the transmitter clock signal used by the BoM. In real-world systems, the frequency of the fundamental clock signal can be expected to vary between slave devices. It can also be expected that the frequency of the fundamental clock signal in a slave device is a non-integer multiple of the frequency of the transmitter clock signal used by the BoM. This variation can cause timing inaccuracies in each clock cycle of the fundamental clock signal, which, while marginal for a single clock cycle, accumulate over a large number of clock cycles and can lead to significant timing deviations between slave devices.

[0099] When the serial bus timing cannot be used to synchronize the internal clock signal at the slave device, the timing deviation between slave devices causes the actual trigger actuation point to deviate from the expected or reference trigger point.

[0100] Figure 11 Timing diagram 1120 illustrates some of the effects of timing variations caused by timing inaccuracies in the basic clock signal in the slave devices. Two triggers 1112 and 1114, configured to be concurrently actuated by two slave devices 1124 and 1126, show the elapsed time between the initiation of a count and the actuation of a trigger. For the purposes of this description, it can be assumed that the counters in the two slave devices 1124 and 1126 are started simultaneously, with the same initial value and the same target count value. The frequency of the basic clock signal in one slave device (slow device 1124) is less than the nominal or desired frequency for the slave device. The frequency of the basic clock signal in the other slave device (fast device 1126) is greater than the nominal or desired frequency for the basic clock signal in the slave device. A nominal trigger actuation point 1130 is shown for a reference device 1122, which operates at the nominal or desired frequency for the basic clock signal in the slave device. As can be observed from timing diagram 1120, fast device 1126 actuates its trigger before the nominal trigger actuation point 1130, and slow device 1124 actuates its trigger after the nominal trigger actuation point 1130.

[0101] In the illustrated example, the transmitter clock signal is configured for 52MHz, the frequency of the base clock signal in fast device 1126 is 10% higher than the nominal or desired frequency of the base clock signal in the slave device, and the frequency of the base clock signal in slow device 1124 is 10% lower than the nominal or desired frequency of the base clock signal in the slave device. In this example, fast device 1126 generates a receiver clock at a frequency of 57.2MHz, and slow device 1124 generates a receiver clock at a frequency of 46.8MHz. Counters in slow device 1124 and fast device 1126 are configured to count 264 clock cycles (clock ticks). When counting the cycles of the nominal 52MHz clock signal, reference device 1122 will reach its target after 5,076ns. Slow device 1124 reaches its target after 5,641ns, and fast device 1126 reaches its target after 4,615ns. In other words, the fast device 1126 actuates its trigger 461ns before the nominal trigger actuation point 1130, and the slow device 1124 actuates its trigger 565ns after the nominal trigger actuation point 1130.

[0102] Figure 12 This is a graph 1200 illustrating the relationship between the size of the trigger window and the number of clock cycles to be counted for slave devices coupled to a mixed-mode serial bus, which use an internal base clock signal not synchronized with the bus clock signal derived from the serial bus to time trigger actuation. The timing of the base clock signal per cycle in the slave device is not accurately accumulated for each counted clock cycle, and the trigger windows 1202, 1204, 1206, 1208 for the trigger group can be constrained to a minimum duration. The size of the trigger windows 1202, 1204, 1206, 1208 can be a function of clock cycle tolerance, rather than defined by application requirements. It can be shown that the trigger window width ( W TRIG ) can be calculated as: in: The number of clock beats counted Reference clock frequency, Maximum clock frequency variation (%).

[0103] Curve 1200 involves Figure 11The example is illustrated in timing diagram 1120, which shows the arrival target time for increasing the counted clock ticks. Graph 1200 illustrates the deviations of arrival target time curve 1214 for slow device 1124 and arrival target time curve 1216 for fast device 1126 from arrival target time curve 1212 defined for reference device 1122.

[0104] .

[0105] The slope of the arrival time curve 1212 defined for reference device 1122 represents the nominal or ideal trigger slope calculated or plotted using a nominal or reference clock frequency. In one example, the reference clock frequency corresponds to the frequency of the transmitter clock signal used by the BoM to control transmissions made via a mixed-mode serial bus.

[0106] Certain aspects of this disclosure can improve the accuracy and reliability of timing triggering managed by single-wire and / or two-wire slave devices coupled to a mixed-mode serial bus. In one aspect, the slave device can use a locally generated clock signal for timing triggering operation. The locally generated clock signal can be used when a reference clock signal is unavailable, including when no clock signal or embedded clock signal is received from the serial bus. In another aspect, a single-wire slave device can manage self-actuated timing by eliminating the need for a reference timing supplied by the bus, without hindering the operation of two-wire slave devices coupled to the same serial bus.

[0107] Certain aspects of this disclosure enable slave devices to adapt to and correct for differences in the slopes of their arrival-to-target time curves 1214 and 1216, in order to more closely match the slope of the nominal arrival-to-target time curve 1212 defined for reference device 1122. The slope of the nominal arrival-to-target time curve 1212 is calculated based on a reference clock. In an example of a mixed-mode serial bus operating according to the RFFE protocol, the reference clock corresponds to the transmitter clock that defines the data transmission rate on the serial bus.

[0108] For ideal operation, the slopes of target curves 1214 and 1216 should be equal to the slope of the nominal target curve 1212. In one example, a positive slope correction can be applied to the slope of the arrival time curve 1216 for the fast device 1126 (i.e., the slope increases). In another example, a negative slope correction can be applied to the slope of the arrival time curve 1214 for the slow device 1124 (i.e., the slope decreases).

[0109] According to certain aspects of this disclosure, a trigger slope correction factor can be provided to a slave device via message transmission and reception via a serial bus. The trigger slope correction factor can be transmitted in a separate message and can be provided independently of messages conveying trigger configuration or trigger timing information. The trigger slope correction factor can be applied according to one or more algorithms, at predefined intervals, and / or at certain points within the trigger timing period configured by the BoM or determined at the slave device.

[0110] Figure 13 This is a schematic representation of a single-wire slave device 1300 including an RFFE interface 1330 and trigger timing circuitry configurable according to certain aspects of this disclosure. The illustrated trigger timing circuitry is provided by way of example for the purpose of illustrating certain concepts disclosed herein. Other configurations of the components may be used to provide trigger timing circuitry operating according to certain aspects of this disclosure.

[0111] In the illustrated example, the trigger timing circuitry includes a controller 1310 configured to manage and implement self-actuation or timed triggering. The controller 1310 can be implemented using a processor, microcontroller, or finite state machine. In some implementations, the controller 1310 may be housed in processing circuitry that controls transmit and receive functions and communicates with the Board of Names (BoM) via a serial bus. In some cases, the controller 1310 may receive trigger configuration information and may load the trigger shadow register 1312 and / or the timed trigger counter 1306. In other implementations, the controller 1310 may receive signals indicating that the trigger shadow register 1312 and / or the timed trigger counter 1306 has been loaded. The controller 1310 may, in response to a command received from the BoM or after the trigger shadow register 1312 has been loaded, cause the timed trigger counter 1306 to begin counting based on timing information provided along with the received trigger configuration information.

[0112] The timer-triggered counter 1306 is clocked by a base clock signal 1320 derived from the local oscillator 1302. The clock generation circuit 1304 can be used to regulate, divide, or otherwise adjust the output of the local oscillator 1302 to derive the base clock signal 1320, a phase-shifted version of the base clock signal 1320, and / or one or more clock signals having a nominal frequency corresponding to the nominal frequency of the BoM transmitter clock signal or other reference signal.

[0113] Controller 1310 may provide one or more signals 1322, 1324, which may configure or adjust the operation of timer-triggered counter 1306. Timer-triggered counter 1306 may be implemented as an increment / decrement counter and may provide a count value 1326 as an output. Controller 1310 may be configured to monitor the count value 1326 and generate a trigger signal 1328 when the count value 1326 reaches a target value for actuating trigger 1308 associated with trigger element 1314. In some specific implementations, counter 1306 may directly generate trigger signal 1328 when, for example, the count value 1326 reaches zero or when counter 1306 overflows.

[0114] Controller 1310 may be coupled to a register or other storage device that maintains a trigger slope correction factor 1316, which can be used to adjust the slope of the arrival-to-target time curve characterizing the count rate of counter 1306 to more closely match the slope of the nominal arrival-to-target time curve defined for a reference device. In one example, trigger slope correction factor 1316 may be configured to adjust the frequency difference between the BoM transmitter clock signal or reference signal and the basic clock signal 1320 or another clock signal generated by clock generation circuitry 1304. In some examples, controller 1310 may be configured to modify the current count value 1326, causing counter 1306 to pause counting or otherwise modify the count rate based on a preloaded trigger slope correction factor 1316.

[0115] According to certain aspects of this disclosure, the Board of Management (BoM) in the host device can determine a trigger slope correction factor for multiple slave devices coupled to a serial bus. Each slave device can be configured to measure the duration of a measurement pulse transmitted by the BoM. In some embodiments, the slave device uses a counter to count clock ticks defined by an internally generated clock signal to measure the duration of the measurement pulse. In one example, each clock tick corresponds to the period of the internally generated clock signal. In another example, each clock tick corresponds to an edge of the internally generated clock signal. In the latter example, the counter can count the rising edge, falling edge, or both rising and falling edges of the internally generated clock signal. In one embodiment, the counter corresponds to... Figure 13 The trigger timing circuit illustrated in the figure has a timing trigger counter 1306, and the clock signal generated internally corresponds to the basic clock signal 1320 of the trigger timing circuit.

[0116] Figure 14 An example is illustrated according to certain aspects of this disclosure, wherein the trigger slope correction factor for a plurality of slave devices can be determined by the BoM and can be provided to the slave devices for timing trigger actuation.

[0117] Figure 14 The first timing diagram 1400 illustrates a slope estimation transaction addressing to one or more single-wire slave devices coupled to a serial bus. The serial bus can operate according to certain aspects of this disclosure. In the illustrated example, the transaction is a broadcast transaction and is initiated when the BoM sends SSC 1406 via a single line of the serial bus (here, designated SDATA 1402). Synchronization mode 1408 is sent after SSC 1406, followed by command 1410. This command is recognized as a slope estimation broadcast command by any active single-wire slave device coupled to the serial bus. In other examples, a directional slope estimation command may be addressed to a single slave device or a group address shared by multiple slave devices. After command 1410 has been sent, SDATA 1402 is in a low signaling state or driven to a low signaling state.

[0118] Typically, a measurement pulse (slope estimation pulse 1412) is sent within one or two BoM transmitter clock cycles after the transmission of command 1410 has been completed. The rising edge 1416 of the slope estimation pulse 1412 causes a counter to begin counting in each slave device that responded to command 1410. The counter can be configured to count clock ticks defined by an internally generated clock signal. In some implementations, the internally generated clock signal can be a base clock signal 1404 generated by the slave device, the frequency of which is a multiple of the BoM transmitter clock frequency. In some implementations, the internally generated clock signal has the same nominal frequency as the BoM transmitter clock. The falling edge 1418 of the slope estimation pulse 1412 causes the counter in each slave device to stop counting. The transaction can then be terminated using an end-of-frame signaling (EoF 1414). Each participating slave device maintains a copy of the final slope estimation count value output by its respective counter.

[0119] Figure 14 The second timing diagram 1420 illustrates the readback of the final slope estimate count value captured and maintained by one or more slave devices after a slope estimation transaction has been performed. The readback can be implemented using one or more transactions. The BoM sends SSC 1422 via SDATA 1402, followed by synchronization mode 1424. The BoM then sends a read command 1426 addressed to the slave device. Only one read command 1426 is shown in the illustrated example. The transmission of line turnaround signaling and additional synchronization modes is not explicitly shown. For example, after the read command is sent via SDATA 1402 and the slave device responds by signaling via SDATA 1402, line turnaround signaling and synchronization modes are sent.

[0120] In the illustrated example, each slave device receiving a read command for a readback of the final slope estimation count value captured during the slope estimation transaction responds to the read command by sending its final slope estimation count value. Therefore, payloads 1432, 1434, 1436, and 1438 are transmitted by the corresponding slave device via SDATA 1402. Each readback transaction is terminated by an end-of-frame signaling (EoF 1430).

[0121] The BoM or master device receiving the final slope estimate count value can calculate or estimate trigger slope correction factors, which can be used by the slave device reporting the final slope estimate count value. The BoM or master device can determine the trigger slope correction factor based on the difference between the BoM transmitter clock signal frequency and the frequency of the basic clock signal available to the slave device. In some specific implementations, the BoM or master device can calculate the trigger slope correction factor as the difference between the number of cycles of the BoM transmitter clock signal used to transmit the slope estimation pulse 1412 and the final slope estimate count value obtained by the slave device.

[0122] The trigger slope correction factor obtained according to certain aspects of this disclosure can be optimized or improved by counting the periods of a higher-frequency fundamental clock signal to measure the slope estimation pulse 1412. In some embodiments, a single-wire slave device generates an internal fundamental clock signal at a frequency four times (4x) that of the BoM transmitter clock signal to recover clock information from the Manchester-coded data signal. The 4x fundamental clock signal can be used to measure the slope estimation pulse 1412 with greater granularity and allows the trigger slope correction factor to be used over longer trigger timing intervals. In some embodiments, a counter can be configured to count the rising and falling edges of the 4x fundamental clock signal when the slope estimation pulse 1412 is measured. When the 4x fundamental clock signal is available and used at the slave device and / or when the slave device counts the rising and falling edges when measuring the slope estimation pulse 1412, the BoM or master device can employ a multiplier to obtain a reference clock tick (period or edge) for calculating the trigger slope correction factor.

[0123] In one example, a trigger slope correction factor can be obtained for the slope estimation pulse 1412, which has a duration of 256 cycles of the BoM transmitter clock signal, according to certain aspects of this disclosure. C T =256). In an ideal system, the slope estimation pulse 1412 is measured by the slave device as 256 cycles with a basic clock signal ( K T =256). Therefore, .when At that time, the trigger slope correction factor can be calculated.

[0124] Slave devices that generate an internal basic clock signal at a frequency higher than the BoM transmitter clock signal can report 260 cycles of the faster basic clock signal. K T The slope estimation pulse 1412 is measured at (=260), thus indicating the slope. The host or BoM can calculate a trigger slope correction factor of 260-256=4, which indicates that 4 clock cycles will be ignored during the 256-cycle countdown period to allow for recovery. .

[0125] Slave devices that generate an internal basic clock signal at a frequency lower than the BoM transmitter clock signal can report 250 cycles of the slower basic clock signal. K T The slope estimation pulse 1412 is measured at (=250) to indicate the slope. The host or BoM can calculate a trigger slope correction factor of 260-256=6, which indicates that 6 clock cycles will be added to the actual counted clock cycles during the 256-cycle countdown period.

[0126] Figure 15 This is a graph 1500 illustrating the application of the trigger slope correction factor calculated according to certain aspects of this disclosure. Graph 1500 depicts the relationship between the elapsed time and the number of clock cycles counted by different slave devices. The first arrival time curve 1502 uses... This is characterized and related to the slave device that measures the slope estimation pulse 1412 using a basic clock signal with the same frequency as the BoM transmitter clock signal. The second arrival time curve 1504 uses... This is used to characterize and is related to the slave device that uses a fundamental clock signal with a frequency greater than the BoM transmitter clock signal to measure the slope estimation pulse 1412. The third arrival time curve 1506 uses... This is used to characterize and is related to the slave device that uses a basic clock signal with a frequency lower than that of the BoM transmitter clock signal to measure the slope estimation pulse 1412.

[0127] In some implementations, a trigger slope correction factor can be applied within a slope correction application region 1508, which can be measured in clock cycles. In the illustrated example, when 256 clock cycles have been counted from the total programmed count 512, the trigger slope correction factor can be applied at times 1514 and 1516. Applying the trigger slope correction factor at the midpoint of the count minimizes the maximum trigger window. In other examples, the trigger slope correction factor can be applied in multiple steps throughout the entire slope correction application region 1508. For example, applying the trigger slope correction factor after every 256 clock cycles simplifies the logic required to increment or decrement the trigger slope correction factor value. When the count is 256 or a multiple of 256, each of the eight least significant bits of the counter has a value of zero. Therefore, a non-zero trigger slope correction factor can be loaded into the eight least significant bits of the counter to compensate for the slow basic clock signal. The trigger slope correction factor for a fast basic clock signal can be applied by suppressing the clock signal supplied to the counter for one or more clock ticks.

[0128] According to certain aspects of this disclosure, the number of opportunities to apply the trigger slope correction factor can be increased by using a base clock signal whose frequency is a multiple of the frequency of the BoM transmitter clock signal. In one example, twice the opportunity to apply the trigger slope correction factor is available when it is applied after every 256 clock cycles and when the frequency of the base clock signal is twice the frequency of the BoM transmitter clock signal. In another example, four times the opportunity to apply the trigger slope correction factor is available when it is applied after every 256 clock cycles and when the frequency of the base clock signal is four times the frequency of the BoM transmitter clock signal. The latter can be implemented in a single-wire slave device that has already generated its base clock signal, the frequency of which is four times the frequency of the BoM transmitter clock signal.

[0129] When the counter in the slave device measures the slope estimation pulse 1412 by counting the period or edge of a higher-frequency basic clock signal, the BoM or master device can take advantage of the availability of the higher-frequency basic clock signal. The BoM or master device can then use the period count corresponding to the increased frequency to calculate the trigger slope correction factor.

[0130] Certain aspects of this disclosure relate to a protocol for writing trigger configuration information to a slave device configured to manage timed trigger actuation. In one example, the trigger configuration information includes information to be written to the trigger shadow register of the slave device. In another example, the trigger configuration information includes timing information to be written to the timed trigger counter of the slave device. In yet another example, the trigger configuration information includes information to start the counter counting down to the trigger event.

[0131] Figure 16 This includes a timing diagram 1600 illustrating the writing of trigger configuration information according to the standard RFFE protocol. The BoM can use one or more transactions to write the trigger configuration information to... N A collection of slave devices. In the illustrated example, the BoM uses SDATA 1602 to link the various commands and payloads 16041-1604. N Send to the configured sequence N A slave device is configured to trigger an action at a common time point 1606. This is based on the standard RFFE protocol. N Each of the slave devices in the slave device is responsible for completing the corresponding command and payload 16041-1604. N The reception time defined as 16081-1608 N The countdown begins at the location configured. The BoM is required to calculate the countdown for its configuration. N Each slave device in the slave device has its own countdown value, and depends on the payload sequence 16041-1604. N Successful writing ensures actuation triggering at the expected time point of 1606.

[0132] Based on certain aspects disclosed herein, each slave device in a slave device group can be configured to begin a countdown after all slave devices have been configured with timed trigger information. For example... Figure 16 As illustrated in timing diagram 1620, the BoM can use one or more transactions to write trigger configuration information to... N A collection of slave devices. In the illustrated example, the BoM uses SDATA 1622 to link the various commands and payloads 16241-1624. N Send to N A slave device is configured to trigger actuation at a common time point of 1606. No definition is required for writing the payload 16241-1624. N A specific sequence. According to the standard RFFE protocol, N Each of the slave devices, after completing the last command and payload 1604, NThe countdown begins at the target time point 1608 as defined by the transmission. The BoM can calculate the countdown based on the common countdown duration and the target time point 1608. N The countdown value for each slave device in the slave device group.

[0133] Examples of processing circuits and methods Figure 17 This is a diagram illustrating an example of a hardware implementation of device 1700. In some examples, device 1700 may perform one or more functions disclosed herein. According to various aspects of this disclosure, processing circuitry 1702 may be used to implement elements, any portion of elements, or any combination of elements as disclosed herein. Processing circuitry 1702 may include one or more processors 1704 controlled by some combination of hardware modules and software modules. Examples of processors 1704 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuitry, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors 1704 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 1716. One or more processors 1704 may be configured by a combination of software modules 1716 loaded during initialization and may be further configured by loading or unloading one or more software modules 1716 during operation.

[0134] In the illustrated example, processing circuitry 1702 can be implemented using a bus architecture, typically represented by bus 1710. Bus 1710 may include any number of interconnect buses and bridges, depending on the specific application of processing circuitry 1702 and overall design constraints. Bus 1710 links together various circuits including one or more processors 1704 and storage devices 1706. Storage device 1706 may include memory devices and mass storage devices, and may be referred to herein as computer-readable storage media and / or processor-readable storage media. Bus 1710 may also link various other circuits, such as timing sources, timers, peripheral devices, voltage regulators, and power management circuitry. ƒ 1708 provides an interface between bus 1710 and one or more transceivers 1712a, 1712b. Transceivers 1712a, 1712b may be provided for each networking technology supported by the processing circuitry. In some cases, multiple networking technologies may share some or all of the circuitry or processing modules found in transceivers 1712a, 1712b. Each transceiver 1712a, 1712b provides components for communicating with various other devices via a transmission medium. In one example, transceiver 1712a may be used to couple device 1700 to a multi-wire bus. In another example, transceiver 1712b may be used to connect device 1700 to a radio access network. Depending on the nature of device 1700, a user interface 1718 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and this user interface may be communicatively coupled to bus 1710, either directly or via bus interface 1708.

[0135] Processor 1704 may be responsible for managing bus 1710 and for general processing, which may include executing software stored in a processor-readable storage medium that may include illustrated storage device 1706. In this regard, processing circuitry 1702 (including processor 1704) may be used to implement any of the methods, functions, and techniques disclosed herein. Storage device 1706 may be used to store data manipulated by processor 1704 during software execution, and the software may be configured to implement any of the methods disclosed herein.

[0136] One or more processors 1704 in processing circuitry 1702 can execute software. Software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or other names. Software may reside in a computer-readable form in storage device 1706 or on an external processor-readable storage medium. External processor-readable storage media and / or storage device 1706 may include non-transitory processor-readable storage media. Non-transitory processor-readable storage media include, for example, magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical disks (e.g., compact discs (CDs) or digital versatile discs (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or flash disks), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable media for storing software and / or instructions that can be accessed and read by a computer. The processor-readable storage medium and / or storage device 1706 may also include, for example, a carrier wave, a transmit line, and any other suitable media for transmitting software and / or instructions that can be accessed and read by a computer. The processor-readable storage medium and / or storage device 1706 may reside in processing circuitry 1702, in processor 1704, outside of processing circuitry 1702, or distributed across multiple entities including processing circuitry 1702. The processor-readable storage medium and / or storage device 1706 may be embodied in a computer program product. As an example, a computer program product may include a processor-readable storage medium in packaging material. Those skilled in the art will recognize how best to achieve the functionality described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system as a whole.

[0137] Storage device 1706 can maintain and / or organize software within loadable code segments, modules, applications, programs, etc., which may be referred to herein as software module 1716. Each software module in software module 1716 may include instructions and data that, when installed or loaded onto processing circuitry 1702 and executed by one or more processors 1704, contribute to a runtime image 1714 controlling the operation of one or more processors 1704. Certain instructions, when executed, may cause processing circuitry 1702 to perform functions according to certain methods, algorithms, and processes described herein.

[0138] Some software modules in software module 1716 may be loaded during the initialization of processing circuitry 1702, and these software modules 1716 may configure processing circuitry 1702 to perform the various functions disclosed herein. For example, some software modules 1716 may configure the internal devices and / or logic circuitry 1722 of processor 1704, and may manage access to external devices such as transceivers 1712a, 1712b, bus interface 1708, user interface 1718, timers, math coprocessors, etc. Software module 1716 may include control programs and / or operating systems that interact with interrupt handlers and device drivers and control access to various resources provided by processing circuitry 1702. Resources may include memory, processing time, access to transceivers 1712a, 1712b, user interface 1718, etc.

[0139] One or more processors 1704 of the processing circuitry 1702 can be multifunctional, whereby some software modules in software module 1716 are loaded and configured to perform different functions or different instances of the same function. One or more processors 1704 may additionally be adapted to manage background tasks initiated in response to inputs, such as from user interface 1718, transceivers 1712a, 1712b, and device drivers. To support the execution of multiple functions, one or more processors 1704 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks to be served by one or more processors 1704 as needed or desired. In one example, the multitasking environment can be implemented using a time-sharing program 1720 that transfers control of the processors 1704 between different tasks, whereby each task returns control of the one or more processors 1704 to the time-sharing program 1720 upon completion of any incomplete operation and / or in response to inputs such as interrupts. When a task has control over one or more processors 1704, the processing circuitry is effectively dedicated to the purpose addressed by the function associated with the control task. The time-sharing program 1720 may include an operating system, a main loop for transferring control on a loop-based basis, functions for allocating control of one or more processors 1704 according to the priority of functions, and / or an interrupt-driven main loop for responding to external events by providing control of one or more processors 1704 to processing functions.

[0140] Processing circuitry 1702 may be configured to perform one or more of the functions disclosed herein. For example, processing circuitry 1702 may be configured to operate as a master device coupled to a serial bus. Processing circuitry 1702 may be configured to initiate a pulse on a line coupling processing circuitry 1702 to a slave device, present a high impedance to the line after initiating the pulse, and determine whether the slave device has prematurely terminated the pulse, thereby indicating a first encoded value. If the slave device has not terminated the pulse, processing circuitry 1702 may be configured to terminate the pulse after a duration sufficient to indicate a second encoded value. In one example, the first encoded value is assigned binary 1 and the second encoded value is assigned binary 0. In another example, the first encoded value is assigned binary 0 and the second encoded value is assigned binary 1. Processing circuitry 1702 may be configured to determine the encoded value or may employ a separate PWM decoder.

[0141] Figure 18 This is a flowchart 1800 illustrating a method for timing triggers, which can be performed by a slave receiving device coupled to a single-line (SDATA) of a mixed-mode or multi-mode serial bus. One or more single-line slave devices and one or more two-line slave devices can be coupled to a multi-mode serial bus. The master device can exchange Manchester-encoded data with the single-line slave devices. The master device can send Manchester-encoded data and commands to the single-line slave devices via the data lines of the multi-mode serial bus.

[0142] At box 1802, the receiving device can generate a basic clock signal. At box 1804, when receiving measurement pulses via the single-wire serial bus during the first transaction, the receiving device can use a counter to count the period or edges of the basic clock signal, the measurement pulse having a pulse duration defined by the number of clock cycles of the transmitter clock signal. At box 1806, the receiving device can use a correction value to adjust the counter's count value while the counter is timing a triggered actuation; this correction value represents the difference between the period or edges of the basic clock signal counted when receiving measurement pulses and the number of clock cycles of the transmitter clock signal defining the pulse duration.

[0143] In some implementations, the receiving device can receive Manchester-encoded commands via a single-wire serial bus. Upon receiving the Manchester-encoded command, the receiving device can receive measurement pulses. The Manchester-encoded command can indicate the need for measurement pulses. Manchester-encoded commands can be received within datagrams configured according to the RFFE protocol. The transmitter clock signal can be embedded within the Manchester-encoded command.

[0144] In some specific implementations, the frequency of the basic clock signal is a multiple of the frequency of the transmitter clock signal.

[0145] In some examples, adjusting the counter's count value includes increasing the counter's count value when the frequency of the base clock signal is less than the frequency of the transmitter clock signal. Adjusting the counter's count value may also include decreasing the counter's count value when the frequency of the base clock signal is greater than the frequency of the transmitter clock signal.

[0146] In some implementations, the receiving device may use trigger information received in a second transaction via a single-wire serial bus to configure the trigger shadow register, and use timing information received in the second transaction to configure the counter with an initial count value. The receiving device may be one of multiple receiving devices coupled to the single-wire serial bus. Each of the multiple receiving devices may be configured using trigger and timing information received in the second transaction. Each of the multiple receiving devices may be configured to initiate the timing of the corresponding trigger's actuation when the second transaction terminates.

[0147] In some implementations, the receiving device may adjust the counter's count value, including periodically adjusting the counter's count value using a correction value when the counter is timing a triggered actuation. Periodically adjusting the counter's count value may include adjusting the counter's count value periodically, determined by the frequency of a fundamental clock signal.

[0148] Figure 19 This is an illustration of an example of a hardware implementation of a device 1900 employing processing circuitry 1902. The processing circuitry typically has a controller or processor 1916 that may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuitry 1902 may be implemented using a bus architecture, typically represented by bus 1920. Bus 1920 may include any number of interconnect buses and bridges, depending on the specific application of processing circuitry 1902 and overall design constraints. Bus 1920 links together various circuits including one or more processors and / or hardware modules represented by controller or processor 1916, modules or circuits 1904, 1906, 1908, and 1910, and processor-readable storage medium 1918. One or more physical layer circuits and / or modules 1914 may be provided to support communication links implemented using multi-wire bus 1912, communication via antennas or antenna arrays 1922 (e.g., to a radio access network), etc. Bus 1920 can also link various other circuits, such as timing sources, peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will therefore not be described further.

[0149] Processor 1916 is responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1918. Processor-readable storage medium 1918 may include non-transitory storage. When executed by processor 1916, the software causes processing circuitry 1902 to perform various functions described herein and for any particular device. Processor-readable storage medium 1918 may be used to store data manipulated by processor 1916 during software execution. Processing circuitry 1902 also includes at least one of modules 1904, 1906, 1908, and 1910. Modules 1904, 1906, 1908, and 1910 may be software modules residing in / stored in processor-readable storage medium 1918 that run in processor 1916, one or more hardware modules coupled to processor 1916, or some combination thereof. Modules 1904, 1906, 1908, and 1910 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0150] In one configuration, device 1900 includes modules and / or circuitry 1904 adapted to monitor the activity, inactivity, and control signaling of a single-wire bus. Device 1900 also includes modules and / or circuitry 1906 adapted to generate one or more internal basic clock signals for decoding signals received via the single-wire bus, or to control the generation of said one or more internal basic clock signals. Device 1900 further includes modules and / or circuitry 1908 configured to manage counter operation during trigger timing operation. Device 1900 also includes modules and / or circuitry 1910 adapted to manage trigger configuration and actuation.

[0151] In one example, device 1900 includes: a clock generator circuit configured to generate a fundamental clock signal having a fundamental frequency; and a counter configured to count the period or edge of the fundamental clock signal when a measurement pulse is received via a single-wire serial bus during a first transaction. The measurement pulse has a pulse duration that can be defined by the number of clock cycles of the transmitter clock signal. Device 1900 also includes a controller configured to adjust the counter's count value using a correction value that represents the difference between the period or edge of the fundamental clock signal being counted when a measurement pulse is received and the number of clock cycles of the transmitter clock signal defining the pulse duration.

[0152] In some examples, a measurement pulse is received after receiving the associated Manchester-encoded command via a single-wire serial bus. The Manchester-encoded command can be received in a datagram configured according to the RFFE protocol. The transmitter clock signal can be embedded in the Manchester-encoded command. In one example, the frequency of the base clock signal is a multiple of the frequency of the transmitter clock signal.

[0153] In some examples, the controller is further configured to increment the counter value when the frequency of the base clock signal is less than the frequency of the transmitter clock signal. The controller may be further configured to decrement the counter value when the frequency of the base clock signal is greater than the frequency of the transmitter clock signal.

[0154] In some examples, the receiving device has a trigger shadow register, which is configured by trigger information received in a second transaction via a single-wire serial bus. A counter can be configured with an initial count value using timing information received in the second transaction. The receiving device can be one of multiple receiving devices coupled to the single-wire serial bus. Each of the multiple receiving devices can be configured by trigger and timing information received in the second transaction. Each of the multiple receiving devices can be configured to initiate the timing of the corresponding trigger's actuation when the second transaction terminates.

[0155] In some examples, the controller is further configured to periodically adjust the counter's count value using a correction value while the counter is timing the triggered actuation. The controller can adjust the counter's count value periodically, determined by the frequency of the fundamental clock signal.

[0156] The processor-readable storage medium 1918 stores code and data. This code can be executed by the processor 1916, a state machine, or a sequencer. When executed by the processor 1916, the code causes the processing circuitry 1902 to configure an oscillator or clock generator circuit to generate a basic clock signal; when receiving measurement pulses via a single-wire serial bus during the first transaction, the period or edge of the basic clock signal is counted using a counter of the receiving device, the measurement pulse having a pulse duration defined by the number of clock cycles of the transmitter clock signal; and when the counter is timing a triggered actuation, a correction value is used to adjust the counter's count value, representing the difference between the period or edge of the basic clock signal being counted while receiving measurement pulses and the number of clock cycles of the transmitter clock signal defining the pulse duration.

[0157] In some implementations, this code enables processing circuitry 1902 to receive Manchester-encoded commands via a single-wire serial bus and, upon receiving the Manchester-encoded commands, to receive measurement pulses. The Manchester-encoded commands can indicate the need for measurement pulses. Manchester-encoded commands can be received in datagrams configured according to the RFFE protocol. The transmitter clock signal can be embedded in the Manchester-encoded commands. In one example, the frequency of the base clock signal is a multiple of the frequency of the transmitter clock signal.

[0158] In some implementations, adjusting the counter's count value includes increasing the counter's count value when the frequency of the base clock signal is less than the frequency of the transmitter clock signal. Adjusting the counter's count value may also include decreasing the counter's count value when the frequency of the base clock signal is greater than the frequency of the transmitter clock signal.

[0159] In some implementations, the code causes processing circuitry 1902 to configure the trigger shadow register using trigger information received in a second transaction via a single-wire serial bus, and to configure the counter with an initial count value using timing information received in the second transaction. The receiving device can be one of a plurality of receiving devices coupled to the single-wire serial bus. Each of the plurality of receiving devices is configured by the trigger and timing information received in the second transaction. Each of the plurality of receiving devices can be configured to initiate the timing of the corresponding trigger's actuation when the second transaction terminates.

[0160] In some cases, adjusting the counter's count value involves periodically adjusting the counter's count value using a correction value when the counter is timing a triggered actuation. Periodically adjusting the counter's count value may include adjusting the counter's count value periodically, determined by the frequency of a fundamental clock signal.

[0161] Some specific implementation examples are described in the following numbered clauses: 1. A receiving device comprising: a clock generator circuit configured to generate a basic clock signal; a counter configured to count a period or edge of the basic clock signal when a measurement pulse is received via the single-wire serial bus during a first transaction, the measurement pulse having a pulse duration defined by the number of clock periods of a transmitter clock signal; and a controller configured to adjust the counter's count value using a correction value when the counter is timing a triggered actuation, the correction value representing the difference between the period or edge of the basic clock signal counted while receiving the measurement pulse and the number of clock periods of the transmitter clock signal defining the pulse duration.

[0162] 2. The receiving device according to Clause 1, wherein the measurement pulse is received after receiving the associated Manchester-encoded command via the single-wire serial bus, and wherein the Manchester-encoded command is received in a datagram configured according to the Radio Frequency Front-End (RFFE) protocol.

[0163] 3. The receiving device according to Clause 2, wherein the transmitter clock signal is embedded in the Manchester encoded command.

[0164] 4. The receiving device according to any one of clauses 1 to 3, wherein the frequency of the basic clock signal is a multiple of the frequency of the transmitter clock signal.

[0165] 5. The receiving device according to any one of clauses 1 to 4, wherein the controller is further configured to increment the count value of the counter when the frequency of the basic clock signal is less than the frequency of the transmitter clock signal.

[0166] 6. The receiving device according to any one of clauses 1 to 5, wherein the controller is further configured to decrease the count value of the counter when the frequency of the basic clock signal is greater than the frequency of the transmitter clock signal.

[0167] 7. The receiving device according to any one of Clauses 1 to 6, the receiving device further comprising: a trigger shadow register configured by trigger information received in a second transaction via the single-wire serial bus, wherein the counter is configured with an initial count value using timing information received in the second transaction.

[0168] 8. The receiving device according to Clause 7, wherein the receiving device is one of a plurality of receiving devices coupled to the single-wire serial bus, wherein each of the plurality of receiving devices is configured by trigger and timing information received in the second transaction, and wherein each of the plurality of receiving devices is configured to initiate a timing of the corresponding trigger when the second transaction terminates.

[0169] 9. The receiving device according to any one of clauses 1 to 8, wherein the controller is further configured to periodically adjust the count value of the counter using the correction value when the counter is timing the triggered actuation.

[0170] 10. The receiving device according to Clause 9, wherein the controller adjusts the count value of the counter with a periodicity determined by the frequency of the basic clock signal.

[0171] 11. A method for timing a trigger in a receiving device, the method comprising: generating a basic clock signal; counting a period or edge of the basic clock signal using a counter of the receiving device while receiving a measurement pulse via the single-wire serial bus during a first transaction, the measurement pulse having a pulse duration defined by the number of clock periods of a transmitter clock signal; and adjusting a count value of the counter using a correction value while the counter is timing the actuation of a trigger, the correction value representing the difference between the period or edge of the basic clock signal counted while receiving the measurement pulse and the number of clock periods of the transmitter clock signal defining the pulse duration.

[0172] 12. The method according to Clause 11, further comprising: receiving a Manchester-encoded command via the single-wire serial bus; and receiving the measurement pulse after receiving the Manchester-encoded command, wherein the Manchester-encoded command indicates that the measurement pulse is to be provided, and wherein the Manchester-encoded command is received in a datagram configured according to the Radio Frequency Front-End (RFFE) protocol.

[0173] 13. The method according to Clause 12, wherein the transmitter clock signal is embedded in the Manchester encoded command.

[0174] 14. The method according to any one of clauses 11 to 13, wherein the frequency of the basic clock signal is a multiple of the frequency of the transmitter clock signal.

[0175] 15. The method according to any one of clauses 11 to 14, wherein adjusting the count value of the counter comprises: increasing the count value of the counter when the frequency of the basic clock signal is less than the frequency of the transmitter clock signal.

[0176] 16. The method according to any one of clauses 11 to 15, wherein adjusting the count value of the counter comprises: decreasing the count value of the counter when the frequency of the basic clock signal is greater than the frequency of the transmitter clock signal.

[0177] 17. The method according to any one of clauses 11 to 16, the method further comprising: configuring a trigger shadow register using trigger information received in a second transaction via the single-wire serial bus; and configuring the counter with an initial count value using timing information received in the second transaction.

[0178] 18. The method according to Clause 17, wherein the receiving device is one of a plurality of receiving devices coupled to the single-wire serial bus, wherein each of the plurality of receiving devices is configured by trigger and timing information received in the second transaction, and wherein each of the plurality of receiving devices is configured to initiate a timing of a corresponding trigger when the second transaction terminates.

[0179] 19. The method according to any one of Clauses 11 to 18, wherein adjusting the count value of the counter comprises: periodically adjusting the count value of the counter using the correction value while the counter is timing the actuation of the trigger.

[0180] 20. The method according to Clause 19, wherein periodically adjusting the count value of the counter comprises: adjusting the count value of the counter with a period determined by the frequency of the basic clock signal.

[0181] 21. A system comprising: a host device coupled to a single-wire serial bus; and a plurality of receiving devices coupled to the single-wire serial bus, each of the plurality of receiving devices comprising: a clock generator circuit configured to generate a basic clock signal; and a counter configured to count a period or edge corresponding to the basic clock signal, wherein the host device is configured to: initiate a first transaction to be performed via the single-wire serial bus; transmit a broadcast command in the first transaction; and transmit a measurement pulse in the first transaction after the broadcast command, the measurement pulse having a clock cycle of a transmitter clock signal used by the host device. The number of periods defines the pulse duration; and the measurement duration of the measurement pulse is received from each of the plurality of receiving devices, wherein at least one receiving device is configured to measure the measurement pulse by using its counter to count the period or edge of its basic clock signal when the measurement pulse is transmitted via the single-wire serial bus, and wherein the at least one receiving device is further configured to adjust the count value of its counter using a correction value when the counter is timing a triggered actuation, the correction value representing the difference between the period or edge of the basic clock signal counted when the measurement pulse is received and the number of clock periods of the transmitter clock signal used by the host device.

[0182] 22. The system according to Clause 21, wherein the broadcast command sent in the first transaction is a Manchester-encoded command, and wherein the Manchester-encoded command is sent in a datagram configured according to the Radio Frequency Front-End (RFFE) protocol.

[0183] 23. The system according to Clause 22, wherein the transmitter clock signal is embedded in the Manchester-encoded command.

[0184] 24. The system according to any one of clauses 21 to 23, wherein the frequency of the basic clock signal is a multiple of the frequency of the transmitter clock signal.

[0185] 25. The system according to any one of clauses 21 to 24, wherein the at least one receiving device is further configured to increment the count value of the counter when the frequency of the basic clock signal is less than the frequency of the transmitter clock signal.

[0186] 26. The system according to any one of clauses 21 to 25, wherein the at least one receiving device is further configured to decrease the count value of the counter when the frequency of the basic clock signal is greater than the frequency of the transmitter clock signal.

[0187] 27. The system according to any one of clauses 21 to 26, wherein the at least one receiving device comprises: a trigger shadow register configured by trigger information received in a second transaction via the single-wire serial bus, wherein the counter is configured with an initial count value using timing information received in the second transaction.

[0188] 28. The system according to Clause 27, wherein each of the plurality of receiving devices is configured by triggering and timing information received in the second transaction, and wherein each of the plurality of receiving devices is configured to initiate a timing of the corresponding triggering when the second transaction terminates.

[0189] 29. The system according to any one of Clauses 21 to 28, wherein the at least one receiving device is further configured to use the correction value to periodically adjust the count value of the counter when the counter is timing the actuation of the triggered event.

[0190] 30. The system according to Clause 29, wherein the at least one receiving device adjusts the count value of the counter with a periodicity determined by the frequency of the basic clock signal.

[0191] It should be understood that the specific order or hierarchy of the steps in the disclosed process is an example of the exemplary method. It should be understood that the specific order or hierarchy of the steps in these processes can be rearranged according to design preferences. Furthermore, some steps can be combined or omitted. The appended method claims present elements of multiple steps in a sample order, but are not intended to limit one to the specific order or hierarchy presented.

[0192] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to limit them to the aspects shown herein, but should be given the full scope consistent with the claims, wherein references to elements in the singular form, unless specifically stated otherwise, are not intended to mean “one and only one,” but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. All structural and functional equivalents of elements throughout the various aspects described herein that are known to or will later be known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is explicitly stated in the claims. No claim element should be construed as a component plus a function unless that element is explicitly stated using the phrase “component for…”.

Claims

1. A receiving device, the receiving device comprising: A clock generator circuit configured to generate a basic clock signal; A counter configured to count the period or edge of the basic clock signal when a measurement pulse is received via the single-wire serial bus during a first transaction, the measurement pulse having a pulse duration defined by the number of clock cycles of the transmitter clock signal; as well as A controller configured to adjust the counter's count value using a correction value when the counter is timing a triggered actuation, the correction value representing the difference between the period or edge of the basic clock signal being counted while receiving the measurement pulse and the number of clock periods of the transmitter clock signal defining the pulse duration.

2. The receiving device of claim 1, wherein the measurement pulse is received after receiving the associated Manchester-encoded command via the single-wire serial bus, and wherein the Manchester-encoded command is received in a datagram configured according to the radio frequency front-end (RFFE) protocol.

3. The receiving device according to claim 2, wherein the transmitter clock signal is embedded in the Manchester encoding command.

4. The receiving device according to claim 1, wherein the frequency of the basic clock signal is a multiple of the frequency of the transmitter clock signal.

5. The receiving device of claim 1, wherein the controller is further configured to increment the count value of the counter when the frequency of the basic clock signal is less than the frequency of the transmitter clock signal.

6. The receiving device of claim 1, wherein the controller is further configured to decrease the count value of the counter when the frequency of the basic clock signal is greater than the frequency of the transmitter clock signal.

7. The receiving device according to claim 1, further comprising: A trigger shadow register is configured by trigger information received in a second transaction via the single-wire serial bus, wherein the counter is configured with an initial count value using timing information received in the second transaction.

8. The receiving device of claim 7, wherein the receiving device is one of a plurality of receiving devices coupled to the single-wire serial bus, wherein each of the plurality of receiving devices is configured by trigger and timing information received in the second transaction, and wherein each of the plurality of receiving devices is configured to initiate a timing of the corresponding trigger when the second transaction terminates.

9. The receiving device of claim 1, wherein the controller is further configured to use the correction value to periodically adjust the count value of the counter when the counter is timing the triggered actuation.

10. The receiving device of claim 9, wherein the controller adjusts the count value of the counter with a periodicity determined by the frequency of the basic clock signal.

11. A method for timing a trigger in a receiving device, the method comprising: Generate a basic clock signal; When a measurement pulse is received via the single-wire serial bus during the first transaction, the period or edge of the basic clock signal is counted using a counter of the receiving device, the measurement pulse having a pulse duration defined by the number of clock cycles of the transmitter clock signal; as well as When the counter is timing a triggered actuation, a correction value is used to adjust the counter's count value. The correction value represents the difference between the period or edge of the basic clock signal being counted when the measurement pulse is received and the number of clock periods of the transmitter clock signal that defines the pulse duration.

12. The method according to claim 11, further comprising: Manchester-encoded commands are received via the single-wire serial bus. as well as The measurement pulse is received after the Manchester encoding command is received, wherein the Manchester encoding command indicates that the measurement pulse should be provided, and wherein the Manchester encoding command is received in a datagram configured according to the Radio Frequency Front-End (RFFE) protocol.

13. The method of claim 12, wherein the transmitter clock signal is embedded in the Manchester encoded command.

14. The method of claim 11, wherein the frequency of the basic clock signal is a multiple of the frequency of the transmitter clock signal.

15. The method of claim 11, wherein adjusting the count value of the counter comprises: The counter increments its count value when the frequency of the basic clock signal is less than the frequency of the transmitter clock signal.

16. The method of claim 11, wherein adjusting the count value of the counter comprises: The counter value is decreased when the frequency of the basic clock signal is greater than the frequency of the transmitter clock signal.

17. The method of claim 11, further comprising: The trigger shadow register is configured using trigger information received in the second transaction via the single-wire serial bus; as well as The timing information received in the second transaction is used to configure the counter with an initial count value.

18. The method of claim 17, wherein the receiving device is one of a plurality of receiving devices coupled to the single-wire serial bus, wherein each of the plurality of receiving devices is configured by trigger and timing information received in the second transaction, and wherein each of the plurality of receiving devices is configured to initiate a timing of a corresponding trigger when the second transaction terminates.

19. The method of claim 11, wherein adjusting the count value of the counter comprises: The correction value is used to periodically adjust the counter's count value while the counter is timing the triggered actuation.

20. The method of claim 19, wherein periodically adjusting the count value of the counter comprises: The count value of the counter is adjusted by a periodicity determined by the frequency of the basic clock signal.

21. A system comprising: A host device, the host device being coupled to a single-wire serial bus; as well as Multiple receiving devices coupled to the single-wire serial bus, each of the multiple receiving devices comprising: A clock generator circuit, configured to generate a basic clock signal; and A counter, configured to count the period or edge of a corresponding basic clock signal. The host device is configured as follows: Initiate the first transaction to be performed via the single-wire serial bus; Send a broadcast command in the first transaction; Following the broadcast command, a measurement pulse is sent in the first transaction, the measurement pulse having a pulse duration defined by the number of clock cycles of the transmitter clock signal used by the host device; and The measurement duration of the measurement pulse is received from each of the plurality of receiving devices. At least one of the receiving devices is configured to measure the measurement pulse by using its counter to count the period or edge of its basic clock signal when the measurement pulse is transmitted via the single-wire serial bus, and The at least one receiving device is further configured to use a correction value to adjust the count value of its counter when the counter is timing the triggered actuation, the correction value representing the difference between the period or edge of the basic clock signal being counted when receiving the measurement pulse and the number of clock periods of the transmitter clock signal used by the host device.

22. The system of claim 21, wherein the broadcast command sent in the first transaction is a Manchester-encoded command, and wherein the Manchester-encoded command is sent in a datagram configured according to the Radio Frequency Front-End (RFFE) protocol.

23. The system of claim 22, wherein the transmitter clock signal is embedded in the Manchester encoded command.

24. The system of claim 21, wherein the frequency of the basic clock signal is a multiple of the frequency of the transmitter clock signal.

25. The system of claim 21, wherein the at least one receiving device is further configured to increment the count value of the counter when the frequency of the basic clock signal is less than the frequency of the transmitter clock signal.

26. The system of claim 21, wherein the at least one receiving device is further configured to decrease the count value of the counter when the frequency of the basic clock signal is greater than the frequency of the transmitter clock signal.

27. The system of claim 21, wherein the at least one receiving device comprises: A trigger shadow register is configured by trigger information received in a second transaction via the single-wire serial bus, wherein the counter is configured with an initial count value using timing information received in the second transaction.

28. The system of claim 27, wherein each of the plurality of receiving devices is configured by triggering and timing information received in the second transaction, and wherein each of the plurality of receiving devices is configured to initiate a timing of the corresponding triggering when the second transaction terminates.

29. The system of claim 21, wherein the at least one receiving device is further configured to use the correction value to periodically adjust the count value of the counter when the counter is timing the triggered actuation.

30. The system of claim 29, wherein the at least one receiving device adjusts the count value of the counter with a periodicity determined by the frequency of the basic clock signal.

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