Synchronization of electronic devices

Abstract

Embodiments of the present disclosure relate to synchronization of electronic devices. In one embodiment, a device includes a switching power supply configured to have a first operating mode synchronized by a first clock signal generated by a clock generator and a second asynchronous operating mode. The clock generator is configured such that upon transitioning from the second operating mode to the first operating mode, the first clock signal becomes equal to a signal having a most recent rising edge of the second clock signal and a third clock signal complementary to the second clock signal.

Description

[0001] Cross-references to related applications

[0002] This application is a translation of French patent application number FR 2100869 entitled “Synchronisationd 'undispositif éelectronique'” filed on January 29, 2021, and claims priority to it, which is incorporated herein by reference to the fullest extent permitted by law.

[0003] This application relates to co-pending U.S. Patent Application No. 17 / 571,741 entitled “Synchronization of an electronic device”, filed on the same date as this application and associated with Attorney General’s File No. ST-20-RO-0222US01, which claims priority to French Patent Application No. FR 2100872 entitled “Synchronisationd 'undispartitif électronique'”, filed January 29, 2021, which is incorporated herein by reference. Technical Field

[0004] This disclosure generally relates to electronic systems and methods, and in certain embodiments relates to the synchronization of electronic devices. Background Technology

[0005] In a switching converter, the converter's power supply voltage is chopped by switching to achieve an energy accumulation phase in the components, including inductive and capacitive elements, and a recovery phase of the energy accumulation in the components by connecting a load to the converter output.

[0006] To enable various operational phases of the converter, the switching converter includes, for example, circuitry for generating a clock signal. The clock signal is, for example, a signal that periodically varies between high and low levels, corresponding respectively to the high and low states of a binary signal. Summary of the Invention

[0007] Some embodiments relate to the synchronization of electronic devices with clock signals. Some embodiments relate to power supply circuits including at least one switching power supply.

[0008] One embodiment provides an apparatus including: a switching power supply configured to have a first operating mode and a second asynchronous operating mode synchronized by a first clock signal generated by a first clock signal generation circuit, wherein the first generation circuit is configured to, upon transitioning from the second operating mode to the first operating mode, make the first signal equal to the signal having the closest rising edge among the second clock signal and a third clock signal, the third clock signal being complementary to the second clock signal.

[0009] Another embodiment provides a method for controlling a device, the device including a switching power supply configured to have a first operating mode and a second asynchronous operating mode synchronized by a first clock signal generated by a first clock signal generation circuit, wherein when switching from the second operating mode to the first operating mode, the first signal becomes equal to the signal having the closest rising edge among the second clock signal and a third clock signal, the third clock signal being complementary to the second clock signal.

[0010] According to one embodiment, the device includes a first transistor and a second transistor connected in series between a node for applying a power supply voltage and a node for applying a reference voltage, the first transistor and the second transistor being connected to each other via internal nodes, and the first transistor and the second transistor being controlled by a second circuit for generating control signals for the first transistor and the second transistor.

[0011] According to one embodiment, the device includes a capacitor connected between an output node of the switching power supply and a node for applying a reference voltage, and the device also includes an inductor connected between an internal node and an output node.

[0012] According to one embodiment, in a first operating mode, the first transistor and the second transistor are configured to periodically alternate between on and off states.

[0013] According to one embodiment, in the second operating mode, the second transistor is configured to be in a turned-off state, and the first transistor is configured to be turned off when the voltage on the output node is less than a set voltage.

[0014] According to one embodiment, the device is configured to generate a fourth signal having a first value during a first operating mode and a second value during a second operating mode.

[0015] According to one embodiment, the first clock signal generation circuit includes a third selection circuit configured to receive the second clock signal and the third clock signal as inputs and having a control input connected to the output of a D flip-flop, the flip-flop being configured to receive the second clock signal at a data input and the fourth signal at a clock input.

[0016] According to one embodiment, the first clock signal generation circuit includes a fourth circuit configured to provide a second clock signal at its output, which is connected to one of the inputs of a third selection circuit via an inverter circuit.

[0017] According to one embodiment, the device includes a comparator that compares the voltage of an internal node with a reference voltage, and a fourth signal having a second value when the comparator determines that the voltage on the internal node is lower than the reference voltage.

[0018] Another embodiment provides an apparatus including a switching power supply configured to have a first operating mode and a second asynchronous operating mode synchronized by a first clock signal generated by a first clock signal generation circuit, wherein the first generation circuit is configured such that the first signal is maintained at a constant value during the second operating mode.

[0019] Another embodiment provides a method for controlling a device, the device including a switching power supply configured to have a first operating mode synchronized by a first clock signal generated by a first clock signal generation circuit and a second asynchronous operating mode, wherein the first generation circuit maintains the first signal at a constant value during the second operating mode.

[0020] According to one embodiment, the device includes a first transistor and a second transistor connected in series between a node for applying a first power supply voltage and a node for applying a second reference voltage, the first transistor and the second transistor being connected to each other via internal nodes, and the first transistor and the second transistor being controlled by a second circuit for generating control signals for the first transistor and the second transistor.

[0021] According to one embodiment, the device includes a first capacitor connected between an output node of the switching power supply and a node for applying a second reference voltage, and the first capacitor includes an inductor connected between an internal node and an output node.

[0022] According to one embodiment, in a first operating mode, the first transistor and the second transistor are configured to periodically alternate between on and off states.

[0023] According to one embodiment, in a second operating mode, when the third voltage on the output node is less than the fourth setpoint voltage, the second transistor is configured to be off and the first transistor is configured to be off.

[0024] According to one embodiment, the device is configured to generate a fourth signal having a first value during a first operating mode and a second value during a second operating mode.

[0025] According to one embodiment, the first circuit includes: a first current source connected in series with a second capacitor between a first power supply voltage application node and a second reference voltage application node; a first switch connected in parallel with the first capacitor; a second current source connected in series with the second switch and a third capacitor between the first power supply voltage application node and the second reference voltage application node; and a third switch connected in parallel with a component including the third capacitor and the second switch.

[0026] According to one embodiment, the second switch is controlled by a fourth signal.

[0027] According to one embodiment, the first switch and the third switch are configured to be in an ON state during the second operating mode and in a relative state during the first operating mode.

[0028] According to one embodiment, the first switch and the third switch are configured to receive substantially equal control signals during a second operating mode and complementary control signals during a first operating mode.

[0029] According to one embodiment, the second switch and the third capacitor are connected via an intermediate node, which is connected to the fifth voltage application node via a fourth switch.

[0030] According to one embodiment, the fifth voltage is greater than or equal to the fourth setpoint voltage.

[0031] According to one embodiment, the fourth switch is configured to be controlled by a signal complementary to the fourth signal. Attached Figure Description

[0032] The foregoing features and advantages, as well as other features and advantages, will be set forth in the following detailed description of embodiments by way of illustration rather than limitation, with reference to the accompanying drawings, in which:

[0033] Figure 1 An embodiment of an electronic device is shown.

[0034] Figure 2 This is a set of timing diagrams illustrating the operation of an embodiment of a circuit used to generate clock signals.

[0035] Figure 3 An embodiment of a circuit for generating a clock signal is schematically shown, which operates in... Figure 2 As described in the text.

[0036] Figure 4 This means that the explanation includes Figure 3 Implementation examples Figure 1 A set of timing diagrams for the operation of the device.

[0037] Figure 5This is a set of timing diagrams illustrating the operation of another embodiment of a circuit used to generate clock signals.

[0038] Figure 6 The operation is illustrated schematically. Figure 5 An embodiment of the clock signal generation circuit described herein; and

[0039] Figure 7 This means that the explanation includes Figure 6 Implementation examples Figure 1 A set of timing diagrams for the operation of the device. Detailed Implementation

[0040] In the various figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features in various embodiments may be represented by the same reference numerals and may have the same structure, dimensions, and material properties.

[0041] For clarity, only the operations and elements that can be used to understand the embodiments described herein are described in detail.

[0042] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled through one or more other elements.

[0043] In the following description, unless otherwise stated, when referring to absolute position qualifiers such as “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or relative position qualifiers such as “above,” “below,” “higher,” “lower,” etc., or orientation qualifiers such as “horizontal,” “vertical,” etc., the orientation shown in the figure is used.

[0044] Unless otherwise stated, the expressions “about,” “approximately,” “basically,” and “in the order of” indicate within 10%, preferably within 5%.

[0045] Figure 1 An embodiment of an electronic device 10 is shown. Device 10 is a voltage converter. In this example, converter 10 is a DC / DC converter of the switch-mode power supply type, which converts a DC power supply voltage into a DC output voltage.

[0046] Converter 10 is configured to provide a DC output voltage VOUT. The converter includes an output node 12, at which the voltage VOUT is available.

[0047] A DC power supply voltage VDD is supplied to converter 10. Converter 10 is then connected between a first conductive rail or node 14 connected to voltage VDD and a second conductive rail or node 16 connected to a reference potential GND (e.g., ground).

[0048] Converter 10 is configured to provide voltage VOUT at a value substantially equal to the setpoint value. For this purpose, converter 10 receives a DC setpoint voltage VREF at input node 18, for example, with reference to the GND potential, the value of which is shown as the setpoint value of voltage VOUT, preferably equal to the setpoint value of voltage VOUT. In this example, voltages VOUT, VDD, and VREF are positive.

[0049] In this example, converter 10 is a step-down or "buck" converter, meaning the voltage VOUT setpoint is less than the voltage VDD setpoint. In other words, the value of voltage VOUT is lower than the value of voltage VDD. Some embodiments can be implemented in other types of converters, such as boost or buck-boost converters.

[0050] The converter 10 includes a first MOS ("metal-oxide-semiconductor") transistor 20, preferably a PMOS (P-channel MOS transistor). The MOS transistor 20 is connected between rail 14 and an internal node 22 to which a voltage VLX is applied. In other words, a first conductive terminal (e.g., its source) of the transistor 20 is connected to rail 14, while a second conductive terminal (e.g., its drain) of the transistor 20 is connected to node 22.

[0051] The converter 10 also includes a second MOS transistor 24, preferably an NMOS transistor (N-channel MOS transistor). Transistor 24 is connected between node 22 and rail 16. In other words, a first conductive terminal (e.g., its source) of transistor 24 is connected to rail 16, while a second conductive terminal (e.g., its drain) of transistor 24 is connected to node 22.

[0052] Therefore, transistors 20 and 24 are connected in series between rails 14 and 16, and are connected to each other at internal node 22.

[0053] The converter 10 includes an inductive element or inductor 26. Inductor 26 is connected between node 22 and node 12.

[0054] The converter 10 includes an output capacitor 30 connected between node 12 and track 16. As an example, this capacitor 30 is in the range of 2.2 μF to 20 μF or greater. This output capacitor acts as a filter. In other words, the output capacitor 30 of the converter smooths the current present at node 12 and stores the energy supplied to node 12 by the converter.

[0055] During operation, a load (not shown) is connected between node 12 and rail 16 to be powered by voltage VOUT.

[0056] The converter 10 includes a control circuit 28. The circuit 28 is configured to control the operation of the converter 10 to, for example, adjust the voltage VOUT such that its value is equal to the setpoint value VREF.

[0057] The converter 10 includes two operating modes: synchronous operating mode and asynchronous operating mode.

[0058] The first operating mode is referred to as "Continuous On-Mode" (CCM), such as pulse width modulation (PWM) or pulse frequency modulation (PFM) type, in which each operating cycle of the converter includes an energy accumulation phase in inductor 26 and capacitor 30, followed by an energy recovery phase to the load connected to the converter. During the energy accumulation phase, the current flowing through inductor 26 increases. During the energy recovery phase, the current flowing through inductor 26 decreases. This operating mode is a synchronous mode, synchronized by, for example, a binary clock signal CLK with a frequency of 2.4 MHz. This operating mode is considered, for example, the normal operating mode of the converter.

[0059] In some embodiments, the signal CLK is a periodic signal such that it has a high value during a portion of the signal period, such as half of the signal CLK period, and a low value during the remainder of the period, such as the other half of the signal CLK period. The signal CLK has a duty cycle that is, for example, substantially equal to, for example, 50%.

[0060] The second operating mode is called "Pulse Skip" (PSK) mode. In this mode, when the output voltage VOUT is lower than a reference voltage, such as the setpoint voltage VREF, transistor 24 remains off, while transistor 20 is on. Therefore, an energy accumulation phase is achieved when the output voltage is lower than the setpoint voltage VREF. This operating mode is implemented, for example, when the current drawn from the load is low. This is an asynchronous operating mode.

[0061] Control circuit 28 includes circuitry 32, such as a state machine, that generates control signals for transistors 20 and 24. Therefore, circuitry 32 includes an output coupled to (preferably connected to) a control terminal of transistor 20, at which control signals for transistor 20 are provided. Circuitry 32 also includes an output coupled to (preferably connected to) a control terminal of transistor 24, at which control signals for transistor 24 are provided.

[0062] Circuit 32 also includes an input connected to control circuit 34 for a first operating mode, in which circuit 32 receives a PWM signal based on the difference between the output voltage VOUT and the setpoint voltage VREF, thereby determining the amplitude or frequency of the energy accumulation or energy recovery phase in the first operating mode. Therefore, the PWM signal is used by circuit 32 in the first operating mode and is not used, for example, during a second operating mode.

[0063] Circuit 34 includes, for example, a comparator 36 configured to compare an output voltage VOUT with a setpoint voltage VREF. Comparator 36 includes an input (preferably non-inverting) coupled (preferably connected) to the voltage application node 18 VREF. Comparator 36 also includes an input (preferably inverting) coupled (preferably connected) to node 12. Comparator 36 includes an output providing a signal representing the difference between the voltage VOUT and the setpoint voltage VREF.

[0064] Circuit 34 includes another comparator 38. Comparator 38 includes an input, preferably a non-inverting input, coupled to, and preferably connected to, the output of comparator 36. Comparator 38 also includes another input, preferably an inverting input, coupled to, and preferably connected to, the voltage ramp application node VRAMP. Comparator 38 includes an output that provides a PWM signal. The output of the comparator is coupled to, and preferably connected to, one of the inputs of circuit 32.

[0065] Circuit 32 also includes an input connected to control circuitry 40 for a second operating mode, in which circuit 32 receives signal PSK based on the difference between the output voltage VOUT and the setpoint voltage VREF, thereby determining the timing of energy accumulation in the second operating mode. In other words, for a first value of signal PSK obtained when the output voltage is below the setpoint voltage VREF, transistor 20 is in an on state to allow capacitor 30 to be charged. For a second value of signal PSK, transistor 20 is in an off state, and transistor 24 is preferably kept off during the second operating mode. Therefore, signal PSK is used by circuit 32 in the second operating mode and, for example, is not used during the first operating mode.

[0066] Circuit 40 includes, for example, a comparator 42 configured to compare an output voltage VOUT with a setpoint voltage VREF. Comparator 42 includes an input (preferably inverting) coupled to (preferably connected to) the voltage application node 18 VREF. Comparator 42 also includes an input coupled to, preferably connected to, node 12, preferably non-inverting. Comparator 42 includes an output providing a signal representing the difference between the voltage VOUT and the setpoint voltage VREF.

[0067] Circuit 40 includes another comparator 44. Comparator 44 includes an input (preferably non-inverting) coupled to (preferably connected to) a voltage ramp application node (e.g., ramp VRAMP). Comparator 44 also includes another input, preferably inverting, coupled to, and preferably connected to, a setpoint voltage application node 18 VREF. Comparator 44 includes a control input, which is preferably connected to the output of comparator 42. Comparator 44 includes an output that provides a signal PSK for the value of the output signal of comparator 42. The output of the comparator is coupled to, and preferably connected to, one of the inputs of circuit 32.

[0068] Therefore, when converter 10 is in the first operating mode, circuit 32 considers the PWM signal to determine the control signals for transistors 20 and 24, but ignores the PSK signal. When converter 10 is in the second operating mode, circuit 32 considers the PSK signal to determine the control signals for transistors 20 and 24, but ignores the PWM signal.

[0069] Circuit 28 also includes a comparator 46. Comparator 46 includes a first input (preferably non-inverting input) coupled to (preferably connected to) the voltage application node GND 16 and a second input (preferably inverting input) coupled to (preferably connected to) node 22. Comparator 46 includes an output, preferably connected to circuit 32, which provides a signal representing the difference between the voltage VLX at node 22 and the voltage at node 16. In other words, comparator 46 provides circuit 32 with a signal representing the sign of voltage VLX. If the converter operates in a first operating mode and the comparator determines that voltage VLX is less than voltage GND, circuit 32 causes the converter to enter a second operating mode.

[0070] Circuit 28 also includes circuit 48 for generating a clock signal CLK. Therefore, circuit 28 includes an output coupled to, and preferably connected to, the circuit 32 that provides the signal CLK.

[0071] Circuit 48 includes an input coupled to (preferably connected to) circuit 32, on which a signal MODE representing the operating mode of the converter is provided. For example, when the converter 10 operates in a first operating mode, the signal MODE takes a first value, and when the converter 10 operates in a second operating mode, the signal MODE takes a second value. Therefore, when the converter changes from the first operating mode to the second operating mode, i.e., when comparator 46 determines that the voltage VLX is lower than the voltage GND, the signal MODE exhibits the second value. For example, when the current drawn by the load increases significantly, the signal MODE changes to the first value.

[0072] When the converter switches from the second operating mode to the first operating mode, it switches from asynchronous mode to synchronous mode. Circuit 48, and in particular circuit 32, must be resynchronized. Circuit 32 is synchronized with the rising or falling edge of the clock signal CLK, preferably with the rising or falling edge of the clock signal CLK. During the transition to the first operating mode, there may be a time period between the change in the value of the signal MODE and the next rising edge of the clock signal, during which a large amount of energy is drawn by the load, and the transistor 20 connecting the power supply voltage application node and node 22 is in the off state. Therefore, capacitor 30 discharges rapidly during this time period, which may result in a significant drop in the power supply voltage to the load.

[0073] Figure 2 , Figure 3 and Figure 4 An embodiment of a circuit for generating a clock signal based on the signal MODE and therefore on the operating mode of the converter is shown.

[0074] Figure 2 This is a set of timing diagrams illustrating the operation of one embodiment of the circuit used to generate clock signal 48. In this embodiment, circuit 48 is configured to provide one of a binary clock signal CLK1 and a clock signal / CLK1 complementary to the first clock signal, having the closest rising edge, during the transition from a second asynchronous operation mode to a first synchronous operation mode.

[0075] Figure 2 The timing diagram includes a timing diagram representing, for example, a time-dependent clock signal CLK1 generated by an oscillator included in circuit 48, a timing diagram representing a time-dependent complementary clock signal / CLK1, and a timing diagram representing a time-dependent signal MODE, thereby illustrating the operating modes of the converter.

[0076] Figure 2 Four different and independent cases are shown for switching from the second operating mode to the first operating mode.

[0077] exist Figure 2In the example, the first value of the signal MODE corresponding to the first operating mode, i.e., the synchronous operating mode, is a high value, while the second value of the signal MODE corresponding to the second operating mode, i.e., the asynchronous operating mode, is a low value.

[0078] In the first case, the transition from the second operating mode to the first operating mode is time T1. At time T1, the signal MODE changes from a low value to a high value. Furthermore, at time T1, the signal CLK1 has a low value while its complementary signal / CLK1 has a high value. The duration between time T1 and the most recent rising edge of signal CLK1 is duration D1, while the duration between time T1 and the most recent rising edge of the complementary signal / CLK1 is duration D1'. Duration D1 is shorter than duration D1'. Therefore, the clock signal CLK provided by circuit 48 to circuit 32 and synchronized with the converter is signal CLK1.

[0079] In the second case, the transition from the second operating mode to the first operating mode occurs at time T2. At time T2, the signal MODE changes from a low value to a high value. Furthermore, at time T2, signal CLK1 has a high value, while its complementary signal / CLK1 has a low value. The duration between time T2 and the most recent rising edge of signal CLK1 is duration D2', while the duration between time T2 and the most recent rising edge of the complementary signal / CLK1 is duration D2. Duration D2 is shorter than duration D2'. Therefore, the clock signal CLK provided by circuit 48 to circuit 32 and synchronized with the converter is the complementary signal of signal CLK1.

[0080] In the third case, the transition from the second operating mode to the first operating mode is at time T3. At time T3, the MODE signal changes from a low value to a high value. Furthermore, time T3 essentially corresponds to the rising edge of signal CLK1 and the falling edge of its complementary signal / CLK1. The duration between time T3 and the next most recent rising edge of signal CLK1 is essentially equal to the duration D3' of one cycle of clock signal CLK1, while the duration between time T3 and the most recent rising edge of the complementary signal / CLK1 of signal CLK1 is the duration D3 corresponding to half a cycle of clock signal CLK1. Duration D3 is shorter than duration D3'. Therefore, the clock signal CLK provided by circuit 48 to circuit 32 and synchronized with the converter is the complementary signal / CLK1 of signal CLK1.

[0081] Similarly, in the fourth case, the transition from the second operating mode to the first operating mode is time T4. At time T4, the MODE signal changes from a low value to a high value. Furthermore, time T4 essentially corresponds to the falling edge of signal CLK1 and the rising edge of its complementary signal / CLK1. The duration between time T4 and the next most recent rising edge of signal CLK1 is essentially equal to half the period of clock signal CLK1, duration D4, and the duration between time T4 and the most recent rising edge of complementary signal / CLK1 of signal CLK1 corresponds to the duration D4' of one period of clock signal CLK1. Duration D4 is shorter than duration D4'. Therefore, the clock signal CLK provided by circuit 48 to circuit 32 and synchronized with the converter is signal CLK1.

[0082] During the transition from the second asynchronous operation mode to the first synchronous operation mode, if signal CLK1 has a low value, the most recent rising edge is the rising edge of signal CLK1, and if signal CLK1 has a high value, the most recent rising edge is the rising edge of signal / CLK1.

[0083] In the worst-case scenario, namely the third and fourth cases, the duration between the rising edge of the signal MODE (i.e., the transition between the second and first operating modes) and the next rising edge of the clock signal CLK (i.e., the duration of capacitor discharge) is equal to half a cycle of the clock signal.

[0084] Signal CLK1 can be provided directly to circuit 32. However, in the worst case, the duration between the rising edge of signal MODE and the next rising edge of clock signal CLK can be substantially equal to the entire cycle of signal CLK1. This is the case, for example, at time T3.

[0085] Figure 3 The diagram illustrates an example implementation of a circuit used to generate clock signal 48, which operates in... Figure 2 As described in the text.

[0086] Circuit 48 includes circuit 50 (OSC), such as an oscillator circuit, which generates a clock signal CLK1 at output 51. Signal CLK1 is periodic and has a constant period. Signal CLK1 preferably remains unchanged during the first and second operating modes of converter 10, and particularly preferably remains unchanged during transitions from the first operating mode to the second operating mode or vice versa.

[0087] Circuit 48 includes a selection circuit or multiplexer 52. Multiplexer 52 includes an input 53 for receiving signal CLK1. Therefore, input 53 is coupled to, and preferably connected to, output 51 of circuit 50, providing signal CLK1 at output 51 of circuit 50. Multiplexer 52 includes an input 55 for a complementary signal / CLK1 of the received signal CLK1. Input 55 is connected to output 51 via an inverter circuit 54 that generates the complementary signal of the input signal at the output. Circuit 54 includes an input coupled (preferably connected) to input 51 of multiplexer 52 and an output coupled (preferably connected) to input 55 of multiplexer 52.

[0088] Circuit 48 further includes a flip-flop 58, preferably a D flip-flop. Flip-flop 58 includes a data input D coupled (preferably connected) to node 51. The flip-flop also includes a clock signal input coupled to, preferably connected to, the signal MODE application node. Flip-flop 58 includes an output Q coupled to, preferably connected to, the control terminal of multiplexer 52.

[0089] Therefore, input D continuously receives the clock signal CLK1. During the transition from the second operating mode to the first operating mode, that is, when the signal MODE has a rising edge, the output Q presents the value of signal CLK1 at that moment.

[0090] If signal CLK1 has a low value, such as Figure 2 In the first case, the output Q is a low value, such as the binary value '0'. The multiplexer is configured to output the signal CLK1 received at input 53 when the control signal received at the control input has this low value.

[0091] Similarly, if signal CLK1 has a high value, such as Figure 2 In the second case, the output Q is a high value, such as the binary value '1'. The multiplexer is configured to output a signal complementary to the signal CLK1 received at input 55 when the control signal received at the control input has this high value.

[0092] Therefore, the multiplexer is configured to output signal CLK1 if signal CLK1 has a low value on the rising edge of signal MODE, and to output the complementary signal / CLK1 of signal CLK1 if signal CLK1 has a high value on the rising edge of signal MODE.

[0093] Figure 4 This means that the explanation includes Figure 3 Implementation examples Figure 1 A set of timing diagrams for the operation of the equipment. Specifically, Figure 4Includes a timing diagram showing the current (I):

[0094] The current drawn by the load is shown by curve 60;

[0095] As shown by curve 62, in Figures 1 to 3 The current flowing through inductor 26 in the embodiment; and

[0096] As shown by curve 64, in a similar manner... Figure 1 The current flowing through the inductor 26 in the converter 10 is equal to the signal CLK1 regardless of the operating mode.

[0097] Figure 4 Includes a timing diagram of the binary signals:

[0098] The signal CLK is illustrated by curve 66;

[0099] The signal CLK1 illustrated by curve 68; and

[0100] The signal MODE is shown in curve 70.

[0101] Figure 4 Including the timing diagram of the voltage (VOUT):

[0102] The figure shown by curve 72 Figures 1 to 3 The voltage VOUT in the embodiment; and

[0103] The curve 74 is illustrated with the figure. Figure 1 The voltage VOUT in the converter 10 is similar to that in the converter, and the signal CLK is the same as the signal CLK1 regardless of the operating mode.

[0104] At time T11, the load begins to draw a larger current than before time T11. In other words, at time T11, the current drawn by the load (curve 60) changes from a low value to a high value. The output voltage VOUT begins to decrease more than before time T11. At time T11, the converter is still in the same operating mode it was in before time T11, i.e., asynchronous operating mode (PSK). The signal MODE has a low value at time T11 and before time T11.

[0105] At time T13, following time T11, the signal MODE goes high, meaning the converter will switch to synchronous operation mode (PWM). This change is caused by the voltage VOUT shifting to a value lower than the voltage VREF at the end of the PSK cycle.

[0106] Before time T13, signal CLK is equal to signal CLK1. At time T13, signal CLK1 has a high value, so the nearest edge is the falling edge of signal CLK1, which is the rising edge of the complementary signal / CLK1. As mentioned above, signal CLK thus becomes equal to the complementary signal / CLK1 of signal CLK1.

[0107] The first rising edge of the signal CLK after time T13 occurs at time T15. From time T15 onwards, the average current flowing through inductor 26 increases, thereby charging capacitor 30 and supplying power to the load. The voltage VOUT, represented by curve 72, decreases less significantly, and then begins to increase when the current, represented by curve 62, reaches a sufficiently large value, charging the capacitor.

[0108] At time T17, the first rising edge of signal CLK1 occurs after time T13. With signal CLK remaining equal to signal CLK1, time T17 is the moment when the average current in the load begins to increase due to transistors 20 and 24, which then alternately switch between off and on states (mode PWM).

[0109] Starting from time T15 Figure 2 and Figure 3 The converter in this embodiment behaves similarly to the converter for signal CLK1 starting at time T17. However, time T17 occurs half a cycle after time T15 for signal CLK1. This delay results in… Figure 2 and Figure 3 In the case of the converter in this embodiment, the drop in voltage VOUT during the transition from asynchronous to synchronous operation mode is lower than in the case of a converter where signal CLK is signal CLK1. In fact, at time T19, and after times T15 and T17, the difference between curves 72 and 74 representing voltage VOUT in both cases is on the order of 5mV in this example, which corresponds to approximately 10% of the total voltage drop after time T11.

[0110] therefore, Figures 2 to 4 The advantage of this embodiment is that the maximum possible capacitor discharge duration is half a cycle of signal CLK1, that is, half the length when signal CLK1 is directly provided to circuit 32. Therefore, the drop in voltage VOUT during the transition from the second operating mode to the first operating mode is less than the drop when signal CLK1 is directly provided to circuit 32.

[0111] Figure 5 , Figure 6 and Figure 7Another embodiment of a circuit for generating a clock signal based on the signal MODE and therefore the operating mode of the converter is shown.

[0112] Figure 5 This is a set of timing diagrams illustrating the operation of another embodiment of the clock generation circuit 48.

[0113] Figure 5 This includes a timing diagram of the signal MODE based on time (t). Figure 5 It also includes a timing diagram of the clock signal CLK provided by circuit 48 to circuit 32 according to time (t).

[0114] Figure 5 express Figure 1 The converter operation consists of three stages. Specifically, Figure 5 This indicates two synchronous phases (PWM) separated by an asynchronous phase (PSK).

[0115] During the first synchronization phase, the signal CLK periodically alternates between high and low values. During the transition between the first synchronization phase and the asynchronous phase, that is, when the signal MODE changes from a high value to a low value, the signal CLK takes its low value, preferably a value that is essentially zero.

[0116] The transition between the asynchronous phase and the second synchronous phase, i.e., the moment when the signal MODE changes from a low value to a high value, corresponds to the rising edge of the signal CLK.

[0117] In other words, during asynchronous operation mode, the signal CLK is held at a constant value, preferably a low value, and during transition to synchronous mode, its periodicity is preferably restored by a rising edge.

[0118] Figure 6 This schematically illustrates its operation in Figure 5 An embodiment of the clock generation circuit 48 described herein.

[0119] Circuit 48 includes a current source 80, which is coupled in series with a capacitor 82, preferably connected between a power supply voltage application node (e.g., voltage VDD application node 14) and a reference voltage application node (e.g., voltage GND application node 16). Preferably, the source 80 includes one terminal coupled (preferably connected) to node 14 and another terminal coupled (preferably connected) to node 84. Preferably, the capacitor 82 includes one terminal coupled (preferably connected) to node 84 and another terminal coupled (preferably connected) to node 16.

[0120] Circuit 48 also includes another current source 86, which is series-coupled (preferably connected) to a switch 88 (e.g., a transistor) and a capacitor 90, located between a power supply voltage application node (e.g., voltage VDD application node 14) and a reference voltage application node (e.g., voltage GND application node 16). Preferably, source 86 includes a terminal coupled (preferably connected) to node 14 and another terminal coupled (preferably connected) to node 92. Preferably, the switch includes a terminal coupled (preferably connected) to node 92, such as a conductive terminal, and another terminal coupled (preferably connected) to node 94, such as a conductive terminal. Preferably, capacitor 90 includes a terminal coupled (preferably connected) to node 94 and another terminal coupled (preferably connected) to node 16.

[0121] Therefore, the assembly including source 80 and capacitor 82 is connected in parallel with the assembly including source 86, switch 88 and capacitor 90.

[0122] Furthermore, circuit 48 preferably includes a switch 96, such as a transistor, connected between node 94 and voltage application node VCH. More specifically, one terminal (e.g., a conductive terminal) of switch 96 is coupled (preferably connected) to node 94, while the other terminal (preferably a conductive terminal) is coupled (preferably connected) to voltage application node VCH. Voltage VCH is preferably greater than or equal to setpoint voltage VREF, for example, greater than or equal to 0.8V.

[0123] Transistors 88 and 96 are controlled by complementary signals. Therefore, when one transistor is off, the other is on. Preferably, one transistor is controlled by a signal MODE, and the other is controlled by a signal / MODE that is complementary to the MODE signal. Therefore, the control terminal of switch 88 is preferably coupled to (preferably connected to) the application node of signal MODE, and the control terminal of switch 96 is preferably coupled to (preferably connected to) the application node of signal / MODE.

[0124] Circuit 48 also includes a switch 98, such as a transistor, connected between nodes 84 and 14. More specifically, switch 98 includes a terminal coupled to (preferably connected to) node 84, such as a conductive terminal, and another terminal coupled to (preferably connected to) node 16, such as another conductive terminal. Therefore, switch 98 is connected in parallel with capacitor 82. Thus, switch 98 and source 80 are connected in series between nodes 14 and 16.

[0125] Similarly, circuit 48 includes a switch 100, such as a transistor, connected between nodes 92 and 14. More specifically, switch 100 includes a terminal (e.g., a conductive terminal) coupled (preferably connected) to node 92 and another terminal (e.g., another conductive terminal) coupled (preferably connected) to node 16. Therefore, switch 100 is connected in parallel with an assembly including capacitor 90 and switch 88. Thus, switch 100 and source 86 are connected in series between nodes 14 and 16.

[0126] During asynchronous operation, the control signals for transistors 98 and 100 are complementary. In other words, when transistor 98 is on, transistor 100 is off, and vice versa.

[0127] Circuit 48 includes comparator circuit 102, which is configured to compare the voltage at node 84 with a reference voltage (preferably a setpoint voltage VREF) and to compare the voltage at node 92 with a reference voltage (preferably the same voltage as the voltage at node 84 (preferably voltage VREF)).

[0128] Circuit 102 includes an input (preferably connected) to node 84 (preferably the inverting input of a comparator). Circuit 102 includes an input (preferably connected) to node 92 (preferably the inverting input of a comparator). Circuit 102 includes an input (preferably connected) to a reference voltage application node. Circuit 102 includes an output (preferably connected) to node 104, providing a signal S at node 104 representing a comparison between the voltage at node 84 and the reference voltage. Circuit 102 includes an output (preferably connected) to node 106, providing a signal R at node 106 representing a comparison between the voltage at node 92 and the reference voltage.

[0129] Circuit 102 is connected at its output to an RS flip-flop 108, for example, formed by NAND logic gates. More specifically, flip-flop 108 includes a first input (preferably connected) to node 104 (preferably a so-called "set" input) and a second input (preferably a "reset" input) connected to node 106. The flip-flop includes a first output referred to as "Q" and a second output referred to as "Q". The second output is the second output of the transistor 98. The first output provides the binary control signal P2 for the switch 98. Therefore, the first output of the flip-flop 108 is coupled (preferably connected) to the control terminal of the transistor 98. The second output provides a signal P1 that is complementary to the signal P2.

[0130] In some embodiments, signal P1 may be a clock signal CLK provided to circuit 32.

[0131] Circuit 48 also includes selection circuit 110. Circuit 110 receives signals P1 and P2 as inputs and provides a signal P for controlling switch 100 as an output. More specifically, one input of circuit 110 is coupled (preferably connected) to the "Q" output of flip-flop 108, and the other input of circuit 110 is coupled (preferably connected) to the "Q" output of flip-flop 108. "Output. The output of circuit 110 is coupled (preferably connected) to the control terminal of switch 100."

[0132] Circuit 110 also includes a control input for receiving a signal MODE. Circuit 110 is configured to output signal P1 if signal MODE has a first value (preferably a high value), and to output signal P2 if signal MODE has a low value.

[0133] Figure 7 The illustration includes Figure 6 Implementation examples Figure 1 A set of timing diagrams for the operation of the device.

[0134] Figure 7 Including the timing diagram of the current (I):

[0135] The current drawn by the load is represented by curve 115;

[0136] exist Figure 6 The current flowing through inductor 26 during operation of the embodiment is represented by curve 117; and

[0137] Flowing and Figure 1 The current in inductor 26 in a converter similar to the converter, wherein a periodic, unmodified clock signal is provided to circuit 32, as shown in curve 119.

[0138] Figure 7 Includes a timing diagram of the binary signals:

[0139] The clock signal CLK' provided to circuit 32 in the converter, corresponding to curve 119, is represented by curve 121;

[0140] The signal MODE' from the converter, corresponding to curve 119, is represented by curve 123;

[0141] exist Figure 6 In the embodiment, the clock signal CLK provided to circuit 32 is represented by curve 125; and

[0142] Figure 6 The signal MODE in the embodiment is represented by curve 127.

[0143] Figure 7This includes timing diagrams illustrating the voltages (V): voltage VREF, represented by curve 129; voltage at node 84, represented by curve 131; and voltage at node 92, represented by curve 133.

[0144] Figure 7 Includes timing diagrams illustrating binary signals:

[0145] Signal P1 is represented by curve 135;

[0146] Signal P, represented by curve 137; and

[0147] Signal P2 is represented by curve 139.

[0148] At time T21, the load begins to draw a larger current than it had before time T21. In other words, at time T21, the current drawn by the load (curve 115) changes from a low value to a high value. Time T21 occurs when the device is operating in asynchronous mode.

[0149] In asynchronous operation mode, corresponding to a low value of signal MODE, signal CLK remains at a constant value, which is low in this case.

[0150] The signal P2 controlling transistor 98 has a high value, keeping transistor 98 in the ON state. Therefore, node 84 is connected to node 16 through the ON transistor, and the voltage on node 84 (curve 131) is essentially equal to the voltage on node 16, i.e., 0V, while capacitor 82 discharges at node 16.

[0151] Furthermore, transistor 88 is in the off state while transistor 96 is in the on state; these transistors are controlled by signals MODE and / MODE, respectively. Therefore, transistors 88 and 96 are in a relative state. Thus, node 94 is connected to the voltage application node VCH via a conductive transistor. In other words, the voltage across capacitor 90 is voltage VCH.

[0152] Since signal MODE has a low value, signal P takes the value of signal P2, which is a high value. Therefore, transistor 100 is in the ON state, and the capacitor discharges at node 16. The voltage at node 92 (curve 133) is essentially equal to the voltage at node 16, which is 0V.

[0153] Therefore, in asynchronous mode, the control signals for transistors 98 and 100 turn the transistors on, and preferably, the control signals for transistors 98 and 100 are substantially equal.

[0154] At time T22, the voltage VLX at node 22 ( Figure 7(Not shown) becomes lower than the voltage on node 16, for example, below 0V. Then, the value of signal MODE changes from low to high.

[0155] Therefore, at time T22, signal P takes the value of signal P1, which is complementary to signal P2, i.e., a low value. Then transistor 100 is in the off state. Furthermore, transistor 88 becomes on, and transistor 96 becomes off. The voltage at node 92 is essentially equal to voltage VCH, close to the threshold voltage of transistor 88. At time T23, the voltage at node 92 increases until it reaches the value VREF.

[0156] At time T23, the control signal of transistor 98, i.e., signal P2, is low, while the control signal P, i.e., signal P1, is high. Therefore, when capacitor 84 is charged by source 80, the voltage at node 92 (curve 133) essentially represents the value at node 16, while the voltage at node 84 (curve 131) increases. Consequently, at time T23, the clock signal CLK is high, and it remains high until time T24, at which time the voltage at node 84 reaches the value VREF.

[0157] Then, circuit 48 alternates between the first phases corresponding to the low state of the CLK signal, during which:

[0158] Transistor 98 is in the ON state, and the voltage at node 84 is essentially 0V; and

[0159] Transistors 100 and 96 are in the off state, transistor 88 is in the on state, and the voltage at node 92 increases until it reaches the value VREF, which leads to the transition to the second stage.

[0160] During the second phase, corresponding to the high value of signal CLK:

[0161] Transistor 98 is in the off state, and the voltage on node 84 increases until it reaches the value VREF, thereby causing the transition to the first stage;

[0162] Transistors 100 and 88 are on, while transistor 96 is off. Furthermore, the voltage at node 92 is essentially 0V.

[0163] Therefore, the duration between the transition from asynchronous mode to synchronous mode (i.e., the transition of the signal MODE from a low value to a high value) and the first rising edge of the clock signal is the duration between times T22 and T23. This duration is mainly caused by the time it takes for the voltage at node 92 to reach the voltage at node 94 when transistor 88 becomes on. This duration is relatively short, for example, between 1 ns and 10 ns.

[0164] It is possible to choose not to hold the signal CLK at a constant value during asynchronous operation mode. Curves 119, 125, and 127 correspond to this example of a clock signal generation circuit. In this example, the circuit will not include transistors 88 and 96 and circuit 110. In this example, node 94 will be connected to node 92, and transistor 100 will be controlled by signal P1. The duration between the transition from asynchronous mode to synchronous mode (i.e., the transition of signal MODE' from a low value to a high value) and the first rising edge of the clock signal CLK' depends on the value of signal CLK' when transitioning from asynchronous mode to synchronous mode, and can be up to the value of the period of signal CLK'. Figure 7 In the example shown, the period corresponds to the duration between times T25 and T26, which is much longer than the duration between times T22 and T23.

[0165] Figures 5 to 7 The advantage of this embodiment is that, in asynchronous mode, the voltage on node 94, namely voltage VCH, is sufficiently close to voltage VREF, such that the time required for the voltage on node 92 to reach the value VREF is small, and the first rising edge of the clock signal is close to the transition time between asynchronous and synchronous modes.

[0166] Figure 5 and Figure 7 Another advantage of the embodiment is that it requires very few additional electronic components compared to most clock signal generation circuits.

[0167] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily occur to them. In particular, in the described embodiments, the circuitry is synchronized with the rising edge of a clock signal. Clearly, the described embodiments are compatible with circuitry synchronized on the falling edge, and these modifications are within the scope of what those skilled in the art can derive from this specification.

[0168] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

Claims

1. A switching power supply, comprising: Output stage; A clock generator configured to generate a first clock signal, a second clock signal, and a third clock signal, wherein the third clock signal is complementary to the second clock signal; as well as A control circuit configured to control the output stage based on the first clock signal, wherein the switching power supply is configured to have a first operating mode synchronized by the first clock signal and an asynchronous second operating mode, wherein during mode transition from the second operating mode to the first operating mode, the clock generator is configured to: When the nearest edge of the second clock signal in the first direction is closer to the mode transition than the nearest edge of the third clock signal in the first direction, the first clock signal is made equal to the second clock signal. When the nearest edge of the third clock signal in the first direction is closer to the mode transition than the nearest edge of the second clock signal in the first direction, the first clock signal is made equal to the third clock signal.

2. The switching power supply according to claim 1, wherein the edge in the first direction is a rising edge.

3. The switching power supply according to claim 1, further comprising: A power supply terminal configured to receive a first power supply voltage; as well as A reference terminal is configured to receive a reference voltage, wherein the output stage includes a first transistor and a second transistor, and wherein the control circuit is configured to control the first transistor and the second transistor.

4. The switching power supply according to claim 3, wherein the first transistor and the second transistor are coupled in series between the power supply terminal and the reference terminal, the first transistor and the second transistor are coupled to each other through an intermediate node, and the switching power supply further comprises: Output terminals, which are configured to provide an output voltage; A first capacitor is coupled between the output terminal and the reference terminal; as well as An inductor is coupled between the intermediate node and the output terminal.

5. The switching power supply according to claim 3, wherein in the first operating mode, the control circuit is configured to control the first transistor and the second transistor to periodically alternate between an on state and an off state.

6. The switching power supply according to claim 3, wherein in the second operating mode, the control circuit is configured to: control the second transistor to be in a turn-off state and control the first transistor to be in a disconnected state when the output voltage coupled to the output terminal of the output stage is lower than the set point voltage.

7. The switching power supply of claim 1, wherein the control circuit is configured to generate a mode signal having a first value during a first operating mode and a second value during a second operating mode.

8. The switching power supply of claim 7, wherein the clock generator includes a selector circuit configured to receive the second clock signal and the third clock signal as inputs, and the selector circuit has a control input coupled to the output of a flip-flop, the flip-flop being configured to receive the second clock signal at a first input of the flip-flop and to receive the mode signal at a second input of the flip-flop.

9. The switching power supply according to claim 8, wherein the trigger is a D trigger, wherein the first input of the trigger is a data input terminal, and wherein the second input of the trigger is a clock input terminal.

10. The switching power supply of claim 8, wherein the clock generator comprises: An oscillator circuit having an output configured to provide the second clock signal; as well as An inverter having an input coupled to the output of the oscillator circuit and an output configured to provide the third clock signal.

11. The switching power supply according to claim 7, further comprising: The power supply terminal is configured to receive a first power supply voltage; A reference terminal is configured to receive a reference voltage, wherein the output stage includes a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled in series between the power supply terminal and the reference terminal, the first transistor and the second transistor are coupled to each other through an intermediate node, and wherein the control circuit is configured to control the first transistor and the second transistor. as well as A comparator is configured to compare the voltage of the intermediate node with the reference voltage, wherein the mode signal is configured to have the second value when the output of the comparator indicates that the voltage of the intermediate node is lower than the reference voltage.

12. A method for controlling a switching power supply having a first operating mode and a second operating mode, the method comprising: Generate the first clock signal; The output stage of the switching power supply is controlled based on the first clock signal, wherein the first operating mode is synchronized by the first clock signal, and the second operating mode is asynchronous; as well as After the mode transition from the second operating mode to the first operating mode, When the nearest edge of the second clock signal in the first direction is closer to the mode transition than the nearest edge of the third clock signal, which is complementary to the second clock signal, in the first direction, the first clock signal is made equal to the second clock signal. When the nearest edge of the third clock signal in the first direction is closer to the mode transition than the nearest edge of the second clock signal in the first direction, the first clock signal is made equal to the third clock signal.

13. The method of claim 12, further comprising: The output voltage is supplied to the load based on the setpoint voltage; as well as In response to an increase in the current drawn by the load, the system switches from the second operating mode to the first operating mode.

14. The method of claim 12, further comprising: Generate a mode signal that has a first value during the first operating mode and a second value during the second operating mode; The second clock signal is received at the first input of the flip-flop; as well as The mode signal is received at the second input of the trigger, wherein generating the first clock signal includes: making the first clock signal equal to the second clock signal or the third clock signal based on the output of the trigger.

15. The method of claim 14, wherein the trigger is a D trigger, wherein the first input of the trigger is a data input, and wherein the second input of the trigger is a clock input.

16. The method of claim 14, further comprising: The second clock signal is generated using an oscillator circuit. as well as The third clock signal is generated by using an inverter with an input having an output coupled to the output of the oscillator circuit.

17. A circuit comprising: Power terminals; Reference terminal; A clock generator, configured to generate a first clock signal; as well as A control circuit having a first input coupled to the output of the clock generator and a first output configured to be coupled to a control terminal of an output stage, wherein the control circuit is configured to: The output stage is controlled to adjust the output voltage based on the setpoint voltage using either a first operating mode synchronized by the first clock signal or an asynchronous second operating mode. Generating a mode signal having a first value during the first operating mode and a second value during the second operating mode, wherein the clock generator includes: A trigger having a first input configured to receive a second clock signal and a second input configured to receive the mode signal; as well as The selector circuit has a first input configured to receive the second clock signal, a second input configured to receive a third signal complementary to the second clock signal, a control input coupled to the output of the flip-flop, and an output configured to provide the first clock signal.

18. The circuit of claim 17, wherein the clock generator further comprises: An oscillator having an output configured to provide the second clock signal; as well as An inverter having an input coupled to the output of the oscillator and an output coupled to the second input of the selector circuit.

19. The circuit of claim 17, further comprising: A power supply terminal configured to receive a first power supply voltage; A reference terminal, configured to receive a reference voltage; The output stage includes a first transistor and a second transistor connected in series between the power supply terminal and the reference terminal; An output terminal configured to provide the output voltage; as well as An inductor is coupled between an intermediate node and the output terminal, the intermediate node being coupled between the first transistor and the second transistor.

20. The circuit of claim 19, further comprising: A comparator having an input coupled to the intermediate node and an output coupled to the control circuit, wherein the mode signal is configured to have the second value when the output of the comparator indicates that the voltage of the intermediate node is lower than the reference voltage.

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