Chip packaging structure and packaging method thereof

Abstract

The invention discloses a chip packaging structure and a packaging method thereof, and belongs to the technical field of microelectronic packaging. The packaging structure comprises a sintering base and an insulating cover, the shape of a bearing surface of a Kovar seat in the sintering base is matched with that of a stress induction region at the bottom of a chip, the area is smaller, and an insulating layer is arranged between the Kovar seat and a base blank to realize electric insulation; and the limiting hole of the insulating cover is used for accommodating and positioning the chip and corresponds to the bearing surface of the Kovar seat. The packaging method comprises the steps of base pretreatment, accurate gluing, insulation cover installation and alignment, chip gravity self-alignment mounting and curing and the like. Through customization of the Kovar seat, a non-pressure mounting process and multiple insulation design, the glue area and the chip functional area are accurately matched, the packaging stress and glue pollution are reduced, the whole-process electrostatic protection is enhanced, the precision, long-term stability and product yield of the sensor are improved, and the pressure sensor chip is suitable for scenes such as high-precision pressure sensor chips with harsh packaging requirements.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of microelectronic packaging, and particularly relates to a chip packaging structure and a packaging method thereof. BACKGROUND

[0002] In the packaging process of high-precision micro-electro-mechanical system (MEMS) chips, especially high-precision pressure sensor chips, an adhesive material is usually used to fix the chip on a sintered metal base. The bottom of the chip is often designed with a stress sensing area, and the performance of the stress sensing area is extremely sensitive to packaging stress.

[0003] At present, the chip bearing area of the commonly used base is usually a simple continuous plane or a boss structure, which leads to insufficient matching precision of the glue area and the functional area of the chip, and obvious defects. First, the matching of the glue amount and the functional area is poor. The adhesive is usually coated globally, and cannot accurately correspond to the core stress sensing area. This not only causes waste, but also introduces significant additional thermal mechanical stress when the temperature changes due to the mismatch of the coefficient of thermal expansion (CTE) of the glue and the chip material, which seriously affects the zero point, sensitivity and long-term stability of the sensor. Second, the packaging process itself introduces stress. The conventional pressing process is easy to cause uneven flow of glue and offset of the chip, and the excess adhesive may contaminate the functional area and cause local stress concentration, increasing the risk of failure.

[0004] In addition, insufficient electro-static discharge (ESD) protection is also a key problem. When the chip directly contacts the conductive base, the potential difference in operation is easy to produce electro-static discharge, damaging the internal sensitive circuit. Even if the existing scheme uses a surface coated insulation glue layer, it often lacks structural electrical isolation design, and cannot realize electro-static protection from mounting to use, and the ESD risk is still significant.

[0005] Therefore, the existing technology cannot meet the stringent requirements of high-precision chips for packaging stress control and electro-static protection. There is an urgent need for a new packaging scheme that can accurately match the functional area, minimize process stress and strengthen electro-static isolation. SUMMARY

[0006] The purpose of the embodiments of the present application is to provide a chip packaging structure and a packaging method thereof. To solve the problems of insufficient matching precision of the glue area and the stress sensing area at the bottom of the chip, the packaging process easily introduces additional stress, and the lack of effective electrical insulation between the Kovar base and the base blank leads to the risk of electro-static discharge.

[0007] To achieve the above purpose, the following technical solutions are adopted in the present application: In a first aspect, a chip packaging structure is provided, comprising: a sintered base, comprising a base blank, a Kovar base, an insulating layer, a Kovar tube leg for signal lead-out, and a pressure lead tube for pressure conduction; the Kovar base is arranged on the base blank, and a bearing surface of the Kovar base is shaped to match a stress sensing area of a bottom of the chip, and has an area smaller than the stress sensing area; the insulating layer is arranged between the Kovar base and the base blank, and realizes electrical insulation between the Kovar base and the base blank; an insulating cover is provided with a limiting hole for accommodating and positioning the chip, and the insulating cover is mounted on the sintered base, so that the limiting hole corresponds to the bearing surface of the Kovar base in the vertical direction.

[0008] In a possible implementation, the bearing surface of the Kovar base is a square, and a ring-shaped groove for accommodating excess adhesive is arranged at the root of the bearing surface.

[0009] In a possible implementation, the insulating layer comprises a ceramic sheet and a glass insulator; the ceramic sheet is arranged at the bottom of the Kovar base, and the glass insulator is filled in the gap between the Kovar base and the base blank, and forms airtight sealing through a high-temperature sintering process.

[0010] In a possible implementation, the limiting hole of the insulating cover is a square hole, and a single-side gap between the inner wall of the limiting hole and the side wall of the chip is less than or equal to 5 μm.

[0011] In a possible implementation, the insulating cover is made of alumina ceramic material.

[0012] In a second aspect, a chip packaging method is provided, which is applied to the packaging structure of the first aspect, and comprises the following steps: S1: cleaning and activating the surface of the sintered base, in particular the Kovar base; S2: applying adhesive to the bearing surface of the Kovar base, and the range of adhesive application is limited to covering the bearing surface; S3: mounting the insulating cover to the sintered base, and ensuring that the center of the limiting hole of the insulating cover is aligned with the geometric center of the Kovar base; S4: placing the chip into the limiting hole, and relying on the gravity of the chip to make the chip naturally sink and contact the adhesive on the Kovar base, to complete the mounting; S5: curing the adhesive to form a packaging body.

[0013] In one possible implementation, in step S2, a high-precision dispensing device is used to apply adhesive, and the adhesive is a modified epoxy resin with a low coefficient of thermal expansion.

[0014] In one possible implementation, in step S3, an optical alignment system is used for precise positioning, and the alignment deviation is controlled within ±10μm.

[0015] In one possible implementation, in step S4, no external pressure is applied during the chip mounting process; during the chip sinking process, the excess adhesive that is squeezed out flows into and is contained in the annular groove at the root of the Kovar base.

[0016] In one possible implementation, after step S5, step S6 is further included: establishing an electrical connection between the circuitry on the chip and the Kova pins on the sintered substrate via a bonding process.

[0017] Compared with the prior art, this application has the following beneficial effects: This application provides a chip packaging structure that ensures precise matching between the adhesive area and the chip's stress-sensing area by setting the bearing surface of the Kova socket to a geometric structure that is adapted to the shape of the stress-sensing area on the bottom of the chip and has a smaller area, thereby reducing the impact of thermomechanical stress. The insulating layer provides reliable electrical insulation between the Kova socket and the substrate blank, reducing the risk of electrostatic discharge. The distributed layout of the Kova pins and pressure taps has clear functions and does not interfere with each other, ensuring the reliability of signal output and pressure transmission respectively. The limiting holes of the insulating cover are perpendicular to the bearing surface of the Kova socket, providing precise positioning for the chip. The overall structure collaboratively solves the core problems of poor adhesive area matching, stress introduction, insufficient electrostatic protection, and poor functional structure synergy in the prior art, laying the foundation for high-precision packaging.

[0018] In one possible implementation, the square bearing surface is further adapted to the square stress-sensitive area commonly found in chips, ensuring precise adhesive coating. The annular groove at the root can effectively accommodate excess adhesive squeezed out during the mounting process, preventing the adhesive from climbing along the chip side and contaminating the functional area. At the same time, it prevents local stress concentration, reduces the risk of chip breakage or performance degradation, and improves the reliability of the package.

[0019] In one possible implementation, the double insulation structure composed of ceramic sheet and glass insulator significantly improves the insulation reliability between the Kova base and the base blank, and strengthens electrostatic protection throughout the process; the airtight seal formed by the high-temperature sintering process can prevent external moisture, impurities and other contaminants from entering the package, protect the chip's sensitive circuits, and at the same time enhance the mechanical stability of the structure and extend the product's service life.

[0020] In one possible implementation, the single-sided gap is controlled within 5μm, which can provide precise guidance and positioning for the chip, ensuring that the horizontal deviation of the chip is minimal during the mounting process, and achieving precise alignment between the chip and the carrier surface of the Kova socket; the tight fit gap design can also prevent the chip from micro-shifting during the packaging process, ensuring precise matching between the adhesive coating area and the stress-sensing area of ​​the chip, and further improving the packaging accuracy.

[0021] A chip packaging method is disclosed, which features a simple and controllable process. Plasma cleaning activates the surface of the Kova socket, improving adhesive adhesion. Precise adhesive application and accurate alignment ensure matching between the adhesive area and the functional area. Gravity mounting eliminates the need for external pressure, avoiding uneven adhesive extrusion and chip misalignment. Stepped temperature curing allows the adhesive to fully cross-link, improving bonding strength. The overall process is optimized to effectively reduce packaging stress, improve packaging accuracy and efficiency, and facilitate automated production.

[0022] In one possible implementation, gold wire bonding enables reliable electrical interconnection between the chip circuit and the pins, ensuring that the pressure signal sensed by the chip can be stably and with low loss led out to the external acquisition circuit. The gold alloy wire has excellent conductivity and oxidation resistance, and the solder joints formed by thermo-ultrasonic bonding have high mechanical strength and stable electrical performance, ensuring the reliability of the electrical connection of the package and enabling the sensor to work normally. Attached Figure Description

[0023] Figure 1 A cross-sectional view of a chip packaging structure provided in this application; Figure 2 for Figure 1 Enlarged view of the middle section (I); Figure 3 An exploded view of a chip packaging structure provided in this application; Figure 4 Another exploded view of a chip packaging structure provided in this application.

[0024] The attached figures are labeled as follows: 1. Kova base; 2. Glass insulator; 3. Ceramic sheet; 4. Base blank; 5. Pressure tube; 6. Kova tube leg; 7. Annular groove; 8. Chip; 9. Insulating cover. Detailed Implementation

[0025] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0026] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly defined. The specific embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0028] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0029] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] like Figures 1-4 As shown, this application discloses a chip packaging structure, which may include a sintered base and an insulating cover 9.

[0032] The sintered substrate may include a substrate blank 4, a Kova base 1, an insulating layer, Kova leads 6 for signal output, and pressure leads 5 for pressure conduction. The Kova base 1 is disposed on the substrate blank 4, and the shape of its bearing surface facing the chip 8 is adapted to the shape of the stress-sensing area on the bottom of the chip 8, and its area is smaller than that stress-sensing area. The insulating layer is disposed between the Kova base 1 and the substrate blank 4 to achieve electrical insulation between the Kova base 1 and the substrate blank 4.

[0033] Optionally, the base blank 4 of the sintered base is made of metal. The Kova base 1 is fixed to the base blank 4 by a mold. Its bearing surface facing the chip 8 is designed as a square, which matches the square stress-sensing area at the bottom of the chip 8. The bearing surface area of ​​the Kova base 1 is 0.6 mm² smaller than the stress-sensing area of ​​the chip 8. An insulating layer composed of a ceramic sheet 3 and a glass insulator 2 is provided between the Kova base 1 and the base blank 4 to achieve electrical insulation between the two. The Kova tube leg 6 and the pressure tube 5 are fixed to the base blank 4 by glass sintering process and are used for electrical signal output and external pressure transmission, respectively.

[0034] The insulating cover 9 is provided with a limiting hole for accommodating and positioning the chip 8. The insulating cover 9 is mounted on the sintering base such that the limiting hole corresponds to the bearing surface of the Kova base 1 in the vertical direction.

[0035] Specifically, the insulating cover 9 is made of alumina ceramic with square limiting holes. The insulating cover 9 is fixed to the sintered base with adhesive so that the limiting holes and the bearing surface of the Kova base 1 are precisely aligned in the vertical direction. The Kova tube 6 is used for electrical interconnection of subsequent chip circuits, and the pressure tube 5 is used to transmit external pressure to the stress sensing area of ​​the chip 8.

[0036] In this embodiment, by setting the bearing surface of the Kova base 1 to a geometric structure that is adapted to the shape of the stress-sensing area at the bottom of the chip 8 and has a smaller area, the precise matching between the adhesive area and the stress-sensing area of ​​the chip 8 is ensured, reducing the impact of thermomechanical stress. The setting of the insulating layer achieves reliable electrical insulation between the Kova base 1 and the base blank 4, reducing the risk of electrostatic discharge. The distributed layout of the Kova tubes 6 and the pressure tubes 5 has a clear function and does not interfere with each other, respectively ensuring the reliability of signal output and pressure transmission. The limiting hole of the insulating cover 9 is perpendicular to the bearing surface of the Kova base 1, providing precise positioning for the chip 8. The overall structure collaboratively solves the core problems of poor adhesive area matching, stress introduction, insufficient electrostatic protection, and poor functional structure synergy in the prior art, laying the foundation for high-precision packaging.

[0037] In one possible embodiment, the bearing surface of the Kova seat 1 is square, and its root is provided with an annular groove 7 for accommodating excess adhesive.

[0038] Specifically, the square bearing surface of the Kova base 1 has a side length of 1.4mm, and the stress-sensing area at the bottom of the chip 8 has a side length of 1.6mm. A ring groove 7 with a width of 1.8mm and a depth of 0.5mm is formed at the root of the Kova base 1 through mechanical processing. When the chip 8 and the Kova base 1 are bonded together with adhesive, the excess adhesive will naturally flow into the ring groove 7.

[0039] In this embodiment, the square bearing surface is further adapted to the common square stress-sensitive area of ​​the chip 8 to ensure accurate adhesive coating range; the annular groove 7 at the root can effectively accommodate excess adhesive squeezed out during the mounting process, preventing the adhesive from climbing along the side of the chip 8 and contaminating the functional area, while preventing local stress concentration, reducing the risk of chip 8 cracking or performance degradation, and improving the reliability of the package.

[0040] In one possible embodiment, the insulating layer comprises a ceramic sheet 3 and a glass insulator 2; The ceramic sheet 3 is located at the bottom of the Kovar base 1, and the glass insulator 2 fills the gap between the Kovar base 1 and the base blank 4, and forms an airtight seal through a high-temperature sintering process.

[0041] Optionally, the ceramic sheet 3 is made of zirconia ceramic or other insulating material with a thickness of 0.5 mm, and is attached and fixed to the bottom of the Kova seat 1; a 1 mm gap is reserved between the Kova seat 1 and the base blank 4, and the glass insulator 2 is filled into the gap. Then, the glass insulator 2 is solidified and formed by high-temperature sintering process, which not only achieves electrical insulation between the Kova seat 1 and the base blank 4, but also forms a good airtight seal; the Kova tube leg 6 and the pressure tube 5 are fixed at the same time by glass sintering process to ensure the connection strength and airtightness with the base blank 4.

[0042] In this embodiment, the double insulation structure composed of ceramic sheet 3 and glass insulator 2 significantly improves the insulation reliability between Kova base 1 and base blank 4, and strengthens electrostatic protection throughout the process; the airtight seal formed by the high-temperature sintering process can prevent external moisture, impurities and other contaminants from entering the package, protect the sensitive circuit of chip 8, and at the same time enhance the connection stability between Kova pin 6, pressure tube 5 and base blank 4, and extend the product service life.

[0043] In one possible embodiment, the limiting hole of the insulating cover 9 is a square hole, and the single-sided gap between its inner wall and the side wall of the chip 8 is less than or equal to 5 μm.

[0044] Optionally, the side length of the square limiting hole on the insulating cover 9 is 10μm longer than the side length of the chip 8, that is, the single-sided gap between the inner wall of the limiting hole and the side wall of the chip 8 is 5μm. After the chip 8 is placed in the limiting hole, the side wall and the inner wall of the limiting hole fit tightly, leaving only a small gap for guidance. When installing the insulating cover 9, avoid the positions of the Kova tube leg 6 and the pressure tube 5 to ensure that their functions are not interfered with.

[0045] In this embodiment, the single-sided gap is controlled within 5μm, which can provide precise guidance and positioning for the chip 8, ensuring that the horizontal deviation of the chip 8 is minimal during the mounting process, and achieving precise alignment between the chip 8 and the bearing surface of the Kova socket 1; the tight fit gap design can also prevent the chip 8 from undergoing micro-displacement during the packaging process, ensuring precise matching between the adhesive coating area and the stress-sensing area of ​​the chip 8, and further improving the packaging accuracy; at the same time, the position avoidance design between the insulating cover 9 and the Kova tube leg 6 and the pressure tube 5 ensures the coordinated operation of each functional structure.

[0046] In one possible embodiment, the insulating cover 9 is made of alumina ceramic material.

[0047] Optionally, the insulating cover 9 is made of alumina ceramic material with 95% alumina content. It is prepared by dry pressing and high-temperature sintering. Its external dimensions are adapted to the sintering base. The insulating cover 9 is formed by sintering through a mold. The insulating cover 9 has reserved clearance holes corresponding to the Kovar leg 6 and the pressure tube 5.

[0048] In this embodiment, the alumina ceramic material has excellent insulation properties, which can effectively block electrostatic conduction and enhance the electrostatic protection effect. At the same time, the material has high mechanical strength, high temperature resistance and good chemical stability, which can provide reliable protection for the chip 8, resist the influence of external forces and temperature changes during packaging and use, and ensure the long-term stability of the packaging structure. The design of the clearance hole makes the insulating cover 9 perfectly fit with the Kova tube leg 6 and the pressure tube 5, ensuring the compactness and functionality of the overall structure.

[0049] In one possible embodiment, a chip packaging method is provided, applied to the aforementioned packaging structure, comprising the following steps: S1: The surface of the sintered base, especially the Kova base 1, is cleaned and activated.

[0050] The sintered base is surface cleaned using plasma cleaning equipment. A mixture of argon and hydrogen is used as the cleaning gas to thoroughly remove organic contaminants and dust from the surface of the Kovar base 1, activate the surface, and protect the surface of the Kovar leg 6 and pressure tube 5 during the cleaning process to avoid residual contaminants affecting the reliability of subsequent connections.

[0051] S2: Apply adhesive to the bearing surface of the Kovar seat 1, with the adhesive application area limited to covering the bearing surface.

[0052] High-precision dispensing equipment, equipped with a dispensing needle with an inner diameter of 0.1mm, is used to apply modified epoxy resin adhesive with a low coefficient of thermal expansion. The equipment's preset program sets the dispensing path to a spiral trajectory from the edge to the center of the Kova seat 1's bearing surface. The dispensing area is strictly limited to the square bearing surface of the Kova seat 1, ensuring that the adhesive completely covers the bearing surface without overflow. This achieves precise control of the adhesive amount from a physical structural perspective, avoiding waste or insufficient application.

[0053] S3: Install the insulating cover 9 onto the sintering base, and ensure that the center of the limiting hole of the insulating cover 9 is aligned with the geometric center of the Kova base 1.

[0054] First, the insulating cover 9 is placed on the sintering base, and its initial positioning is achieved using the outline of the Kova leg 6. This ensures that the clearance hole of the insulating cover 9 initially aligns with the Kova leg 6 and the pressure tap 5, limiting significant displacement of the insulating cover 9. Then, an optical alignment system is activated. A high-definition industrial camera captures the geometric center mark of the Kova base 1 and the center mark of the limiting hole of the insulating cover 9. The alignment deviation between the two is calculated in real time, and the position of the insulating cover 9 is automatically adjusted via an electric adjustment platform. The alignment deviation is strictly controlled within ±10μm, ensuring that the limiting hole and the bearing surface of the Kova base 1 are precisely aligned vertically, providing a foundation for the self-aligned mounting of the chip 8.

[0055] S4: Place chip 8 into the limiting hole, and let chip 8 sink naturally under its own weight to contact the adhesive on the Kova seat 1 to complete the mounting.

[0056] High-precision placement equipment is used to smoothly pick up the pressure chip 8 using a vacuum nozzle, avoiding surface damage or electrostatic adsorption. The chip 8 is then moved directly above the limiting hole of the insulating cover 9. After ensuring initial alignment between the center of the chip 8 and the center of the limiting hole, the vacuum suction is turned off, allowing the chip 8 to sink naturally along the inner wall of the limiting hole under its own gravity. The precise guiding effect of the inner wall of the limiting hole automatically corrects minor horizontal deviations of the chip 8, ensuring precise contact between the stress-sensitive area at the bottom of the chip 8 and the adhesive on the Kova base 1. No external pressure is applied during the placement process. The small amount of excess adhesive squeezed out flows along the side of the Kova base 1 into the annular groove 7 at the root under the action of gravity and surface tension, effectively collecting excess adhesive and preventing adhesive from climbing and contaminating the functional areas of the chip 8. At this time, the pressure tube 5 remains hollow and conductive to avoid blockage by adhesive.

[0057] S5: Curing the adhesive to form an encapsulation.

[0058] The assembled unit with 8 chips mounted is placed in a hot air circulating curing oven and cured according to a stepped temperature curing curve: In the first stage, the temperature is raised from room temperature to 80°C and kept at that temperature for 1 hour to allow the adhesive to initially level and remove air bubbles. In the second stage, the temperature is raised to 120℃ and kept at that temperature for 2 hours to allow the adhesive to fully cross-link and cure. After curing, the package is cooled to room temperature in the oven to avoid excessive temperature difference that could introduce thermal stress. After curing, a package with sufficient adhesive strength is formed to ensure that the chip 8 is firmly bonded to the Kova socket 1. During the curing process, the Kova leads 6 and the pressure taps 5 maintain structural stability and do not deform or shift.

[0059] In this embodiment, the method is simple and controllable. Plasma cleaning activates the surface of the Kova socket 1, improving adhesive adhesion. Precise application and accurate alignment ensure matching between the adhesive area and the functional area. Gravity mounting eliminates the need for external pressure, avoiding uneven adhesive compression and chip 8 misalignment. Stepped temperature curing allows the adhesive to fully cross-link, improving bonding strength. Simultaneously, the operational requirements of the Kova pins 6 and the pressure tubes 5 are clearly defined in each step to ensure that their functions are not affected. The overall process is optimized collaboratively, effectively reducing packaging stress, improving packaging accuracy and efficiency, and facilitating automated production.

[0060] In one possible embodiment, in step S2, a high-precision dispensing device is used to apply adhesive, which is a modified epoxy resin with a low coefficient of thermal expansion.

[0061] In step S2, a high-precision dispensing device is used to calculate the required amount of adhesive based on the area of ​​the bearing surface of the Kova seat 1, precisely dispensing the modified epoxy resin adhesive. The coefficient of thermal expansion of this adhesive is 20~40×10⁻⁶. -6 / ℃, which is close to the thermal expansion coefficient of the chip 8 material; during the adhesive application process, ensure that the adhesive does not come into contact with the surface of the Kova tube leg 6 and the pressure tube 5 to avoid affecting subsequent electrical connections and pressure transmission.

[0062] In this embodiment, the high-precision dispensing equipment achieves precise control of the amount of adhesive, avoiding adhesive waste and ensuring uniform application. The modified epoxy resin with a low coefficient of thermal expansion can significantly reduce the thermomechanical stress caused by the mismatch of coefficients of thermal expansion, reducing the impact on the zero-point output, sensitivity and long-term stability of the sensor, and is especially suitable for high-precision pressure sensing scenarios. The avoidance design between the Kova tube leg 6 and the pressure tap 5 ensures the realization of the core functions of both.

[0063] In one possible embodiment, in step S3, an optical alignment system is used for precise positioning to control the alignment deviation within ±10μm.

[0064] In step S3, after initial positioning using the Kova tube leg 6, the optical alignment system is activated. The edge contours of the Kova base 1 and the limiting hole are captured by a high-definition camera, and the center deviation is calculated in real time. By finely adjusting the position of the insulating cover 9, the alignment deviation between the center of the limiting hole and the geometric center of the Kova base 1 is controlled within ±10μm. At the same time, it is ensured that the clearance hole of the insulating cover 9 is completely aligned with the pressure tube 5 and the chip 8, without obstruction or offset.

[0065] In this embodiment, the application of the optical alignment system achieves high-precision alignment between the insulating cover 9 and the Kova seat 1, significantly reducing alignment deviation and ensuring that the Kova seat 1 can be accurately attached to the bearing surface after being guided by the limiting hole. This ensures accurate matching between the adhesive area and the stress sensing area of ​​the chip 8, and accurate alignment between the avoidance hole and the pressure tube 5, preventing the pressure transmission path from being blocked. This provides a key guarantee for improving packaging accuracy and sensor performance.

[0066] In one possible embodiment, in step S4, no external pressure is applied during the chip 8 mounting process; during the chip 8 sinking process, the excess adhesive that is squeezed out flows into and is contained in the annular groove 7 at the root of the Kovar 1.

[0067] In step S4, after the chip 8 is placed into the limiting hole, it sinks naturally by its own weight without any external pressure. After the chip 8 comes into contact with the adhesive, the small amount of excess adhesive squeezed out flows along the side of the Kova seat 1 into the annular groove 7 at the root under the action of gravity and surface tension. The volume of the groove is just enough to accommodate the excess adhesive. The excess adhesive will not flow into the hollow channel of the pressure tube 5, ensuring that the pressure transmission path is unobstructed.

[0068] In this embodiment of the application, in step S4, after the chip 8 is placed into the limiting hole, it sinks naturally by its own weight without any external pressure. After the chip 8 comes into contact with the adhesive, the small amount of excess adhesive squeezed out flows along the side of the Kova seat 1 into the annular groove 7 at the root under the action of gravity and surface tension. The volume of the groove is just enough to accommodate the excess adhesive.

[0069] In one possible embodiment, after step S5, step S6 is further included: establishing an electrical connection between the circuitry on the chip 8 and the Kova pin 6 on the sintered substrate through a bonding process.

[0070] After the curing in step S5 is completed, the package is transferred to the gold wire bonding equipment. Using a gold alloy wire with a diameter of 25μm, the pads on the chip 8 are connected to the Kova tube legs 6 on the sintered base one by one through the thermo-ultrasonic bonding process. At this time, the pressure tube 5 remains in a hollow and conductive state and can be directly used for subsequent pressure conduction tests or practical applications.

[0071] In this embodiment, the gold wire bonding process enables reliable electrical interconnection between the chip circuit and the Kova pin 6, ensuring that the pressure signal sensed by the chip 8 can be stably and with low loss led out to the external acquisition circuit; the pressure tube 5 ensures that the external pressure is accurately transmitted to the stress sensing area of ​​the chip 8, and the two work together to realize the complete functions of sensor pressure sensing and signal output; the gold alloy wire has excellent conductivity and oxidation resistance, and the solder joint formed by thermo-ultrasonic bonding has high mechanical strength and stable electrical performance, ensuring the electrical connection reliability of the package and enabling the sensor to work normally.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications to the technical solutions described in the foregoing embodiments, or equivalent substitutions for some or all of the technical features, do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A chip package structure, characterized by, The application relates to a sintering base, which comprises a base blank (4), a Kovar base (1), an insulating layer, Kovar tube legs (6) for signal lead-out and pressure lead pipes (5) for pressure conduction. The Kovar base (1) is arranged on the base blank (4), and the bearing surface of the Kovar base (1) towards a chip (8) is matched with the shape of a stress sensing area at the bottom of the chip (8) and has an area smaller than the stress sensing area. The insulating layer is arranged between the Kovar base (1) and the base blank (4) to realize electrical insulation between the Kovar base (1) and the base blank (4). An insulating cover (9) is arranged on the sintering base, and a limiting hole for accommodating and positioning the chip (8) is arranged on the insulating cover (9), so that the limiting hole is corresponded to the bearing surface of the Kovar base (1) in the vertical direction. The bearing surface of the Kovar base (1) is a square, and a ring-shaped groove (7) for accommodating excess adhesive is arranged at the root of the bearing surface.

2. The chip package structure of claim 1, wherein: The insulating layer comprises ceramic sheets (3) and glass insulators (2).

3. The chip package structure of claim 1 or 2, wherein: The ceramic sheets (3) are arranged at the bottom of the Kovar base (1), the glass insulators (2) are filled in the gap between the Kovar base (1) and the base blank (4), and airtight sealing is formed through a high-temperature sintering process. The limiting hole of the insulating cover (9) is a square hole, and the single-side gap between the inner wall of the limiting hole and the side wall of the chip (8) is less than or equal to 5 mu m.

4. The chip package structure of claim 1, wherein: The insulating cover (9) is made of alumina ceramic material.

5. The chip package structure of claim 1, wherein: The application further discloses a chip mounting method, which comprises the following steps:

6. A method of packaging a chip, applied to the packaging structure according to any one of claims 1 to 5, characterized in that, S1: surface cleaning is performed on the sintering base, and the surface of the Kovar base (1) is activated; S2: adhesive is coated on the bearing surface of the Kovar base (1), and the adhesive coating range is limited to covering the bearing surface; S3: the insulating cover (9) is mounted to the sintering base, and the center of the limiting hole of the insulating cover (9) is aligned with the geometric center of the Kovar base (1); S4: the chip (8) is placed into the limiting hole, and the chip (8) is naturally sunk to contact the adhesive on the Kovar base (1) by gravity, so that the mounting is completed; S5: curing treatment is performed on the adhesive to form a packaging body. In step S2, high-precision dispensing equipment is adopted for adhesive coating, and the adhesive is modified epoxy resin with low thermal expansion coefficient.

7. The packaging method of a chip according to claim 6, wherein: In step S3, an optical alignment system is adopted for positioning, and the alignment deviation is controlled to be within + / - 10 mu m.

8. The packaging method of a chip according to claim 6, wherein: In step S4, no external pressure is applied during the chip (8) mounting process; during the sinking process of the chip (8), the excess adhesive is squeezed and flows into and is accommodated in the ring-shaped groove (7) at the root of the Kovar base (1).

9. The packaging method of a chip according to claim 6, wherein: After step S5, step S6 is further included, that is, a bonding process is adopted to realize electrical connection between the circuit on the chip (8) and the Kovar tube legs (6) on the sintering base.

10. The packaging method of a chip according to claim 6, wherein: ​

Images