Memory data reading circuit and memory

Abstract

According to the memory data reading circuit and the memory provided by the embodiment of the invention, a memory array unit driving module determines first output data corresponding to different data lines at each sampling moment according to output data read from a memory array, and determines a data bus overturn enable signal corresponding to each sampling moment; the memory array unit group driving module determines second output data corresponding to different sampling moments of each data line according to the first output data, and performs serial output sequence adjustment on the second output data to obtain second target output data corresponding to different sampling moments of each data line; the data selection module determines third output data corresponding to different data lines at each sampling moment according to second target output data corresponding to different sampling moments of each data line, and processes the third output data corresponding to different data lines at each sampling moment according to the data bus overturning enable signal corresponding to each sampling moment, so that the data bus overturning enable signal corresponding to each sampling moment is obtained; and the waiting time for reading the data is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory and related technical field, in particular, to a memory data reading circuit and a memory. BACKGROUND

[0002] The Data Bus Inversion (DBI) function of DDR4 memory is a key data coding technology, which aims to reduce dynamic power consumption and improve signal integrity. The core principle is: when transmitting 8-bit data, if the number of data "0" exceeds 4 bits, the controller sending end will transmit the entire data byte after flipping and set the DM pin to low to indicate this operation; if the number of "0" does not exceed 4 bits, the original data is directly transmitted and the DM port is set to high. When reading memory data, the controller receiving end decides whether to perform inverse flipping on the data to recover the original value according to the DM state.

[0003] For memory write operation, the write data is provided by the memory controller, and the controller calculates the number of "0"s in the current burst; if the number of "0"s exceeds 4, the entire burst data is flipped, and the DM data is set to 0. For memory read operation, 64-bit data is taken out from the "memory array", and then it is calculated whether the data in each burst needs to be flipped; if flipped, the DM of the corresponding burst is set to 0, and finally the processed 64-bit DQ and 8-bit DM are sent to the memory controller. In order to realize the DBI read operation function, a logic circuit needs to be added in the memory to confirm the number of "0"s in the data, which makes the data transmission time longer, resulting in higher delay of DRAM and reduced performance. SUMMARY

[0004] The embodiments described herein provide a memory data reading circuit and a memory, which solve the problems existing in the prior art.

[0005] In a first aspect, according to the content of the present disclosure, a memory data reading circuit is provided, comprising: a memory array unit driving module, a memory array unit group driving module, and a data selection module; The memory array unit driving module is configured to determine first output data corresponding to different data lines at each sampling time according to output data read from the memory array, and determine a data bus inversion enable signal corresponding to each sampling time according to the first output data corresponding to different data lines at each sampling time. The memory array unit group driving module is configured to determine second output data corresponding to different sampling time instants of each data line according to the first output data corresponding to different data lines at different sampling time instants, adjust the serial output order of the second output data corresponding to different sampling time instants of each data line, obtain second target output data corresponding to different sampling time instants of each data line, and receive a data bus inversion enable signal corresponding to each sampling time instant. The data selection module is configured to determine third output data corresponding to different data lines at different sampling time instants according to the second target output data corresponding to different sampling time instants of each data line, process the third output data corresponding to different data lines at different sampling time instants according to the data bus inversion enable signal corresponding to each sampling time instant, and output through a data transmission port.

[0006] In some embodiments of the present disclosure, the memory array unit driving module includes an output data processing unit and a data bus inversion enable signal determination unit. The output data processing unit is configured to determine reverse output data corresponding to output data read from a storage array, and output target output data and target reverse output data after signal amplification of the output data and the reverse output data. The data bus inversion enable signal determination unit is configured to determine first output data corresponding to different data lines at different sampling time instants according to the target output data, and determine a data bus inversion enable signal corresponding to each sampling time instant according to the first output data corresponding to different data lines at different sampling time instants.

[0007] In some embodiments of the present disclosure, the output data processing unit includes a first switch subunit, a second switch subunit, a third switch subunit, and an amplification subunit. The first switch subunit is configured to, in a memory read operation state, control a path between a first output data node and a first reverse output data node to be turned off and a path between a second output data node and a second reverse output data node to be turned off according to a received first enable signal, wherein the first output data node receives output data and the first reverse output data node receives reverse output data. The second switch subunit is configured to, in a memory read operation state, be turned off according to a received second enable signal. The third switch subunit is configured to, in a memory read operation state, be turned on according to a received third enable signal, so that a path between the first output data node and the second output data node is turned on and a path between the first reverse output data node and the second reverse output data node is turned on. The amplification subunit is configured to amplify and output target output data and target reverse output data after amplifying the output data and the reverse output data.

[0008] In some embodiments of the present disclosure, the first switch subunit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch, the second switch subunit includes a first inverter, a second inverter, a seventh switch, an eighth switch, a ninth switch and a tenth switch, the third switch subunit includes an eleventh switch and a twelfth switch, and the amplification subunit includes a third inverter, a fourth inverter, a fifth inverter and a sixth inverter. The first end of the first switch, the first end of the third switch, the first end of the seventh switch, the first end of the ninth switch and the first end of the eleventh switch are electrically connected with the first output data node respectively, the second end of the first switch is electrically connected with the first end of the second switch, the second end of the second switch, the second end of the third switch, the second end of the eighth switch, the second end of the tenth switch and the second end of the twelfth switch are electrically connected with the first reverse output data node respectively, and the control end of the first switch, the control end of the second switch and the control end of the third switch receive a first sub-enable signal of a first enable signal; the first end of the fourth switch, the first end of the sixth switch, the second end of the eleventh switch, the output end of the third inverter, the input end of the fourth inverter and the input end of the fifth inverter are electrically connected with the second output data node respectively, the second end of the fourth switch is electrically connected with the first end of the fifth switch, the second end of the fifth switch, the second end of the sixth switch, the second end of the twelfth switch, the input end of the third inverter, the output end of the fourth inverter and the input end of the sixth inverter are electrically connected with the second reverse output data node respectively, and the control end of the fourth switch, the control end of the fifth switch and the control end of the sixth switch receive a second sub-enable signal of the first enable signal. The input end of the first inverter and the control end of the eighth switch receive a first sub-enable signal of a second enable signal, the input end of the second inverter and the control end of the seventh switch receive a second sub-enable signal of the second enable signal, the output end of the first inverter is electrically connected with the control end of the ninth switch, the second end of the ninth switch is electrically connected with the first end of the tenth switch, the control end of the tenth switch is electrically connected with the output end of the second inverter, and the second end of the seventh switch is electrically connected with the first end of the eighth switch. The control end of the eleventh switch and the control end of the twelfth switch receive a third enable signal. The output end of the fifth inverter outputs target output data, and the output end of the sixth inverter outputs target reverse output data.

[0009] In some embodiments of the present disclosure, the memory array unit group driving module comprises a data selection unit and a serial output order adjustment unit. The data selection unit is configured to determine second output data corresponding to different sampling time instants of each data line according to first output data corresponding to different data lines at different sampling time instants. The serial output order adjustment unit is configured to adjust the serial output order of the second output data corresponding to different sampling time instants of each data line to obtain second target output data corresponding to different sampling time instants of each data line.

[0010] In some embodiments of the present disclosure, the serial output order adjustment unit comprises a plurality of sub-selection units, each of the sub-selection units receives second output data corresponding to the i-th sampling time instant and the n / 2+i-th sampling time instant of the same data line, wherein n is the total number of sampling time instants of each data line, and the number of the sub-selection units is n / 2. The sub-selection unit is configured to receive second output data corresponding to the i-th sampling time instant and the n / 2+i-th sampling time instant of the same data line, and when the selection signal is low, the first node outputs the second output data corresponding to the i-th sampling time instant and the second node outputs the second output data corresponding to the n / 2+i-th sampling time instant, and when the selection signal is high, the first node outputs the second output data corresponding to the n / 2+i-th sampling time instant and the second node outputs the second output data corresponding to the i-th sampling time instant.

[0011] In some embodiments of the present disclosure, the sub-selection unit comprises a first NAND gate, a second NAND gate, a third NAND gate, a seventh inverter, an eighth inverter, a ninth inverter, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a thirteenth switch, a fourteenth switch, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth inverter, an eleventh inverter, a twelfth inverter, a tenth NAND gate, an eleventh NAND gate, a twelfth NAND gate, a fifteenth switch, and a sixteenth switch. The first input end of the first NAND gate, the first input end of the second NAND gate, the first input end of the fourth NAND gate, the first input end of the fifth NAND gate, the first input end of the seventh NAND gate, the first input end of the eighth NAND gate, the first input end of the tenth NAND gate and the first input end of the eleventh NAND gate respectively receive a selection signal, the second input end of the first NAND gate, the input end of the eighth inverter, the second input end of the eighth NAND gate and the input end of the twelfth inverter respectively receive the second output data corresponding to the n / 2+i sampling moment of a data line, the second input end of the second NAND gate, the input end of the ninth inverter, the second input end of the seventh NAND gate and the input end of the eleventh inverter respectively receive the second output data corresponding to the i sampling moment of a data line, the first input end of the third NAND gate is electrically connected with the output end of the first NAND gate, the second input end of the third NAND gate is electrically connected with the output end of the second NAND gate, the output end of the third NAND gate is electrically connected with the input end of the seventh inverter, the output end of the seventh inverter is electrically connected with the control end of the thirteenth switch, the first input end of the sixth NAND gate is electrically connected with the output end of the fourth NAND gate, the second input end of the sixth NAND gate is connected with the output end of the fifth NAND gate, the output end of the sixth NAND gate is electrically connected with the control end of the fourteenth switch, the first input end of the ninth NAND gate is electrically connected with the output end of the seventh NAND gate, the second input end of the ninth NAND gate is electrically connected with the output end of the eighth NAND gate, the output end of the ninth NAND gate is electrically connected with the input end of the tenth inverter, the output end of the tenth inverter is electrically connected with the control end of the fifteenth switch, the first input end of the twelfth NAND gate is electrically connected with the output end of the tenth NAND gate, the second input end of the twelfth NAND gate is electrically connected with the output end of the eleventh NAND gate, the output end of the twelfth NAND gate is electrically connected with the control end of the sixteenth switch, the first end of the thirteenth switch and the fifteenth switch is electrically connected with a power voltage node, the second end of the fourteenth switch and the second end of the sixteenth switch is electrically connected with a reference voltage node, the second end of the thirteenth switch is electrically connected with the first end of the fourteenth switch, the second end of the fifteenth switch is electrically connected with the first end of the sixteenth switch.

[0012] In some embodiments of the present disclosure, the memory data reading circuit further comprises a DM data line, which is a bidirectional data line, and the memory array unit driving module sends the data bus inversion enable signal to the memory array unit group driving module through the DM data line.

[0013] In some embodiments of the present disclosure, the data selection module comprises a first data processing unit and a second data processing unit. The first data processing unit is configured to determine third output data corresponding to different data lines at each sampling time according to second target output data corresponding to different data lines at different sampling times. The second data processing unit is configured to determine a target sampling time corresponding to a high level of the data bus inversion enable signal according to the data bus inversion enable signal corresponding to each sampling time, and screen third target output data corresponding to each data line at the target sampling time from the third output data corresponding to different data lines at each sampling time, and output the third target output data corresponding to each data line at the target sampling time through the data transmission port after inverting the third target output data.

[0014] In a second aspect, according to the content of the present disclosure, a memory is provided, comprising the memory data reading circuit of any one of the first aspect.

[0015] The memory data reading circuit and the memory provided by the embodiments of the present disclosure first determine first output data corresponding to different data lines at each sampling time according to output data read from a storage array, and determine a data bus inversion enable signal corresponding to each sampling time according to the first output data corresponding to different data lines at each sampling time; then the memory array unit group driving module determines second output data corresponding to different data lines at different sampling times according to the first output data corresponding to different data lines at each sampling time, adjusts the serial output order of the second output data corresponding to different data lines at different sampling times, obtains second target output data corresponding to different data lines at different sampling times, and receives the data bus inversion enable signal corresponding to each sampling time; finally, the third output data corresponding to different data lines at each sampling time is determined according to the second target output data corresponding to different data lines at different sampling times, and the third output data corresponding to different data lines at each sampling time is processed according to the data bus inversion enable signal corresponding to each sampling time, and then output through the data transmission port. By changing the storage mode of the output data in the memory array unit driving module, the output data read from the storage array is stored as a group of first output data of different data lines at the same sampling time, and then the data bus inversion enable signal corresponding to each sampling time is calculated in advance in the memory array unit driving module according to the first output data of different data lines at the same sampling time stored in the memory array unit driving module. Therefore, the data selection module can directly obtain the data bus inversion enable signal from the memory array unit driving module in the process of processing the output data, which reduces the waiting time of the read data and improves the data reading efficiency of the memory.

[0016] The above description is only a summary of the technical solutions of the embodiments of the present application. In order to make the technical means of the embodiments of the present application more clear, they can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, not limit the present disclosure. Among them: Figure 1 is a structural schematic diagram of a memory data reading circuit provided by an embodiment of the present disclosure; Figure 2 is a chip architecture structural schematic diagram of a memory provided by an embodiment of the present disclosure; Figure 3 is a structural schematic diagram of another memory data reading circuit provided by an embodiment of the present disclosure; Figure 4 is a circuit structural schematic diagram of an output data processing unit provided by an embodiment of the present disclosure; Figure 5 is a circuit structural schematic diagram of a memory array unit group driving module provided by an embodiment of the present disclosure; Figure 6 is a circuit structural schematic diagram of a sub-selection unit provided by an embodiment of the present disclosure.

[0018] In the drawings, the last two digits of the same mark correspond to the same element. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0019] In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative labor also belong to the scope of protection of the present disclosure.

[0020] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts or components are "connected" or "coupled" together shall mean that the parts are joined or operate together either directly or through one or more intermediate parts or components.

[0021] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiment, or to a single alternative embodiment.

[0022] The term "and / or", merely describes association relationship of associated objects, which means that there can be three relationships, for example, A and / or B, which can represent three cases of existence of A, existence of A and B, and existence of B. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0023] In addition, in all embodiments of the present disclosure, terms such as "first" and "second" are only used to distinguish one component (or part of component) from another component (or another part of component).

[0024] In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is more than two (including two), and similarly, "a plurality of groups" means more than two groups (including two groups).

[0025] In order to enable persons skilled in the art to better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings.

[0026] Based on the problems existing in the prior art, the present embodiment provides a memory data reading circuit, Figure 1 is a structural schematic diagram of a memory data reading circuit provided by the present embodiment, like Figure 1As shown, the memory data reading circuit includes: a memory array unit driving module 10, a memory array unit group driving module 20 and a data selection module 30; the memory array unit driving module 10 is configured to determine the first output data corresponding to different data lines at each sampling time according to the output data read from the storage array, and determine the data bus flip enable signal corresponding to each sampling time according to the first output data corresponding to different data lines at each sampling time; the memory array unit group driving module 20 is configured to determine the second output data corresponding to different sampling times of each data line according to the first output data corresponding to different data lines at each sampling time, and adjust the serial output order of the second output data corresponding to different sampling times of each data line to obtain the second target output data corresponding to different sampling times of each data line, and receive the data bus flip enable signal corresponding to each sampling time; the data selection module 30 is configured to determine the third output data corresponding to different data lines at each sampling time according to the second target output data corresponding to different sampling times of each data line, and after processing the third output data corresponding to different data lines at each sampling time according to the data bus flip enable signal corresponding to each sampling time, output through the data transmission port.

[0027] The memory data reading circuit provided by the embodiments of the present disclosure is applied to a DDR4 memory. Specifically, when the DDR4 memory transmits 8-bit data at the same sampling time, if the number of data "0" exceeds 4 bits, the transmitted data byte at the sampling time is flipped and then transmitted, and the DM pin is set to low to indicate this operation; if the number of "0" does not exceed 4 bits, the original data is directly transmitted and the DM port is set to high. When reading DRAM data, the controller receiving end determines whether to perform inverse flipping on the data to recover the original value according to the DM state.

[0028] Taking an x8, BL8 mode as an example, x8 represents that the memory has 8 ports to transmit data, which are DQ0~DQ7 in the table, and they are parallel transmission data. BL8 represents that the data burst length is 8, such as burst0~burst7 in Table 1, which are serially transmitted in order. For example, burst0 of each DQ is transmitted at t0 sampling time, burst1 of each DQ is transmitted at t1 sampling time, and so on. Therefore, the read and write operation of the memory is 8bit*8 times=64bit data.

[0029] Table 1: Data transmission diagram when DBI is not turned on

[0030] The default value of the DM port of the DDR4 is high level "1", when the circuit transmits "0", the port voltage needs to be pulled down, and the level conversion process will increase the power consumption of the circuit, therefore, the less the port transmits "0", the better. For the memory write operation, the write data is provided by the controller, the controller calculates the number of "0" at the current sampling time, if the number of "0" is more than 4, the write data of the whole sampling time is flipped, and the data bus flip enable signal is set to 0. When the write DBI is turned on, the corresponding data of table 1 will be changed into the form of table 2 and input into the memory, the number of "0" in the write data of the sampling time corresponding to burst3 and burst7 is 6, the controller flips the write data and sets the corresponding data bus flip enable signal DM to 0, and the memory internally restores the data according to the values of DQ and DM and stores it into the memory array.

[0031] Table 2 data transmission diagram when DBI is turned on

[0032] For the memory read operation, 64bit data is taken out from the "memory array", and then it is calculated whether the data corresponding to each sampling time needs to be flipped, if it needs to be flipped, the data bus flip enable signal corresponding to the sampling time is set to 0, finally, the processed 64bit DQ and 8bit DM are sent to the controller together, based on this technology, the transmission power consumption between the memory and the controller can be reduced and the data integrity can be improved. However, the disadvantage of DBI is that the memory needs time to determine the number of "0" in the read data, therefore, the waiting time of the read data is increased.

[0033] Based on the problems existing in the prior art, the embodiment of the present disclosure provides a memory data reading circuit, which reduces the waiting time of the read data and improves the data reading efficiency of the memory.

[0034] Specifically, the chip architecture of the DDR4 memory is as shown in Figure 2 The "memory array" includes 4 memory array unit groups (BG), each memory array unit group includes 4 memory array units (BA), the memory array unit group is selected according to the address BG<1:0> of the write data, the memory array unit is selected according to the address BA<1:0> of the write data, in an implementable manner, one memory array unit is divided into two memory array unit blocks.

[0035] For the data write operation of the DDR4 memory, the external controller writes data into the DDR4 memory through the DQ0~7 pins, wherein the DDR4 memory comprises 8 DQ pins in total, each DQ pin is connected with a data line, and 8 bits of data are serially transmitted through each data line (i.e. the data corresponding to 8 sampling moments), which is equivalent to 8 times of transmission, and 1 bit of data is transmitted through each DQ each time. In addition, the DDR4 memory also has a DM pin, the DM pin receives a data bus inversion enable signal and serially transmits 8 bits of data through the connected data line. During the writing, the DDR4 memory judges whether each sampling moment needs to be recovered according to the data bus inversion enable signal. During the reading, whether each sampling moment needs to be inverted is calculated, and the result is output to the external controller through the DM pin.

[0036] Firstly, 64 bits of DQ data and 8 bits of DM data are transmitted to the data selection module through the DQ pin and the DM pin, and then in the data selection module, the 64 bits of data are transmitted to the corresponding memory array unit group driving module according to the address information corresponding to the 64 bits of data. In a preferred implementation manner, each memory array unit group driving module corresponds to a data driving circuit, so as to avoid the increase of data delay caused by long distance transmission. The memory array unit group driving module is used for transmitting the 64 bits of data to each memory array unit driving module, and the data is written into the corresponding memory through the memory array unit driving module.

[0037] For the data read operation, the transmission path is basically the same as that of the write operation, and the advantage of path multiplexing is to save the data line channel. The data line channel for reading and writing is 2 times of that in the multiplexing.

[0038] Then, when the memory performs the read operation, the number of "0"s in the 8 bits of data in each sampling moment needs to be judged, therefore, the application adjusts the correspondence between the storage position in the memory array unit driving module and the data, so as to determine the first output data corresponding to different data lines in each sampling moment according to the output data read from the memory array. In a specific example, MIOT<7:0> represents the first output data corresponding to different data lines in the first sampling moment, MIOT<15:8> represents the first output data corresponding to different data lines in the second sampling moment, and so on, and MIOT<63:56> represents the first output data corresponding to different data lines in the eighth sampling moment.

[0039] After the first output data corresponding to different data lines in each sampling moment is determined, the data bus inversion enable signal corresponding to each sampling moment can be determined according to the first output data corresponding to different data lines in each sampling moment.

[0040] Then the memory array unit group driving module, according to the first output data corresponding to different data lines at different sampling time, changes the connection relationship between the memory array unit driving module and the memory array unit group driving module, converts the first output data corresponding to different data lines at different sampling time into the second output data corresponding to each data line at different sampling time, adjusts the serial output order of the second output data corresponding to each data line at different sampling time, obtains the second target output data corresponding to each data line at different sampling time, and the memory array unit group driving module receives the data bus inversion enable signal corresponding to each sampling time determined by the memory array unit driving module.

[0041] Further, by changing the connection relationship between the memory array unit group driving module and the data selection module, the second target output data corresponding to each data line at different sampling time is converted into the third output data corresponding to different data lines at different sampling time, and finally, according to the data bus inversion enable signal corresponding to each sampling time, the third output data corresponding to different data lines at different sampling time is processed and output through the data transmission port.

[0042] The memory data reading circuit provided by the embodiments of the present disclosure first determines the first output data corresponding to different data lines at each sampling moment according to the output data read from the memory array, and determines the data bus flip enable signal corresponding to each sampling moment according to the first output data corresponding to different data lines at each sampling moment; then the memory array unit group driving module determines the second output data corresponding to different sampling moments of each data line according to the first output data corresponding to different data lines at each sampling moment, and adjusts the serial output order of the second output data corresponding to different sampling moments of each data line to obtain the second target output data corresponding to different sampling moments of each data line, and receives the data bus flip enable signal corresponding to each sampling moment; finally, the third output data corresponding to different data lines at each sampling moment is determined according to the second target output data corresponding to different sampling moments of each data line, and the third output data corresponding to different data lines at each sampling moment is processed according to the data bus flip enable signal corresponding to each sampling moment, and then output through the data transmission port. By changing the storage mode of the output data in the memory array unit driving module, the output data read from the memory array is stored as a group of first output data of different data lines at the same sampling moment, and then the data bus flip enable signal corresponding to each sampling moment is calculated in advance in the memory array unit driving module according to the first output data of different data lines at the same sampling moment stored in the memory array unit driving module. Therefore, the data selection module can directly obtain the data bus flip enable signal from the memory array unit driving module in the process of processing the output data, thereby reducing the waiting time of the read data and improving the data reading efficiency of the memory.

[0043] In the specific implementation process, the memory array unit driving module 10 includes an output data processing unit 11 and a data bus flip enable signal determination unit 12. Figure 3 The output data processing unit 11 is configured to determine the reverse output data corresponding to the output data according to the output data read from the memory array, and output the target output data and the target reverse output data after signal amplification of the output data and the reverse output data; and the data bus flip enable signal determination unit 12 is configured to determine the first output data corresponding to different data lines at each sampling moment according to the target output data, and determine the data bus flip enable signal corresponding to each sampling moment according to the first output data corresponding to different data lines at each sampling moment.

[0044] Specifically, in combination with Figure 3 and Figure 4The output data processing unit 11 comprises a first switch subunit 110, a second switch subunit 111, a third switch subunit 112, and an amplification subunit 113. The first switch subunit 110 is configured to, in a memory read operation state, control the path between the first output data node A1 and the first reverse output data node B1 to be off according to the received first enable signal, and control the path between the second output data node and the second reverse output data node to be off, wherein the first output data node receives output data, and the first reverse output data node receives reverse output data. The second switch subunit 111 is configured to, in the memory read operation state, control the second switch subunit 111 to be off according to the received second enable signal. The third switch subunit 112 is configured to, in the memory read operation state, control the third switch subunit to be on according to the received third enable signal, so as to make the path between the first output data node A1 and the second output data node A2 to be on, and the path between the first reverse output data node B1 and the second reverse output data node B2 to be on. The amplification subunit 113 is configured to amplify and output the target output data BITT and the target reverse output data BITB after amplifying the output data and the reverse output data.

[0045] The first switch subunit 110 includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, and a sixth switch K6, the second switch subunit 111 includes a first inverter F1, a second inverter F2, a seventh switch K7, an eighth switch K8, a ninth switch K9, and a tenth switch K10, the third switch subunit 112 includes an eleventh switch K11 and a twelfth switch K12, and the amplification subunit 113 includes a third inverter F3, a fourth inverter F4, a fifth inverter F5, and a sixth inverter F6; the first end of the first switch K1, the first end of the third switch K3, the first end of the seventh switch K7, the first end of the ninth switch K9, and the first end of the eleventh switch K11 are electrically connected with the first output data node A1, the second end of the first switch K1 is electrically connected with the first end of the second switch K2, the second end of the second switch K2, the second end of the third switch K3, the second end of the eighth switch K8, the second end of the tenth switch K10, and the second end of the twelfth switch K12 are electrically connected with the first reverse output data node B1, the control end of the first switch K1, the control end of the second switch K2, and the control end of the third switch K3 receive the first sub-enable signal DMIOEQB of the first enable signal; the first end of the fourth switch K4, the first end of the sixth switch K6, the second end of the eleventh switch K11, the output end of the third inverter F3, the input end of the fourth inverter F4, and the input end of the fifth inverter F5 are electrically connected with the second output data node A2, the second end of the fourth switch K4 is electrically connected with the first end of the fifth switch K5, the second end of the fifth switch K5, the second end of the sixth switch K6, the second end of the twelfth switch K12, the input end of the third inverter F3, the output end of the fourth inverter F4, and the input end of the sixth inverter F6 are electrically connected with the second reverse output data node B2, the control end of the fourth switch K4, the control end of the fifth switch K5, and the control end of the sixth switch K6 receive the second sub-enable signal DRAEQB of the first enable signal; the input end of the first inverter F1 and the control end of the eighth switch K8 receive the first sub-enable signal WRT of the second enable signal, the input end of the second inverter F2 and the control end of the seventh switch K7 receive the second sub-enable signal WRB of the second enable signal, the output end of the first inverter F1 is electrically connected with the control end of the ninth switch K9, the second end of the ninth switch K9 is electrically connected with the first end of the tenth switch K10, the control end of the tenth switch K10 is electrically connected with the output end of the second inverter F2, the second end of the seventh switch K7 is electrically connected with the first end of the eighth switch K8; the control end of the eleventh switch K11 and the control end of the twelfth switch K12 receive the third enable signal DRATGB; the output end of the fifth inverter F5 outputs the target output data, and the output end of the sixth inverter F6 outputs the target reverse output data BITB.

[0046] As Figure 3As shown, the memory array unit driver module 10 includes an output data processing unit 11 and a data bus toggle enable signal determination unit 12. The output data processing unit 11 first reads the output data from the memory array. The inverse output data corresponding to the output data can be determined based on the output data. Then, the output data and the inverse output data are amplified to obtain the target output data and the target inverse output data.

[0047] Among them, such as Figure 4 As shown, in the read operation state of the memory, the first sub-enable signal DMIOEQB and the second sub-enable signal DRAEQB of the first enable signal are at a high level "1", the first sub-enable signal WRT of the second enable signal and the second sub-enable signal WRB of the second enable signal are at a high level "1", the third enable signal DRATGB is at a low level "0", the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5 and the sixth switch K6 in the first switch sub-unit 110 are turned off, and the first output data node A1 (the first output data node A1 receives output data) and the first inverted output data node B1 (the first inverted output data node B1 receives inverted output data) are... The connection between the first output data node A1 and the second output data node B2 is broken. The seventh switch K7, the eighth switch K8, the ninth switch K9 and the tenth switch K10 of the second switch subunit 111 are turned off. The eleventh switch K11 and the twelfth switch K12 of the third switch subunit 112 are turned on. At this time, the path between the first output data node A1 and the second output data node A2 is turned on, and the path between the first reverse output data node B1 and the second reverse output data node B2 is turned on. This enables the output data and the reverse output data to be sent to the amplification subunit 113. The amplification subunit 113 amplifies the output data and the reverse output data and outputs the target output data and the target reverse output data.

[0048] After the output data processing unit amplifies the output data and outputs the target output data and the target inverse output data, the output data processing unit 11 of the memory array unit driver module 10 sends the target output data BITT to the data bus flip enable signal determination unit 12. Based on the data bus flip enable signal determination unit 12, it determines the first output data corresponding to different data lines at each sampling time, and determines the data bus flip enable signal corresponding to each sampling time according to the first output data corresponding to different data lines at each sampling time. On the other hand, it sends the target inverse output data BITB to the memory array unit group driver module 20. Based on the memory array unit group driver module 20, it adjusts the serial output order of the second output data corresponding to different sampling times of each data line to obtain the second target output data corresponding to different sampling times of each data line.

[0049] On the basis of the above embodiments, in combination with Figure 3 and Figure 5 The memory array unit group driving module 20 comprises a data selection unit 21 and a serial output order adjustment unit 22; the data selection unit 21 is configured to determine the second output data corresponding to different sampling time instants of each data line according to the first output data corresponding to different data lines at each sampling time instant; the serial output order adjustment unit 22 is configured to adjust the serial output order of the second output data corresponding to different sampling time instants of each data line to obtain the second target output data corresponding to different sampling time instants of each data line.

[0050] The BITB<7:0> received by the data selection unit 21 is the first output data corresponding to different data lines at the first sampling time instant, the BITB<15:8> is the first output data corresponding to different data lines at the second sampling time instant, the BITB<23:16> is the first output data corresponding to different data lines at the third sampling time instant, the BITB<31:24> is the first output data corresponding to different data lines at the fourth sampling time instant, the BITB<39:32> is the first output data corresponding to different data lines at the fifth sampling time instant, the BITB<47:40> is the first output data corresponding to different data lines at the sixth sampling time instant, the BITB<55:48> is the first output data corresponding to different data lines at the seventh sampling time instant, and the BITB<63:56> is the first output data corresponding to different data lines at the eighth sampling time instant. After receiving the first output data corresponding to different data lines at each sampling time instant, the data selection unit 21 processes the data to obtain the second output data corresponding to different sampling time instants of each data line, for example, Figure 5 The DBITB<7:0> exemplarily represents the second output data of the first data line at different sampling time instants, and the second output data of the second data line at different sampling time instants is sequentially obtained in the same way, and so on.

[0051] In combination with Figure 3 and Figure 5 The serial output order adjustment unit 22 comprises a plurality of sub-selection units, each of which receives the second output data corresponding to the i-th sampling time instant and the n / 2+i-th sampling time instant of the same data line, wherein n is the total number of sampling time instants of each data line, and the number of sub-selection units is n / 2. The sub-selection unit is configured to receive the second output data corresponding to the i-th sampling moment and the n / 2+i-th sampling moment of the same data line, and when the selection signal is low, the first node outputs the second output data corresponding to the i-th sampling moment, and the second node outputs the second output data corresponding to the n / 2+i-th sampling moment; when the selection signal is high, the first node outputs the second output data corresponding to the n / 2+i-th sampling moment, and the second node outputs the second output data corresponding to the i-th sampling moment.

[0052] That is, when taking the x8, BL8 mode as an example, the memory has 8 ports to transmit data, and the data lines corresponding to the ports include 8 data lines. After the serial output order adjustment unit 22 receives the second output data DBITB<7:0> corresponding to different sampling moments of the first data line, at this time, the first sub-selection unit receives the second output data DBITB<0> and DBITB<4> corresponding to the first sampling moment and the fifth sampling moment of the first data line, the second sub-selection unit receives the second output data DBITB<1> and DBITB<5> corresponding to the second sampling moment and the sixth sampling moment of the first data line, the third sub-selection unit receives the second output data DBITB<2> and DBITB<6> corresponding to the third sampling moment and the seventh sampling moment of the first data line, and the fourth sub-selection unit receives the second output data DBITB<3> and DBITB<7> corresponding to the fourth sampling moment and the eighth sampling moment of the first data line. Similarly, after the serial output order adjustment unit 22 receives the second output data DBITB<15:8> corresponding to different sampling moments of the second data line.

[0053] As Figure 6As shown, the sub-selection unit includes a first NAND gate NA1, a second NAND gate NA2, a third NAND gate NA3, a seventh inverter F7, an eighth inverter F8, a ninth inverter F8, a fourth NAND gate NA4, a fifth NAND gate NA5, a sixth NAND gate NA6, a thirteenth switch K13, a fourteenth switch K14, a seventh NAND gate NA7, an eighth NAND gate NA8, a ninth NAND gate NA9, a tenth inverter F10, an eleventh inverter F11, a twelfth inverter F12, a tenth NAND gate NA10, an eleventh NAND gate NA11, a twelfth NAND gate NA12, a fifteenth switch K15, and a sixteenth switch K16;The first input terminal of the first NAND gate NA1, the first input terminal of the second NAND gate NA2, the first input terminal of the fourth NAND gate NA4, the first input terminal of the fifth NAND gate NA5, the first input terminal of the seventh NAND gate NA7, the first input terminal of the eighth NAND gate NA8, the first input terminal of the tenth NAND gate NA10 and the first input terminal of the eleventh NAND gate NA11 receive the selection signal DRAOLT<1:0> respectively, the second input terminal of the first NAND gate NA1, the input terminal of the eighth inverter F8, the second input terminal of the eighth NAND gate NA8 and the input terminal of the twelfth inverter F12 receive the second output data corresponding to the n / 2+i sampling moment of a data line respectively, the second input terminal of the second NAND gate NA2, the input terminal of the ninth inverter F9, the second input terminal of the seventh NAND gate NA7 and the input terminal of the eleventh inverter F11 receive the second output data corresponding to the i sampling moment of a data line respectively, the first input terminal of the third NAND gate NA3 is electrically connected with the output terminal of the first NAND gate NA1, the second input terminal of the third NAND gate NA3 is electrically connected with the output terminal of the second NAND gate NA2, the output terminal of the third NAND gate NA3 is electrically connected with the input terminal of the seventh inverter F7, the output terminal of the seventh inverter F7 is electrically connected with the control terminal of the thirteenth switch K13, the first input terminal of the sixth NAND gate NA6 is electrically connected with the output terminal of the fourth NAND gate NA4, the second input terminal of the sixth NAND gate NA6 is connected with the output terminal of the fifth NAND gate NA5, the output terminal of the sixth NAND gate NA6 is electrically connected with the control terminal of the fourteenth switch K14, the first input terminal of the ninth NAND gate NA9 is electrically connected with the output terminal of the seventh NAND gate NA7, the second input terminal of the ninth NAND gate NA9 is electrically connected with the output terminal of the eighth NAND gate NA8, the output terminal of the ninth NAND gate NA9 is electrically connected with the input terminal of the tenth inverter F10, the output terminal of the tenth inverter F10 is electrically connected with the control terminal of the fifteenth switch K15, the first input terminal of the twelfth NAND gate NA12 is electrically connected with the output terminal of the tenth NAND gate NA10, the second input terminal of the twelfth NAND gate NA12 is electrically connected with the output terminal of the eleventh NAND gate NA11, the output terminal of the twelfth NAND gate NA12 is electrically connected with the control terminal of the sixteenth switch K16, the first terminals of the thirteenth switch K13 and the fifteenth switch K15 are electrically connected with the power voltage node VDD, the second terminal of the fourteenth switch K14 and the second terminal of the sixteenth switch K16 are electrically connected with the reference voltage node VSS, the second terminal of the thirteenth switch K13 is electrically connected with the first terminal of the fourteenth switch K14, the second terminal of the fifteenth switch K15 is electrically connected with the first terminal of the sixteenth switch K16.

[0054] The memory array cell group driver module 20 serves two purposes: firstly, as a driver circuit for the memory array cell group, and secondly, to adjust the order of output data. It is known that at the DQ pin of the memory, the 8 bits of data for each DQ pin are output serially. However, the output data in the memory array is retrieved in parallel simultaneously. Therefore, the order of the serial output from the DQ pin can be adjusted by regulating the arrangement of the parallel output data. The memory data reading circuit provided in this embodiment adjusts the order of the first 4 bits and the last 4 bits of output data within the memory array cell group driver module.

[0055] Taking an 8-bit DQ data as an example, combined with Figure 5 and Figure 6 The data selection unit will DBITB <0> and DBITB <4> Pass the first sub-selection unit, and set DBITB <1> and DBITB <5> Passing to the second sub-selection unit, DBITB <2> and DBITB <6> Passing to the third sub-selection unit, DBITB <3> and DBITB <7> The selection signal is passed to the fourth sub-selection unit, and the first sub-selection unit determines the DBITB based on the selection signal DRAOLT<1:0>. <0> In DRRWBSB <0> The output is still in DRWBSB <4> Output, and determine DBITB <4> In DRWBSB <0> The output is still in DRWBSB <4> The output, the second sub-selection unit determines the DBITB based on the selection signal DRAOLT<1:0>. <1> In DRWBSB <1> The output is still in DRWBSB <5> Output, and determine DBITB <5> In DRWBSB <1> The output is still in DRWBSB <5> The output, the third sub-selection unit determines the DBITB based on the selection signal DRAOLT<1:0>. <2> In DRWBSB <2> The output is still in DRWBSB <6> Output, and determine DBITB <6> In DRWBSB <2> The output is still in DRWBSB <6> The output, the fourth sub-selection unit, determines the DBITB based on the selection signal DRAOLT<1:0>. <3> In DRWBSB <3> The output is still in DRWBSB <7> Output, and determine DBITB <7> In DRWBSB <3> The output is still in DRWBSB <7> Output.

[0056] For example, when the selection signal DRAOLT<1:0> is high ("1"), DBITB <0> In DRRWBSB <0> Output, DBITB <4> In DRWBSB <4> The output, when the selection signal DRAOLT<1:0> is low ("0"), is DBITB. <0> In DRRWBSB <4> Output, DBITB <4> In DRRWBSB <0> Output.

[0057] pass Figure 6The provided sub-selection unit enables the serial output order adjustment of the second output data corresponding to different sampling times of each data line, that is, the adjustment of the positions of the first 4 bits and the last 4 bits of the second output data corresponding to different sampling times of each data line.

[0058] In a specific implementation, the memory data read circuit also includes a DM data line, which is a bidirectional data transmission line. The memory array unit driver module sends the data bus flip enable signal to the memory array unit group driver module through the DM data line.

[0059] Since the data bus toggle enable signal corresponding to each sampling moment is pre-calculated in the memory array unit driver module, and the control of whether the output data is toggled is executed in the data selection module, it is necessary to transmit the data bus toggle enable signal corresponding to each sampling moment pre-calculated by the memory array unit driver module to the data selection module to control whether the output data is toggled. Because the data bus toggle enable signal corresponding to each sampling moment is not read from the memory array, there is no data bus toggle enable signal readout path from the memory array unit driver module to the data selection module in the original memory circuit. However, there is an input path for the data bus toggle enable signal from the data selection module to the memory array unit driver module. Therefore, this invention changes the DM data line corresponding to the input path of the data bus toggle enable signal from the data selection module to the memory array unit driver module to a bidirectional transmission path. No additional lines are needed; only the driver circuit type needs to be changed, and this modification does not affect the normal operating logic of the DM data line.

[0060] Based on the above embodiments, such as Figure 3 As shown, the data selection module 30 includes a first data processing unit 31 and a second data processing unit 32. The first data processing unit 31 is configured to determine the third output data corresponding to different data lines at each sampling time based on the second target output data corresponding to different sampling times of each data line. The second data processing unit is configured to determine the target sampling time corresponding to the high level of the data bus toggle enable signal based on the data bus toggle enable signal corresponding to each sampling time, and to filter out the third target output data corresponding to each data line at the target sampling time from the third output data corresponding to different data lines at each sampling time, and to output the third target output data corresponding to each data line at the target sampling time through the data transmission port after toggling the data.

[0061] Since the first output data corresponding to different data lines at each sampling time is converted into the second output data corresponding to different sampling times of each data line by the data selection unit 21 in the memory array unit group driver module 20, and the serial data output order of each data line is adjusted, the data output to the data selection module 30 is the second target output data corresponding to different sampling times of each data line after the serial output order adjustment. Therefore, the first data processing unit 31 firstly needs to convert the second target output data corresponding to different sampling times of each data line into the third output data corresponding to different data lines at each sampling time. Then, the second data processing unit determines the target sampling time corresponding to the high level of the data bus toggling enable signal according to the data bus toggling enable signal corresponding to each sampling time, and filters out the third target output data corresponding to each data line of the target sampling time from the third output data corresponding to different data lines at each sampling time. After toggling the third target output data corresponding to each data line of the target sampling time, it outputs it through the data transmission port. This realizes that during the memory read operation, the second target output data corresponding to the sampling time when the data bus toggling enable signal is high is output after signal toggling.

[0062] This application also provides a memory, including the memory data reading circuit described in any of the above embodiments, which has the beneficial effects of the memory data reading circuit described in any of the above embodiments. This disclosure will not provide specific details on this aspect.

[0063] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0064] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0065] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A memory data read circuit, characterized by, The application relates to a memory array unit driving module, a memory array unit group driving module and a data selection module. The memory array unit driving module is configured to determine first output data corresponding to different data lines at different sampling moments according to output data read from a storage array, and determine a data bus flip enable signal corresponding to each sampling moment according to the first output data corresponding to different data lines at different sampling moments. The memory array unit group driving module is configured to determine second output data corresponding to different sampling moments of each data line according to the first output data corresponding to different data lines at different sampling moments, adjust the serial output order of the second output data corresponding to different sampling moments of each data line, obtain second target output data corresponding to different sampling moments of each data line, and receive the data bus flip enable signal corresponding to each sampling moment. The data selection module is configured to determine third output data corresponding to different data lines at different sampling moments according to the second target output data corresponding to different sampling moments of each data line, process the third output data corresponding to different data lines at different sampling moments according to the data bus flip enable signal corresponding to each sampling moment, and output the third output data through a data transmission port. The memory array unit driving module comprises an output data processing unit and a data bus flip enable signal determination unit.

2. The circuit of claim 1, wherein, The output data processing unit is configured to determine reverse output data corresponding to output data read from a storage array, and output target output data and target reverse output data after signal amplification of the output data and the reverse output data. The data bus flip enable signal determination unit is configured to determine first output data corresponding to different data lines at different sampling moments according to the target output data, and determine a data bus flip enable signal corresponding to each sampling moment according to the first output data corresponding to different data lines at different sampling moments. The output data processing unit comprises a first switch subunit, a second switch subunit, a third switch subunit and an amplification subunit.

3. The circuit of claim 2, wherein, The first switch subunit is configured to control the off of a path between a first output data node and a first reverse output data node and the off of a path between a second output data node and a second reverse output data node according to a received first enable signal in a memory read operation state, wherein the first output data node receives output data, and the first reverse output data node receives reverse output data. The second switch subunit is configured to be off according to a received second enable signal in the memory read operation state. The third switch subunit is configured to be on in the memory read operation state according to a received third enable signal, so as to make the path between the first output data node and the second output data node on, and the path between the first reverse output data node and the second reverse output data node on. ​ The amplification subunit is configured to amplify and output target output data and target reverse output data after amplifying the output data and the reverse output data.

4. The circuit of claim 3, wherein, The first switch subunit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch, the second switch subunit includes a first inverter, a second inverter, a seventh switch, an eighth switch, a ninth switch and a tenth switch, the third switch subunit includes an eleventh switch and a twelfth switch, and the amplification subunit includes a third inverter, a fourth inverter, a fifth inverter and a sixth inverter. The first end of the first switch, the first end of the third switch, the first end of the seventh switch, the first end of the ninth switch and the first end of the eleventh switch are electrically connected with the first output data node respectively, the second end of the first switch is electrically connected with the first end of the second switch, the second end of the second switch, the second end of the third switch, the second end of the eighth switch, the second end of the tenth switch and the second end of the twelfth switch are electrically connected with the first reverse output data node respectively, and the control end of the first switch, the control end of the second switch and the control end of the third switch receive a first sub-enabling signal of a first enabling signal; the first end of the fourth switch, the first end of the sixth switch, the second end of the eleventh switch, the output end of the third inverter, the input end of the fourth inverter and the input end of the fifth inverter are electrically connected with the second output data node respectively, the second end of the fourth switch is electrically connected with the first end of the fifth switch, the second end of the fifth switch, the second end of the sixth switch, the second end of the twelfth switch, the input end of the third inverter, the output end of the fourth inverter and the input end of the sixth inverter are electrically connected with the second reverse output data node respectively, and the control end of the fourth switch, the control end of the fifth switch and the control end of the sixth switch receive a second sub-enabling signal of the first enabling signal. The input end of the first inverter and the control end of the eighth switch receive a first sub-enabling signal of a second enabling signal, the input end of the second inverter and the control end of the seventh switch receive a second sub-enabling signal of the second enabling signal, the output end of the first inverter is electrically connected with the control end of the ninth switch, the second end of the ninth switch is electrically connected with the first end of the tenth switch, the control end of the tenth switch is electrically connected with the output end of the second inverter, and the second end of the seventh switch is electrically connected with the first end of the eighth switch. The control end of the eleventh switch and the control end of the twelfth switch receive a third enabling signal. The output end of the fifth inverter outputs target output data, and the output end of the sixth inverter outputs target reverse output data.

5. The circuit of claim 2, wherein, The memory array unit group driving module includes a data selection unit and a serial output sequence adjustment unit. The data selection unit is configured to determine the second output data corresponding to different sampling time instants of each data line according to the first output data corresponding to different data lines at different sampling time instants; The serial output sequence adjustment unit is configured to adjust the serial output sequence of the second output data corresponding to different sampling time instants of each data line to obtain second target output data corresponding to different sampling time instants of each data line.

6. The circuit of claim 5, wherein, The serial output sequence adjustment unit comprises a plurality of sub-selection units, each of the sub-selection units receives the second output data corresponding to the i-th sampling time instant and the n / 2+i-th sampling time instant of the same data line, wherein n is the total number of sampling time instants of each data line, and the number of the sub-selection units is n / 2. The sub-selection unit is configured to receive the second output data corresponding to the i-th sampling time instant and the n / 2+i-th sampling time instant of the same data line, and when the selection signal is low, the first node outputs the second output data corresponding to the i-th sampling time instant, and the second node outputs the second output data corresponding to the n / 2+i-th sampling time instant; when the selection signal is high, the first node outputs the second output data corresponding to the n / 2+i-th sampling time instant, and the second node outputs the second output data corresponding to the i-th sampling time instant.

7. The circuit of claim 6, wherein, The sub-selection unit comprises a first NAND gate, a second NAND gate, a third NAND gate, a seventh inverter, an eighth inverter, a ninth inverter, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a thirteenth switch, a fourteenth switch, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth inverter, an eleventh inverter, a twelfth inverter, a tenth NAND gate, an eleventh NAND gate, a twelfth NAND gate, a fifteenth switch, and a sixteenth switch. The first input end of the first NAND gate, the first input end of the second NAND gate, the first input end of the fourth NAND gate, the first input end of the fifth NAND gate, the first input end of the seventh NAND gate, the first input end of the eighth NAND gate, the first input end of the tenth NAND gate and the first input end of the eleventh NAND gate respectively receive a selection signal, the second input end of the first NAND gate, the input end of the eighth inverter, the second input end of the eighth NAND gate and the input end of the twelfth inverter respectively receive second output data corresponding to an n / 2+i sampling moment of a data line, the second input end of the second NAND gate, the input end of the ninth inverter, the second input end of the seventh NAND gate and the input end of the eleventh inverter respectively receive second output data corresponding to an i sampling moment of a data line, the first input end of the third NAND gate is electrically connected with the output end of the first NAND gate, the second input end of the third NAND gate is electrically connected with the output end of the second NAND gate, the output end of the third NAND gate is electrically connected with the input end of the seventh inverter, the output end of the seventh inverter is electrically connected with the control end of the thirteenth switch, the first input end of the sixth NAND gate is electrically connected with the output end of the fourth NAND gate, the second input end of the sixth NAND gate is connected with the output end of the fifth NAND gate, the output end of the sixth NAND gate is electrically connected with the control end of the fourteenth switch, the first input end of the ninth NAND gate is electrically connected with the output end of the seventh NAND gate, the second input end of the ninth NAND gate is electrically connected with the output end of the eighth NAND gate, the output end of the ninth NAND gate is electrically connected with the input end of the tenth inverter, the output end of the tenth inverter is electrically connected with the control end of the fifteenth switch, the first input end of the twelfth NAND gate is electrically connected with the output end of the tenth NAND gate, the second input end of the twelfth NAND gate is electrically connected with the output end of the eleventh NAND gate, the output end of the twelfth NAND gate is electrically connected with the control end of the sixteenth switch, the first end of the thirteenth switch and the fifteenth switch is electrically connected with a power voltage node, the second end of the fourteenth switch and the second end of the sixteenth switch is electrically connected with a reference voltage node, the second end of the thirteenth switch is electrically connected with the first end of the fourteenth switch, the second end of the fifteenth switch is electrically connected with the first end of the sixteenth switch.

8. The circuit of claim 1, wherein, The memory data reading circuit further comprises a DM data line, which is a bidirectional data line, and the memory array unit driving module sends the data bus flip enable signal to the memory array unit group driving module through the DM data line.

9. The circuit of claim 1, wherein, The data selection module comprises a first data processing unit and a second data processing unit; The first data processing unit is configured to determine third output data corresponding to different data lines at different sampling moments according to second target output data corresponding to different sampling moments of different data lines. The second data processing unit is configured to determine a target sampling time corresponding to a high level of the data bus inversion enable signal according to the data bus inversion enable signal corresponding to each sampling time, screen third target output data corresponding to each data line at the target sampling time from third output data corresponding to each data line at each sampling time, and output the third target output data corresponding to each data line at the target sampling time through the data transmission port after inverting the third target output data.

10. A memory, comprising: A memory data reading circuit comprising the memory data reading circuit of any one of claims 1-9.

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