Switched capacitor circuit and electronic equipment

Abstract

The embodiment of the invention provides a switched capacitor circuit and electronic equipment, relates to the technical field of electronics, and is used for reducing the turn-on loss of the switched capacitor circuit. The switched capacitor circuit comprises two phases of SFIPS circuits, a plurality of auxiliary circuits are additionally arranged between the two phases of SFIPS circuits, and in the dead time of the switched capacitor circuit, voltage of a key node in one phase of SFIPS circuit can be transferred or clamped to a key node in the other phase of SFIPS circuit through the auxiliary circuits, so that the voltage difference between the two ends of a transistor in the two phases of SFIPS circuits is reduced, and the voltage difference between the two ends of the transistor in the two phases of SFIPS circuits is reduced. Therefore, the impact current of the transistor at the turn-on moment is reduced, and the turn-on loss of the switched capacitor circuit is reduced.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a switched capacitor circuit and electronic device. Background Technology

[0002] Electronic devices such as mobile phones, watches, and tablets achieve wired or wireless fast charging by outputting a voltage twice (or four times) higher than the battery voltage through a power adapter or wireless charging circuit. This high voltage is then reduced to half (or a quarter) of the battery voltage by a switched capacitor converter (SC) within the electronic device. This high voltage reduces transmission current and line loss while maintaining the same power output. Furthermore, the switched capacitor circuit (SC) is highly efficient in an open-loop manner. Combined with voltage or current regulation by the charging protocol control adapter or wireless charging circuit, the entire charging system of the electronic device can be made highly efficient, reducing heat dissipation and achieving super-fast charging.

[0003] Currently, the turn-on loss of switched capacitor circuits is a major factor limiting their efficiency. Summary of the Invention

[0004] This application provides a switched capacitor circuit and an electronic device including the switched capacitor circuit, for reducing the turn-on loss of the switched capacitor circuit.

[0005] A first aspect of this application provides a switched capacitor circuit, comprising at least one switched capacitor group. The switched capacitor group includes a first auxiliary circuit, a second auxiliary circuit, and a first-phase switched capacitor sub-circuit and a second-phase switched capacitor sub-circuit, interleaved and parallelly coupled between the input and output terminals. The first-phase and second-phase switched capacitor sub-circuits can be, for example, single-first interleaved second-stage (SFIPS) circuits. The first-phase and second-phase switched capacitor sub-circuits respectively include a first capacitor, a first-stage switching network, and a switched capacitor network. The switched capacitor network includes a second capacitor, a third capacitor, and a second-stage switching network. The first-stage switching network is coupled to both the input terminal and the first capacitor, and is used to adjust the on / off state between the first capacitor and the input terminal. The second-stage switching network is coupled to the first, second, and third capacitors, and is used to adjust the series-parallel relationship between the first, second, and third capacitors. A first auxiliary circuit is coupled between the first node and the second node, used to switch the voltage of the first node and the voltage of the second node during the period when both the first-phase switched capacitor sub-circuit and the second-phase switched capacitor sub-circuit are off. The first node is coupled to the negative terminal of the first capacitor of the first-phase switched capacitor sub-circuit, and the second node is coupled to the negative terminal of the first capacitor of the second-phase switched capacitor sub-circuit. A second auxiliary circuit is coupled between the third node and the fourth node, used to switch the voltage of the third node and the voltage of the fourth node during the period when both the first-phase switched capacitor sub-circuit and the second-phase switched capacitor sub-circuit are off. The third node is coupled to the negative terminals of the second capacitors of both the first-phase switched capacitor sub-circuit and the second-phase switched capacitor sub-circuit, and the fourth node is coupled to the negative terminals of the third capacitors of both the first-phase switched capacitor sub-circuit and the second-phase switched capacitor sub-circuit, respectively.

[0006] The switched capacitor circuit provided in this application embodiment has a first-phase switched capacitor sub-circuit and a second-phase switched capacitor sub-circuit connected in parallel with a staggered phase. Therefore, when the switched capacitor circuit operates in the first state, the voltage of the first node is twice the output voltage 2Vvo, and the voltage of the second node is 0. When the switched capacitor circuit operates in the second state, the voltage of the first node is 0, and the voltage of the second node is twice the output voltage 2Vvo. By setting a first auxiliary circuit in the switched capacitor circuit, the voltage conversion between the first node and the second node can be realized to pull down 2Vvo and pull up 0. For example, when the voltage of the first node is 2Vvo and the voltage of the second node is 0, after the voltage conversion between the first node and the second node, the voltage of the first node becomes less than 2Vvo, and the voltage of the second node becomes greater than 0. By changing the voltage of the first node and the second node, the voltage difference across some transistors in the first-stage switching network and the second-stage switching network can be changed, thereby reducing the "inrush" current of some transistors at the moment of turn-on. Similarly, when the switched capacitor circuit operates in the first state, the voltage of the third node is the output voltage Vvo, and the voltage of the fourth node is 0. When the switched capacitor circuit operates in the second state, the voltage at the third node is 0, and the voltage at the fourth node is the output voltage Vvo. By setting the aforementioned second auxiliary circuit in the switched capacitor circuit, the voltage conversion between the third and fourth nodes can be achieved, thus pulling Vvo low and pulling it high. By changing the voltage between the third and fourth nodes, the voltage difference across some transistors in the second-stage switching network can be changed, thereby reducing the "inrush" current of some transistors at the moment of turn-on. With the combined use of the first and second auxiliary circuits, the "inrush" current of some or all transistors in the switched capacitor circuit at the moment of turn-on can be reduced, the turn-on loss of the switched capacitor circuit can be reduced, and the efficiency and frequency of the switched capacitor circuit can be improved. After the frequency of the switched capacitor circuit is increased, the capacitance requirement in the switched capacitor circuit can be reduced, and the occupied area of ​​the switched capacitor circuit can be reduced. Moreover, after the voltage conversion between the third and fourth nodes, the voltage change rate (dv / dt) of the third and fourth nodes can be reduced, effectively reducing electromagnetic interference. Furthermore, the third node is coupled to both the first-phase and second-phase switched capacitor sub-circuits, and the fourth node is coupled to both the first-phase and second-phase switched capacitor sub-circuits. That is, the first-phase and second-phase switched capacitor sub-circuits share the second auxiliary circuit, which simplifies the structure of the switched capacitor circuit.

[0007] In one possible implementation, the first auxiliary circuit includes a first inductor, a fourth capacitor, a second inductor, and a fifth capacitor; the first inductor, the fourth capacitor, the second inductor, and the fifth capacitor are connected in series between the first node and the second node; the end of the second inductor facing the fourth capacitor is also coupled to a reference ground voltage terminal. The first auxiliary circuit only includes capacitors and inductors, requiring no change to the transistor topology of the switched capacitor circuit, making it easy to implement.

[0008] In one possible implementation, the first auxiliary circuit includes a bidirectional switching circuit coupled between the first and second nodes. The second auxiliary circuit includes only the bidirectional switching circuit, excluding capacitors and inductors, making it simple to manufacture and easy to implement.

[0009] In one possible implementation, the first auxiliary circuit includes a first switching transistor, a second switching transistor, and a third inductor; the first switching transistor, the third inductor, and the second switching transistor are connected in series between the first node and the second node. This structure of the first auxiliary circuit can achieve zero-voltage turn-on of the transistors in the switched capacitor circuit, greatly reducing the turn-on loss of the switched capacitor circuit and improving the efficiency and frequency of the switched capacitor circuit.

[0010] In one possible implementation, the first auxiliary circuit further includes a third switch and a fourth switch; the third switch is coupled between the end of the third inductor facing the first switch and the reference ground voltage terminal, and the fourth switch is coupled between the end of the third inductor facing the second switch and the reference ground voltage terminal. This structure of the first auxiliary circuit can achieve zero-voltage turn-on of the transistors in the switched capacitor circuit and can simplify the structure of the first auxiliary circuit.

[0011] In one possible implementation, the switched capacitor circuit includes multiple switched capacitor groups connected in parallel between the input and output terminals. By incorporating multiple staggered first-phase and second-phase switched capacitor sub-circuits in the switched capacitor circuit, the ripple of the charging voltage can be reduced, and the stability of the charging voltage can be improved.

[0012] In one possible implementation, the second-stage switching network includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the first terminal of the first transistor is coupled to the negative terminal of the first capacitor, and the second terminal of the first transistor is coupled to the first terminal of the second transistor and the positive terminal of the second capacitor, respectively; the second terminal of the second transistor is coupled to the output terminal and the first terminal of the third transistor, respectively; the second terminal of the third transistor is coupled to the negative terminal of the second capacitor and the first terminal of the fourth transistor, respectively; the second terminal of the fourth transistor is coupled to a reference ground voltage terminal; the first terminal of the fifth transistor is coupled to the positive terminal of the first capacitor, and the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor and the positive terminal of the third capacitor, respectively; the second terminal of the sixth transistor is coupled to the output terminal and the first terminal of the seventh transistor, respectively; the second terminal of the seventh transistor is coupled to the negative terminal of the third capacitor and the first terminal of the eighth transistor, respectively; and the second terminal of the eighth transistor is coupled to a reference ground voltage terminal.

[0013] In one possible implementation, the seventh transistor in the first-phase switched-capacitor sub-circuit and the third transistor in the second-phase switched-capacitor sub-circuit are the same transistor. And / or, the eighth transistor in the first-phase switched-capacitor sub-circuit and the fourth transistor in the second-phase switched-capacitor sub-circuit are the same transistor. This topology reduces the number of transistors in the switched-capacitor circuit and decreases its footprint.

[0014] In one possible implementation, both the first-phase switched capacitor sub-circuit and the second-phase switched capacitor sub-circuit include multi-stage series-coupled switched capacitor networks. The switched capacitor circuit also includes multiple second auxiliary circuits; each of the multiple second auxiliary circuits is coupled one-to-one with the multi-stage switched capacitor network. By setting multiple (N-stage) switched capacitor networks in each phase switched capacitor sub-circuit, the input voltage to output voltage ratio Vvi:Vvo can be 2. N+1 :1, to achieve a high transformation ratio and meet different application requirements. On this basis, each stage of the switching capacitor network is coupled with a second auxiliary circuit, which can reduce the "inrush" current of the transistor in each stage of the switching capacitor network at the moment of turn-on, thereby reducing the turn-on loss of the transistor.

[0015] In one possible implementation, the second-stage switching network in each stage of the switched capacitor network includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. In each stage of the switched capacitor network, the first terminal of the fourth transistor is coupled to the second terminal of the third transistor, and the second stage of the fourth transistor is coupled to a reference ground voltage terminal. The first terminal of the eighth transistor is coupled to the second terminal of the seventh transistor, and the second stage of the eighth transistor is coupled to a reference ground voltage terminal. In the first-stage switched capacitor network, the first terminal of the first transistor is coupled to the negative terminal of the first capacitor, and the second terminal of the first transistor is coupled to the first terminal of the second transistor and the positive terminal of the second capacitor, respectively. The first terminal of the fifth transistor is coupled to the positive terminal of the first capacitor, and the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, respectively. The first transistor's first terminal is coupled to the positive terminal of the third capacitor. In the switched capacitor network except for the first stage, the first terminal of the first transistor is coupled to the second terminal of the second transistor in the preceding stage's switched capacitor network, and the second terminal of the first transistor is coupled to the first terminal of the second transistor and the positive terminal of the second capacitor, respectively. The first terminal of the fifth transistor is coupled to the second terminal of the sixth transistor in the preceding stage's switched capacitor network, and the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor and the positive terminal of the third capacitor, respectively. In the last stage of the switched capacitor network, the second terminal of the second transistor, the first terminal of the third transistor, the second terminal of the sixth transistor, and the first terminal of the seventh transistor are all coupled to the output terminal. In the switched capacitor network except for the last stage, the second terminal of the second transistor is coupled to the first terminal of the seventh transistor, and the second terminal of the sixth transistor is coupled to the first terminal of the third transistor. This is a simple topology.

[0016] In one possible implementation, the seventh transistor of the last stage of the switched capacitor network in the first-phase switched capacitor sub-circuit is the same transistor as the third transistor of the last stage of the switched capacitor network in the second-phase switched capacitor sub-circuit. And / or, the eighth transistor of the last stage of the switched capacitor network in the first-phase switched capacitor sub-circuit is the same transistor as the fourth transistor of the last stage of the switched capacitor network in the second-phase switched capacitor sub-circuit. This topology reduces the number of transistors in the switched capacitor circuit and decreases its footprint.

[0017] In one possible implementation, the first-stage switching network includes a ninth transistor and a tenth transistor; the first terminal of the ninth transistor is coupled to the input terminal, and the second terminal of the ninth transistor is coupled to the positive terminal of the first capacitor and the first terminal of the fifth transistor, respectively; the first terminal of the tenth transistor is coupled to the negative terminal of the first capacitor and the first terminal of the first transistor, respectively, and the second terminal of the tenth transistor is coupled to the reference ground voltage terminal. This is a simple topology.

[0018] A second aspect of this application provides a switched capacitor circuit, comprising: a first-phase switched capacitor sub-circuit, a second-phase switched capacitor sub-circuit, a third-phase switched capacitor sub-circuit, and a fourth-phase switched capacitor sub-circuit connected in parallel between an input terminal and an output terminal; the first-phase switched capacitor sub-circuit and the second-phase switched capacitor sub-circuit are out of phase by 180°, the first-phase switched capacitor sub-circuit and the third-phase switched capacitor sub-circuit are out of phase by 90°, and the third-phase switched capacitor sub-circuit and the fourth-phase switched capacitor sub-circuit are out of phase by 180°; the first-phase switched capacitor sub-circuit, the second-phase switched capacitor sub-circuit, the third-phase switched capacitor sub-circuit, and the fourth-phase switched capacitor sub-circuit each include a first capacitor, a first-stage switching network, and a switched capacitor network, the switched capacitor network including a second capacitor, a third capacitor, and a second-stage switching network; the first A first-stage switching network is coupled to the input terminal and the first capacitor, respectively, and is used to adjust the on / off state between the first capacitor and the input terminal. A second-stage switching network is coupled to the first capacitor, the second capacitor, and the third capacitor, respectively, and is used to adjust the series-parallel relationship between the first capacitor, the second capacitor, and the third capacitor. A first bidirectional switching circuit is coupled between the fifth node and the sixth node, and is used to clamp the voltage of the sixth node to the fifth node during the period when both the first-phase switching capacitor sub-circuit and the second-phase switching capacitor sub-circuit are off. The fifth node is coupled to the negative terminal of the second capacitor of the first-phase switching capacitor sub-circuit and the negative terminal of the third capacitor of the second-phase switching capacitor sub-circuit, respectively, and the sixth node is coupled to the negative terminal of the third capacitor of the third-phase switching capacitor sub-circuit and the negative terminal of the second capacitor of the fourth-phase switching capacitor sub-circuit, respectively.

[0019] The switched capacitor circuit provided in this application embodiment has a first bidirectional switching circuit between the fifth and sixth nodes. When both the first and second phase switched capacitor sub-circuits are turned off, the third and fourth phase switched capacitor sub-circuits operate normally. At this time, the voltage at the sixth node can be clamped to the fifth node by the first bidirectional switching circuit. By changing the voltage at the fifth node, the voltage difference between the second-stage switching network in the first phase switched capacitor sub-circuit and some transistors in the second-stage switching network of the second phase switched capacitor sub-circuit is reduced, thereby reducing the "inrush" current at the moment of transistor turn-on and lowering transistor turn-on losses. Furthermore, the first bidirectional switching circuit has a simple structure, is easy to manufacture, and is readily implemented.

[0020] In one possible implementation, the switched capacitor circuit further includes a second bidirectional switching circuit. The second bidirectional switching circuit is coupled between the seventh and eighth nodes and is used to clamp the voltage of the eighth node to the seventh node during the period when both the first and second phase switched capacitor sub-circuits are off. The seventh node is coupled to the negative terminals of the third capacitors of the first and second phase switched capacitor sub-circuits, respectively. The eighth node is coupled to the negative terminals of the second capacitors of the third and fourth phase switched capacitor sub-circuits, respectively. By incorporating a second bidirectional switching circuit into the switched capacitor circuit, the voltage difference across some transistors in the second-stage switching network of the first and second phase switched capacitor sub-circuits can be reduced, thereby reducing the "inrush" current at the moment of transistor turn-on and lowering transistor turn-on losses.

[0021] In one possible implementation, the switched capacitor circuit further includes a third bidirectional switching circuit. This third bidirectional switching circuit is coupled between the ninth and tenth nodes and is used to clamp the voltage of the tenth node to the ninth node during the period when both the first and second phase switched capacitor sub-circuits are off. The ninth node is coupled to the negative terminal of the first capacitor of the first phase switched capacitor sub-circuit, and the tenth node is coupled to the negative terminal of the first capacitor of the third phase switched capacitor sub-circuit. By setting the third bidirectional switching circuit between the ninth and tenth nodes, the third phase switched capacitor sub-circuit operates normally when both the first and second phase switched capacitor sub-circuits are off. At this time, the voltage of the tenth node can be clamped to the ninth node by the third bidirectional switching circuit. By changing the voltage of the ninth node, the voltage difference across the transistors in the first-stage switching network of the first phase switched capacitor sub-circuit is reduced, thereby reducing the "inrush" current of the transistors at the moment of turn-on and lowering the transistor turn-on losses. Furthermore, the third bidirectional switching circuit has a simple structure, is easy to manufacture, and is easy to implement.

[0022] In one possible implementation, the switched capacitor circuit further includes a fourth bidirectional switching circuit. This fourth bidirectional switching circuit is coupled between the eleventh and twelfth nodes and is used to clamp the voltage at the twelfth node to the eleventh node during the period when both the first and second phase switched capacitor sub-circuits are off. The eleventh node is coupled to the negative terminal of the first capacitor of the second phase switched capacitor sub-circuit, and the twelfth node is coupled to the negative terminal of the first capacitor of the fourth phase switched capacitor sub-circuit. By setting the fourth bidirectional switching circuit between the eleventh and twelfth nodes, the fourth phase switched capacitor sub-circuit operates normally when both the first and second phase switched capacitor sub-circuits are off. At this time, the voltage at the twelfth node can be clamped to the eleventh node by the fourth bidirectional switching circuit. By changing the voltage at the eleventh node, the voltage difference across the transistors in the first-stage switching network of the second phase switched capacitor sub-circuit is reduced, thereby reducing the "inrush" current at the moment of transistor turn-on and lowering the transistor's turn-on losses. Furthermore, the fourth bidirectional switching circuit has a simple structure, is easy to manufacture, and is readily implemented.

[0023] In one possible implementation, each phase switched capacitor subcircuit includes a multi-stage series-coupled switched capacitor network, and the switched capacitor circuit includes multiple first bidirectional switching circuits; the multiple first bidirectional switching circuits are coupled one-to-one with the multi-stage switched capacitor network. By setting multiple (N-stage) switched capacitor networks in each phase switched capacitor subcircuit, the input voltage to output voltage ratio Vvi:Vvo can be 2. N+1 :1, to achieve a high transformation ratio and meet different usage needs.

[0024] In one possible implementation, the second-stage switching network includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first transistor's first terminal is coupled to the negative terminal of a first capacitor, and its second terminal is coupled to the first terminal of the second transistor and the positive terminal of the second capacitor. The second terminal of the second transistor is coupled to the output terminal and the first terminal of the third transistor. The second terminal of the third transistor is coupled to the negative terminal of the second capacitor and the first terminal of the fourth transistor. The second terminal of the fourth transistor is coupled to a reference ground voltage terminal. The first terminal of the fifth transistor is coupled to the positive terminal of the first capacitor, and its second terminal is coupled to the first terminal of the sixth transistor and the positive terminal of the third capacitor. The second terminal of the sixth transistor is coupled to the output terminal and the first terminal of the seventh transistor. The second terminal of the seventh transistor is coupled to the negative terminal of the third capacitor and the first terminal of the eighth transistor. The second terminal of the eighth transistor is coupled to a reference ground voltage terminal. This is a structurally simple topology.

[0025] In one possible implementation, the seventh transistor in the first-phase switched-capacitor sub-circuit and the third transistor in the second-phase switched-capacitor sub-circuit are the same transistor; or, the eighth transistor in the first-phase switched-capacitor sub-circuit and the fourth transistor in the second-phase switched-capacitor sub-circuit are the same transistor. This topology reduces the number of transistors in the switched-capacitor circuit and decreases its footprint.

[0026] In one possible implementation, the seventh transistor in the third-phase switched-capacitor sub-circuit is the same transistor as the third transistor in the fourth-phase switched-capacitor sub-circuit; or, the eighth transistor in the third-phase switched-capacitor sub-circuit is the same transistor as the fourth transistor in the fourth-phase switched-capacitor sub-circuit. This topology reduces the number of transistors in the switched-capacitor circuit and decreases its footprint.

[0027] In one possible implementation, the second-stage switching network in each stage of the switched capacitor network includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. In each stage of the switched capacitor network, the first terminal of the fourth transistor is coupled to the second terminal of the third transistor, and the second stage of the fourth transistor is coupled to a reference ground voltage terminal. The first terminal of the eighth transistor is coupled to the second terminal of the seventh transistor, and the second stage of the eighth transistor is coupled to a reference ground voltage terminal. In the first-stage switched capacitor network, the first terminal of the first transistor is coupled to the negative terminal of the first capacitor, and the second terminal of the first transistor is coupled to the first terminal of the second transistor and the positive terminal of the second capacitor, respectively. The first terminal of the fifth transistor is coupled to the positive terminal of the first capacitor, and the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, respectively. The first transistor's first terminal is coupled to the positive terminal of the third capacitor. In the switched capacitor network except for the first stage, the first terminal of the first transistor is coupled to the second terminal of the second transistor in the preceding stage's switched capacitor network, and the second terminal of the first transistor is coupled to the first terminal of the second transistor and the positive terminal of the second capacitor, respectively. The first terminal of the fifth transistor is coupled to the second terminal of the sixth transistor in the preceding stage's switched capacitor network, and the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor and the positive terminal of the third capacitor, respectively. In the last stage of the switched capacitor network, the second terminal of the second transistor, the first terminal of the third transistor, the second terminal of the sixth transistor, and the first terminal of the seventh transistor are all coupled to the output terminal. In the switched capacitor network except for the last stage, the second terminal of the second transistor is coupled to the first terminal of the seventh transistor, and the second terminal of the sixth transistor is coupled to the first terminal of the third transistor. This is a simple topology.

[0028] In one possible implementation, the seventh transistor of the last stage of the switched capacitor network in the first-phase switched capacitor sub-circuit is the same transistor as the third transistor of the last stage of the switched capacitor network in the second-phase switched capacitor sub-circuit. And / or, the eighth transistor of the last stage of the switched capacitor network in the first-phase switched capacitor sub-circuit is the same transistor as the fourth transistor of the last stage of the switched capacitor network in the second-phase switched capacitor sub-circuit. This topology reduces the number of transistors in the switched capacitor circuit and decreases its footprint.

[0029] In one possible implementation, the seventh transistor of the last stage of the switched capacitor network in the third-phase switched capacitor sub-circuit is the same transistor as the third transistor of the last stage of the switched capacitor network in the fourth-phase switched capacitor sub-circuit. And / or, the eighth transistor of the last stage of the switched capacitor network in the third-phase switched capacitor sub-circuit is the same transistor as the fourth transistor of the last stage of the switched capacitor network in the fourth-phase switched capacitor sub-circuit. This topology reduces the number of transistors in the switched capacitor circuit and decreases its footprint.

[0030] In one possible implementation, the first-stage switching network includes a ninth transistor and a tenth transistor; the first terminal of the ninth transistor is coupled to the input terminal, and the second terminal of the ninth transistor is coupled to the positive terminal of the first capacitor and the first terminal of the fifth transistor, respectively; the first terminal of the tenth transistor is coupled to the negative terminal of the first capacitor and the first terminal of the first transistor, respectively, and the second terminal of the tenth transistor is coupled to the reference ground voltage terminal. This is a simple topology.

[0031] A third aspect of this application provides a switched capacitor circuit, comprising: a first-phase switched capacitor sub-circuit, a second-phase switched capacitor sub-circuit, a third-phase switched capacitor sub-circuit, and a fourth-phase switched capacitor sub-circuit connected in parallel between an input terminal and an output terminal; the first-phase switched capacitor sub-circuit and the second-phase switched capacitor sub-circuit are out of phase by 180°, the first-phase switched capacitor sub-circuit and the third-phase switched capacitor sub-circuit are out of phase by 90°, and the third-phase switched capacitor sub-circuit and the fourth-phase switched capacitor sub-circuit are out of phase by 180°; each of the first-phase, second-phase, third-phase, and fourth-phase switched capacitor sub-circuit includes a first capacitor, a first-stage switching network, and a switched capacitor network, the switched capacitor network including a second capacitor, a third capacitor, and a second-stage switching network; the first-stage switching network is coupled to the input terminal and the first capacitor, and is used to adjust the on / off state between the first capacitor and the input terminal; the second-stage switching network is coupled to the first capacitor, the second capacitor, and the third capacitor, and is used to adjust the series-parallel relationship between the first capacitor, the second capacitor, and the third capacitor. A bidirectional switching circuit is coupled between the ninth and tenth nodes to clamp the voltage of the tenth node to the ninth node during the period when both the first and second phase switched capacitor subcircuits are off. The ninth node is coupled to the negative terminal of the first capacitor of the first phase switched capacitor subcircuit, and the tenth node is coupled to the negative terminal of the first capacitor of the third phase switched capacitor subcircuit. By setting a bidirectional switching circuit between the ninth and tenth nodes, the third phase switched capacitor subcircuit operates normally when both the first and second phase switched capacitor subcircuits are off. At this time, the voltage of the tenth node can be clamped to the ninth node by the third bidirectional switching circuit. By changing the voltage of the ninth node, the voltage difference across the transistor in the first-stage switching network of the first phase switched capacitor subcircuit is reduced, thereby reducing the "inrush" current of the transistor at the moment of turn-on and reducing the turn-on loss of the transistor. Moreover, the bidirectional switching circuit has a simple structure, simple manufacturing process, and is easy to implement.

[0032] A fourth aspect of this application provides a switched capacitor circuit, comprising: a first capacitor and a first switching network; the first capacitor is coupled to the first switching network, and the first switching network is used to adjust the on / off state between the first capacitor and an input terminal; a multi-stage series-coupled first switched capacitor network, each stage of the first switched capacitor network including a second capacitor and a second switching network; a second switching network coupled to both the second capacitor and the first switching network, and the second switching network is used to adjust the series and parallel connection between the second capacitor and the first capacitor; each stage of the first switched capacitor network further includes a thirteenth node coupled to the negative terminal of the second capacitor; a multi-stage series-coupled second switched capacitor network, each stage of the second switched capacitor network including a third capacitor and a third switching network; the third switching network coupled to both the third capacitor and the first switching network, and the third switching network is used to adjust the series and parallel connection between the third capacitor and the first capacitor; each stage of the second switched capacitor network further includes a fourteenth node coupled to the negative terminal of the third capacitor; and a plurality of auxiliary circuits, each auxiliary circuit being coupled to a thirteenth node and a fourteenth node respectively, for converting the voltage of the thirteenth node and the voltage of the fourteenth node during a period when the first switching network, the second switching network, and the third switching network are all off.

[0033] The switched capacitor circuit provided in this application includes a first switched capacitor network with multiple (N) stages connected in series and a second switched capacitor network with multiple (N) stages connected in series, which can achieve an input voltage to output voltage ratio Vvi:Vvo of 2. N+1 To achieve a high transformation ratio and meet different application requirements, an auxiliary circuit is connected between the first and second switched capacitor networks in each stage. This circuit reduces the "inrush" current of the transistors in each stage's first and second switched capacitor networks at the moment of turn-on, thereby reducing transistor turn-on losses.

[0034] A fifth aspect of the embodiments of this application provides an electronic device, including a switched capacitor circuit according to any one of the first to fourth aspects and a battery, wherein the switched capacitor circuit is coupled to the battery. Attached Figure Description

[0035] Figure 1 An architectural diagram of an electronic device provided in an embodiment of this application;

[0036] Figure 2 This is a schematic diagram of the connection relationship of a switched capacitor circuit provided in an embodiment of this application;

[0037] Figure 3 A schematic diagram of the topology of a switched capacitor circuit provided in an embodiment of this application;

[0038] Figure 4A An intermediate mode diagram of the switched capacitor circuit provided in the embodiments of this application;

[0039] Figure 4B An equivalent diagram of an intermediate mode of the switched capacitor circuit provided in the embodiments of this application;

[0040] Figure 5A Another intermediate mode diagram of a switched capacitor circuit provided in an embodiment of this application;

[0041] Figure 5B An equivalent diagram of another intermediate mode of the switched capacitor circuit provided in the embodiments of this application;

[0042] Figure 6A and Figure 6B A schematic diagram of a switched capacitor circuit provided in an embodiment of this application;

[0043] Figure 7A A schematic diagram of the topology of a second auxiliary circuit provided in an embodiment of this application;

[0044] Figure 7B This application provides a schematic diagram of a circuit control signal and its corresponding current and voltage waveforms.

[0045] Figure 7C This is a schematic diagram of the topology of a resonant network provided in an embodiment of this application;

[0046] Figure 8 A schematic diagram of the topology of another second auxiliary circuit provided in an embodiment of this application;

[0047] Figure 9A A schematic diagram of the topology of yet another second auxiliary circuit provided in an embodiment of this application;

[0048] Figure 9B This application provides a schematic diagram of a circuit control signal and its corresponding current and voltage waveforms.

[0049] Figure 10A A schematic diagram of the topology of yet another second auxiliary circuit provided in an embodiment of this application;

[0050] Figure 10B This is a schematic diagram of another circuit control signal and corresponding current and voltage waveforms provided in an embodiment of this application;

[0051] Figure 11A and Figure 11B A schematic diagram of the topology of a switched capacitor circuit provided in an embodiment of this application;

[0052] Figure 12A A schematic diagram of another switched capacitor circuit provided in an embodiment of this application;

[0053] Figure 12BA schematic diagram of another switched capacitor circuit topology provided in an embodiment of this application;

[0054] Figure 12C A schematic diagram of another switched capacitor circuit topology provided in an embodiment of this application;

[0055] Figure 13 A schematic diagram of the topology of another switched capacitor circuit provided in an embodiment of this application;

[0056] Figure 14A and Figure 14B A schematic diagram of the topology of another switched capacitor circuit provided in an embodiment of this application;

[0057] Figure 15A and Figure 15B A schematic diagram of the topology of another switched capacitor circuit provided in an embodiment of this application;

[0058] Figure 16A and Figure 16B A schematic diagram of the topology of another switched capacitor circuit provided in an embodiment of this application;

[0059] Figure 17 This is a schematic diagram of another switched capacitor circuit provided in an embodiment of this application. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0061] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0062] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0063] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0064] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0065] This application provides an electronic device, which may be a consumer electronics product, a home electronics product, an in-vehicle electronics product, or a financial electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronics products include smart door locks, televisions, refrigerators, and small rechargeable household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle DVDs, etc. Financial electronics products include ATMs and self-service electronic devices, etc.

[0066] This application does not impose any special restrictions on the specific form of the above-mentioned electronic device. For the sake of convenience, the following embodiments all use mobile phones as an example for illustration.

[0067] Figure 1 This is an architectural diagram of an electronic device provided in an embodiment of this application.

[0068] An electronic device 100 is provided in this application embodiment, such as Figure 1As shown, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 01, an antenna 02, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, a camera 193, and a display screen 194, etc.

[0069] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0070] The wireless communication function of electronic device 100 can be implemented through antenna 01, antenna 02, mobile communication module 150, wireless communication module 160, modem processor, and baseband processor.

[0071] The processor 110 may include one or more processing units, such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU).

[0072] Electronic device 100 implements display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connecting the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering.

[0073] Electronic device 100 can perform shooting functions through ISP, camera 193, video codec, GPU, display 194 and application processor.

[0074] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to perform data storage functions.

[0075] Internal memory 121 can be used to store one or more computer programs, which include instructions. Processor 110 can cause electronic device 100 to perform the methods provided in some embodiments of this application, as well as various functional applications and data processing, by executing the aforementioned instructions stored in internal memory 121.

[0076] Electronic device 100 can implement audio functions, such as music playback and recording, through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.

[0077] The sensor module 180 may include pressure sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, distance sensors, proximity sensors, fingerprint sensors, temperature sensors, touch sensors, ambient light sensors, bone conduction sensors, etc.

[0078] The power management module 141 connects the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and supplies power to the processor 110, internal memory 121, display screen 194, camera 193, and wireless communication module 160, etc. The power management module 141 can also monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance). In some other embodiments, the power management module 141 may also be located within the processor 110. In other embodiments, the power management module 141 and the charging management module 140 may be located in the same device.

[0079] The charging management module 140 is used to receive charging input from a charger. The charger can be a wireless charger or a wired charger (or adapter). In some wired charging embodiments, the charging management module 140 can receive charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 can receive wireless charging input via the wireless charging coil of the electronic device 100.

[0080] Figure 2 This is a schematic diagram of the connection relationship of a switched capacitor circuit provided in an embodiment of this application.

[0081] like Figure 2As shown, the charging management module 140 can be connected to the USB interface 130 via an overvoltage protection (OVP) circuit 131. When the OVP circuit 131 detects that the voltage connected to the USB interface 130 is too high (exceeding a threshold voltage), it can actively disconnect the charging management module 140 from the USB interface 130. For example, refer to... Figure 2 As shown, the charging management module 140 is specifically connected to the wireless charging coil 132 via a receive integrated circuit (Rx IC) 133. Furthermore, to achieve normal or fast charging of the battery, refer to... Figure 2 As shown, the charging management module 140 may include a switched capacitor converter (SC) for fast charging of the battery and a buck converter circuit BUCK for normal charging of the battery. The switched capacitor circuit SC and BUCK are connected to the USB interface 130 through the OVP protection circuit 131 and to the wireless charging coil 132 through the Rx IC 133.

[0082] The processor 110 or the charging management module 140 can detect the buck converter circuit BUCK or the switched capacitor circuit SC to charge the battery according to the charging protocol. Usually, the switched capacitor circuit SC and the buck converter circuit BUCK are buck converter circuits with a fixed buck ratio. For example, when the voltage on the input side of the switched capacitor circuit SC and the buck converter circuit BUCK is detected to be 5V according to the charging protocol, the buck converter circuit BUCK is controlled to convert the 5V voltage to a voltage slightly higher than the battery voltage, 2V, to charge the battery. Or, when the voltage on the input side of the switched capacitor circuit SC and the buck converter circuit BUCK is detected to be 20V according to the charging protocol, it is determined that this is a fast charging scenario, and the switched capacitor circuit SC is controlled to convert the 20V voltage to a voltage near the battery voltage to charge the battery.

[0083] When the battery voltage or capacity rises to a certain level, or when the charging power becomes excessive due to heat dissipation, the adapter or wireless charger needs to switch to a lower charging power (e.g., 40W). The voltage output from the adapter or wireless charger to the switched-capacitor circuit SC will drop to around 10V. To maintain the original charging current and ensure fast charging, the charging protocol controls the switched-capacitor circuit SC to use a 2:1 buck conversion to reduce the input 10V to around 5V to continue charging the battery. Of course, when the charging protocol further reduces the voltage of the adapter or wireless charger, it needs to further switch the switched-capacitor circuit SC to the buck conversion mode to ensure the output voltage remains around 5V, thus ensuring the effectiveness of fast charging.

[0084] That is, the switched capacitor circuit SC can receive an input voltage through its input terminals and provide an output voltage through its output terminals. The input voltage can be provided by a charger outside the electronic device 100 or by any node in the power network inside the electronic device 100. The switched capacitor circuit SC can generate an output voltage that is proportional to the input voltage and can output it to any node in the power network outside or inside the system.

[0085] Figure 3 This is a schematic diagram of the topology of a switched capacitor circuit provided in an embodiment of this application.

[0086] In some embodiments, such as Figure 3 As shown, the switched capacitor circuit SC includes: a first capacitor Cf1, a second capacitor Cf2, a third capacitor Cf3, a first-stage switching network 10, and a second-stage switching network 20. The first-stage switching network 10 includes a first switching network, and the second-stage switching network 20 includes a second switching network 21 and a third switching network 22.

[0087] The first capacitor Cf1 is coupled to the first-stage switching network 10 (i.e., the first switching network), which is used to adjust the continuity between the first capacitor Cf1 and the input terminal VI. The second switching network 21 is coupled to both the second capacitor Cf2 and the first-stage switching network 10, and is used to adjust the series-parallel connection between the second capacitor Cf2 and the first capacitor Cf1. The third switching network 22 is coupled to both the third capacitor Cf3 and the first-stage switching network 10, and is used to adjust the series-parallel connection between the third capacitor Cf3 and the first capacitor Cf1. The second and third switching networks 21 and 22 are coupled to the output terminal VO, used to output the stepped-down charging voltage.

[0088] For example, the second switching network 21 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4; the third switching network 22 includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8; and the first-stage switching network 10 includes a ninth transistor Q9 and a tenth transistor Q10.

[0089] The first terminal of the first transistor Q1 is coupled to the negative terminal of the first capacitor Cf1. The second terminal of the first transistor Q1 is coupled to the first terminal of the second transistor Q2 and the positive terminal of the second capacitor Cf2. The second terminal of the second transistor Q2 is coupled to the output terminal VO and the first terminal of the third transistor Q3. The second terminal of the third transistor Q3 is coupled to the negative terminal of the second capacitor Cf2 and the first terminal of the fourth transistor Q4. The second terminal of the fourth transistor Q4 is coupled to the reference ground voltage terminal GND.

[0090] The first terminal of the fifth transistor Q5 is coupled to the positive terminal of the first capacitor Cf1. The second terminal of the fifth transistor Q5 is coupled to the first terminal of the sixth transistor Q6 and the positive terminal of the third capacitor Cf3. The second terminal of the sixth transistor Q6 is coupled to the output terminal VO and the first terminal of the seventh transistor Q7. The second terminal of the seventh transistor Q7 is coupled to the negative terminal of the third capacitor Cf3 and the first terminal of the eighth transistor Q8. The second terminal of the eighth transistor Q8 is coupled to the reference ground voltage terminal GND.

[0091] The first terminal of the ninth transistor Q9 is coupled to the input terminal VI, and the second terminal of the ninth transistor Q9 is coupled to the positive terminal of the first capacitor Cf1 and the first terminal of the fifth transistor Q5. The first terminal of the tenth transistor Q10 is coupled to the negative terminal of the first capacitor Cf1 and the first terminal of the first transistor Q1, and the second terminal of the tenth transistor Q10 is coupled to the reference ground voltage terminal GND.

[0092] Among them, the first transistor Q1 to the tenth transistor Q10 all include a control electrode. Under the control of their control electrodes, the switch can switch its first and second electrodes between an on or off state. In the embodiments of this application, the transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs). Furthermore, in... Figure 3In the illustrated examples, only one transistor is shown at each transistor location. This is to understand that, to reduce resistance when the switch is on, two or more transistors could also be connected in parallel at each transistor location. In the embodiments of this application, transistors are classified into two types: negative (N) type transistors and positive (P) type transistors. A transistor includes a source, a drain, and a gate. The transistor's conduction (on), off, or open circuit can be controlled by controlling the level of the input gate. When the transistor is on, the source and drain conduct, generating an on-state current. Furthermore, the magnitude of the on-state current generated between the source and drain varies depending on the gate level. When the transistor is off, the source and drain do not conduct, and no current is generated. In the embodiments of this application, the transistor's gate is also referred to as the control electrode, the source as the first electrode, and the drain as the second electrode; or, the gate is referred to as the control electrode, the drain as the first electrode, and the source as the second electrode. Furthermore, an N-type transistor turns on when its control electrode is high, with its first and second terminals conducting, generating an on-state current between them. When its control electrode is low, it turns off, with no conduction between the first and second terminals, and no current is generated. A P-type transistor turns on when its control electrode is low, with its first and second terminals conducting, generating an on-state current. When its control electrode is high, it turns off, with no conduction between the first and second terminals, and no current is generated. The transistors used in the switches in the following schemes can all be referenced to the description here.

[0093] Figure 4A This is an intermediate mode diagram of the switched capacitor circuit provided in the embodiments of this application. Figure 4B An equivalent diagram of an intermediate mode of the switched capacitor circuit provided in the embodiments of this application.

[0094] like Figure 4A As shown, in the first mode, transistors Q1, Q3, Q6, Q8, and Q9 are turned on, while transistors Q2, Q4, Q5, Q7, and Q10 are turned off, connecting the capacitors to form... Figure 4B The equivalent circuit shown.

[0095] When implementing the 4:1 buck mode, in the first time period of a time cycle, such as Figure 4AAs shown, the first-stage switching network 10 connects the input terminal VI to the positive terminal of the first capacitor Cf1. The second switching network 21 connects the negative terminal of the first capacitor Cf1 to the positive terminal of the second capacitor Cf2, and connects the negative terminal of the second capacitor Cf2 to the output terminal VO. The third switching network 22 connects the negative terminal of the third capacitor Cf3 to the reference ground voltage terminal GND, and connects the positive terminal of the third capacitor Cf3 to the output terminal VO. The capacitors are connected as follows: Figure 4B The equivalent circuit shown has the following configuration: the first capacitor Cf1 and the second capacitor Cf2 are connected in series and then in parallel with the third capacitor Cf3 and the output terminal VO, respectively. When the system is stable: Vvi = Vcf1 + Vcf2 + Vvo, Vcf3 = Vvo; where Vvi is the input voltage, Vcf1 is the voltage across the first capacitor Cf1, Vcf2 is the voltage across the second capacitor Cf2, Vcf3 is the voltage across the third capacitor Cf3, and Vvo is the output voltage.

[0096] Figure 5A This is another intermediate mode diagram of a switched capacitor circuit provided in an embodiment of this application. Figure 5B An equivalent diagram of another intermediate mode of the switched capacitor circuit provided in the embodiments of this application.

[0097] like Figure 5A As shown, in the second mode, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5, the seventh transistor Q7, and the tenth transistor Q10 are turned on, while the first transistor Q1, the third transistor Q3, the sixth transistor Q6, the eighth transistor Q8, and the ninth transistor Q9 are turned off, connecting the various capacitors to form... Figure 5B The equivalent circuit shown.

[0098] In the second time period of a cycle, such as Figure 5A As shown, the first-stage switching network 10 connects the negative terminal of the first capacitor Cf1 to the reference ground voltage terminal GND. The second switching network 21 connects the positive terminal of the second capacitor Cf2 to the output terminal VO and the negative terminal of the second capacitor Cf2 to the reference ground voltage terminal GND. The third switching network 22 connects the positive terminal of the third capacitor Cf3 to the positive terminal of the first capacitor Cf1 and the negative terminal of the third capacitor Cf3 to the output terminal VO. The capacitors are connected as follows: Figure 5B The equivalent circuit shown has the first capacitor Cf1 and the third capacitor Cf3 connected in series, and then connected in parallel with the second capacitor Cf2 and the output terminal VO, respectively. When the system is stable: Vcf2 = Vvo, Vcf1 = Vcf2 + Vvo.

[0099] In summary, we can obtain Vvi = 4Vvo, Vcf1 = 2Vvo, Vcf2 = Vvo, and Vcf3 = Vvo, thus achieving a 4:1 voltage ratio conversion. That is, since the input voltage Vvi is four times the output voltage Vvo, therefore, when... Figure 3 The switched capacitor circuit SC shown is... Figure 4A and Figure 5A When operating in the mode shown, a voltage conversion ratio of 4:1 can be achieved. In this mode, the voltage Vcf1 across the first capacitor Cf1 is twice the output voltage Vvo, and each of the voltages Vcf2 across the second capacitor Cf2 and Vcf3 across the third capacitor Cf3 is equal to the output voltage Vvo.

[0100] Therefore, the first capacitor Cf1, the second capacitor Cf2, and the third capacitor Cf3 all have low voltage stress. Since the effective capacitance value is greatly affected by the DC bias voltage, lower voltage stress means fewer capacitors are required. Figure 3 The switched capacitor circuit SC shown has a relatively small board area.

[0101] Since the principle of switched capacitors is based on the mutual charging and discharging between capacitors. Figure 3 In the switched-capacitor circuit SC shown, the turn-off current of any transistor is very small (the tail of the "rush" current is close to zero), resulting in low turn-off losses. However, any transistor in the switched-capacitor circuit SC experiences a large "rush" current at the moment of turn-on, causing significant turn-on losses. These transistor turn-on losses are a major factor limiting the efficiency of the switched-capacitor circuit SC.

[0102] For example, taking the fourth transistor Q4 as an example, in the first mode, node A, coupled to the first terminal of the fourth transistor Q4, is connected in series with the output terminal VO, and the voltage at node A is equal to the voltage at the output terminal VO. In the second mode, the fourth transistor Q4 needs to be turned on. At the instant the fourth transistor Q4 is turned on, the voltage at the first terminal of the fourth transistor Q4 is equal to the voltage at the output terminal VO, and the voltage at the second terminal of the fourth transistor Q4 is equal to the voltage at the reference ground terminal GND. There is a large voltage difference between the first and second terminals of the fourth transistor Q4, resulting in a large "inrush" current at the instant the fourth transistor Q4 is turned on, thus causing a large turn-on loss.

[0103] Figure 6A and Figure 6B This is a schematic diagram of a switched capacitor circuit provided in an embodiment of this application.

[0104] This application provides a switched capacitor circuit, such as... Figure 6AAs shown, the switched capacitor circuit SC includes a switched capacitor bank; the switched capacitor bank includes a first-phase switched capacitor sub-circuit SC1 and a second-phase switched capacitor sub-circuit SC2, which are alternately coupled in parallel between the input terminal VI and the output terminal VO. For example, the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are coupled in parallel between the input terminal VI and the output terminal VO, and their phases are offset by 180°. That is, at any given time, the transistor turned on by the second-stage switching network 20A in the first-phase switched capacitor sub-circuit SC1 is completely different from the transistor turned on by the second-stage switching network 20B in the second-phase switched capacitor sub-circuit SC2. For example, when the first-phase switched capacitor sub-circuit SC1 enters… Figure 4A In the first mode shown, the second-phase switched capacitor sub-circuit SC2 then enters... Figure 5A The second mode is shown. The first phase switched capacitor sub-circuit SC1 enters... Figure 5A In the second mode shown, the second-phase switched capacitor sub-circuit SC2 then enters... Figure 4A The first mode is shown.

[0105] For example, the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are the same as described above. Figure 3 The switched capacitor circuits SC shown have the same structure. For example, the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are single-first interleaved second-stage (SFIPS) circuits.

[0106] For example, the first-phase switched capacitor sub-circuit SC1 includes a first switched capacitor network 1A and a second switched capacitor network 2A. The first switched capacitor network 1A includes a first capacitor Cf1A and a first-stage switching network 10A. The second switched capacitor network 2A includes a second capacitor Cf2A, a third capacitor Cf3A, and a second-stage switching network 20A. The first-stage switching network 10A is coupled to the input terminal VI and the second-stage switching network 20A, respectively. The second-stage switching network 20A is coupled to the output terminal VO. The first capacitor Cf1A is coupled to the first-stage switching network 10A, and the first-stage switching network 10A is used to adjust the on / off state between the first capacitor Cf1A and the input terminal VI. The second-stage switching network 20A is coupled to the first capacitor Cf1A, the second capacitor Cf2A, and the third capacitor Cf3A, respectively. The second-stage switching network 20A is used to adjust the series and parallel relationships among the third capacitor Cf3A, the second capacitor Cf2A, and the first capacitor Cf1A. The first-level switch network 10A includes, for example, the first switch network described above, and the second-level switch network 20A includes, for example, the second switch network 21 and the third switch network 22 described above.

[0107] The second-phase switched-capacitor sub-circuit SC2 also includes a first switched-capacitor network 1B and a second switched-capacitor network 2B. The first switched-capacitor network 1B includes a first capacitor Cf1B and a first-stage switching network 10B. The second switched-capacitor network 2B includes a second capacitor Cf2B, a third capacitor Cf3B, and a second-stage switching network 20B. The first-stage switching network 10B is coupled to the input terminal VI and the second-stage switching network 20B, respectively. The second-stage switching network 20B is coupled to the output terminal VO. The first capacitor Cf1B is coupled to the first-stage switching network 10B, and the first-stage switching network 10B is used to adjust the on / off connection between the first capacitor Cf1B and the input terminal VI. The second-stage switching network 20B is coupled to the first capacitor Cf1B, the second capacitor Cf2B, and the third capacitor Cf3B, respectively. The second-stage switching network 20B is used to adjust the series and parallel connection relationship between the third capacitor Cf3B, the second capacitor Cf2B, and the first capacitor Cf1B. The first-level switch network 10B includes, for example, the first switch network described above, and the second-level switch network 20B includes, for example, the second switch network 21 and the third switch network 22 described above.

[0108] In some embodiments, such as Figure 6A As shown, the second-stage switching network 20A of the first-phase switched capacitor sub-circuit SC1 includes transistors Q1A, Q2A, Q3A, Q4A, Q5A, Q6A, Q7A, and Q8A. The first-stage switching network 10A includes transistors Q9A and Q10A. The connection relationships of the transistors can be found in the above description. Figure 3 The description.

[0109] The second-stage switching network 20B of the second-phase switched capacitor sub-circuit SC2 includes transistors Q1B, Q2B, Q3B, Q4B, Q5B, Q6B, Q7B, and Q8B. The first-stage switching network 10B includes transistors Q9B and Q10B. The connection relationships of these transistors can be found in the above description. Figure 3 The description.

[0110] In other embodiments, such as Figure 6B As shown, the seventh transistor Q7A in the first phase switched capacitor sub-circuit SC1 and the third transistor Q3B in the second phase switched capacitor sub-circuit SC2 are the same transistor.

[0111] Alternatively, the eighth transistor Q8A in the first-phase switched capacitor sub-circuit SC1 and the fourth transistor Q4B in the second-phase switched capacitor sub-circuit SC2 may be the same transistor.

[0112] Alternatively, the seventh transistor Q7B in the second-phase switched capacitor sub-circuit SC2 and the third transistor Q3A in the first-phase switched capacitor sub-circuit SC1 may be the same transistor.

[0113] Alternatively, the eighth transistor Q8B in the second-phase switched capacitor sub-circuit SC2 and the fourth transistor Q4A in the first-phase switched capacitor sub-circuit SC1 may be the same transistor.

[0114] This topology can reduce the number of transistors in the switched capacitor circuit SC and reduce the area occupied by the switched capacitor circuit SC.

[0115] The transistors in the interleaved parallel first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are complementary, which can be understood as a correspondence between on and off states. For example, if the ninth transistor Q9A in the first-phase switched capacitor sub-circuit SC1 is on, then the ninth transistor Q9B in the second-phase switched capacitor sub-circuit SC2 is off.

[0116] In some embodiments, such as Figure 6A As shown, the switched capacitor circuit SC also includes a second auxiliary circuit 32.

[0117] The second auxiliary circuit 32 is coupled between the third node A3 and the fourth node A4, and is used to switch the voltage of the third node A3 and the fourth node A4 during the period when both the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are off. The third node A3 is coupled to the negative terminal of the second capacitor Cf2A of the first phase switched capacitor sub-circuit SC1 and the negative terminal of the third capacitor Cf3B of the second phase switched capacitor sub-circuit SC2, respectively. The fourth node A4 is coupled to the negative terminal of the third capacitor Cf3A of the first phase switched capacitor sub-circuit and the negative terminal of the second capacitor Cf2B of the second phase switched capacitor sub-circuit SC2, respectively.

[0118] The aforementioned "transformation" can be understood as changing the voltage between nodes, shifting the high voltage between two nodes to a low voltage, and vice versa. For example, the voltage at the third node A3 can be transferred to the fourth node A4, or vice versa. The principle of voltage transformation between nodes varies depending on the auxiliary circuit architecture.

[0119] The switched capacitor circuit SC provided in this application embodiment has a first-phase switched capacitor sub-circuit SC1 and a second-phase switched capacitor sub-circuit SC2 connected in parallel with a 180° phase shift. Therefore, when the switched capacitor circuit operates in the first state, the voltage at the third node is the output voltage Vvo, and the voltage at the fourth node is 0. When the switched capacitor circuit operates in the second state, the voltage at the third node is 0, and the voltage at the fourth node is the output voltage Vvo. By setting the aforementioned second auxiliary circuit 32 in the switched capacitor circuit SC, the voltage conversion between the third node A3 and the fourth node A4 can be realized to pull Vvo low and pull 0 high. For example, when the voltage at the third node A3 is Vvo and the voltage at the fourth node A4 is 0, after the voltage conversion between the third node A3 and the fourth node A4, the voltage at the third node A3 becomes less than Vvo, and the voltage at the fourth node A4 becomes greater than 0. By changing the voltages at the third node A3 and the fourth node A4, the voltage difference across some transistors in the second-stage switching network 20A and the second-stage switching network 20B can be altered. This reduces the "inrush" current at the moment of turn-on for some transistors, lowers the turn-on loss of the switched capacitor circuit SC, and improves the efficiency and frequency of the switched capacitor circuit SC. Furthermore, increasing the frequency of the switched capacitor circuit SC reduces the capacitance requirement and decreases its footprint. Moreover, switching the voltages at the third node A3 and the fourth node A4 reduces the rate of change of voltage (dv / dt) at these nodes, effectively reducing electromagnetic interference. Additionally, the third node A3 is coupled to both the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2, and the fourth node A4 is also coupled to both. That is, the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 share the second auxiliary circuit 32, simplifying the structure of the switched capacitor circuit SC.

[0120] In some embodiments, the first auxiliary circuit 31 is used to swap the voltage of the third node A3 and the voltage of the fourth node A4 during the dead time period of the switched capacitor circuit SC.

[0121] Figure 7A This is a schematic diagram of the topology of a second auxiliary circuit 32 provided in an embodiment of this application. Figure 7B This is a schematic diagram of a circuit control signal and its corresponding current and voltage waveforms provided in an embodiment of this application. Figure 7C This is a schematic diagram of the topology of a resonant network provided in an embodiment of this application.

[0122] In some embodiments, such as Figure 7AAs shown, the second auxiliary circuit 32 includes a first switch T1, a second switch T2, a third inductor L3, a third switch T3, and a fourth switch T4. The first switch T1, the third inductor L3, and the second switch T2 are connected in series between the third node A3 and the fourth node A4.

[0123] The first switch T1 and the second switch T2 can be P-type transistors, N-type transistors, insulated gate bipolar transistors (IGBTs), field-controlled thyristors (MCTs), gate turn-off thyristors (GTOs), bipolar junction transistors (BJTs), gallium nitride (GaN) devices, etc.

[0124] One end of the first switch transistor T1 is coupled to the third node A3, the other end of the first switch transistor T1 is coupled to one end of the third inductor L3, the other end of the third inductor L3 is coupled to one end of the second switch transistor T2, and the other end of the second switch transistor T2 is coupled to the fourth node A4.

[0125] The third switch T3 and the fourth switch T4 can be P-type transistors, N-type transistors, IGBTs, MCTs, GTOs, BJTs, diodes, etc.

[0126] The third switch T3 is coupled between the end of the third inductor L3 facing the first switch T1 and the reference ground voltage terminal GND, and the fourth switch T4 is coupled between the end of the third inductor L3 facing the second switch T2 and the reference ground voltage terminal GND.

[0127] like Figure 7B As shown, during the time period t0-t1, the first phase switched capacitor sub-circuit SC1 enters... Figure 4A In the first mode shown, transistors Q1A, Q3A, Q6A, Q8A, and Q9A are turned on. The second-phase switched capacitor sub-circuit SC2 then enters... Figure 5A In the second mode shown, transistors Q2B, Q4B, Q5B, Q7B, and Q10B are turned on. The voltage at node A3 is Vvo, and the voltage at node A4 is 0. Switches T2 and T3 are turned on, the voltage across inductor L3 is 0, and the current flowing through inductor L3 is 0.

[0128] During the time interval t1-t2, the dead zone begins. All transistors in the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are turned off, while the first switching transistor T1 and the second switching transistor T2 are turned on. Figure 7C As shown, the parasitic capacitance Coss of the third inductor L3, the fourth transistor Q4A, and the eighth transistor Q8B form a resonant network. If the dead time is exactly equal to half the resonant cycle of the above resonant network, the inductor current iL will start resonating from 0 and return to 0. At this time, the voltages of the parasitic capacitances Coss of the fourth transistor Q4A and the eighth transistor Q8B are interchanged, and the voltages of the third node A3 and the fourth node A4 are exchanged. The voltage of the third node A3 drops from Vvo to 0, and the voltage of the fourth node A4 rises from 0 to Vvo.

[0129] At time t2, the first phase switched capacitor sub-circuit SC1 enters... Figure 5A In the second mode shown, the second transistor Q2A, fourth transistor Q4A, fifth transistor Q5A, seventh transistor Q7A, and tenth transistor Q10A of the first-phase switched capacitor sub-circuit SC1 are turned on. The second-phase switched capacitor sub-circuit SC2 then enters... Figure 4A In the first mode shown, the first transistor Q1B, the third transistor Q3B, the sixth transistor Q6B, the eighth transistor Q8B, and the ninth transistor Q9B of the second phase switched capacitor sub-circuit SC2 are turned on.

[0130] When the voltage at node A3 drops from Vvo to 0, it enables the second transistor Q2A and the fourth transistor Q4A of the first-phase switched-capacitor subcircuit SC1 to achieve zero-voltage switching (ZVS), and the sixth transistor Q6B and the eighth transistor Q8B of the second-phase switched-capacitor subcircuit SC2 to achieve ZVS. When the voltage at node A4 rises from 0 to Vvo, it enables the seventh transistor Q7A of the first-phase switched-capacitor subcircuit SC1 and the third transistor Q3B of the second-phase switched-capacitor subcircuit SC2 to achieve ZVS.

[0131] During the time period t2-t3, the first phase switched capacitor sub-circuit SC1 enters... Figure 5A The second mode shown includes the second transistor Q2A, the fourth transistor Q4A, the fifth transistor Q5A, the seventh transistor Q7A, and the tenth transistor Q10A. The second-phase switched capacitor sub-circuit SC2 enters... Figure 4AIn the first mode shown, transistors Q1B, Q3B, Q6B, Q8B, and Q9B are turned on. The voltage at the third node A3 is 0, and the voltage at the fourth node A4 is Vvo. Switches T1 and T4 are turned on, the voltage across the third inductor L3 is 0, and the current flowing through the third inductor L3 is 0.

[0132] During the t3-t4 time period, the dead zone begins. All transistors in the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are turned off, while the first switching transistor T1 and the second switching transistor T2 are turned on. Figure 7C As shown, the parasitic capacitance Coss of the third inductor L3, the fourth transistor Q4A, and the eighth transistor Q8B form a resonant network. If the dead time is exactly equal to half the resonant cycle of the above resonant network, the inductor current iL will start resonating from 0 and return to 0. At this time, the voltages of the parasitic capacitances Coss of the fourth transistor Q4A and the eighth transistor Q8B are interchanged, realizing the voltage exchange between the third node A3 and the fourth node A4. The voltage of the third node A3 rises from 0 to Vvo, and the voltage of the fourth node A4 falls from Vvo to 0.

[0133] At time t4, the first phase switched capacitor sub-circuit SC1 enters... Figure 4A In the first mode shown, transistors Q1A, Q3A, Q6A, Q8A, and Q9A are turned on. The second-phase switched capacitor sub-circuit SC2 then enters... Figure 5A The second mode shown turns on the second transistor Q2B, the fourth transistor Q4B, the fifth transistor Q5B, the seventh transistor Q7B, and the tenth transistor Q10B.

[0134] When the voltage at the third node A3 rises from 0 to Vvo, it enables the third transistor Q3A of the first-phase switched capacitor sub-circuit SC1 and the seventh transistor Q7B of the second-phase switched capacitor sub-circuit SC2 to achieve zero-voltage turn-on. When the voltage at the fourth node A4 drops from Vvo to 0, it enables the sixth transistor Q6A and the eighth transistor Q8A of the first-phase switched capacitor sub-circuit SC1, as well as the second transistor Q2B and the fourth transistor Q4B of the second-phase switched capacitor sub-circuit SC2 to achieve zero-voltage turn-on.

[0135] By incorporating the second auxiliary circuit 32 in the switched capacitor circuit SC, zero-voltage turn-on of some transistors in the second-stage switching network 20A and the second-stage switching network 20B can be achieved, thereby reducing the "inrush" current of some transistors at the moment of turn-on and reducing the turn-on losses of some transistors. Furthermore, the third switch T3 and the fourth switch T4 in the second auxiliary circuit 32 can act as freewheeling transistors. When the current in the third inductor L3 does not exactly resonate to zero, the current in the third inductor L3 can be freewheeled to the reference ground voltage terminal GND, ensuring safe operation even when the second auxiliary circuit 32 has errors.

[0136] Figure 8 This is a schematic diagram of the topology of another second auxiliary circuit 32 provided in an embodiment of this application.

[0137] In other embodiments, such as Figure 8 As shown, the second auxiliary circuit 32 may also include only the first switch T1, the second switch T2, and the third inductor L3, excluding the third switch T3 and the fourth switch T4.

[0138] Figure 8 The principle of the second auxiliary circuit 32 shown is the same as... Figure 7A The principle of the second auxiliary circuit 32 shown is the same, and you can refer to the above description.

[0139] Figure 9A This is a schematic diagram of the topology of another second auxiliary circuit provided in an embodiment of this application. Figure 9B This is a schematic diagram of another circuit control signal and its corresponding current and voltage waveforms provided in an embodiment of this application.

[0140] In some other embodiments, such as Figure 9A As shown, the second auxiliary circuit 32 includes a first inductor L1, a fourth capacitor C4, a second inductor L2, and a fifth capacitor C5. The first inductor L1, the fourth capacitor C4, the second inductor L2, and the fifth capacitor C5 are connected in series between the third node A3 and the fourth node A4. The end of the second inductor L2 facing the fourth capacitor C4 is also coupled to the reference ground voltage terminal GND.

[0141] like Figure 9B As shown, during the time period t0-t1, the first phase switched capacitor sub-circuit SC1 enters... Figure 4A In the first mode shown, transistors Q1A, Q3A, Q6A, Q8A, and Q9A are turned on. The second-phase switched capacitor sub-circuit SC2 then enters... Figure 5AIn the second mode shown, transistors Q2B, Q4B, Q5B, Q7B, and Q10B are turned on. The voltage at node A3 is Vvo, and the voltage at node A4 is 0.

[0142] During the time interval t1-t2, the dead zone begins. All transistors in the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are turned off. A resonant network is formed between the first inductor L1, the fourth capacitor C4, and the reference ground voltage terminal GND. The voltages at the third node A3 and the reference ground voltage terminal GND are interconnected, and the voltage at the third node A3 drops from Vvo to 0. The voltage at the fourth node A4 remains unchanged at 0.

[0143] At time t2, the first phase switched capacitor sub-circuit SC1 enters... Figure 5A In the second mode shown, the second phase switched capacitor sub-circuit SC2 enters... Figure 4A The first mode is shown. When the voltage at the third node A3 drops from Vvo to 0, the voltage difference across the second transistor Q2A and the fourth transistor Q4A in the first phase switched capacitor sub-circuit SC1 decreases.

[0144] During the time period t2-t3, the first phase switched capacitor sub-circuit SC1 enters... Figure 5A In the second mode shown, the second phase switched capacitor sub-circuit SC2 enters... Figure 4A The first mode is shown. The voltage at the third node A3 is 0, and the voltage at the fourth node A4 is Vvo.

[0145] During the t3-t4 time period, the dead zone begins. All transistors in the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are turned off. A resonant network is formed between the second inductor L2, the fifth capacitor C5, and the reference ground voltage terminal GND. The voltage at the fourth node A4 and the reference ground voltage terminal GND are interconnected, and the voltage at the fourth node A4 drops from Vvo to 0. The voltage at the third node A3 remains unchanged at 0.

[0146] At time t4, the first phase switched capacitor sub-circuit SC1 enters... Figure 4A In the first mode shown, the second-phase switched capacitor sub-circuit SC2 enters... Figure 5A The second mode is shown. When the voltage at the fourth node A4 drops from Vvo to 0, the voltage difference across the second transistor Q2B and the fourth transistor Q4B in the second-phase switched capacitor sub-circuit SC2 decreases.

[0147] The second auxiliary circuit 32 only includes capacitors and inductors, and does not require changes to the transistor topology of the switched capacitor circuit SC, making it easy to implement.

[0148] Figure 10AThis is a schematic diagram of the topology of another second auxiliary circuit provided in an embodiment of this application. Figure 10B This is a schematic diagram of another circuit control signal and its corresponding current and voltage waveforms provided in an embodiment of this application.

[0149] In other embodiments, the second auxiliary circuit 32 is used to connect the third node A3 and the fourth node A4 during the dead time period of the switched capacitor circuit SC, so as to realize the voltage switching between the third node A3 and the fourth node A4.

[0150] For example, such as Figure 10A As shown, the second auxiliary circuit 32 includes a bidirectional switching circuit M; the bidirectional switching circuit M is coupled between the third node A3 and the fourth node A4.

[0151] A bidirectional switching circuit M may include, for example, two transistors connected in series, or a bidirectional switching circuit M may include a single bidirectional switching transistor.

[0152] like Figure 10B As shown, during the time period t0-t1, the first phase switched capacitor sub-circuit SC1 enters... Figure 4A In the first mode shown, the second-phase switched capacitor sub-circuit SC2 enters... Figure 5A The second mode is shown. The voltage at the third node A3 is Vvo, and the voltage at the fourth node A4 is 0.

[0153] During the t1-t2 time period, the dead zone begins. All transistors in the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are turned off, and the bidirectional switching circuit M is turned on. The voltages of the third node A3 and the fourth node A4 are interconnected. The voltage of the third node A3 drops from Vvo to 0.5Vvo, and the voltage of the fourth node A4 rises from 0 to 0.5Vvo.

[0154] At time t2, the first phase switched capacitor sub-circuit SC1 enters... Figure 5A In the second mode shown, the second phase switched capacitor sub-circuit SC2 enters... Figure 4A The first mode is shown. When the voltage at the third node A3 drops from Vvo to 0.5Vvo, the voltage difference across the second transistor Q2A and the fourth transistor Q4A in the first-phase switched capacitor sub-circuit SC1 decreases. When the voltage at the fourth node A4 rises from 0 to 0.5Vvo, the voltage difference across the seventh transistor Q7A in the first-phase switched capacitor sub-circuit SC1 and the third transistor Q3B in the second-phase switched capacitor sub-circuit SC2 decreases.

[0155] During the time period t2-t3, the first phase switched capacitor sub-circuit SC1 enters... Figure 5A In the second mode shown, the second phase switched capacitor sub-circuit SC2 enters... Figure 4AThe first mode is shown. The voltage at node A3 is 0, and the voltage at node A4 is Vvo. During the time interval t3-t4, the dead zone begins. All transistors in the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are turned off, and the bidirectional switching circuit M is turned on. The voltages at nodes A3 and A4 are interconnected; the voltage at node A3 rises from 0 to 0.5Vvo, and the voltage at node A4 falls from Vvo to 0.5Vvo.

[0156] At time t4, the first phase switched capacitor sub-circuit SC1 enters... Figure 4A In the first mode shown, the second-phase switched capacitor sub-circuit SC2 enters... Figure 5A The second mode is shown. When the voltage at the third node A3 rises from 0 to 0.5Vvo, the voltage difference across the third transistor Q3A of the first-phase switched capacitor sub-circuit SC1 and the seventh transistor Q7B of the second-phase switched capacitor sub-circuit SC2 decreases. When the voltage at the fourth node A4 drops from Vvo to 0.5Vvo, the voltage difference across the sixth transistor Q6A and the eighth transistor Q8A of the first-phase switched capacitor sub-circuit SC1, and the second transistor Q2B and the fourth transistor Q4B of the second-phase switched capacitor sub-circuit SC2 decreases.

[0157] The second auxiliary circuit 32 only includes a bidirectional switching circuit M, without capacitors and inductors, making it simple to manufacture and easy to implement.

[0158] In other embodiments, such as Figure 6A As shown, the switched capacitor circuit SC includes a first auxiliary circuit 31.

[0159] The first auxiliary circuit 31 is coupled between the first node A1 and the second node A2, and is used to switch the voltage of the first node A1 and the voltage of the second node A2 during the period when both the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are off (e.g., the dead time period as referred to in the art). The first node A1 is coupled to the negative terminal of the first capacitor Cf1A of the first phase switched capacitor sub-circuit SC1, and the second node A2 is coupled to the negative terminal of the first capacitor Cf1B of the second phase switched capacitor sub-circuit SC2.

[0160] The structure and principle of the first auxiliary circuit 31 can be referred to the above description of the second auxiliary circuit 32. The main difference is that the second auxiliary circuit 32 is coupled between the third node A3 and the fourth node A4, while the first auxiliary circuit 31 is coupled between the first node A1 and the second node A2.

[0161] During the time period t0-t1, the first phase switched capacitor sub-circuit SC1 enters... Figure 4AIn the first mode shown, transistors Q1A, Q3A, Q6A, Q8A, and Q9A are turned on. The second-phase switched capacitor sub-circuit SC2 then enters... Figure 5A The second mode shown activates the second transistor Q2B, the fourth transistor Q4B, the fifth transistor Q5B, the seventh transistor Q7B, and the tenth transistor Q10B. For example... Figure 7B As shown, the voltage at the first node A1 is 2Vvo, and the voltage at the second node A2 is 0.

[0162] During the t1-t2 time period, the dead zone begins. All transistors in the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are turned off, the first auxiliary circuit 31 is turned on, and the voltages of the first node A1 and the second node A2 are exchanged. For example... Figure 7B As shown, the voltage at the first node A1 drops from 2Vvo to 0, and the voltage at the second node A2 rises from 0 to 2Vvo.

[0163] At time t2, the first phase switched capacitor sub-circuit SC1 enters... Figure 5A In the second mode shown, the second transistor Q2A, fourth transistor Q4A, fifth transistor Q5A, seventh transistor Q7A, and tenth transistor Q10A of the first-phase switched capacitor sub-circuit SC1 are turned on. The second-phase switched capacitor sub-circuit SC2 then enters... Figure 4A In the first mode shown, the first transistor Q1B, the third transistor Q3B, the sixth transistor Q6B, the eighth transistor Q8B, and the ninth transistor Q9B of the second phase switched capacitor sub-circuit SC2 are turned on.

[0164] When the voltage at the first node A1 drops from 2Vvo to 0, the fifth transistor Q5A and the tenth transistor Q10A in the first-phase switched-capacitor sub-circuit SC1 can achieve zero-voltage turn-on. When the voltage at the second node A2 rises from 0 to 2Vvo, the ninth transistor Q9B and the first transistor Q1B in the second-phase switched-capacitor sub-circuit SC2 can achieve zero-voltage turn-on.

[0165] During the time period t2-t3, the first phase switched capacitor sub-circuit SC1 enters... Figure 5A In the second mode shown, transistors Q2A, Q4A, Q5A, Q7A, and Q10A are turned on. The second-phase switched capacitor sub-circuit SC2 then enters... Figure 4A In the first mode shown, transistors Q1B, Q3B, Q6B, Q8B, and Q9B are turned on. Figure 7B As shown, the voltage at the first node A1 is 0, and the voltage at the second node A2 is 2Vvo.

[0166] During the t3-t4 time period, the dead zone begins. All transistors in the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are turned off, the first auxiliary circuit 31 is turned on, and the voltages of the first node A1 and the second node A2 are exchanged. For example... Figure 7B As shown, the voltage at the first node A1 rises from 0 to 2Vvo, and the voltage at the second node A2 falls from 2Vvo to 0.

[0167] At time t4, the first phase switched capacitor sub-circuit SC1 enters... Figure 4A In the first mode shown, transistors Q1A, Q3A, Q6A, Q8A, and Q9A are turned on. The second-phase switched capacitor sub-circuit SC2 then enters... Figure 5A The second mode shown turns on the second transistor Q2B, the fourth transistor Q4B, the fifth transistor Q5B, the seventh transistor Q7B, and the tenth transistor Q10B.

[0168] When the voltage at node A1 rises from 0 to 2Vvo, it enables the ninth transistor Q9A and the first transistor Q1A in the first-phase switched capacitor subcircuit SC1 to achieve zero-voltage turn-on. When the voltage at node A2 drops from 2Vvo to 0, it enables the tenth transistor Q10B and the fifth transistor Q5B in the second-phase switched capacitor subcircuit SC2 to achieve zero-voltage turn-on.

[0169] By setting a first auxiliary circuit 31 in the switched capacitor circuit SC, the "rush" current of the transistors in the first-stage switching network 10A and some transistors in the second-stage switching network 20A in the first-phase switched capacitor sub-circuit SC1 at the moment of turn-on can be reduced, as can the "rush" current of the transistors in the first-stage switching network 10B and some transistors in the second-stage switched capacitor sub-circuit SC2 at the moment of turn-on can be reduced.

[0170] When the switched capacitor circuit SC includes both the first auxiliary circuit 31 and the second auxiliary circuit 32, the "rush" current of all transistors in the first phase switched capacitor sub-circuit SC1 at the moment of turn-on can be reduced, as can the "rush" current of all transistors in the second phase switched capacitor sub-circuit SC2 at the moment of turn-on. This further reduces the turn-on loss of the switched capacitor circuit SC, improves the overall efficiency of the switched capacitor circuit SC, and enables electronic devices to have a faster charging experience or lower heat generation.

[0171] Figure 11A and Figure 11B This is a schematic diagram of the topology of a switched capacitor circuit provided in an embodiment of this application.

[0172] In some embodiments, such as Figure 11AAs shown, the switched capacitor circuit includes multiple switched capacitor groups connected in parallel between the input terminal VI and the output terminal VO. Each switched capacitor group includes the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 mentioned above. Figure 11A The example is illustrated by dividing multiple first-phase switched capacitor sub-circuits SC1 and multiple second-phase switched capacitor sub-circuits SC2 into two groups.

[0173] In the same switched capacitor group, the first phase switched capacitor sub-circuit SC1 and the second phase switched capacitor sub-circuit SC2 are out of phase by 180°. In different switched capacitor groups, the first phase switched capacitor sub-circuit SC1 is out of phase by 180° / n, and the second phase switched capacitor sub-circuit SC2 in different groups is out of phase by 180° / n.

[0174] Example, Figure 11A In the left-side switched capacitor bank, the phase of the first-phase switched capacitor sub-circuit SC1 is 0°, and the phase of the second-phase switched capacitor sub-circuit SC2 is 180°. In the right-side switched capacitor bank, the phase of the first-phase switched capacitor sub-circuit SC1 is 90°, and the phase of the second-phase switched capacitor sub-circuit SC2 is 270°.

[0175] For example, one drive cycle of a switched capacitor bank is T, and the drive timings of different switched capacitor banks do not affect each other. If the phase of the first phase switched capacitor sub-circuit SC1 in the right-side switched capacitor bank is out of phase with the first phase switched capacitor sub-circuit SC1 in the left-side switched capacitor bank by 180° / n, then the drive timing of each transistor in the first phase switched capacitor sub-circuit SC1 in the right-side switched capacitor bank is delayed by ((180° / n) / 360°)*T compared to the drive timing of each transistor in the first phase switched capacitor sub-circuit SC1 in the left-side switched capacitor bank. If the phase of the first phase switched capacitor sub-circuit SC1 in the right-side switched capacitor bank is out of phase with the first phase switched capacitor sub-circuit SC1 in the left-side switched capacitor bank by 90°, then the drive timing of each transistor in the first phase switched capacitor sub-circuit SC1 in the right-side switched capacitor bank is delayed by 1 / 4T compared to the drive timing of each transistor in the first phase switched capacitor sub-circuit SC1 in the left-side switched capacitor bank.

[0176] Or, for example, such as Figure 11B As shown, in the left group, the first phase switched capacitor sub-circuit SC1 operates with a 180° phase, while in the right group, the first phase switched capacitor sub-circuit SC1 operates with a 270° phase. In the left group, the second phase switched capacitor sub-circuit SC2 operates with a 0° phase, while in the right group, the second phase switched capacitor sub-circuit SC2 operates with a 90° phase.

[0177] Each set of first-phase switched capacitor sub-circuit SC1 and second-phase switched capacitor sub-circuit SC2 is correspondingly coupled to a set of first auxiliary circuit 31 and second auxiliary circuit 32. Alternatively, the switched capacitor circuit SC can be understood as comprising multiple parallel circuits. Figure 6A or Figure 6B The structure shown.

[0178] By setting multiple sets of staggered parallel first-phase switched capacitor sub-circuits SC1 and second-phase switched capacitor sub-circuits SC2 in the switched capacitor circuit SC, the ripple of the charging voltage can be reduced and the stability of the charging voltage can be improved.

[0179] Figure 12A This is a schematic diagram of another switched capacitor circuit provided in an embodiment of this application. Figure 12B and Figure 12C This is a schematic diagram of another switched capacitor circuit topology provided in an embodiment of this application.

[0180] In some embodiments, such as Figure 12A As shown, the first-phase switched capacitor sub-circuit SC1 includes multiple (e.g., N) series-coupled second switched capacitor networks 2A, and the second-phase switched capacitor sub-circuit SC2 includes multiple (e.g., N) series-coupled second switched capacitor networks 2B. The switched capacitor circuit SC includes multiple second auxiliary circuits 32, each coupled to a corresponding second switched capacitor network 2A, 2B. A second auxiliary circuit 32 is coupled between the third node A3 of each second switched capacitor network 2A and the fourth node A4 of each second switched capacitor network 2B.

[0181] For example, let's take the third node A3 as an example. Figure 12A In the middle, the third node A3 (1) This represents the third node A3 of the first-stage second switched capacitor network 2A. (N-1) This represents the third node A3 of the (N-1)th stage second switched capacitor network 2A. (N) This represents the third node A3 of the Nth stage second switched capacitor network 2A. Other markings follow the same schematic representation.

[0182] In some embodiments, such as Figure 12B As shown, the first-stage switching network 10A includes a ninth transistor Q9A and a tenth transistor Q10A. The second-stage switching network 20A in each stage of the second-stage switching capacitor network 2A includes a first transistor Q1A, a second transistor Q2A, a third transistor Q3A, a fourth transistor Q4A, a fifth transistor Q5A, a sixth transistor Q6A, a seventh transistor A, and an eighth transistor Q8A.

[0183] The first terminal of the ninth transistor Q9A is coupled to the input terminal VI, and the second terminal of the ninth transistor Q9A is coupled to the positive terminal of the first capacitor Cf1A and the first terminal of the fifth transistor Q5A. The first terminal of the tenth transistor Q10A is coupled to the negative terminal of the first capacitor Cf1A and the first terminal of the first transistor Q1A, and the second terminal of the tenth transistor Q10A is coupled to the reference ground voltage terminal GND.

[0184] In each stage of the second switched capacitor network 2A, the first terminal of the fourth transistor Q4A is coupled to the second terminal of the third transistor Q3A, and the second stage of the fourth transistor Q4A is coupled to the reference ground voltage terminal GND. The first terminal of the eighth transistor Q8A is coupled to the second terminal of the seventh transistor Q7A, and the second stage of the eighth transistor Q8A is coupled to the reference ground voltage terminal.

[0185] In the first-stage second switched-capacitor network 2A, the first terminal of the first transistor Q1A is coupled to the negative terminal of the first capacitor Cf1A, and the second terminal of the first transistor Q1A is coupled to the first terminal of the second transistor Q2A and the positive terminal of the second capacitor Cf2A. The first terminal of the fifth transistor Q5A is coupled to the positive terminal of the first capacitor Cf1A, and the second terminal of the fifth transistor Q5A is coupled to the first terminal of the sixth transistor Q6A and the positive terminal of the third capacitor Cf3A. In the second switched-capacitor network 2A other than the first stage, the first terminal of the first transistor Q1A is coupled to the second terminal of the second transistor Q2A in the previous stage second switched-capacitor network 2A, and the second terminal of the first transistor Q1A is coupled to the first terminal of the second transistor Q2A and the positive terminal of the second capacitor Cf2A. The first terminal of the fifth transistor Q5A is coupled to the second terminal of the sixth transistor Q6A in the previous stage second switched-capacitor network 2A, and the second terminal of the fifth transistor Q5A is coupled to the first terminal of the sixth transistor Q6A and the positive terminal of the third capacitor Cf3A.

[0186] In the final stage of the second switched-capacitor network 2A, the second terminal of the second transistor Q2A, the first terminal of the third transistor Q3A, the second terminal of the sixth transistor Q6A, and the first terminal of the seventh transistor Q7A are all coupled to the output terminal VO. In the second switched-capacitor network 2A excluding the last stage, the second terminal of the second transistor Q2A is coupled to the first terminal of the seventh transistor Q7A, and the second terminal of the sixth transistor Q6A is coupled to the first terminal of the third transistor Q3A.

[0187] For example, taking the first transistor Q1 as an example, the first transistor Q1A1 represents the first transistor Q1A in the first stage second switched capacitor network 2A, and the first transistor Q1AN represents the first transistor Q1A in the Nth stage second switched capacitor network 2A. Other markings are also illustrated in this way.

[0188] In some embodiments, such as Figure 12BAs shown, the first-stage switching network 10B in the second-phase switched capacitor sub-circuit SC2 includes a ninth transistor Q9B and a tenth transistor Q10B. The second-stage switching network 20B in each stage of the second-phase switched capacitor network 2B includes a first transistor Q1B, a second transistor Q2B, a third transistor Q3B, a fourth transistor Q4B, a fifth transistor Q5B, a sixth transistor Q6B, a seventh transistor (B-type), and an eighth transistor Q8B. The connections between the transistors can be referred to the above descriptions of the first-stage switching network 10A and the second-stage switching network 20A in the first-phase switched capacitor sub-circuit SC1.

[0189] In other embodiments, such as Figure 12C As shown, the seventh transistor Q7AN in the last stage of the second-stage switching network 20A in the first-phase switched capacitor sub-circuit SC1 and the third transistor Q3BN in the last stage of the second-stage switching network 20B in the second-phase switched capacitor sub-circuit SC2 are the same transistor.

[0190] Alternatively, the eighth transistor Q8AN in the last stage of the second-stage switching network 20A in the first-phase switched capacitor sub-circuit SC1 and the fourth transistor Q4BN in the last stage of the second-stage switching network 20B in the second-phase switched capacitor sub-circuit SC2 are the same transistor.

[0191] Alternatively, the seventh transistor Q7BN in the last stage of the second-stage switching network 20B in the second-phase switched capacitor sub-circuit SC2 and the third transistor Q3AN in the last stage of the second-stage switching network 20A in the first-phase switched capacitor sub-circuit SC1 are the same transistor.

[0192] Alternatively, the eighth transistor Q8BN in the last stage of the second-stage switching network 20B in the second-phase switched capacitor sub-circuit SC2 and the fourth transistor Q4AN in the last stage of the second-stage switching network 20A in the first-phase switched capacitor sub-circuit SC1 are the same transistor.

[0193] This topology can reduce the number of transistors in the switched capacitor circuit SC and reduce the area occupied by the switched capacitor circuit SC.

[0194] By setting up multiple (N-stage) second switched capacitor networks 2A and 2B in each phase switched capacitor sub-circuit, the input voltage to output voltage ratio Vvi:Vvo at input terminal VI can be achieved to be 2. N+1 :1, to achieve a high transformation ratio and meet different application requirements. On this basis, each stage of the second switched capacitor network 2A, 2B is coupled with a second auxiliary circuit 32, which can reduce the "inrush" current of the transistors in each stage of the second switched capacitor network 2A, 2B at the moment of turn-on, so as to reduce the turn-on loss of the transistors.

[0195] In some embodiments, the switched capacitor circuit SC includes multiple sets of... Figure 12B or Figure 12C The first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 shown are used to reduce the ripple of the charging voltage and improve the stability of the charging voltage.

[0196] Figure 13 This is a schematic diagram of the topology of another switched capacitor circuit provided in an embodiment of this application.

[0197] This application also provides a switched capacitor circuit SC, which includes only a single-phase switched capacitor sub-circuit.

[0198] like Figure 13 As shown, the switched capacitor circuit SC includes: a first switched capacitor network 1, a third switched capacitor network 3 with multiple stages (e.g., N stages) connected in series, a fourth switched capacitor network 4 with multiple stages (e.g., N stages) connected in series, and multiple auxiliary circuits 30.

[0199] The first switched capacitor network 1 includes a first capacitor Cf1 and a first switched network 11. The first capacitor Cf1 is coupled to the first switched network 11, and the first switched network 11 is used to adjust the on / off state between the first capacitor Cf1 and the input terminal VI.

[0200] For example, the first switching network 11 includes a ninth transistor Q9 and a tenth transistor Q10. The first terminal of the ninth transistor Q9 is coupled to the input terminal VI, and the second terminal of the ninth transistor Q9 is coupled to the positive terminal of the first capacitor Cf1 and the first terminal of the fifth transistor Q5. The first terminal of the tenth transistor Q10 is coupled to the negative terminal of the first capacitor Cf1 and the first terminal of the first transistor Q1, and the second terminal of the tenth transistor Q10 is coupled to the reference ground voltage terminal GND.

[0201] Each stage of the third switched capacitor network 3 includes a second capacitor Cf2 and a second switched network 21. The second switched network 21 is coupled to the second capacitor Cf2 and the first switched network 11, respectively. The second switched network 21 is used to adjust the series and parallel connection between the second capacitor Cf2 and the first capacitor Cf1. Each stage of the third switched capacitor network 3 also includes a thirteenth node A13 coupled to the negative terminal of the second capacitor Cf2.

[0202] Each stage of the fourth switched capacitor network 4 includes a third capacitor Cf3 and a third switched network 22. The third switched network 22 is coupled to the third capacitor Cf3 and the first switched network 11, respectively. The third switched network 22 is used to adjust the series and parallel connection between the third capacitor Cf3 and the first capacitor Cf1. Each stage of the fourth switched capacitor network 4 also includes a fourteenth node A14 coupled to the negative terminal of the third capacitor Cf3.

[0203] Each auxiliary circuit 30 is coupled to a thirteenth node A13 and a fourteenth node A14, respectively, and is used to convert the voltage of the thirteenth node A13 and the voltage of the fourteenth node A14 during the period when the first switch network 11, the second switch network 21 and the third switch network 22 are all off.

[0204] The structure and principle of the auxiliary circuit 30 can be referred to the above description of the second auxiliary circuit 32, and will not be repeated here.

[0205] Taking the first transistor Q1 as an example, the first transistor Q11 represents the first transistor Q1 in the first-stage third switched capacitor network 3. N This represents the first transistor Q1 in the Nth stage third switched capacitor network 3, and other markings are also indicated in this way.

[0206] The first terminal of the ninth transistor Q9 is coupled to the input terminal VI, and the second terminal of the ninth transistor Q9 is coupled to the positive terminal of the first capacitor Cf1 and the first terminal of the fifth transistor Q51.

[0207] The first terminal of the tenth transistor Q10 is coupled to the negative terminal Cf1 of the first capacitor and the first terminal of the first transistor Q11, respectively. The second terminal of the tenth transistor Q10 is coupled to the reference ground voltage terminal GND.

[0208] In the first-stage second-switch-capacitor network 2, the first terminal of the first transistor Q11 is coupled to the negative terminal of the first capacitor Cf1, and the second terminal of the first transistor Q11 is coupled to the first terminal of the second transistor Q21 and the positive terminal of the second capacitor Cf21. The second terminal of the second transistor Q21 is coupled to the first terminal of the first transistor Q11 in the adjacent stage second-switch-capacitor network 2. The first terminal of the third transistor Q31 is coupled to the second terminal of the sixth transistor Q61, and the second terminal of the third transistor Q31 is coupled to the negative terminal of the second capacitor Cf21 and the first terminal of the fourth transistor Q41. The second terminal of the fourth transistor Q41 is coupled to the reference ground voltage terminal GND. The first terminal of the fifth transistor Q51 is coupled to the positive terminal of the first capacitor Cf1, and the second terminal of the fifth transistor Q51 is coupled to the first terminal of the sixth transistor Q61 and the positive terminal of the third capacitor Cf31. The second terminal of the sixth transistor Q61 is also coupled to the first terminal of the fifth transistor Q51 in the adjacent stage second-switch-capacitor network 2. The first terminal of the seventh transistor Q71 is coupled to the second terminal of the second transistor Q21. The second terminal of the seventh transistor Q71 is coupled to the negative terminal of the third capacitor Cf31 and the first terminal of the eighth transistor Q81. The second terminal of the eighth transistor Q81 is coupled to the reference ground voltage terminal GND.

[0209] In the second switched capacitor network 2 (excluding the first stage, M>1), the first transistor Q1 MThe first electrode and the second transistor Q2 of the previous stage M-1 The second electrode is coupled to the fifth transistor Q5. M The first electrode and the sixth transistor Q6 of the previous stage M-1 The second electrode is coupled. The coupling method of other transistors is the same as in the first-stage second switched capacitor network 2.

[0210] In the final stage of the second switched capacitor network 2, the second transistor Q2 N The second and third transistors Q3 N The first and sixth transistors, Q6 N The second electrode and the seventh transistor Q7 N The first pole is coupled to the output terminal VO.

[0211] The switched capacitor circuit SC provided in this application embodiment includes a third switched capacitor network 3 with multiple (N) series couplings and a fourth switched capacitor network 4 with multiple (N) series couplings, which can achieve an input voltage to output voltage ratio Vvi:Vvo of input terminal VI of 2. N+1 :1, to achieve a high transformation ratio and meet different application requirements. On this basis, an auxiliary circuit 30 is correspondingly coupled between the third switched capacitor network 3 and the fourth switched capacitor network 4 of each stage, which can reduce the "inrush" current of the transistors in the third switched capacitor network 3 and the fourth switched capacitor network 4 at the moment of turn-on, so as to reduce the turn-on loss of the transistors.

[0212] Figure 14A and Figure 14B This is a schematic diagram of the topology of another switched capacitor circuit provided in an embodiment of this application.

[0213] This application also provides a switched capacitor circuit SC, such as Figure 14A As shown, the switched capacitor circuit SC includes a multi-phase switched capacitor sub-circuit and a first bidirectional switching circuit M1.

[0214] A multiphase switched capacitor sub-circuit may include, for example, a first-phase switched capacitor sub-circuit SC1, a second-phase switched capacitor sub-circuit SC2, a third-phase switched capacitor sub-circuit SC3, and a fourth-phase switched capacitor sub-circuit SC4 connected in parallel between the input terminal VI and the output terminal VO. For example, the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are out of phase by 180°, the first-phase switched capacitor sub-circuit SC1 and the third-phase switched capacitor sub-circuit SC3 are out of phase by 90°, and the third-phase switched capacitor sub-circuit SC3 and the fourth-phase switched capacitor sub-circuit SC4 are out of phase by 180°. Figure 14AIn the circuit, the phase of the first-phase switched capacitor sub-circuit SC1 is 0°, the phase of the second-phase switched capacitor sub-circuit SC2 is 180°, the phase of the third-phase switched capacitor sub-circuit SC3 is 90°, and the phase of the fourth-phase switched capacitor sub-circuit SC4 is 270°. Of course, Figure 14A This is for illustrative purposes only and is not intended to impose any limitations.

[0215] For example, the first-phase switched capacitor sub-circuit SC1, the second-phase switched capacitor sub-circuit SC2, the third-phase switched capacitor sub-circuit SC3, and the fourth-phase switched capacitor sub-circuit SC4 are respectively related to the above. Figure 3 The switched capacitor circuit SC shown has the same structure.

[0216] In some embodiments, the first-phase switched capacitor sub-circuit SC1 includes a first switched capacitor network 1A and a second switched capacitor network 2A. The first switched capacitor network 1A includes a first capacitor Cf1A and a first-stage switching network 10A. The second switched capacitor network 2A includes a second capacitor Cf2A, a third capacitor Cf3A, and a second-stage switching network 20A. The first-stage switching network 10A is coupled to the input terminal VI and the second-stage switching network 20A, respectively. The second-stage switching network 20A is coupled to the output terminal VO. The first capacitor Cf1A is coupled to the first-stage switching network 10A, and the first-stage switching network 10A is used to adjust the on / off state between the first capacitor Cf1A and the input terminal VI. The second-stage switching network 20A is coupled to the first capacitor Cf1A, the second capacitor Cf2A, and the third capacitor Cf3A, respectively. The second-stage switching network 20A is used to adjust the series and parallel relationships among the third capacitor Cf3A, the second capacitor Cf2A, and the first capacitor Cf1A. The first-level switch network 10A includes, for example, the first switch network described above, and the second-level switch network 20A includes, for example, the second switch network 21 and the third switch network 22 described above.

[0217] The second-phase switched-capacitor sub-circuit SC2 includes a first switched-capacitor network 1B and a second switched-capacitor network 2B. The first switched-capacitor network 1B includes a first capacitor Cf1B and a first-stage switching network 10B. The second switched-capacitor network 2B includes a second capacitor Cf2B, a third capacitor Cf3B, and a second-stage switching network 20B. The first-stage switching network 10B is coupled to the input terminal VI and the second-stage switching network 20B, respectively. The second-stage switching network 20B is coupled to the output terminal VO. The first capacitor Cf1B is coupled to the first-stage switching network 10B, which is used to adjust the on / off state between the first capacitor Cf1B and the input terminal VI. The second-stage switching network 20B is coupled to the first capacitor Cf1B, the second capacitor Cf2B, and the third capacitor Cf3B, respectively. The second-stage switching network 20B is used to adjust the series and parallel relationships among the third capacitor Cf3B, the second capacitor Cf2B, and the first capacitor Cf1B. The first-level switch network 10B includes, for example, the first switch network described above, and the second-level switch network 20B includes, for example, the second switch network 21 and the third switch network 22 described above.

[0218] The third-phase switched-capacitor sub-circuit SC3 includes a first switched-capacitor network 1C and a second switched-capacitor network 2C. The first switched-capacitor network 1C includes a first capacitor Cf1C and a first-stage switching network 10C. The second switched-capacitor network 2C includes a second capacitor Cf2C, a third capacitor Cf3C, and a second-stage switching network 20C. The first-stage switching network 10C is coupled to the input terminal VI and the second-stage switching network 20C, respectively. The second-stage switching network 20C is coupled to the output terminal VO. The first capacitor Cf1C is coupled to the first-stage switching network 10C, which is used to adjust the on / off state between the first capacitor Cf1C and the input terminal VI. The second-stage switching network 20C is coupled to the first capacitor Cf1C, the second capacitor Cf2C, and the third capacitor Cf3C, respectively. The second-stage switching network 20C is used to adjust the series and parallel relationships among the third capacitor Cf3C, the second capacitor Cf2C, and the first capacitor Cf1C. The first-level switch network 10C includes, for example, the first switch network described above, and the second-level switch network 20C includes, for example, the second switch network 21 and the third switch network 22 described above.

[0219] The fourth-phase switched-capacitor sub-circuit SC4 includes a first switched-capacitor network 1D and a second switched-capacitor network 2D. The first switched-capacitor network 1D includes a first capacitor Cf1D and a first-stage switching network 10D. The second switched-capacitor network 2D includes a second capacitor Cf2D, a third capacitor Cf3D, and a second-stage switching network 20D. The first-stage switching network 10D is coupled to the input terminal VI and the second-stage switching network 20D, respectively. The second-stage switching network 20D is coupled to the output terminal VO. The first capacitor Cf1D is coupled to the first-stage switching network 10D, which is used to adjust the on / off connection between the first capacitor Cf1D and the input terminal VI. The second-stage switching network 20D is coupled to the first capacitor Cf1D, the second capacitor Cf2D, and the third capacitor Cf3D, respectively. The second-stage switching network 20D is used to adjust the series and parallel connections between the third capacitor Cf3D, the second capacitor Cf2D, and the first capacitor Cf1D. The first-level switch network 10D includes, for example, the first switch network described above, and the second-level switch network 20D includes, for example, the second switch network 21 and the third switch network 22 described above.

[0220] For example, such as Figure 14A As shown, the second-stage switching network 20A of the first-phase switched capacitor sub-circuit SC1 includes transistors Q1A, Q2A, Q3A, Q4A, Q5A, Q6A, Q7A, and Q8A. The first-stage switching network 10A includes transistors Q9A and Q10A. The connection relationships of the transistors can be found in the above description. Figure 3 The description.

[0221] The second-stage switching network 20B of the second-phase switched capacitor sub-circuit SC2 includes transistors Q1B, Q2B, Q3B, Q4B, Q5B, Q6B, Q7B, and Q8B. The first-stage switching network 10B includes transistors Q9B and Q10B. The connection relationships of these transistors can be found in the above description. Figure 3 The description.

[0222] The second-stage switching network 20C of the third-phase switched capacitor sub-circuit SC3 includes transistors Q1C, Q2C, Q3C, Q4C, Q5C, Q6C, Q7C, and Q8C. The first-stage switching network 10C includes transistors Q9C and Q10C. The connection relationships of the transistors can be found in the above description. Figure 3 The description.

[0223] The second-stage switching network 20D of the fourth-phase switched capacitor sub-circuit SC4 includes transistors Q1D, Q2D, Q3D, Q4D, Q5D, Q6D, Q7D, and Q8D. The first-stage switching network 10D includes transistors Q9D and Q10D. The connection relationships of the transistors can be found in the above description. Figure 3 The description.

[0224] Or, for example, such as Figure 14B As shown, the seventh transistor Q7A in the first-phase switched capacitor sub-circuit SC1 and the third transistor Q3B in the second-phase switched capacitor sub-circuit SC2 are the same transistor. Alternatively, the eighth transistor Q8A in the first-phase switched capacitor sub-circuit SC1 and the fourth transistor Q4B in the second-phase switched capacitor sub-circuit SC2 are the same transistor.

[0225] Alternatively, the seventh transistor Q7B in the second-phase switched capacitor sub-circuit SC2 and the third transistor Q3A in the first-phase switched capacitor sub-circuit SC1 may be the same transistor. Alternatively, the eighth transistor Q8B in the second-phase switched capacitor sub-circuit SC2 and the fourth transistor Q4A in the first-phase switched capacitor sub-circuit SC1 may be the same transistor.

[0226] Alternatively, the seventh transistor Q7C in the third-phase switched capacitor sub-circuit SC3 and the third transistor Q3D in the fourth-phase switched capacitor sub-circuit SC4 are the same transistor. Alternatively, the eighth transistor Q8C in the third-phase switched capacitor sub-circuit SC3 and the fourth transistor Q4D in the fourth-phase switched capacitor sub-circuit SC4 are the same transistor.

[0227] Alternatively, the seventh transistor Q7D in the fourth-phase switched capacitor sub-circuit SC4 and the third transistor Q3C in the third-phase switched capacitor sub-circuit SC3 are the same transistor. Alternatively, the eighth transistor Q8D in the fourth-phase switched capacitor sub-circuit SC4 and the fourth transistor Q4C in the third-phase switched capacitor sub-circuit SC3 are the same transistor.

[0228] This topology can reduce the number of transistors in the switched capacitor circuit SC and reduce the area occupied by the switched capacitor circuit SC.

[0229] The negative terminal of the second capacitor Cf2 of the first phase switched capacitor sub-circuit SC1 and the negative terminal of the third capacitor Cf3 of the second phase switched capacitor sub-circuit SC2 are coupled to point A5. The negative terminal of the third capacitor Cf3 of the third phase switched capacitor sub-circuit SC3 and the negative terminal of the second capacitor Cf2 of the fourth phase switched capacitor sub-circuit SC4 are coupled to point A6. Figure 14A The coupling positions of points A5 (fifth point) and A6 (sixth point) are only illustrative and can also be represented as... Figure 14A The positions of the seventh point A7 and the eighth point A8 in the diagram are taken as the fifth point A5 and the sixth point A6 here.

[0230] The first bidirectional switching circuit M1 is connected between point 5 A5 and point 6 A6. The first bidirectional switching circuit M1 is used to clamp the voltage at point 6 A6 to point 5 A5 during the period when both the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are off. The first bidirectional switching circuit M1 is also used to clamp the voltage at point 5 A5 to point 6 A6 during the period when both the third-phase switched capacitor sub-circuit SC3 and the fourth-phase switched capacitor sub-circuit SC4 are off (dead time period).

[0231] The first bidirectional switching circuit M1 may be, for example, a bidirectional switching circuit transistor, or may include two unidirectional conducting transistors, which are not limited in this application embodiment.

[0232] The third-phase switched capacitor circuit SC3 and the first-phase switched capacitor circuit SC1 are out of phase by 90°, and the fourth-phase switched capacitor circuit SC4 and the second-phase switched capacitor circuit SC2 are out of phase by 90°. During the period when both the first-phase switched capacitor circuit SC1 and the second-phase switched capacitor circuit SC2 are off, all transistors in the first-phase switched capacitor circuit SC1 and the second-phase switched capacitor circuit SC2 are off, while the third-phase switched capacitor circuit SC3 and the fourth-phase switched capacitor circuit SC4 enter... Figure 4A The first mode or Figure 5A The second mode in the process.

[0233] The third-phase switched capacitor sub-circuit SC3 and the fourth-phase switched capacitor circuit SC4 enter... Figure 4A In the first mode, the eighth transistor Q8C of the third-phase switched capacitor sub-circuit SC3 and the fourth transistor Q4D of the fourth-phase switched capacitor sub-circuit SC4 are turned on, the first bidirectional switching circuit M1 is turned on, and the zero voltage at point A6 is clamped to point A5. When the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 enter... Figure 4A In the first mode, the second transistor Q2A, the fourth transistor Q4A, and the seventh transistor Q7A in the first phase switched capacitor sub-circuit SC1, and the eighth transistor Q8B, the sixth transistor Q6B, and the third transistor Q3B in the second phase switched capacitor sub-circuit SC2 can achieve zero-voltage turn-on.

[0234] The switched capacitor circuit SC provided in this application embodiment has a first bidirectional switching circuit M1 between point A5 and point A6. When both the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are turned off, the third-phase switched capacitor sub-circuit SC3 and the fourth-phase switched capacitor sub-circuit SC4 operate normally. At this time, the voltage at point A6 can be clamped to point A5 by the first bidirectional switching circuit M1. By changing the voltage at point A5, the voltage difference between some transistors in the second-stage switching network 20A of the first-phase switched capacitor sub-circuit SC1 and the second-stage switching network 20B of the second-phase switched capacitor sub-circuit SC2 is reduced, thereby reducing the "inrush" current of the transistors at the moment of turn-on and reducing the turn-on loss of the transistors. Moreover, the first bidirectional switching circuit M1 has a simple structure, simple manufacturing process, and is easy to implement.

[0235] In some embodiments, such as Figure 14A As shown, the switched capacitor circuit SC also includes a second bidirectional switching circuit M2.

[0236] The second bidirectional switching circuit M2 is coupled between point 7 A7 and point 8 A8. It is used to clamp the voltage at point 8 A8 to point 7 A7 during the period when both the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are off. Point 7 A7 is coupled to the negative terminal of the third capacitor Cf3 of the first-phase switched capacitor sub-circuit SC1 and the negative terminal of the second capacitor Cf2 of the second-phase switched capacitor sub-circuit SC2. Point 8 A8 is coupled to the negative terminal of the second capacitor Cf2 of the third-phase switched capacitor sub-circuit SC3 and the negative terminal of the third capacitor Cf3 of the fourth-phase switched capacitor sub-circuit SC4.

[0237] The third-phase switched capacitor sub-circuit SC3 and the fourth-phase switched capacitor circuit SC4 enter... Figure 5A In the second mode, the fourth transistor Q4C and the eighth transistor Q8D of the third-phase switched capacitor sub-circuit SC3 are turned on, the second bidirectional switching circuit M2 is turned on, and the Vvo voltage at point A8 is clamped to point A7. This occurs when the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor circuit SC2 are in operation. Figure 5A In the second mode, the eighth transistor Q8A, the sixth transistor Q6A, and the third transistor Q3A in the first phase switched capacitor sub-circuit SC1, and the second transistor Q2B, the fourth transistor Q4B, and the seventh transistor Q7B in the second phase switched capacitor sub-circuit SC2 can achieve zero-voltage turn-on.

[0238] By setting a second bidirectional switching circuit M2 in the switched capacitor circuit SC, the voltage difference between some transistors in the second-stage switching network 20A in the first-phase switched capacitor sub-circuit SC1 and the second-stage switching network 20B in the second-phase switched capacitor sub-circuit SC2 can be reduced, thereby reducing the "rush" current of the transistor at the moment of turn-on and reducing the turn-on loss of the transistor.

[0239] Figure 15A and Figure 15B This is a schematic diagram of the topology of another switched capacitor circuit provided in an embodiment of this application.

[0240] This application also provides a switched capacitor circuit SC, such as Figure 15A and Figure 15B As shown, the switched capacitor circuit SC includes a multi-phase switched capacitor sub-circuit and a third bidirectional switching circuit M3. The structure of the multi-phase switched capacitor sub-circuit can be found in [reference needed]. Figure 14A and Figure 14B Related descriptions.

[0241] The third bidirectional switching circuit M3 is coupled between point 9 A9 and point 10 A10. It is used to clamp the voltage at point 10 A10 to point 9 A9 during the period when both the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are off. Point 9 A9 is coupled to the negative terminal of the first capacitor Cf1 of the first-phase switched capacitor sub-circuit SC1, and point 10 A10 is coupled to the negative terminal of the first capacitor Cf1 of the third-phase switched capacitor sub-circuit SC3.

[0242] Entering the third-phase switched capacitor sub-circuit SC3 Figure 4A In the first mode, the voltage at point 10 A10 is the input voltage 2Vvo. The third bidirectional switch circuit M3 is turned on, clamping the 2Vvo at point 10 A10 to point 9 A9. The first phase switched capacitor sub-circuit SC1 then enters... Figure 4A In the first mode, the ninth transistor Q9A and the first transistor Q1A can be turned on at zero voltage.

[0243] Entering the third-phase switched capacitor sub-circuit SC3 Figure 5A In the second mode, the voltage at point 10 A10 is 0, the third bidirectional switch circuit M3 is turned on, clamping the 0 voltage at point 10 A10 to point 9 A9, and the first phase switched capacitor sub-circuit SC1 enters... Figure 5A In the second mode, the tenth transistor Q10A and the fifth transistor Q5A can be turned on at zero voltage.

[0244] The switched capacitor circuit SC provided in this application embodiment has a third bidirectional switching circuit M3 between point A9 and point A10. When both the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are turned off, the third-phase switched capacitor sub-circuit SC3 operates normally. At this time, the voltage at point A10 can be clamped to point A9 by the third bidirectional switching circuit M3. By changing the voltage at point A9, the voltage difference across the transistor in the first-stage switching network 10A of the first-phase switched capacitor sub-circuit SC1 is reduced, thereby reducing the "inrush" current at the moment of transistor turn-on and lowering the transistor's turn-on loss. Furthermore, the third bidirectional switching circuit M3 has a simple structure, is easy to manufacture, and is readily implemented.

[0245] In some embodiments, such as Figure 15A As shown, the switched capacitor circuit SC also includes a fourth bidirectional switching circuit M4.

[0246] The fourth bidirectional switching circuit M4 is coupled between point 11 A11 and point 12 A12. During the period when both the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are off, it clamps the voltage at point 12 A11 to point 11 A11. Point 11 A11 is coupled to the negative terminal of the first capacitor Cf1 of the second-phase switched capacitor sub-circuit SC2, and point 12 A12 is coupled to the negative terminal of the first capacitor Cf1 of the fourth-phase switched capacitor sub-circuit SC4.

[0247] Entering the fourth phase switched capacitor sub-circuit SC4 Figure 5A In the first mode, the voltage at point 12 A12 is 2Vvo. The fourth bidirectional switch circuit M4 is turned on, clamping the 2Vvo at point 12 A12 to point 11 A11. Then, the second phase switched capacitor sub-circuit SC2 enters... Figure 4A In the first mode, the ninth transistor Q9B and the first transistor Q1B can be turned on at zero voltage.

[0248] Entering the fourth phase switched capacitor sub-circuit SC4 Figure 5A In the second mode, the voltage at point 12 A12 is 0, the fourth bidirectional switch circuit M4 is turned on, clamping the 0 at point 12 A12 to point 11 A11, and the second phase switched capacitor sub-circuit SC2 enters... Figure 5A In the second mode, the tenth transistor Q10B and the fifth transistor Q5B can be turned on at zero voltage.

[0249] The switched capacitor circuit SC provided in this application embodiment has a fourth bidirectional switching circuit M4 between point 11 A11 and point 12 A12. When both the first-phase switched capacitor sub-circuit SC1 and the second-phase switched capacitor sub-circuit SC2 are turned off, the fourth-phase switched capacitor sub-circuit SC4 operates normally. At this time, the voltage at point 12 A12 can be clamped to point 11 A11 by the fourth bidirectional switching circuit M4. By changing the voltage at point 11 A11, the voltage difference across the transistor in the first-stage switching network 10B of the second-phase switched capacitor sub-circuit SC2 is reduced, thereby reducing the "inrush" current at the moment of transistor turn-on and lowering the transistor's turn-on loss. Furthermore, the fourth bidirectional switching circuit M4 has a simple structure, is easy to manufacture, and is readily implemented.

[0250] Figure 16A and Figure 16B This is a schematic diagram of the topology of another switched capacitor circuit provided in an embodiment of this application.

[0251] In some embodiments, such as Figure 16A and Figure 16B As shown, the switched capacitor circuit SC includes a multi-phase switched capacitor sub-circuit and one or more of the aforementioned first bidirectional switching circuit M1, second bidirectional switching circuit M2, third bidirectional switching circuit M3, and fourth bidirectional switching circuit M4. Figure 16A and Figure 16B The example shown is a switched capacitor circuit SC comprising a first bidirectional switching circuit M1, a second bidirectional switching circuit M2, a third bidirectional switching circuit M3, and a fourth bidirectional switching circuit M4. This allows each transistor in the switched capacitor circuit SC to achieve zero-voltage turn-on, thereby reducing the "inrush" current of the transistor at the moment of turn-on and lowering the turn-on loss of the transistor.

[0252] Figure 17 This is a schematic diagram of another switched capacitor circuit provided in an embodiment of this application.

[0253] In some embodiments, such as Figure 17 As shown, each phase switched capacitor sub-circuit includes a multi-stage (e.g., N-stage) series-coupled second switched capacitor network 2. The switched capacitor circuit SC includes multiple first bidirectional switching circuits M1 and / or multiple second bidirectional switching circuits M2. The multiple first bidirectional switching circuits M1 are coupled one-to-one with the multi-stage (e.g., N-stage) second switched capacitor network 2, and the multiple second bidirectional switching circuits M2 are coupled one-to-one with the multi-stage (e.g., N-stage) second switched capacitor network 2.

[0254] The coupling relationship between each first bidirectional switching circuit M1 and the various stages of the second switched capacitor networks 2A, 2B, 2C, and 2D can be referred to... Figure 14AThe description of the coupling relationship between the first bidirectional switching circuit M1 and the second switched capacitor networks 2A, 2B, 2C, and 2D is provided above. The series connection method of the second switched capacitor network 2 in each phase switched capacitor sub-circuit can be found in the above description. Figure 12B and Figure 12C A description of the series connection method of the second switched capacitor network 2.

[0255] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A switched-capacitor circuit, characterized by, The switch capacitor circuit comprises at least one switch capacitor group; the switch capacitor group comprises a first auxiliary circuit, a second auxiliary circuit, and the first phase switch capacitor sub-circuit and the second phase switch capacitor sub-circuit which are coupled in parallel between an input end and an output end; The first phase switch capacitor sub-circuit and the second phase switch capacitor sub-circuit respectively comprise a first capacitor, a first stage switch network, and a switch capacitor network, the switch capacitor network comprising a second capacitor, a third capacitor, and a second stage switch network; the first stage switch network is coupled with the input end and the first capacitor respectively, and is used for adjusting the on-off of the first capacitor and the input end; The second stage switch network is coupled with the first capacitor, the second capacitor, and the third capacitor respectively, and is used for adjusting the series-parallel relationship among the first capacitor, the second capacitor, and the third capacitor; The first auxiliary circuit is coupled between a first node and a second node, and is used for converting the voltage of the first node and the voltage of the second node in a period when the first phase switch capacitor sub-circuit and the second phase switch capacitor sub-circuit are both off; the first node is coupled with the negative electrode of the first capacitor of the first phase switch capacitor sub-circuit, and the second node is coupled with the negative electrode of the first capacitor of the second phase switch capacitor sub-circuit; The second auxiliary circuit is coupled between a third node and a fourth node, and is used for converting the voltage of the third node and the voltage of the fourth node in a period when the first phase switch capacitor sub-circuit and the second phase switch capacitor sub-circuit are both off; the third node is coupled with the negative electrode of the second capacitor of the first phase switch capacitor sub-circuit and the negative electrode of the third capacitor of the second phase switch capacitor sub-circuit respectively, and the fourth node is coupled with the negative electrode of the third capacitor of the first phase switch capacitor sub-circuit and the negative electrode of the second capacitor of the second phase switch capacitor sub-circuit respectively.

2. The switched-capacitor circuit of claim 1, wherein, The first auxiliary circuit comprises a first inductor, a fourth capacitor, a second inductor, and a fifth capacitor; The first inductor, the fourth capacitor, the second inductor, and the fifth capacitor are coupled in series between the first node and the second node in sequence; one end of the second inductor towards the fourth capacitor is further coupled with a reference ground voltage end.

3. The switched-capacitor circuit of claim 1, wherein, The first auxiliary circuit comprises a bidirectional switch circuit; The bidirectional switch circuit is coupled between the first node and the second node.

4. The switched-capacitor circuit of claim 1, wherein, The first auxiliary circuit comprises a first switch tube, a second switch tube, and a third inductor; The first switch tube, the third inductor, and the second switch tube are coupled in series between the first node and the second node in sequence.

5. The switched-capacitor circuit of claim 4, wherein, The first auxiliary circuit further comprises a third switch tube and a fourth switch tube; The third switch tube is coupled between one end of the third inductor towards the first switch tube and a reference ground voltage end, and the fourth switch tube is coupled between one end of the third inductor towards the second switch tube and the reference ground voltage end.

6. The switched-capacitor circuit of any of claims 1-5, wherein, The switched-capacitor circuit comprises a plurality of the switched-capacitor groups, and the plurality of the switched-capacitor groups are coupled in parallel between the input terminal and the output terminal.

7. The switched-capacitor circuit of any of claims 1-6, wherein, The first-phase switched-capacitor sub-circuit and the second-phase switched-capacitor sub-circuit each comprise a plurality of the switched-capacitor networks coupled in series, and the switched-capacitor circuit further comprises a plurality of the second auxiliary circuits; the plurality of the second auxiliary circuits are coupled one-to-one with the plurality of the switched-capacitor networks.

8. The switched-capacitor circuit according to any one of claims 1-6, characterized in that, The second-stage switched network comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; a first electrode of the first transistor is coupled with a negative electrode of the first capacitor, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of the second capacitor respectively; a second electrode of the second transistor is coupled with the output terminal and a first electrode of the third transistor respectively; a second electrode of the third transistor is coupled with a negative electrode of the second capacitor and a first electrode of the fourth transistor respectively; a second electrode of the fourth transistor is coupled with a reference ground voltage terminal; a first electrode of the fifth transistor is coupled with a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of the third capacitor respectively; a second electrode of the sixth transistor is coupled with the output terminal and a first electrode of the seventh transistor respectively; a second electrode of the seventh transistor is coupled with a negative electrode of the third capacitor and a first electrode of the eighth transistor respectively; a second electrode of the eighth transistor is coupled with the reference ground voltage terminal; the seventh transistor in the first-phase switched-capacitor sub-circuit and the third transistor in the second-phase switched-capacitor sub-circuit are the same transistor; or, the eighth transistor in the first-phase switched-capacitor sub-circuit and the fourth transistor in the second-phase switched-capacitor sub-circuit are the same transistor.

9. The switched-capacitor circuit of claim 7, wherein, The second-stage switched network in each of the switched-capacitor networks comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; in each of the switched-capacitor networks, a first electrode of the fourth transistor is coupled with a second electrode of the third transistor, and a second electrode of the fourth transistor is coupled with a reference ground voltage terminal; a first electrode of the eighth transistor is coupled with a second electrode of the seventh transistor, and a second electrode of the eighth transistor is coupled with the reference ground voltage terminal; In the first stage of the switched-capacitor network, a first electrode of the first transistor is coupled to a negative electrode of the first capacitor, and a second electrode of the first transistor is coupled to a first electrode of the second transistor and a positive electrode of the second capacitor, respectively; a first electrode of the fifth transistor is coupled to a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled to a first electrode of the sixth transistor and a positive electrode of the third capacitor, respectively; in the switched-capacitor network except the first stage, the first electrode of the first transistor is coupled to a second electrode of the second transistor in the switched-capacitor network of the previous stage, and the second electrode of the first transistor is coupled to the first electrode of the second transistor and the positive electrode of the second capacitor, respectively; the first electrode of the fifth transistor is coupled to a second electrode of the sixth transistor in the switched-capacitor network of the previous stage, and the second electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the positive electrode of the third capacitor, respectively; In the last stage of the switched-capacitor network, the second electrode of the second transistor, the first electrode of the third transistor, the second electrode of the sixth transistor and the first electrode of the seventh transistor are all coupled to the output terminal; in the switched-capacitor network except the last stage, the second electrode of the second transistor is coupled to the first electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled to the first electrode of the third transistor; the seventh transistor of the last stage of the switched-capacitor network in the first phase switched-capacitor sub-circuit and the third transistor of the last stage of the switched-capacitor network in the second phase switched-capacitor sub-circuit are the same transistor; or, the eighth transistor of the last stage of the switched-capacitor network in the first phase switched-capacitor sub-circuit and the fourth transistor of the last stage of the switched-capacitor network in the second phase switched-capacitor sub-circuit are the same transistor.

10. A switched-capacitor circuit, characterized by The switched-capacitor circuit comprises: The first phase switched-capacitor sub-circuit, the second phase switched-capacitor sub-circuit, the third phase switched-capacitor sub-circuit and the fourth phase switched-capacitor sub-circuit are coupled in parallel between the input terminal and the output terminal; the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are out of phase by 180°, the first phase switched-capacitor sub-circuit and the third phase switched-capacitor sub-circuit are out of phase by 90°, and the third phase switched-capacitor sub-circuit and the fourth phase switched-capacitor sub-circuit are out of phase by 180°; The first phase switched-capacitor sub-circuit, the second phase switched-capacitor sub-circuit, the third phase switched-capacitor sub-circuit and the fourth phase switched-capacitor sub-circuit respectively comprise a first capacitor, a first-stage switch network and a switched-capacitor network, the switched-capacitor network comprising a second capacitor, a third capacitor and a second-stage switch network; the first-stage switch network is coupled with the input terminal and the first capacitor respectively, and is used for adjusting the on-off between the first capacitor and the input terminal; the second-stage switch network is coupled with the first capacitor, the second capacitor and the third capacitor respectively, and is used for adjusting the series-parallel relationship between the first capacitor, the second capacitor and the third capacitor; A first bidirectional switch circuit is coupled between a fifth node and a sixth node, and is used for clamping the voltage of the sixth node to the fifth node in a period when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off. The fifth node is coupled with the negative electrode of the second capacitor of the first phase switched-capacitor sub-circuit and the negative electrode of the third capacitor of the second phase switched-capacitor sub-circuit respectively, and the sixth node is coupled with the negative electrode of the third capacitor of the third phase switched-capacitor sub-circuit and the negative electrode of the second capacitor of the fourth phase switched-capacitor sub-circuit respectively.

11. The switched-capacitor circuit of claim 10, wherein, The switched-capacitor circuit further comprises a second bidirectional switch circuit; The second bidirectional switch circuit is coupled between a seventh node and an eighth node, and is used for clamping the voltage of the eighth node to the seventh node in a period when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off. The seventh node is coupled with the negative electrode of the third capacitor of the first phase switched-capacitor sub-circuit and the negative electrode of the second capacitor of the second phase switched-capacitor sub-circuit respectively, and the eighth node is coupled with the negative electrode of the second capacitor of the third phase switched-capacitor sub-circuit and the negative electrode of the third capacitor of the fourth phase switched-capacitor sub-circuit respectively.

12. The switched-capacitor circuit of claim 10 or 11, wherein, The switched-capacitor circuit further comprises a third bidirectional switch circuit; The third bidirectional switch circuit is coupled between a ninth node and a tenth node, and is used for clamping the voltage of the tenth node to the ninth node in a period when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off. The ninth node is coupled with the negative electrode of the first capacitor of the first phase switched-capacitor sub-circuit, and the tenth node is coupled with the negative electrode of the first capacitor of the third phase switched-capacitor sub-circuit.

13. The switched-capacitor circuit of any of claims 10-12, wherein, The switched-capacitor circuit further comprises a fourth bidirectional switch circuit; The fourth bidirectional switch circuit is coupled between an eleventh node and a twelfth node, and is used for clamping the voltage of the twelfth node to the eleventh node in a period when the first phase switched-capacitor sub-circuit and the second phase switched-capacitor sub-circuit are both off. The eleventh node is coupled with the negative electrode of the first capacitor of the second phase switched-capacitor sub-circuit, and the twelfth node is coupled with the negative electrode of the first capacitor of the fourth phase switched-capacitor sub-circuit.

14. The switched-capacitor circuit of any of claims 10-13, wherein, The switch capacitor circuit of each phase comprises the switch capacitor network of multiple stages connected in series, and the switch capacitor circuit comprises multiple first bidirectional switch circuits; the multiple first bidirectional switch circuits are one-to-one coupled with the multiple-stage switch capacitor network.

15. The switched-capacitor circuit of any of claims 10-13, wherein, The second-stage switch network comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; a first electrode of the first transistor is coupled with a negative electrode of the first capacitor, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of the second capacitor respectively; a second electrode of the second transistor is coupled with the output end and a first electrode of the third transistor respectively; a second electrode of the third transistor is coupled with a negative electrode of the second capacitor and a first electrode of the fourth transistor respectively; a second electrode of the fourth transistor is coupled with a reference ground voltage end; a first electrode of the fifth transistor is coupled with a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of the third capacitor respectively; a second electrode of the sixth transistor is coupled with the output end and a first electrode of the seventh transistor respectively; a second electrode of the seventh transistor is coupled with a negative electrode of the third capacitor and a first electrode of the eighth transistor respectively; a second electrode of the eighth transistor is coupled with the reference ground voltage end; the seventh transistor in the first-phase switch capacitor sub-circuit and the third transistor in the second-phase switch capacitor sub-circuit are the same transistor; or the eighth transistor in the first-phase switch capacitor sub-circuit and the fourth transistor in the second-phase switch capacitor sub-circuit are the same transistor.

16. The switch capacitor circuit of claim 14, wherein, the second-stage switch network in each stage of the switch capacitor network comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor respectively; in each stage of the switch capacitor network, a first electrode of the fourth transistor is coupled with a second electrode of the third transistor, and a second electrode of the fourth transistor is coupled with a reference ground voltage end; a first electrode of the eighth transistor is coupled with a second electrode of the seventh transistor, and a second electrode of the eighth transistor is coupled with the reference ground voltage end; In the first stage of the switched capacitor network, a first electrode of the first transistor is coupled with a negative electrode of the first capacitor, and a second electrode of the first transistor is coupled with a first electrode of the second transistor and a positive electrode of the second capacitor respectively; a first electrode of the fifth transistor is coupled with a positive electrode of the first capacitor, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor and a positive electrode of the third capacitor respectively; in the switched capacitor network except the first stage, the first electrode of the first transistor is coupled with a second electrode of the second transistor in the switched capacitor network of the previous stage, and the second electrode of the first transistor is coupled with the first electrode of the second transistor and the positive electrode of the second capacitor respectively; the first electrode of the fifth transistor is coupled with a second electrode of the sixth transistor in the switched capacitor network of the previous stage, and the second electrode of the fifth transistor is coupled with the first electrode of the sixth transistor and the positive electrode of the third capacitor respectively; In the last stage of the switched capacitor network, the second electrode of the second transistor, the first electrode of the third transistor, the second electrode of the sixth transistor and the first electrode of the seventh transistor are all coupled with the output terminal; in the switched capacitor network except the last stage, the second electrode of the second transistor is coupled with the first electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled with the first electrode of the third transistor; The seventh transistor of the last stage of the switched capacitor network in the first phase switched capacitor sub-circuit and the third transistor of the last stage of the switched capacitor network in the second phase switched capacitor sub-circuit are the same transistor; or, the eighth transistor of the last stage of the switched capacitor network in the first phase switched capacitor sub-circuit and the fourth transistor of the last stage of the switched capacitor network in the second phase switched capacitor sub-circuit are the same transistor.

17. A switched-capacitor circuit, comprising: The switched capacitor circuit comprises: a first capacitor and a first switch network; the first capacitor is coupled with the first switch network, and the first switch network is used for adjusting the on-off between the first capacitor and an input terminal; a plurality of first switched capacitor networks coupled in series, each of the first switched capacitor networks comprising a second capacitor and a second switch network; the second switch network is coupled with the second capacitor and the first switch network respectively, and the second switch network is used for adjusting the series-parallel connection between the second capacitor and the first capacitor; each of the first switched capacitor networks further comprises a thirteenth node coupled with a negative electrode of the second capacitor; a plurality of second switched capacitor networks coupled in series, each of the second switched capacitor networks comprising a third capacitor and a third switch network; the third switch network is coupled with the third capacitor and the first switch network respectively, and the third switch network is used for adjusting the series-parallel connection between the third capacitor and the first capacitor; each of the second switched capacitor networks further comprises a fourteenth node coupled with a negative electrode of the third capacitor; a plurality of auxiliary circuits, each of the auxiliary circuits coupled with one of the thirteenth nodes and one of the fourteenth nodes, for converting the voltage of the thirteenth node and the voltage of the fourteenth node during a period when the first switch network, the second switch network and the third switch network are all turned off.

18. An electronic device, comprising: A battery comprising the switched capacitor circuit of any one of claims 1-17 coupled with the battery.

Images