Temperature-based multiphase current control

Abstract

Temperature-based multi-phase current control is provided. An apparatus includes a power converter controller associated with a first power converter PC1 that receives a first temperature value TPHASE1 indicative of a temperature of the first power converter PC1. A first power converter PC1 supplies a first current I1 to a load. A power converter controller associated with the first power converter PC1 receives a second temperature value TPHASE2 indicative of a temperature of the second power converter PC2. The second power converter supplies a second current I2 to the load. The first power converter PC1 adjusts the magnitude of the first current I1 based on a comparison of the first temperature value TPHASE1 and the second temperature value TPHASE2.

Description

Technical Field

[0001] This invention relates to temperature-based multiphase current control. Background Technology

[0002] One type of conventional power converter is the buck converter. Typically, to maintain the output voltage within a desired range, the controller associated with the buck converter compares the magnitude of the generated output voltage with a setpoint reference voltage. Based on the corresponding error voltage, the controller modifies the corresponding switching frequencies and / or pulse width modulations associated with activating the high-side and low-side switching circuits in the buck converter to maintain the output voltage magnitude.

[0003] In some cases, the controller controls the operation of the buck converter and the generation of the output voltage based on the amount of output current supplied to the load by the generated output voltage. For example, conventional techniques involve receiving a so-called VID (Voltage Identifier) ​​from the load (e.g., a processor powered by the output voltage). The VID indicates the setpoint voltage at which the output voltage is generated to power the load. The magnitude of the VID setting (e.g., a setpoint reference voltage) can vary depending on the magnitude of the output current. In a manner as previously discussed, the power supply controller can be configured to adjust the magnitude of the output voltage supplied to the load based on a target setpoint voltage derived from the received VID value.

[0004] A typical power supply system may include an implementation where multiple buck converters are connected in parallel to produce a corresponding output voltage to power a load. Typically, the power supply system includes a single controller that operates to generate control signals for each of the multiple power converter phases. If there are many phases controlled by a single controller, numerous circuit paths are required to support the transmission of control signals to each of the multiple power converter phases. Furthermore, each power converter phase provides separate feedback to the single controller. Therefore, additional circuit paths are needed to transmit feedback from the multiple power converter phases to the single controller. Summary of the Invention

[0005] The realization of clean energy (or green technology) is crucial for reducing human impact on the environment. Generally, clean energy encompasses any evolving methods and materials used to reduce the overall environmental toxicity caused by energy consumption.

[0006] This disclosure includes observations such as that raw energy received from green or non-green energy sources typically needs to be converted into an appropriate form (e.g., desired AC voltage, DC voltage, etc.) before it can be used to power end devices such as servers, computers, mobile communication devices, etc. Regardless of whether energy is received from green or non-green energy sources, the aim is to utilize the raw energy provided by such systems most efficiently to reduce environmental impact. This disclosure contributes to reducing carbon footprint (and green energy) through more efficient energy conversion.

[0007] Furthermore, this disclosure includes the observation that it is desirable to reduce the number of circuit paths required to support the controller and the multiple power converter phases controlled by the controller for transmitting signals. Reducing the number of circuit paths advantageously reduces the complexity of implementing the corresponding power supply comprising the multiple corresponding power converter phases.

[0008] More specifically, an apparatus as discussed herein includes: a first power converter operable to: receive a first temperature value indicating the temperature of the first power converter, the first power converter supplying a first current to a load; receive a second temperature value indicating the temperature of a second power converter, the second power converter supplying a second current to the load; and adjust the magnitude of the first current based on a comparison of the first temperature value and the second temperature value.

[0009] A comparison of a first temperature value and a second temperature value can indicate that the temperature of the first power converter is lower than that of the second power converter. The first power converter can be configured to: receive a first pulse width modulation (PWM) control signal, which is supplied to both the first and second power converters to control a first current and a second current; and, in response to the first temperature value being lower than the second temperature value, adjust the timing of the edge of the received first PWM control signal to generate a second PWM control signal, which is operable to control the magnitude of the first current.

[0010] In one example, the edge is the trailing edge of the received first pulse width modulation control signal.

[0011] In another example, in response to the first power converter adjusting the magnitude of the first current, the controller adjusts the duty cycle of the first pulse width modulation control signal received by the first power converter.

[0012] Furthermore, the first power converter can be configured to stop increasing the magnitude of the first current in response to detecting that the first temperature value is within a threshold level of the second temperature value.

[0013] Furthermore, the first power converter can be configured to control the magnitude of the first current by selecting a delay signal from a tapped delay line to control the corresponding timing of the edge of the first control signal, thereby adjusting the magnitude of the first current.

[0014] As further discussed herein, the first power converter is operable to adjust the magnitude of the first current via implementing a first current-starved inverter circuit, which is operable to adjust the timing of the trailing edge of the first control signal to generate a second control signal, which is operable to control the magnitude of the first current.

[0015] According to another example, the first power converter can be configured to: i) receive a first control signal for controlling the magnitude of a first current, and ii) convert the first control signal into a second control signal via a continuous delay element circuit, the current continuous delay element circuit being operable to control the timing of the trailing edge of the second control signal.

[0016] Another device, as discussed herein, can be configured to include a first power converter operable to: receive control signals supplied to each of a plurality of power converters including the first power converter and the second power converter; receive temperature information associated with the first power converter and the second power converter; and adjust the control signals based on the received temperature information, the adjusted control signals operable to control a first current output from the first power converter to a load.

[0017] The temperature information may include a first temperature value and a second temperature value, wherein the first temperature value indicates the temperature of the first power converter, and wherein the second temperature value indicates the temperature of the second power converter.

[0018] In one example, the control signal is a pulse-width modulation (PWM) control signal supplied to both the first power converter and the second power converter. Adjustment of the control signal based on temperature information may include: in response to a second temperature value being greater than a first temperature value, the first power converter or other suitable entity adjusting the duty cycle of the PWM control signal implemented by the first power converter to generate a first current. The adjusted duty cycle of the PWM control signal implemented by the first power converter can be operated to reduce: i) the magnitude of the second current supplied to the load by the second power converter, and ii) the temperature of the second power converter.

[0019] Additional examples discussed herein include methods. One method includes: receiving a first temperature value indicating the temperature of a first power converter, the first power converter supplying a first current to a load; receiving a second temperature value indicating the temperature of a second power converter, the second power converter supplying a second current to a load; and adjusting the magnitude of the first current based on a comparison of the first temperature value and the second temperature value.

[0020] The techniques discussed in this paper are more useful than conventional techniques. For example, temperature-based adjustment of the common pulse width modulation control signal, as discussed in this paper, is a novel distributed control function that supports better temperature balance. This, in turn, enables efficient power conversion via less complex power converter circuitry.

[0021] These examples and other more specific examples will be presented in more detail below.

[0022] Note that while the examples discussed in this article apply to power converters, the concepts disclosed herein can be advantageously applied to any other suitable topology as well as general power control applications.

[0023] Note that any resource discussed herein may include one or more computerized devices, controllers, mobile communication devices, servers, base stations, wireless communication devices, communication management systems, workstations, user equipment, handheld or laptop computers, etc., to perform and / or support any or all of the method operations disclosed herein. In other words, one or more computerized devices or processors may be programmed and / or configured to operate as described herein to perform the different examples as described herein.

[0024] Other examples in this document include software programs for performing the steps and operations outlined above and disclosed in detail below. One such example includes a computer program product comprising software instructions encoded thereon for subsequent execution on a non-transitory computer-readable storage medium (i.e., any computer-readable hardware storage medium). When executed in a computerized device (hardware) having a processor, the instructions program the processor (hardware) and / or cause the processor (hardware) to perform the operations disclosed herein. Such arrangements are typically provided as software, code, instructions, and / or other data (e.g., data structures) disposed on or encoded in firmware on a non-transitory computer-readable storage medium such as optical media (e.g., CD-ROM), floppy disk, hard disk, memory stick, storage device, etc., or on other media such as one or more ROMs, RAMs, PROMs, etc., or provided as application-specific integrated circuits (ASICs), etc. Software or firmware or other such configurations may be installed on a computerized device to cause the computerized device to perform the techniques described herein.

[0025] Therefore, the examples in this article involve methods, systems, computer program products, etc., that support the operations discussed herein.

[0026] An example of this document includes a computer-readable storage medium and / or system on which instructions are stored. When executed by computer processor hardware, the instructions cause the computer processor hardware (e.g., one or more processor devices located at the same or different locations) to: receive a first temperature value (TPHASE1) indicating the temperature of a first power converter PC1, which supplies a first current I1 to a load; receive a second temperature value (TPHASE2) indicating the temperature of a second power converter PC2, which supplies a second current I2 to the load; and adjust the magnitude of the first current I1 based on a comparison of the first temperature value TPHASE1 and the second temperature value TPHASE2.

[0027] For clarity, the order of the steps above has been added. Note that any processing operations as discussed in this article can be performed in any suitable order.

[0028] Other examples of this disclosure include software programs and / or corresponding hardware for performing any of the method example steps and operations outlined above and disclosed in detail below.

[0029] It should be understood that the systems, methods, apparatuses, instructions on computer-readable storage media discussed herein can also be strictly implemented as software programs, firmware, a mixture of software, hardware and / or firmware, or only as hardware, such as within a processor (hardware or software), an operating system, or a software application.

[0030] As discussed herein, the techniques described are well-suited for applications requiring the implementation of one or more power converters to deliver current to a load. However, it should be noted that the examples in this paper are not limited to such applications, and the techniques discussed herein are also well-suited for other applications.

[0031] Furthermore, it should be noted that although each of the different features, techniques, configurations, etc., described herein may be discussed in different places, the intention of this disclosure is that each conception in the invention may be selectively implemented independently of each other or in combination of each other, where appropriate. Therefore, one or more of the inventions as described herein can be implemented and observed in many different ways.

[0032] Furthermore, it should be noted that this initial discussion of the examples (a brief description of the examples) is not intended to specify every example and / or incremental novelty aspect of this disclosure or the claimed invention. Rather, this brief description merely presents general examples and corresponding novelty points relative to conventional techniques. For additional details and / or possible perspectives (arrangements) of the invention, the reader should refer to the detailed description section of this disclosure (which is a summary of the examples) and the corresponding drawings, which are discussed further below. Attached Figure Description

[0033] Figure 1 This is an example diagram illustrating an implementation of a power converter, as discussed herein, comprising multiple power converter phases controlled by a multiphase controller.

[0034] Figure 2 This is an example diagram illustrating the power converter and corresponding circuitry discussed herein.

[0035] Figure 3 This is an example diagram illustrating an implementation of a power converter, as discussed herein, comprising multiple power converter phases controlled by a multiphase controller.

[0036] Figure 4 This is an example diagram illustrating the power converter and corresponding circuitry discussed herein.

[0037] Figure 5 This is an example timing diagram illustrating the adjustment of the trailing edge of the pulse width modulation control signal to generate the output control signal, as discussed herein.

[0038] Figure 6 This is an example diagram illustrating a pulse width modulation signal generator as discussed herein, which is operable to adjust the leading and / or trailing edges of a corresponding received control signal.

[0039] Figure 7 This is an example diagram illustrating a pulse width modulation signal generator as discussed herein, which is operable to adjust the leading and / or trailing edges of a corresponding received control signal.

[0040] Figure 8 This is an example diagram illustrating a variable delay circuit, as discussed herein, that can be operated to delay a clock signal.

[0041] Figure 9 This is an example diagram illustrating the delay versus input voltage associated with a variable delay circuit as discussed herein.

[0042] Figure 10 This is an example diagram illustrating a hybrid pulse width modulation signal generator that provides edge delay, as discussed herein.

[0043] Figure 11 This is an example flowchart illustrating the operation of controlling the output current from each of several different power converters, as discussed in this article.

[0044] Figure 12 This is an example diagram illustrating computer processor hardware and related software instructions operable to perform methods as discussed herein.

[0045] Figure 13 This is an example diagram illustrating the methods and corresponding functions associated with the circuits discussed herein.

[0046] The foregoing and other objects, features, and advantages of the invention will become apparent from the following more detailed description of preferred examples as illustrated in the accompanying drawings, in which similar reference numerals refer to the same parts throughout the different views. The drawings are not necessarily drawn to scale, but are intended to illustrate examples, principles, concepts, etc. Detailed Implementation

[0047] The power supply includes multiple power converter phases. As discussed herein, a power converter controller associated with a first power converter receives a first temperature value indicating the temperature of the first power converter. The first power converter supplies a first current to the load. The power converter controller associated with the first power converter also receives a second temperature value indicating the temperature of a second power converter. The second power converter supplies a second current to the load. Based on a comparison of the first and second temperature values, the first power converter adjusts the magnitude of the first current.

[0048] Adjusting the magnitude of the first current supplied to the load by the first power converter may include increasing the magnitude of the first current, which results in a decrease in the second current supplied to the load by the second power converter. Increasing the magnitude of the first current can raise the temperature of the first power converter, while decreasing the magnitude of the second current can lower the temperature of the second power converter, thereby creating a better temperature balance between the first and second power converters, even though they supply different magnitudes of current to the load.

[0049] As discussed in this paper, temperature sensing can be performed on a per-loop basis, where each of the multiple power converter TMON pins is connected together and fed to the TSEN pin of the central controller. In one example, the TMON signal sent to the central controller could be the ORing of the highest voltage (corresponding to the highest-temperature power converter). The highest voltage is encoded to indicate the temperature of the highest-temperature power converter. In this case, the central controller of each power converter phase knows the highest-temperature power converter among the multiple power converters, which together generate an output voltage and a corresponding output current to supply power to the load.

[0050] It should also be noted that the temperature of each power converter in the different power converters can vary depending on the corresponding current supplied to the load. As previously discussed, one function of the power converters and corresponding distributed controllers discussed herein is to achieve better thermal balance among multiple power converters without generating excessive current imbalances. In other words, monitoring the temperature associated with the power converter phases and the thermal balance of multiple power converters, as described herein, can lead to current imbalances. However, as discussed herein, the amount of thermal balance within the power converter phases can be limited so that excessive current imbalances do not exist among the different power converters supplying the corresponding current to the load.

[0051] As a more specific example as discussed herein, to achieve thermal equilibrium, the cooler phases (those with a TMON signal at a temperature lower than that of the hottest power converter) increase their corresponding duty cycles (e.g., by increasing the edge delay of the received pulse width modulation control signal) to increase the current supplied to the load by that power converter phase. The increase in current supplied by one or more cooler power converters reduces the amount of current supplied by the hottest power converter. This reduction in current supplied by the hottest power converter leads to cooling of that hottest power converter.

[0052] It should also be noted that a power converter phase determined to be cooler than the hottest power converter phase can have any edge, such as the trailing edge of the corresponding received pulse width modulation signal, adjusted to increase the duty cycle of the received common pulse width modulation signal and deliver a higher amount of current to the corresponding load. If desired, the leading edge of the received pulse width modulation control signal can be adjusted for finer resolution.

[0053] As previously discussed, an increase in the current supplied by the cooler power converter phase results in a decrease in the current supplied by the hottest power converter phase. Therefore, through a voltage regulation control loop implemented via a central controller, as discussed herein, the hotter phase will ultimately supply less current to the load based on the increased current of the cooler power converter phase. This decrease in the current supplied by the hottest power converter phase leads to a decrease in the temperature of the hottest power converter phase, resulting in a more balanced temperature relative to each other within certain limits.

[0054] Figure 1 This is an example diagram illustrating the implementation of a power supply comprising multiple distributed power converter phases controlled by a (central) multiphase controller, as discussed herein.

[0055] As shown, Figure 1The power supply 100 includes a controller 140 (e.g., a multiphase controller, a current controller, controller hardware, etc.), resistors R11 and R21, power converter phases 111, 112, 121, and 122, output capacitor C110, and dynamic load 118.

[0056] Each power converter in the power converters (e.g., power converter phases) discussed herein can be configured to include a corresponding distributed temperature balancer function DTBxx (also known as a distributed temperature balancer, controller, hardware, circuit, etc., e.g., digital-based, analog-based, or a combination of analog and digital-based circuits). Through the distributed temperature balancer function DTBxx, the cooler power converter phase increases its output current supplied to the dynamic load 118, while the hotter power converter phase ultimately supplies less current (reducing its temperature).

[0057] For example, power converter phase 111 includes a temperature balancing function DTB11 (e.g., a distributed temperature balancer DTB11), power converter phase 112 includes a temperature balancing function DTB12 (e.g., a distributed temperature balancer DTB12), power converter phase 121 includes a temperature balancing function DTB21 (e.g., a distributed temperature balancer DTB21), and power converter phase 122 includes a temperature balancing function DTB22 (e.g., a distributed temperature balancer DTB22).

[0058] The power converters operate in parallel to generate an output voltage 123 and a corresponding output current 122 supplied to the dynamic load 118.

[0059] Therefore, each temperature balancing function discussed in this paper can be considered as a controller, signal generator, etc.

[0060] Each power converter phase in the power supply 100 can be configured to generate a corresponding feedback signal indicating the magnitude of the corresponding current supplied by that power converter phase to the load 118.

[0061] For example, power converter phase 111 includes a corresponding current monitor operable to measure the magnitude of the current i11 supplied by power converter phase 111 to the corresponding load 118 via inductor L11. Current i11 contributes to generating output current 122 and maintaining the magnitude of output voltage 123 at a desired setpoint reference voltage VREF1. Temperature balancing function DTB11 or other suitable entity associated with power converter phase 111 generates a corresponding output signal ISEN11 indicating the magnitude of current i11. In one example, signal ISEN11 is a current proportional to the magnitude of current i11. Signal ISEN11 is output from power converter phase 111 to node N11 (circuit path), where the corresponding current from signal ISEN11 flows through resistor R11 to the ground reference voltage.

[0062] Power converter phase 112 includes a corresponding current monitor operable to measure the magnitude of the current i12 supplied by power converter phase 112 to the corresponding load 118 through inductor L12. Current i12 helps maintain the magnitude of output voltage 123 at a desired setpoint reference voltage VREF1. Temperature balancing function DTB12 or other suitable entity associated with power converter phase 112 generates a corresponding signal ISEN12 indicating the magnitude of current i12. In one example, signal ISEN12 is the output current proportional to the magnitude of current i12. Signal ISEN12 is output from power converter phase 112 to node N11, where the corresponding current from signal ISEN12 flows through resistor R11 to the ground reference voltage.

[0063] In this configuration, the voltage IAVG1 supplied to the multiphase controller 140 at node N11 indicates the magnitude of the total current supplied to the load 118 by the combination of power converter phases 111 and 112 (e.g., the magnitude of the total current is the sum of currents i11 and i12). Therefore, transmitting the signal IAVG1 to the controller 140 indicates the total current provided to the load 118 by the combination of power converter phases 111 and 112.

[0064] As further shown, power converter phase 121 includes a corresponding current monitor operable to measure the magnitude of the current i21 supplied by power converter phase 121 to the corresponding load 118 via inductor L21. Current i21 contributes to generating output current 122 and maintaining the magnitude of output voltage 123 at a desired setpoint reference voltage VREF1. Temperature balancing function DTB21 or other suitable entity associated with power converter phase 121 generates a corresponding signal ISEN21 indicating the magnitude of current i21. In one example, signal ISEN21 is a current proportional to the magnitude of current i21. Signal ISEN21 is output from power converter phase 121 to node N21 (e.g., a circuit path), where the corresponding current from signal ISEN21 flows through resistor R21 to a ground reference voltage.

[0065] Power converter phase 122 includes a corresponding current monitor operable to measure the magnitude of the current i22 supplied by power converter phase 122 to the corresponding load 118 through inductor L22. Current i22 helps maintain the magnitude of output voltage 123 at the desired setpoint reference voltage VREF1. Temperature balancing function DTB22 or other suitable entity associated with power converter phase 122 generates a corresponding signal ISEN22 indicating the magnitude of current i22. In one example, signal ISEN22 is a current proportional to the magnitude of current i22. Signal ISEN22 is output from power converter phase 122 to node N21, where the corresponding current from signal ISEN22 flows through resistor R21 to the ground reference voltage.

[0066] In this case, the voltage IAVG2 at node N21 indicates the magnitude of the total current supplied to load 118 by power converter phases 121 and 122 (e.g., the magnitude of the total current is the sum of currents i21 and i22). Therefore, transmitting the signal IAVG2 to controller 140 indicates the total current supplied to load 118 by the combination of power converter phases 121 and 122.

[0067] It should also be noted that each power converter phase, as discussed herein, includes a corresponding terminal for receiving or transmitting temperature information. For example, power converter phase 111 includes terminal T11 (e.g., node, pin, port, etc.); power converter phase 112 includes terminal T12 (e.g., node, pin, port, etc.); power converter phase 121 includes terminal T21 (e.g., node, pin, port, etc.); and power converter phase 122 includes terminal T22 (e.g., node, pin, port, etc.).

[0068] Each of terminals T11, T12, T21, and T22 is connected to a common node N99, which supplies the signal TPHMAX to the multiphase controller 140. The power converter with the highest temperature outputs the signal TPHMAX to the other power converters. In one example, each power converter phase attempts to output a corresponding signal to node N99, where the output signal is encoded to indicate the temperature of the corresponding power converter phase transmitting the signal. However, the combination of the output temperature signals operates in an ORing manner, such that the signal TPHMAX represents the temperature signal transmitted by the hottest power converter phase. Therefore, the multiphase controller 140 may not know which is the hottest power converter phase, but is instead notified of the hottest power converter phase. Each power converter phase also knows the hottest power converter phase via the signal TPHMAX, which may or may not be itself. Each power converter phase also knows its own temperature.

[0069] like Figure 1 As further shown, the multiphase controller 140 can be configured to receive a feedback signal 131 indicating the magnitude of the output voltage 123. Also note that the controller 140 receives a setpoint reference voltage VREF1 indicating the desired magnitude for controlling the output voltage 123.

[0070] Based on the received feedback 131 (the magnitude of the output voltage 123) and the corresponding reference voltage VREF1, the controller 140: i) generates a pulse width modulation control signal PWM1 to control the magnitude of the corresponding output current supplied to the load 118 by each of the power converter phases 111 and 112; and ii) generates a pulse width modulation control signal PWM2 to control the magnitude of the corresponding output current supplied to the load 118 by each of the power converter phases 121 and 122.

[0071] As further discussed herein, each power converter phase in the power converter phase provides adjustment to the corresponding pulse width modulation signal received from the multiphase controller 140, such that the power converter phase itself also provides temperature regulation of the power converter phase.

[0072] More specifically, to facilitate the control (regulation) of the output voltage 123, the controller 140 generates corresponding pulse width modulation control signals PWM1 and PWM2. Each group of power converter phases receives a corresponding pulse width modulation control signal, which indicates the target magnitude of the corresponding output current controlled to the load. Instead of simply using the pulse width modulation control signals received from the controller 140 to drive the corresponding high-side and low-side switches in the respective power converter phases, each power converter phase also implements a corresponding temperature balancing function that supports equalizing the magnitude of the power converter temperature or providing better balance to the load 118 through the group (e.g., a first group including power converter phases 111, 112, etc., or a second group including power converter phases 121, 122, etc.).

[0073] More specifically, controller 140 generates a corresponding pulse width modulation control signal PWM1 and supplies it to power converter phase 111 and power converter phase 112 via node N12 (i.e., circuit path).

[0074] The controller 140 generates a corresponding pulse width modulation control signal PWM2 and supplies it to power converter phase 121 and power converter phase 122 through node N22 (i.e., the circuit path).

[0075] As discussed herein, typically, the corresponding temperature balancing function associated with each of the power converters 111 and 112 adjusts the received pulse width modulation control signal PWM1 to control its corresponding output current, such that each of the power converter phases 111 and 112 adjusts its corresponding current to the load 118 (e.g., i11 and i12) so that the temperatures of the power converter phases are closer to each other in magnitude. Therefore, unlike controller 140, which has the burden of generating separate control signals and transmitting them to each power converter phase to balance the temperature of the power converter phase, the function of providing temperature balancing among multiple power converter phases, as discussed herein, is distributed among the power converter phases themselves.

[0076] As further illustrated, controller 140 generates a corresponding pulse width modulation control signal PWM2 and supplies it to power converter phases 121 and 122 via node N22 (i.e., the circuit path). As discussed herein, a corresponding temperature balancing function associated with each power converter in the power converters adjusts the received pulse width modulation control signal PWM2 such that each power converter phase in power converter phases 121 and 122 adjusts its corresponding output current to load 118 (e.g., i21 and i22) so that the temperatures of the power converter phases are closer to each other in magnitude, thereby providing better temperature balance among the power converter phases. Therefore, unlike controller 140, which has the burden of generating separate control signals and sending them to each of the power converter phases to balance the temperature of the power converter phases, the function of providing temperature balance among multiple power converter phases is distributed to the power converter phases themselves.

[0077] It should also be noted that controller 140 can be configured to control the grouping of power converter phases to provide different magnitudes of current to the corresponding loads 118. For example, controller 140 can be configured to generate a control signal PWM1 to supply a first magnitude of current (the sum of currents i11 and i12, such as 20 amps or other suitable amount) to the load from a combination of power converter phases 111 and 112. Controller 140 can be configured to generate a control signal PWM2 to supply a second magnitude of current (the sum of currents i21 and i22, such as 40 amps or other suitable amount) to the load 118 from a combination of power converter phases 121 and 122.

[0078] As discussed herein, the additional functionality of providing temperature balance within the power converter phases reduces the stress associated with the power converter phases supplying the corresponding current to the load. For example, if the total current required by the load is 40 amps, and each of the first and second power converter phases is controlled to supply 20 amps to the load without adjustment by the individual power converter phases, this may stress the first power converter phase (e.g., at a temperature of 100 degrees Celsius) but not the second power converter phase (e.g., at a temperature of 70 degrees Celsius). Based on the temperature balance discussed herein, the second power converter phase can increase the magnitude of its current supply to the load from 20 amps to 25 amps. This increase in output current hidden by the second power converter phase may lead to an increase in the temperature of the second power converter phase; however, this reduces the amount of current that the first power converter needs to deliver to the load, thereby lowering the temperature of the first power converter. Based on their respective output current regulation, distributing and balancing each power converter in the power converter to a temperature of approximately 85 degrees Celsius may result in the first power converter supplying 15 amps to the load and the second power converter supplying 25 amps to the load, thus causing the first power converter phase and the second power converter phase to be relatively close to each other in temperature, for example, each at 85 degrees Celsius.

[0079] Figure 2 This is an example diagram illustrating the power converter and corresponding circuitry discussed herein.

[0080] This example illustrates the relationship with, for example Figure 1 The circuitry associated with each power converter phase in the diagram is shown. As discussed below, the value of X can be 1 or 2, corresponding to different power converter phases, each of which operates in a similar manner.

[0081] For example, each power converter phase (power converter phases 111, 112, etc.) includes a temperature balancing function DTB1X, a driver circuit 150-X, a high-side switching circuit S1X-H, a low-side switching circuit S1X-L, an inductor L1X, a temperature monitor 22X, and a current monitor 21X.

[0082] In this case, power converter phase 111 (11) includes temperature balancing function DTB11, driver circuit 150-1, high-side switching circuit S11-H, low-side switching circuit S11-L, inductor L11, temperature monitor 221 and current monitor 211; power converter phase 112 (12) includes temperature balancing function DTB12, driver circuit 150-2, high-side switching circuit S12-H, low-side switching circuit S12-L, inductor L12, temperature monitor 222 and current monitor 212; and so on.

[0083] As previously discussed, the temperature balancing function DTB1X receives the pulse width modulation control signal PWM1 generated by the controller 140. The temperature balancing function DTB1X also receives the local temperature TPHASE1X (its own temperature) of power converter phase 1X and a temperature value (TPHMAX) indicating the highest temperature of the remote power converter phase that generates the corresponding output voltage 123. If the corresponding power converter phase 1X has the highest temperature, then temperature TPHASE1X equals TPHMAX, and the corresponding power converter phase outputs this value to the other power converter phases.

[0084] As discussed herein, if a given power converter phase has the highest temperature among all phases, that power converter phase will not adjust the duty cycle of the received pulse width modulation signal PWM1 to generate the pulse width modulation control signal PWMXC. However, if a given power converter phase does not have the highest temperature among all phases (e.g., determined based on a local temperature value relative to the highest temperature TPHMAX received from the hottest power converter phase via terminal T1X), that power converter phase can be configured to adjust the duty cycle of the received pulse width modulation signal PWM1 to generate the pulse width modulation control signal PWMXC. In the latter case, since the power converter phase is not at the highest temperature, the temperature balancing function DTB1X increases the duty cycle of the received pulse width modulation signal PWM1 to control the switching circuit S1X-H to generate the pulse width modulation control signal PWMXC. The increased duty cycle increases the magnitude of the current i1X supplied by that power converter phase to the load 118.

[0085] As further illustrated, the corresponding power converter phase can be configured to include an adder function 299-X for receiving signals TPHMAX and TDEAD. Signal TDEAD is a temperature margin value. Adder function 299-X generates signal TPHMAX minus TDEAD (TPHMAX - TDEAD) and supplies it to comparator function 191-X. In one example, comparator function 191-X compares the signal (TPHMAX - TDEAD) with the local temperature TPHASE1X of power converter phase 1X. If the local temperature TPHASE1X of power converter phase 1X, as indicated by signal 277-X, is less than the signal (TPHMAX - TDEAD), temperature balancing function DTB1X adjusts (increases) the duty cycle of the received pulse width modulation signal PWM1 to generate a pulse width modulation control signal PWMXC for controlling the corresponding switches S1X-H and S1X-L. The increased duty cycle associated with the pulse width modulation signal PWMXC increases the magnitude of the current i1X supplied by the power converter phase to the corresponding load 118.

[0086] Therefore, if the first power converter phase is determined not to be the hottest power converter phase, it can be configured to increase the magnitude of its output current supplied to load 118, thereby causing an increase in the temperature of the first power converter phase. The increase in the magnitude of the output current supplied to load 118 by the first power converter phase causes a decrease in the temperature of the second power converter phase.

[0087] As discussed herein, by adjusting one or more of the leading or trailing edges of the corresponding control signal PWMXC, the duty cycle or pulse width on-time associated with the adjusted pulse width modulation control signal PWMXC can be increased or decreased. Therefore, the leading or trailing edges of control signals PWM1 and / or PWMXC can be adjusted to allow the lower-temperature power converter to supply more current toward the dynamic load 118.

[0088] Therefore, refer to Figure 1The temperature balancing function DTB11 can be configured to receive a first temperature value (the local temperature TPHASE1 of power converter 111) indicating the temperature of the first power converter 111, which supplies a first current i11 to the dynamic load 118. Power converter 112 can operate at a second temperature (hottest temperature), resulting in the transmission of a second temperature value (TPHASE2 or TPHMAX) to power converter phase 111 via node N99. The second temperature value TPHASE2 or TPHMAX received from power converter phase 112 indicates the temperature of the second power converter 112. The second power converter phase 112 supplies a second current i12 to the load 118. Power converter phase 111 and the corresponding temperature balancing function DTB11 can be configured to compare the first temperature value TPHASE1 or TPHMAX or an adjusted value (TPHMAX-TDEAD) with the second temperature value TPHASE2 to determine if power converter phase 111 is at a significantly lower temperature than power converter phase 112. In this configuration, power converter phase 111 adjusts the duty cycle associated with the received pulse width modulation control signal PWM1 to generate an adjusted pulse width modulation control signal PWM1C that controls the magnitude of the current i11 supplied by power converter phase 111 to load 118. In one example, adjusting the magnitude of the first current i11 based on a comparison of a first temperature value TPHASE1 with a second temperature value TPHASE2 or TPHMAX or (TPHMAX-TDEAD) includes: power converter phase 111 increasing the duty cycle associated with the pulse width modulation control signal PWM1C (relative to the received pulse width modulation control signal PWM1), such that power converter 111 supplies an increased amount of current i11 to load 118. The increase in the magnitude of the current supplied to load 118 may cause a temporary increase in the magnitude of the output voltage 123. Multiphase controller 140 receives feedback 131, such as the magnitude of the output voltage 123, via a first feedback loop, and then adjusts the duty cycle of the pulse width modulation control signal PWM1 to regulate the voltage magnitude relative to a desired setpoint reference voltage VREF1. The second control loop, implemented by the power converter phase, uses temperature as a basis to locally and individually (in a distributed manner with each power converter in different power converter phases) adjust the output current from each phase, so that the temperature associated with each power converter in different power converters is more balanced (more similar in magnitude, although not necessarily exactly equal, but at least within the temperature margin value such as TDEAD).

[0089] Figure 3 This is an example diagram illustrating an implementation of a power converter, as discussed herein, comprising multiple power converter phases controlled by a multiphase controller.

[0090] As shown,Figure 3 The power supply 100-2 includes a controller 140 (e.g., a multiphase controller, a current controller, controller hardware, etc.), a resistor R4, power converter phases 101, 102, 103, and 104, an output capacitor C110, and a dynamic load 118.

[0091] Each power converter in the power converters discussed herein can be configured to include a corresponding temperature balancer function (also referred to as a temperature balancer, controller, hardware, circuit, etc., such as digital circuit-based, analog circuit-based, or a combination of analog and digital circuit-based). For example, power converter phase 101 includes a temperature balancing function DTB1 (e.g., distributed temperature balancer DTB1), power converter phase 102 includes a temperature balancing function DTB2 (e.g., distributed temperature balancer DTB2), power converter phase 103 includes a temperature balancing function DTB3 (e.g., distributed temperature balancer DTB3), and power converter phase 104 includes a temperature balancing function DTB4 (e.g., distributed temperature balancer DTB4).

[0092] Therefore, each temperature balancing function discussed in this paper can be considered as a controller, signal generator, etc.

[0093] Each power converter phase in power supply 100-2 generates a corresponding feedback signal that indicates the magnitude of the corresponding current supplied by that power converter phase to load 118.

[0094] For example, power converter phase 101 includes a corresponding current monitor operable to measure the magnitude of the current i1 supplied by power converter phase 101 to the corresponding load 118 through inductor L1. Current i1 helps maintain the magnitude of output voltage 123 at a desired setpoint reference voltage VREF1. Power converter phase 101 or other suitable entity generates a corresponding signal ISEN1 indicating the magnitude of current i1. In one example, signal ISEN1 is a current proportional to the magnitude of current i1. Signal ISEN1 is output from power converter phase 101 to node N31 (circuit path), where the corresponding current from signal ISEN1 flows through resistor R4 to the ground reference voltage.

[0095] Power converter phase 102 includes a corresponding current monitor operable to measure the magnitude of the current i2 supplied by power converter phase 102 to the corresponding load 118 through inductor L2. Current i2 helps maintain the magnitude of output voltage 123 at the desired setpoint reference voltage VREF1. Power converter phase 102 generates a corresponding signal ISEN2 indicating the magnitude of current i2. In one example, signal ISEN2 is a current proportional to the magnitude of current i2. Signal ISEN2 is output from power converter phase 102 to node N31, where the corresponding current from signal ISEN2 flows through resistor R4 to the ground reference voltage.

[0096] Power converter phase 103 includes a corresponding current monitor operable to measure the magnitude of the current i3 supplied by power converter phase 103 to the corresponding load 118 through inductor L3. Current i3 helps maintain the magnitude of output voltage 123 at the desired setpoint reference voltage VREF1. Power converter phase 103 generates a corresponding signal ISEN3 indicating the magnitude of current i3. In one example, signal ISEN3 is a current proportional to the magnitude of current i3. Signal ISEN3 is output from power converter phase 103 to node N31, where the corresponding current from signal ISEN3 flows through resistor R4 to the ground reference voltage.

[0097] Power converter phase 104 includes a corresponding current monitor operable to measure the magnitude of the current i4 supplied by power converter phase 104 to the corresponding load 118 through inductor L4. Current i4 helps maintain the magnitude of output voltage 123 at the desired setpoint reference voltage VREF1. Power converter phase 104 generates a corresponding signal ISEN4 indicating the magnitude of current i4. In one example, signal ISEN4 is a current proportional to the magnitude of current i4. Signal ISEN4 is output from power converter phase 104 to node N31, where the corresponding current from signal ISEN4 flows through resistor R4 to the ground reference voltage.

[0098] In this case, the voltage IAVG at node N31 indicates the magnitude of the total current supplied to load 118 by power converter phases 101, 102, 103, and 104 (e.g., the magnitude of the total current is the sum of currents i1, i2, i3, and i4). Therefore, the signal IAVG is transmitted to controller 140 to indicate the total current supplied to load 118 by the combination of power converter phases.

[0099] like Figure 3As further shown, the controller 140 can be configured to receive a feedback signal 131 indicating the magnitude of the output voltage 123. Also note that the controller 140 receives a setpoint reference voltage VREF1 indicating the desired magnitude for controlling the output voltage 123.

[0100] The controller 140 generates a pulse width modulation control signal PWM1 to control the magnitude of the corresponding output current i1 supplied by the power converter phase 101 to the load 118.

[0101] The controller 140 generates a pulse width modulation control signal PWM2 to control the magnitude of the corresponding output current i2 supplied by the power converter phase 102 to the load 118.

[0102] The controller 140 generates a pulse width modulation control signal PWM3 to control the magnitude of the corresponding output current i3 supplied by the power converter phase 103 to the load 118.

[0103] The controller 140 generates a pulse width modulation control signal PWM4 to control the magnitude of the corresponding output current i4 supplied by the power converter phase 104 to the load 118.

[0104] To facilitate the control of the output voltage 123, the controller 140 generates corresponding pulse width modulation control signals PWM1, PWM2, PWM3 and PWM4.

[0105] Instead of simply using the received pulse width modulation control signal received from controller 140, each power converter phase in the power converter phase implements a corresponding temperature balancing function, which supports better balancing of the magnitude of the temperature associated with each of the power converter phases 101, 102, 103 and 104.

[0106] More specifically, controller 140 generates a corresponding pulse width modulation control signal PWM1 and supplies it to power converter 101. As discussed herein, the corresponding temperature balancing function DTB1 of power converter 101 adjusts the pulse width modulation control signal PWM1 to generate a pulse width modulation control signal PWM1C; the corresponding temperature balancing function DTB2 of power converter 102 adjusts the pulse width modulation control signal PWM2 to generate a pulse width modulation control signal PWM2C; the corresponding temperature balancing function DTB3 of power converter 103 adjusts the pulse width modulation control signal PWM3 to generate a pulse width modulation control signal PWM3C; the corresponding temperature balancing function DTB4 of power converter 104 adjusts the pulse width modulation control signal PWM4 to generate a pulse width modulation control signal PWM4C; and so on.

[0107] In a similar manner to those previously discussed, the temperature balancing function DTB1 can be configured to receive a first temperature value (the local temperature TPHASE1 of power converter 101) indicating the temperature of the first power converter 101, which supplies a first current i1 to the dynamic load 118. Assuming power converter 102 operates at a second temperature (hottest temperature), a second temperature value (TPHASE2 or TPHMAX) is transmitted to power converter phase 101 via node N29. The second temperature value TPHASE2 or TPHMAX received from power converter phase 102 indicates the temperature of the second power converter 102. The second power converter phase 102 supplies a second current i2 to the load 118. Power converter phase 101 and the corresponding temperature balancing function DTB1 can be configured to compare the first temperature value TPHASE1 or TPHMAX, or an adjusted value (TPHMAX-TDEAD), with the second temperature value TPHASE2 to determine if power converter phase 101 is at a significantly lower temperature than power converter phase 102. In this case, the power converter phase 101 adjusts the duty cycle associated with the received pulse width modulation control signal PWM1 to generate an adjusted pulse width modulation control signal PWM1C to increase the magnitude of the current i1 supplied by the power converter phase 101 to the load 118.

[0108] Therefore, via the first feedback loop, the multiphase controller 140 receives feedback 131, such as the magnitude of the output voltage 123, and then adjusts the duty cycles of the pulse width modulation control signals PWM1, PWM2, PWM3, etc., to regulate the magnitude of the voltage relative to the desired setpoint reference voltage VREF1. The second control loop, implemented by each power converter phase in the power converter phase, uses temperature as a basis to further adjust the output current from each phase locally (in a distributed manner, for each power converter in different power converter phases) to a value greater than the maximum temperature phase adjusted by a threshold amount, so that the temperatures associated with each power converter in the different power converters are more balanced (more similar in magnitude, although not necessarily exactly equal, but at least within a temperature margin such as TDEAD).

[0109] Therefore, unlike controller 140, which has the burden of generating and transmitting separate control signals to balance the temperature associated with each power converter phase in the power converter phase, the function of providing temperature balance among multiple power converter phases is assigned to the power converter phase itself.

[0110] Figure 4 This is an example diagram illustrating the power converter and corresponding circuitry discussed herein.

[0111] like Figure 4As shown in the example, this illustration depicts the circuitry associated with each power converter phase in power converter phase 10Y. As discussed below, the value of Y can be 1 (for power converter phase 101), 2 (for power converter phase 102), 3 (for power converter phase 103), or 4 (for power converter phase 104). This can be extended to include any number of PWM signals if desired.

[0112] For example, each corresponding power converter phase 10Y includes a temperature balancing function DTBY, a driver circuit 150-Y, a high-side switching circuit SY-H, a low-side switching circuit SY-L, an inductor LY, and a current monitor 21Y.

[0113] As previously discussed, the temperature balancing function DTBY receives a pulse width modulation control signal PWMY generated by controller 140. The temperature balancing function DTBY also receives a temperature signal TPHMAX indicating the highest temperature of remote power converter phases other than power converter phase 10Y.

[0114] Comparator 191-Y generates a signal 410-Y indicating whether TPHASEY < [TPHMAX-TDEAD]. If the magnitude of TPHASEY is less than [TPHMAX-TDEAD], the temperature balancing function DTBY adjusts the duty cycle associated with the received pulse width modulation signal PWMY to increase the magnitude of the duty cycle time during which the high-side switching circuit SY-H is active in each cycle, thereby increasing the magnitude of the current iY supplied to the load 118.

[0115] If the local temperature TPHASEY of the current power converter phase 10Y is the highest among all phases, then power converter phase 10Y will output the corresponding signal TPHASEY as the signal TPHMAX from terminal TY to other power converter phases.

[0116] In one example, as previously discussed, the highest temperature power converter phase does not adjust the duty cycle associated with the received pulse width modulation signal PWMY to generate the pulse width modulation signal PWMYC. In other words, in the latter case, the control signal PWMYC is a slightly delayed version of the received pulse width modulation signal PWMY with the same duty cycle.

[0117] Figure 5 This is an example timing diagram illustrating the adjustment of the trailing edge of the pulse width modulation control signal as discussed herein.

[0118] As previously discussed, examples in this paper may include modifying any edge (leading or trailing edge) of the corresponding pulse width modulation control signal (e.g., PWM1, PWM2, PWM3, PWM4, etc.) to provide temperature balance among multiple power converter phases as discussed herein.

[0119] Based on Figure 1 In this example of power converter phase implementing trailing edge timing adjustment, the temperature balancing function DTB1X (where X equals 1 or 2) receives the control signal PWM1 as previously discussed and converts it into a corresponding control signal PWM1XC. When the temperature of the corresponding power converter phase 11X is less than the temperature of the hottest power converter phase, the corresponding temperature balancing function DTB1X delays the corresponding trailing edge of the received control signal PWM1XC, resulting in an increased activation time of the high-side switching circuit S1X-H in the corresponding control cycle. In other words, the delay of the trailing edge associated with the control signal PWM1XC (from time T13 to time T14 or other suitable time, such as indicated by trailing edge delay 392) results in a longer on-time of the corresponding high-side switching circuit S1X-H in the corresponding control cycle, thereby increasing the magnitude of the corresponding output current i1X supplied to the load 118 through the output current i1X-1, such as... Figure 5 As shown in the image. Figure 5 The signal i1X-2 in the signal uses the original signal PWM1X (if used otherwise) to indicate the lower magnitude of the output current i1X without extending the on-time of the high-side switching circuit S1X-H via the delay of the trailing edge.

[0120] Therefore, the pulse width conduction time of the control signal PWM1X is between time T11 and time T13. The adjusted pulse width (longer pulse width) associated with the signal PWM1XC is between time T12 and time T14, and its duration is longer than that between time T11 and time T13.

[0121] Figure 3The temperature balancing function operates in a similar manner. More specifically, in this example implementing trailing edge timing adjustment, the temperature balancing function DTBY (where Y equals 1 to 4) receives the control signal PWMY as discussed previously and converts it into a control signal PWMYC. When the temperature of power converter phase 10Y is less than the temperature TPHMAX of the hottest power converter phase, or when the temperature of power converter phase 10Y is less than TPHMAX-TDEAD, the corresponding temperature balancing function DTBY delays the corresponding trailing edge of the control signal PWMYC, resulting in an increased activation time of the high-side switching circuit SY-H in the corresponding control cycle. The delay of the trailing edge associated with the control signal PWMYC (from time T13 to time T14 or other suitable time) results in a longer on-time of the corresponding high-side switching circuit SY-H in the corresponding control cycle, which increases the magnitude of the corresponding output current iY supplied to the load 118 through the output current iY-1, such as... Figure 5 As shown in the image.

[0122] It should be noted that, as discussed herein, adjusting the trailing edge of the corresponding control signal via, for example, the delay increment TON alters the pulse width modulation (PWM) conduction duration associated with the originally received PWM1X or PWMY signal to generate the corresponding PWM1XC or PWMYC control signal without changing the corresponding switching frequency. In other words, the switching frequency of the trailing edge-adjusted PWM1XC control signal generated and output by the temperature balancing function is the same as the switching frequency of the PWM1XC control signal received from the controller 140 by the temperature balancing function. Figure 5 As further shown, the time period associated with period #1 is equal to the time period associated with period #2.

[0123] Figure 6 This is an example diagram illustrating a pulse width modulation signal generator as discussed herein, which is operable to adjust the leading and trailing edges of a corresponding received control signal.

[0124] In this example, the current balancing function DTBz (as previously discussed, such as any of the current balancing functions DTB11, DTB12, DTB21, DTB22, DTB1, DTB2, DTB3, DTB4, etc.) includes Figure 6 Corresponding examples of the circuits shown include amplifier A11, integrator circuit 551, trailing edge clock generator 511, circuit 541 providing discrete trailing edge duty cycle correction, and circuit 599 providing edge duty cycle control / correction.

[0125] As further shown, the integrator circuit 551 includes a resistor R51 and a capacitor C51.

[0126] The trailing edge clock generator 511 includes a D flip-flop element 521. The leading edge clock generator 512 includes a D flip-flop element 531.

[0127] In this example, the signal PWMIN represents the corresponding signals PWM1, PWM2, PWM3, PWM4, PWM1X, PWMY, etc., as previously discussed. The trailing-edge clock generator 511 includes a D flip-flop 521 that forwards the received PWMIN clock signal to a tapped delay line comprising tapped delay line elements TL11, TL12, TL13, and TL14 connected in series. As their names suggest, each tapped delay line element delays the corresponding input pulse width modulated PWMIN signal by the same or different amounts of time.

[0128] Integrator circuit 551 includes amplifier A11, resistor R51, and capacitor C51. Amplifier A11 generates a corresponding signal VCTRL_TRL at node N51, which indicates or is based on the difference between the local power converter phase temperature TPHASE signal (e.g., any one of TPHASE11, TPHASE12, TPHASE21, TPHASE22, TPHASE1, TPHASE2, TPHASE3, TPHASE4) and the signal TPHMAX-TDEAD (or only TPHMAX) (depending on the instantiation of the temperature balancing function). Node N51, connecting resistor R51 and capacitor C51, stores the corresponding signal VCTRL_TRL supplied to analog-to-digital converter 561. Analog-to-digital converter 561 converts the received signal VCTRL_TRL into signals D1 and D0 supplied to multiplexer 562. Multiplexer 562 uses the received signals D1 and D0 as address lines to select which delayed version of the PWM signal is output as signal 563 to D flip-flop 522. As indicated in the previous timing diagram, subsequent circuitry such as D flip-flop 523, D flip-flop 524, logic 525, and D flip-flop 528 use signal 591 as a basis to control the adjustment of the trailing edge of signal PWMC (e.g., signal PWM1XC or PWMYC).

[0129] As discussed previously, via Figure 6 The temperature balancing function (i.e., the circuit) shown here delays the trailing edge of the corresponding signal PWMC by a different amount selected by the multiplexer 562 when the magnitude of the signal TPHASE (temperature of the local phase) is less than that of the signal TPHMAX-TDEAD or TPHMAX, in order to increase the output current supplied by the local power converter phase.

[0130] For example, if the temperature of the local phase is greater than or equal to the value TPHMAX-TDEAD or TPHMAX, the analog-to-digital converter 561 generates a selection signal in which C0 = 0 and C1 = 0 (inputs of multiplexer 562) cause the duty cycle associated with the pulse width modulation signal PWMC to change minimally or not at all relative to the pulse width modulation signal PWMIN.

[0131] However, since the temperature of the local power converter phase is less than the maximum temperature TPHMAX, the analog-to-digital converter 561 generates different settings for C1 and C0 to delay the trailing edge of the pulse width modulation control signal PWMC relative to the pulse width modulation control signal PWMIN. This results in the pulse width modulation control signal PWMC having a longer on-time to activate the high-side switch, thereby increasing the corresponding current supplied by the power converter phase to the load 118.

[0132] Figure 7 This is an example diagram illustrating a pulse width modulation signal generator as discussed herein, which is operable to adjust the leading and trailing edges of a corresponding received control signal.

[0133] The continuous trailing edge duty cycle correction circuit 641 includes a variable delay circuit 625-1, a D flip-flop 621, a D flip-flop 522, and an amplifier circuit 651. The continuous leading edge duty cycle correction circuit 642 includes a variable delay circuit 625-2, a D flip-flop 622, a D flip-flop 532, and an amplifier circuit 652.

[0134] In this example, leading-edge correction is implemented to maintain high-resolution duty cycle adjustment. As discussed herein, trailing-edge correction allows for current increases. Current limiter 788 prevents excessive duty cycle offsets to limit current imbalance. The voltage_vmin_delay provided by voltage source 552 ensures minimal delay for the leading-edge generator function, resulting in fine-resolution relative pulse width modulation.

[0135] Integrator circuit 551 includes amplifier A11, resistor R51, and capacitor C51. Amplifier A11 generates a corresponding output signal at node N51 based on a comparison of the temperature of the corresponding phase (e.g., indicated by TPHASE1X or TPHASEY). Node N51, connecting resistor R51 and capacitor C51, stores the corresponding signal supplied to amplifier circuit 651, which converts the voltage at node N51 into a corresponding signal VCTRL_TRL supplied to variable delay circuit 625-1. Variable delay circuit 625-1 receives the original signal PWMIN and, as its name suggests, varies the amount of delay (392) applied to the trailing edge of the received control signal PWMIN according to the magnitude of signal VCTRL_TRL to generate control signal PWMC. Details of variable delay circuit 625-1 are provided in [details of variable delay circuit 625-1]. Figure 7 As shown in the image.

[0136] As discussed previously, via Figure 6 The temperature balancing function (i.e., the circuitry) shown delays the trailing edge of the corresponding PWMC signal by a different amount selected by the variable delay circuit 625-X (625-1) when the temperature associated with the local power converter phase is less than the temperature of the hottest power converter phase within the margin TDEAD. For example, as the temperature difference between the corresponding power converter phase and the hottest power converter phase increases, the magnitude of the delay (VCTRL) control adjustment for the trailing edge delay 392 of the final control signal PWMC also increases, causing the corresponding lower-temperature power converter phase to supply additional current to the corresponding load, as previously discussed.

[0137] Figure 8 This is an example diagram illustrating a variable delay circuit, as discussed herein, that can be operated to delay a clock signal.

[0138] In this example, the variable delay circuit 625-X (from Figure 7 (where X=1 or X=2) includes multiple field-effect transistors Q1 to Q9. Power supply 715 applies an input voltage Vcc to power the corresponding variable delay circuit 625-X. The variable delay circuit 625-X receives the clock signal CLK at node N5X and outputs a delayed clock signal CLKd at node N6X. (The following...) Figure 9 The graph 800 in the figure shows the amount of delay between the clock CLK and the output clock CLKd according to the input control signal VCTRL (for the leading edge VCTRL_TRL or the trailing edge VCTRL_LED).

[0139] In one example, the variable delay circuit 625-X can be a current-starved inverter. In this case, a first power converter controller (e.g., a current balancing function DTB) associated with the power converter is configured to implement a first current-starved inverter circuit (e.g., variable delay circuit 625-1) for converting the first control signal PWMIN (PWM1X) into a control signal PWM1XC, wherein the first current-starved inverter circuit is operable to control the timing of the trailing edge of the control signal PWMC as needed.

[0140] As previously discussed, the variable delay circuit 625-X can be a current-starved inverter. In this case, a first power converter controller (e.g., a current balancing function DTB) associated with the power converter is configured to implement a second current-starved inverter circuit (e.g., the variable delay circuit 625-2) for converting the first control signal PWMIN (PWM1X) into a control signal PWM1XC, wherein the second current-starved inverter circuit is operable to control the timing of the leading edge of the control signal PWMC as needed.

[0141] Figure 9 This is an example diagram illustrating the delay versus input voltage associated with the variable delay circuit discussed herein.

[0142] In this example, graph 800 includes function 810, which indicates the amount of time delay provided by the variable delay circuit (for delaying the leading edge or for delaying the trailing edge), as previously discussed. Note that function 810 can vary depending on one or more parameters (e.g., temperature) associated with the corresponding variable delay circuit.

[0143] Refer again Figure 7 Voltage source 552 generates a corresponding voltage signal V_min_delay at node N52. The signal V_min_delay at node N52 is transmitted to amplifier circuit 652, which converts the voltage at node N52 into a corresponding signal VCTRL_LED supplied to variable delay circuit 625-2 to achieve a minimum delay of the leading edge associated with pulse width modulation control signal PWMC relative to pulse width modulation control signal PWMIN.

[0144] Figure 10 This is an example diagram illustrating a hybrid pulse width modulation signal generator as discussed in this paper.

[0145] In this example, the current balancing function DTBz includes a mixed trailing edge duty cycle correction circuit 1041. Additionally, the current balancing function DTBz includes a mixed leading edge duty cycle correction circuit 1042.

[0146] likeFigure 10 As shown, the hybrid post-edge duty cycle correction circuit 1041 includes a variable delay circuit 625-1 and a discrete delay circuit 581. As previously discussed, the integrator circuit 551 generates a corresponding voltage at node N51 indicating the magnitude of the error between the hottest power converter phase and the current power converter phase (the corresponding colder power converter phase). The signal at node N51 is transmitted to the VCTR input of the variable delay circuit 625-1 and the VCTR input of the circuit 581.

[0147] Variable delay circuits 625-1 and 581 receive the original signal PWMIN and, as their names suggest, vary the amount of delay applied to the trailing edge of the received control signal PWMIN according to the magnitude of the signal VCTRL_TRL to generate the control signal PWMC. In this example, multiplexer 1011 selects between continuous delay generator 625-1 or discrete delay generator 581 to output the corresponding signal to D flip-flop 522.

[0148] If the magnitude of the power converter temperature difference, as indicated by the voltage at node N51, is higher than a threshold, circuit 651 uses the output of variable delay circuit 625-1 to cause the multiplexer to select channel S0 for transmission to D flip-flop 522. In this case, the trailing edge associated with signal PWMC is generated based on the output of variable delay circuit 625-1.

[0149] Conversely, if the error is greater than the threshold, circuit 651 uses the output of circuit 581 to cause the multiplexer to select channel S1 to be transmitted to D flip-flop 522, in which case the trailing edge associated with signal PWMC is generated based on the output of circuit 581.

[0150] like Figure 10 As further shown, the hybrid leading-edge duty cycle correction circuit 1042 includes a variable delay circuit 625-2 and a D flip-flop 532. A voltage V_min_delay is input to the VCTR pin of the variable delay circuit 625-2. The output of the variable delay circuit 625-2 is output to the D flip-flop 532 to control the signal 592 and provide a minimum delay associated with the leading edge of the signal PWMC.

[0151] Figure 11 This is an example flowchart illustrating the operation of controlling the output current from each of the multiple different power converters, as discussed in this article.

[0152] Figure 11 Flowchart 1100 illustrates the temperature equilibrium as discussed herein. In the initial state 1110, it is assumed that... Figure 1 or Figure 3Each power converter in the power converter supplies substantially equal amounts of current to the load 118. In other words, it is assumed that currents i11, i12, i21, and i22 are substantially equal.

[0153] However, it is further assumed that power converter phase 112 is the hottest power converter phase in the group. In this case, power converter phase 112 transmits the corresponding signal TPHMAX from the corresponding terminal T12 to node N99. Each component, such as power converter phase 111, power converter phase 121, power converter phase 122, and multiphase controller 140, receives the signal TPHMAX at the corresponding terminals T11, T21, and T22. As previously discussed, the signal TPHMAX indicates the corresponding magnitude of the temperature of power converter phase 112.

[0154] The power converter phase performs the following operations to significantly equalize or better balance the temperature of each power converter phase in the power converter phase.

[0155] More specifically, in processing operation 1120, each power converter phase whose temperature is lower than the temperature of the hottest power converter phase indicated by the signal TPHMAX determines whether to implement current adjustment to increase its corresponding temperature relative to the hottest power converter phase. For example, in processing operation 1120, each power converter phase 111, power converter phase 121, and power converter phase 122 compares the magnitude of its respective detected temperature (TPHASEX) with the magnitude of the hottest temperature indicated by TPHMAX. That is, in one example, each corresponding power converter determines whether its temperature is lower than TPHMAX-TDEAD. On the first pass, it is assumed that each power converter phase 111, 121, and 122 determines (yes) that its temperature is lower than TPHMAX-TDEAD. As previously discussed, the value TDEAD is a temperature margin value. Therefore, based on the determination in operation 1120, processing continues for each of power converter phases 111, 121, and 122 in processing operation 1130.

[0156] Note that in processing operation 1120, power converter phase 112 (e.g., phase 2) determines that its corresponding temperature TPHMAX is not less than TPHMAX–TDEAD, and therefore performs processing operation 1180, in which power converter phase 112 does not adjust its pulse width modulation signal to increase its output current.

[0157] At processing operation 1130, each of the power converter phases 111, 121, and 122 determines whether any duty cycle adjustment associated with the corresponding received pulse width modulation signal PWM1 or PWM2 has reached an adjustment saturation level. If yes, processing continues at processing operation 1180 for those saturated power converter phases. If not, processing continues for those power converter phases at processing operation 1140.

[0158] At processing operation 1140, as previously discussed, each of the power converter phases 111, 121, 122 increases the corresponding duty cycle associated with the corresponding received signals PWM1 and PWM2, such that each of the power converter phases 111, 121, 122 now outputs a higher amount of current to the load 118.

[0159] As indicated in processing operation 1150, the average current supplied to load 118 increases because each of the power converter phases 111, 121, 122 increases its corresponding output current in processing operation 1140. In response to the increased current, in subsequent processing operation 1160, multiphase controller 140 reduces the duty cycle (on-time of the high-side switching circuit of the power converter phase) associated with one or more pulse width modulation signals PWM1 and PWM2, such that the magnitude of output voltage 123 is substantially equal to reference VREF1. In other words, if multiphase controller 140 does not reduce the duty cycle, output voltage 123 will be unregulated.

[0160] In processing operation 1170, each of the power converter phases 111, 121, and 122 further compares its corresponding temperature again with TPHMAX or TPHMAX-TDEAD (i.e., the threshold level). For example, if each of the power converter phases 111, 121, and 122 detects that its corresponding temperature is below TPHMAX-TDEAD, a loopback occurs and execution of flowchart 1100 resumes at processing operation 1130.

[0161] Each of the power converter phases repeats the cycle of this processing operation (1130, 1140, 1150, 1160, 1170) until each power converter detects that its temperature is equal to or greater than TPHMAX-TDEAD. In this case, power converter phase X performs processing operation 1180, where duty cycle adjustments to change the current are no longer performed. In other words, if the current adjustment of each of the power converter phases causes the temperature of the power converter phase to be within or saturated at the margin temperature limit TDEAD of the maximum temperature of the power converter phase (TPHMAX of power converter phase 112), power converter phases 111, 121, and 122 stop increasing their output current to the load.

[0162] The increase in the output current of power converter phases 111, 121, and 122 reduces the current supplied to the load by power converter phase 112 and the temperature of power converter phase 112.

[0163] Figure 12 This is an example block diagram of a computer device used to implement any of the operations discussed herein, based on the examples in this article.

[0164] As shown, the computer system 1200 of this example (e.g., implemented by one or more resources such as controller 140, current balancing function DTB, etc.) includes interconnect 1211, which is coupled to: computer-readable storage medium 1212, such as a non-transitory type medium (or hardware storage medium) capable of storing and retrieving digital information; processor 1213 (e.g., computer processor hardware such as one or more processor devices); I / O interface 1214 (e.g., for outputting control signals to power converters, monitoring current, etc.); and communication interface 1217.

[0165] I / O interface 1214 provides connection to any suitable circuitry, such as a power converter.

[0166] Computer-readable storage medium 1212 can be any hardware storage resource or device, such as memory, optical storage, hard disk drive, floppy disk, etc. In one example, computer-readable storage medium 1212 stores instructions and / or data used by controller application 140-1 (e.g., implemented by any of controller 140, DTB, etc., for supporting leading edge and / or trailing edge signal adjustment) to perform any of the operations described herein.

[0167] Furthermore, in this example, the communication interface 1217 enables the computer system 1200 and the processor 1213 to communicate via resources such as network 190 to retrieve information from remote sources and communicate with other computers.

[0168] As shown, computer-readable storage medium 1212 is encoded with a controller application 140-1 (e.g., software, firmware, etc.) executed by processor 1213. Controller application 140-1 can be configured to include instructions for implementing any of the operations discussed herein.

[0169] During one example operation, processor 1213 accesses computer-readable storage medium 1212 via interconnect 1211 in order to initiate, run, execute, interpret, or otherwise execute instructions in controller application 140-1 stored on computer-readable storage medium 1212.

[0170] The execution of controller application 140-1 produces processing functions, such as controller process 140-2 in processor 1213. In other words, controller process 140-B associated with processor 1213 represents the execution of one or more aspects of controller application 140-A within or on processor 1213 in computer system 1200.

[0171] Depending on the specific example, note that computer system 1200 can be a microcontroller device, logic, hardware processor, mixed analog / digital circuit, etc., configured to control power and perform any of the operations described herein.

[0172] Now will be via Figure 13 The flowchart below illustrates the functionality supported by different resources. Note that the steps in the flowchart can be performed in any suitable order.

[0173] Figure 13 This is an example diagram illustrating the flowchart and implementation of the corresponding method discussed in this article.

[0174] In processing operation 1310, the first power converter receives a first temperature value indicating the temperature of the first power converter (e.g., power converter phase 111 or power converter phase 101). The first power converter supplies a first current to the load.

[0175] In processing operation 1320, the first power converter receives a second temperature value indicating the temperature of the second power converter (e.g., the hottest power converter phase) of the second power converter (e.g., power converter phase 112 or power converter phase 102). The second power converter supplies a second current to the load.

[0176] In processing operation 1330, the first power converter adjusts the magnitude of the first current based on a comparison between a first temperature value and a second temperature value.

[0177] Again, it should be noted that the techniques described in this article are well-suited for circuit applications, such as those that rely at least in part on temperature to achieve power conversion and temperature balance adjustment of power converters. However, it should be understood that the examples in this article are not limited to such applications, and the techniques discussed herein are also well-suited for other applications.

[0178] Based on the description set forth herein, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods, apparatuses, systems, etc., known to those of ordinary skill in the art have not been described in detail so as not to obscure the claimed subject matter. Some portions of the detailed description have been presented as algorithms or symbolic representations of operations performed on data bits or binary digital signals stored in the memory of a computing system (e.g., computer memory). These algorithmic descriptions or representations are examples of techniques used by those of ordinary skill in the field of data processing to communicate the substance of their work to others of ordinary skill in the art. The algorithms described herein are generally considered to be a self-consistent sequence of operations or similar processes that produce the desired result. In this context, the operation or process involves the physical manipulation of a physical quantity. Typically, although not required, such a quantity may take the form of an electrical or magnetic signal that can be stored, transmitted, combined, compared, or otherwise manipulated. Sometimes, primarily for common reasons, it is convenient to refer to such signals as bits, data, values, elements, symbols, characters, items, numbers, digits, etc. However, it should be understood that all these terms and similar terms are associated with appropriate physical quantities and are merely convenient notations. Unless otherwise expressly stated, it will be apparent from the following discussion that, throughout this specification, the use of terms such as “processing,” “computing,” “operation,” “determining,” etc., refers to the actions or processing of a computing platform (e.g., a computer or similar electronic computing device) that manipulates or transforms data of physical electronic or magnetic quantities within a memory, register, or other information storage, transmission, or display device represented as the computing platform.

[0179] While the invention has been specifically shown and described with reference to preferred embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to the invention without departing from the spirit and scope of the invention as defined by the appended claims. Such variations are intended to be covered by the scope of this application. Therefore, the foregoing description of the embodiments of this application is not intended to be limiting. Rather, any limitation on the invention is set forth in the appended claims.

Claims

1. An apparatus comprising a first power converter, wherein, the first power converter is operable to: receive a first temperature value indicative of a temperature of the first power converter, the first power converter supplying a first current to a load; receive a second temperature value indicative of a temperature of a second power converter, the second power converter supplying a second current to the load; and adjust a magnitude of the first current based on a comparison of the first temperature value and the second temperature value.

2. The apparatus of claim 1, wherein, the comparison of the first temperature value and the second temperature value indicates that the temperature of the first power converter is lower than the temperature of the second power converter.

3. The apparatus of claim 2, wherein, the first power converter is further operable to: receive a first pulse width modulation control signal, the first pulse width modulation control signal being supplied to both the first power converter and the second power converter to control the first current and the second current; and in response to the first temperature value being less than the second temperature value, adjust a timing of an edge of the received first pulse width modulation control signal to produce a second pulse width modulation control signal, the second pulse width modulation control signal being operable to control a magnitude of the first current.

4. The apparatus of claim 3, wherein, the edge is a trailing edge of the received first pulse width modulation control signal.

5. The apparatus of claim 3, wherein, in response to the first power converter adjusting the magnitude of the first current, a duty cycle of the first pulse width modulation control signal received by the first power converter is adjusted by a controller.

6. The apparatus of claim 1, wherein, the first power converter is operable to, in response to detecting that the first temperature value is within a threshold level of the second temperature value, cease increasing the magnitude of the first current.

7. The apparatus of claim 1, wherein, the first power converter is operable to adjust the magnitude of the first current via selection of a delay signal from a tapped delay line to control a respective timing of an edge of a first control signal used to control the magnitude of the first current.

8. The apparatus of claim 1, wherein, the first power converter is operable to adjust the magnitude of the first current via implementation of a current-starved inverter circuit, the current-starved inverter circuit being operable to adjust a timing of a trailing edge of a first control signal to produce a second control signal, the second control signal being operable to control the magnitude of the first current.

9. The apparatus of claim 1, wherein, the first power converter is operable to i) receive a first control signal used to control the magnitude of the first current, and ii) convert the first control signal to a second control signal via a continuous delay element circuit, the continuous delay element circuit being operable to control a timing of a trailing edge of the second control signal.

10. An apparatus comprising a first power converter, wherein, the first power converter is operable to: receive a control signal supplied to each of a plurality of power converters comprising the first power converter and a second power converter; receive temperature information associated with the first power converter and the second power converter; and adjust the control signal based on the received temperature information, the adjusted control signal being operable to control a first current output from the first power converter to a load.

11. The apparatus of claim 10, wherein, The temperature information includes a first temperature value and a second temperature value; wherein the first temperature value is indicative of a temperature of the first power converter; and wherein the second temperature value is indicative of a temperature of the second power converter.

12. The apparatus of claim 11, wherein, The control signal is a pulse width modulation control signal that is supplied to both the first power converter and the second power converter.

13. The apparatus of claim 12, wherein, Adjusting the control signal based on the temperature information includes: in response to a case where the second temperature value is greater than the first temperature value, adjusting a duty cycle of the pulse width modulation control signal implemented by the first power converter to produce the first current.

14. The apparatus of claim 13, wherein, The adjusted duty cycle of the pulse width modulation control signal implemented by the first power converter is operable to reduce: i) a magnitude of a second current supplied to the load by the second power converter, and ii) a magnitude of a temperature of the second power converter.

15. A control method comprising: receiving a first temperature value indicative of a temperature of a first power converter, the first power converter supplying a first current to a load; receiving a second temperature value indicative of a temperature of a second power converter, the second power converter supplying a second current to the load; and adjusting a magnitude of the first current based on a comparison of the first temperature value to the second temperature value.

16. The control method according to claim 15, wherein The comparison of the first temperature value to the second temperature value indicates that a temperature of the first power converter is lower than a temperature of the second power converter.

17. The control method according to claim 16, wherein Adjusting the magnitude of the first current includes, in response to detecting that the first temperature value is less than the second temperature value based on the comparison, increasing the magnitude of the first current.

18. The control method according to claim 17, wherein The increase in the magnitude of the first current causes a reduction in a magnitude of the second current supplied to the load by the second power converter; wherein the increase in the magnitude of the first current causes an increase in a temperature of the first power converter; and wherein the reduction in the magnitude of the second current supplied to the load by the second power converter causes a decrease in a temperature of the second power converter.

19. The control method according to claim 15, wherein The adjusted magnitude of the first current causes an increase in a difference between the magnitude of the first current and a magnitude of the second current; and wherein adjusting the magnitude of the first current based on the comparison includes preventing the difference between the magnitude of the first current and the magnitude of the second current from being greater than a threshold level.

20. The control method according to claim 15, wherein Adjusting the magnitude of the first current based on the comparison includes: receiving a first pulse width modulation control signal, the first pulse width modulation control signal being supplied to both the first power converter and the second power converter to control the first current and the second current; and in response to the first temperature value being less than the second temperature value, adjusting a timing of edges of the received first pulse width modulation control signal to produce a second pulse width modulation control signal, the second pulse width modulation control signal being operable to control the magnitude of the first current.

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