Multiphase clock generation and correction method and circuit for interleaved analog-to-digital converter

Abstract

The invention discloses a multi-phase clock generation and correction method and circuit of an interleaved analog-to-digital converter. The method comprises the following steps: generating a first pulse width control signal and a second pulse width control signal related to an actual phase difference between a reference clock signal and a sub-clock signal to be corrected; calculating a first net integral result according to the first group of digital codes, and calculating a second net integral result according to the second group of digital codes; determining a phase error of the to-be-corrected sub-clock signal according to the difference between the first net integration result and the second net integration result, and outputting a delay control signal corresponding to the phase error; and in response to the delay control signal, adjusting the transmission delay of the to-be-corrected sub-clock signal so as to correct the phase of the to-be-corrected sub-clock signal. According to the invention, on the basis of reducing power consumption and reducing cost, the phase precision among multi-phase sampling clocks can be improved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method and circuit for generating and correcting multiphase clocks in an interleaved analog-to-digital converter. Background Technology

[0002] Interleaved analog-to-digital converters (ADCs) increase the sampling rate several times by alternating sampling through multiple sub-ADC channels, and are a core component of modern high-speed communication and data acquisition systems. Their performance is highly dependent on the uniformity and accuracy of the phase between the multiple sampling clocks (i.e., multi-phase clocks) driving each sub-channel.

[0003] To generate the required multiphase clock, existing technologies mainly employ the following approaches: First, a high-frequency master clock is generated via an externally provided or internally provided phase-locked loop (PLL), which is then divided to generate the multiphase clock. Second, a phase interpolator is directly used to interpolate the input clock phase to generate the multiphase signal. For example, a typical approach utilizes a digital PLL combined with a multiphase voltage-controlled oscillator or a delay-locked loop structure to generate and lock each phase clock.

[0004] However, using a high-frequency PLL or an external high-frequency clock source will significantly increase the overall power consumption and cost of the system; while the phase interpolation-based solution is prone to introducing additional phase noise, and the phase accuracy it generates is greatly affected by circuit mismatch and noise, often making it difficult to achieve the phase uniformity required by high-precision ADCs. Summary of the Invention

[0005] This invention provides a method and circuit for generating and correcting multiphase clocks in an interleaved analog-to-digital converter, which can improve the phase accuracy between multiphase sampling clocks while reducing power consumption and cost.

[0006] In a first aspect, embodiments of the present invention provide a method for generating and correcting a multiphase clock for an interleaved analog-to-digital converter (ADC), comprising: providing a single fixed-frequency input clock signal; transmitting the input clock signal through signal transmission paths of different physical lengths to generate multiple sub-clock signals with different phases; using the multiple sub-clock signals to drive multiple sub-ADC channels of the interleaved ADC; performing closed-loop phase calibration on at least one sub-clock signal to be corrected, using one of the multiple sub-clock signals as a reference clock signal, the closed-loop phase calibration comprising: generating a first pulse width control signal and a second pulse width control signal related to the actual phase difference between the reference clock signal and the sub-clock signal to be corrected; generating a chopper signal to control a chopper switch to periodically output differential signals that are opposite in phase. The system generates a voltage signal; during the first calibration period, in response to the first pulse width control signal, the differential voltage signal is integrated by an integrator, and the integration result is converted from analog to digital to obtain a first set of digital codes; during the second calibration period, in response to the second pulse width control signal, the differential voltage signal is integrated by an integrator, and the integration result is converted from analog to digital to obtain a second set of digital codes; a first net integral result is calculated based on the first set of digital codes, and a second net integral result is calculated based on the second set of digital codes; the phase error of the sub-clock signal to be corrected is determined based on the difference between the first net integral result and the second net integral result, and a delay control signal corresponding to the phase error is output; in response to the delay control signal, the transmission delay of the sub-clock signal to be corrected is adjusted to correct the phase of the sub-clock signal to be corrected.

[0007] Secondly, embodiments of the present invention provide a multiphase clock generation and correction circuit for an interleaved analog-to-digital converter, comprising: a clock distribution module for receiving a single fixed-frequency input clock signal and outputting multiple sub-clock signals with different phases via multiple transmission paths of different physical lengths; a phase calibration module for performing phase calibration on at least one sub-clock signal to be corrected, the phase calibration module comprising: a clock logic control unit for receiving a reference clock signal and the sub-clock signal to be corrected, and outputting a first pulse width control signal and a second pulse width control signal; a chopper switch for periodically outputting differential voltage signals that are inversely related to each other under the control of the chopper signal; an integrator; and a connection switch connected between the output of the chopper switch unit and the differential input terminal of the integrator, for responding to a first calibration period during a second calibration period. A pulse width control signal, and responding to a second pulse width control signal during a second calibration period, selectively connects the differential voltage signal to the integrator; an analog-to-digital converter, connected to the output of the integrator, is used to convert the integrated voltage into digital code; a digital processing unit, connected to the output of the analog-to-digital converter, is used to calculate a first net integral result based on a first set of digital codes obtained during the first calibration period, and calculate a second net integral result based on a second set of digital codes obtained during the second calibration period; the phase error of the sub-clock signal to be corrected is determined according to the difference between the first net integral result and the second net integral result, and a delay control signal corresponding to the phase error is output; an adjustable delay unit, set on the transmission path of the sub-clock signal to be corrected, is used to adjust the transmission delay of the sub-clock signal to be corrected in response to the delay control signal.

[0008] The multiphase clock generation and correction method for interleaved analog-to-digital converters provided in this invention generates multiphase clock signals by directly designing traces of different lengths on the package substrate or PCB, eliminating the need for on-chip high-frequency phase-locked loops or off-chip high-frequency clock sources required in traditional solutions. This avoids the huge power consumption and additional chip area caused by active circuits such as PLLs, and also reduces the dependence on external high-speed clock components, achieving a low-cost, low-power clock generation scheme. The phase difference information is encoded as the width difference of two pulse width control signals, and the differential voltage signal is integrated and quantized by an integrator controlled by chopping technology. Subsequently, by performing differential summation operations on the positive and negative polarity digital codes and the negative polarity digital code, the inherent offset voltage and low-frequency noise of analog circuits such as integrators and analog-to-digital converters can be accurately canceled, thereby extracting a pure digital quantity that is only proportional to the phase error. The entire calibration process constitutes a complete digital feedback loop. The system can detect the phase error in real time and automatically generate delay control signals to adjust the adjustable delay units on the clock path, dynamically correcting the clock phase. This process can continue while the ADC is operating normally (background calibration), without interrupting signal conversion or depending on a specific input signal. It can track and compensate for phase changes caused by process deviations, temperature drift, and device aging in real time, thereby maintaining the phase uniformity of the multiphase clock in a long-term and stable manner.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of an interleaved analog-to-digital converter provided in an embodiment of the present invention;

[0012] Figure 2 This is a flowchart of a multiphase clock generation and correction method for an interleaved analog-to-digital converter provided in an embodiment of the present invention;

[0013] Figure 3 This is a waveform diagram of a first pulse width control signal and a second pulse width control signal provided in an embodiment of the present invention;

[0014] Figure 4This is a flowchart of another method for generating and correcting a multiphase clock for an interleaved analog-to-digital converter provided in this embodiment of the invention;

[0015] Figure 5 This is a schematic diagram of the structure of a chopper switch provided in an embodiment of the present invention;

[0016] Figure 6 This is a flowchart of another method for generating and correcting a multiphase clock for an interleaved analog-to-digital converter provided in this embodiment of the invention;

[0017] Figure 7 This is a schematic diagram of the structure of a multiphase clock generation and correction circuit for an interleaved analog-to-digital converter provided in an embodiment of the present invention;

[0018] Figure 8 This is a timing diagram of the control signals of various control switches provided in an embodiment of the present invention;

[0019] Figure 9 This is a schematic diagram of an adjustable delay unit provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0022] To address the problems in the prior art, this application provides a method and circuit for generating and correcting a multiphase clock for an interleaved analog-to-digital converter. The following section first introduces an interleaved analog-to-digital converter that can utilize the method and circuit for generating and correcting a multiphase clock provided in this application.

[0023] Figure 1 This is a schematic diagram of the structure of an interleaved analog-to-digital converter provided in an embodiment of the present invention, as shown below. Figure 1As shown, the interleaved analog-to-digital converter includes N sub-ADC channels 11, and the input terminals of each sub-ADC channel 11 are connected in parallel to a common node A1. Here, N is an integer greater than or equal to 3.

[0024] Wherein, ADC0 represents the first sub-ADC channel, ADC1 represents the second sub-ADC channel, and ADCN-1 represents the Nth sub-ADC channel.

[0025] Figure 2 This is a flowchart illustrating a multiphase clock generation and correction method for an interleaved analog-to-digital converter provided in an embodiment of the present invention. Figure 2 As shown, the multiphase clock generation and correction method includes:

[0026] S101 provides a single fixed-frequency input clock signal.

[0027] Specifically, the input clock refers to the periodic electrical signal introduced from a clock source outside the chip or inside the system.

[0028] In one embodiment, if the interleaved ADC is designed with N channels interleaved and the target total sampling rate is fs, then the operating frequency of each sub-ADC channel is fs / N. In this case, the operating frequency fin of the single fixed-frequency input clock signal can be selected to be equal to fs / N.

[0029] S102. The input clock signal is transmitted through signal transmission paths with different physical lengths to generate multiple sub-clock signals with different phases.

[0030] Specifically, signal transmission paths with different physical lengths refer to conductive traces (such as microstrip lines and striplines) of varying lengths that are specially designed and manufactured on the chip's packaging substrate or printed circuit board (PCB). Their physical length refers to the actual geometric length of the signal line from the branch's starting point to its respective endpoint. Since the propagation speed of electromagnetic waves in a medium is constant, the difference in length directly and linearly translates into a difference in signal transmission time.

[0031] Sub-clock signals with different phases refer to the clock signals that are ultimately delivered to the connection switches of each sub-ADC channel. They have the same frequency as the original input clock signal, but their rising / falling edges are offset from each other on the time axis. This offset (i.e., delay difference) is manifested as the phase difference. For an N-channel interleaved ADC, in practice, the phase difference between adjacent sub-clock signals should be equal to the input clock cycle (…). 1 / N of ).

[0032] In one embodiment, during the chip packaging or system PCB design phase, the theoretically required time delay difference between adjacent channels is calculated based on the required number of channels N and the input clock frequency fin. .

[0033] Based on the speed of signal propagation in the medium (such as FR4 PCB material or packaging substrate medium) (approximately the speed of light in a vacuum) (Relative permittivity of the medium), converting the time delay difference into a length difference. .

[0034] During layout and routing, design N signal traces branching from the common clock input node and precisely control their lengths. For example, use the shortest path... For reference, the length of the second path is designed as follows: Article 3 is And so on, the Nth one is... These paths can be designed as serpentine traces to achieve precise length control, and impedance matching is required to reduce signal reflections.

[0035] A single, fixed-frequency input clock signal is simultaneously fed into N transmission paths of varying physical lengths. Due to the different transmission delays of each path, the arrival times of the input clock signal's edges at the ends of each path also differ. This arrival time difference manifests as the phase difference between the output clock signals. Therefore, N sub-clock signals (CLK_0, CLK_1, ..., CLK_{N-1}) with the same frequency but sequentially lagging (or leading) phases are directly obtained at the ends of the paths. These multiple sub-clock signals are used to drive multiple sub-ADC channels of the interleaved analog-to-digital converter. This method utilizes the passive physical characteristics of transmission lines, eliminating the need for any active circuits such as voltage-controlled oscillators, phase interpolators, or multiphase filters to generate phase differences, thereby eliminating the power consumption, phase noise, and area overhead associated with these circuits.

[0036] Using one of multiple sub-clock signals as a reference clock signal, closed-loop phase calibration is performed on at least one sub-clock signal to be corrected. The closed-loop phase calibration includes:

[0037] S103. Generate a first pulse width control signal and a second pulse width control signal that are related to the actual phase difference between the reference clock signal and the sub-clock signal to be corrected.

[0038] Specifically, in this calibration loop, one of the multiple sub-clock signals (e.g., the clock CLK_0 of the first channel) is selected as the reference clock signal.

[0039] The sub-clock signal to be corrected refers to the sub-clock signal that needs phase calibration (e.g., the clock CLK_i of the i-th channel, where i is an integer greater than 0 and less than or equal to N), and its phase relative to the reference clock signal may have an undesigned deviation.

[0040] Actual phase difference refers to the actual time offset between the sub-clock signal to be corrected and the reference clock signal due to factors such as manufacturing deviations and temperature changes. The deviation between the actual phase difference and the theoretical phase difference is the phase error that needs to be calibrated.

[0041] Figure 3 This is a waveform diagram of a first pulse width control signal and a second pulse width control signal provided in an embodiment of the present invention. Figure 3 As shown, the reference clock signal CLK_ref is divided by two to obtain a clock with a duty cycle of 50% and a period of... The first pulse width control signal is PWM1. The high-level interval of this divided-by-two signal serves as the effective pulse of the first pulse width control signal PWM1. Therefore, the effective pulse width T1 of the first pulse width control signal PWM1 is equal to the period of the reference clock signal. .

[0042] Continue to refer to Figure 3 A pulse is triggered by the rising edge of the sub-clock signal CLK_target to be corrected, and terminated by the rising edge of the reference clock signal CLK_ref that immediately follows. The effective pulse width of the second pulse width control signal PWM2 generated in this way reflects the actual time interval between the rising edge of the sub-clock signal CLK_target to be corrected and the rising edge of the next reference clock signal CLK_ref.

[0043] In an N-channel interleaved system, if CLK_0 is used as the reference clock, the ideal phase difference design value of the i-th channel clock CLK_i relative to CLK_0 is... In an ideal situation with no phase error, the theoretical pulse width T2_ideal of the second pulse width control signal should be: - .

[0044] However, due to factors such as manufacturing deviations and temperature drift, the actual generated CLK_i will introduce phase errors. This makes its actual phase difference Accordingly, the actual measured pulse width T2_actual of the second pulse width control signal will become .

[0045] Compare this equation with T1= Combining these, we can obtain T1-T2_actual= + .

[0046] because Since these are known system design constants, by measuring T1 and T2_actual and calculating their difference, we can obtain the sum including the ideal phase difference and the phase error to be measured.

[0047] To physically achieve and accurately complete the indirect measurement and digitization of the time quantities T1 and T2_actual, since directly measuring the tiny time difference (T1-T2_actual) on the order of picoseconds or even femtoseconds is extremely difficult in circuitry and easily affected by noise, this invention transforms the control of the time width (T1 or T2) into an integration time window over a known reference voltage. Then, it utilizes the charge accumulation characteristic of the integrator to linearly convert the time length into an analog voltage amplitude, and finally quantizes the voltage into a digital code using an analog-to-digital converter (ADC).

[0048] S104 generates a chopper signal to control the chopper switch to periodically output differential voltage signals that are opposite to each other.

[0049] Specifically, a chopper signal is a periodic square wave signal with an operating frequency much lower than that of the input clock signal. For example, its frequency may be a fraction of the operating frequency of the input clock signal or a hundredth of the operating frequency. The chopper signal can be generated by a separate low-frequency oscillator, a digital counter that deeply divides the system master clock, or a timer or pulse generator configured by a microcontroller.

[0050] A chopper switch is an analog switch array controlled by a chopper signal. Its function is to connect a fixed reference voltage source to the input of subsequent circuits in different polarity combinations, depending on the polarity of the chopper signal.

[0051] During the high-level range of the chopper signal, the chopper switch outputs a set of differential reference voltages with the first polarity; during the low-level range of the chopper signal, the chopper switch outputs the same reference voltages with the opposite polarity. These two differential voltage signals have equal amplitudes but opposite polarities.

[0052] S105. During the first calibration period, in response to the first pulse width control signal, the differential voltage signal is connected to the integrator for integration, and the integration result is converted from analog to digital to obtain the first set of digital codes.

[0053] Specifically, the first calibration period is a preset, continuous time interval used to complete the first reference measurement. This period includes M chopping cycles of the chopping signal, where M is an integer greater than or equal to 1. During this period, the system uses the first pulse width control signal PWM1 to control the integration window.

[0054] The first set of digital codes refers to the collection of all output digital codes obtained through the above process during the first calibration period. Due to chopper control, this set of codes includes both positive polarity digital codes obtained by integrating the first differential voltage signal and negative polarity digital codes obtained by integrating the second differential voltage signal.

[0055] S106. During the second calibration period, in response to the second pulse width control signal, the differential voltage signal is connected to the integrator for integration, and the integration result is converted from analog to digital to obtain the second set of digital codes.

[0056] Specifically, the second calibration period is a continuous time interval of equal length to the first calibration period, also containing M chopping cycles. During this period, the system logic switches to using the second pulse width control signal PWM2 to control the integration window.

[0057] The second set of digital codes refers to the set of all output digital codes obtained through the above process during the second calibration period. Similar to the first set of digital codes, it also includes two types of digital codes obtained by integrating the first differential voltage signal and the second differential voltage signal.

[0058] S107. Calculate the first net integral result based on the first set of digital codes, and calculate the second net integral result based on the second set of digital codes.

[0059] The first net integral result refers to a scalar value calculated using a specific digital differential algorithm based on the original digital code obtained during the first calibration period and obtained by integrating the first differential voltage signal and the second differential voltage signal under multiple T1 time windows. The first net integral result is proportional to T1.

[0060] Similarly, the second net integral result is a scalar value calculated based on the original digital code obtained within the second calibration period and across multiple T2 time windows. The second net integral result is proportional to T2_actual.

[0061] In some embodiments, the sum of all positive polarity digital codes in the first group of digital codes is subtracted from the sum of all negative polarity digital codes to obtain a first net integral result; the sum of all positive polarity digital codes in the second group of digital codes is subtracted from the sum of all negative polarity digital codes to obtain a second net integral result.

[0062] For example, assuming the first set of numeric codes is {P1,N1,P2,N2,P3,N3}, then the first net integral result Net1 = (P1 + P2 + P3) - (N1 + N2 + N3). Assuming the second set of numeric codes is {A1,B1,A2,B2,A3,B3}, then the second net integral result Net2 = (A1 + A2 + A3) - (B1 + B2 + B3).

[0063] Assume that the digital quantity corresponding to the overall offset voltage of the integrator and ADC path is Vos, and the conversion coefficient corresponding to the differential voltage signal is G.

[0064] For the first set of numeric codes:

[0065] Any positive polarity digital code P obtained during the positive polarity phase can be expressed as: P≈G V1 T1+Vos.

[0066] Any negative polarity digital code N obtained in the negative polarity phase can be expressed as: N≈G (-V1) T1+Vos.

[0067] Where V1 is the difference between the positive reference voltage and the negative reference voltage.

[0068] The difference between individual paired data is: PN≈2 G V1 T1. In this operation, the misalignment term Vos is precisely canceled out.

[0069] The differences between all paired data are summed to obtain the first net integral result Net1:

[0070] Net1=Σ(P)-Σ(N)≈M (2 G V1 T1)=K T1.

[0071] Where M is the number of pairs (i.e., the number of chopping cycles), K=2M G V1 is a constant.

[0072] The first net integral result is a digital quantity that is proportional to the effective pulse width T1 of the first pulse width signal and completely eliminates the offset error.

[0073] Similarly, for the second set of numerical codes:

[0074] Any positive polarity digital code A obtained during the positive polarity phase can be expressed as: A≈G (+V1) T2+Vos.

[0075] Correspondingly, the negative polarity digital code B obtained in the negative polarity phase can be expressed as: B≈ G(-V1) T² + Vos. Therefore, AB ≈ 2G. V1 In T2, the imbalance term Vos is also canceled out.

[0076] The differences between all M pairs of paired data are summed to obtain the second net integral result Net2:

[0077] Net2=Σ(A)-Σ(B)≈M (2G V1T 2)=K T2.

[0078] Therefore, the second net integral result Net2 is a digital quantity that is proportional to the effective pulse width T2 of the second pulse width control signal and completely eliminates the offset error.

[0079] This embodiment transforms the problem of measuring the time difference (T1-T2_actual) into a comparison problem of two sets of digital quantities (Net1 and Net2) obtained under strictly controlled conditions, thereby providing a basis for the final calculation of the phase error. It provides reliable, interference-resistant, and easily digitally processed input data.

[0080] S108. Determine the phase error of the sub-clock signal to be corrected based on the difference between the first net integral result and the second net integral result, and output the delay control signal corresponding to the phase error.

[0081] Specifically, the phase error refers to the deviation of the actual phase of the sub-clock signal CLK_target to be corrected from the theoretically designed phase difference between it and the reference clock signal CLK_ref, denoted as... This is the amount that needs to be eliminated eventually.

[0082] The difference refers to the numerical relationship between the first net integral result Net1 and the second net integral result Net2, including but not limited to the difference (Net1-Net2), the ratio (Net2 / Net1), or the deviation from a theoretically calculated value. This difference directly and uniquely maps the difference between T1 and T2, and thus maps the phase error. .

[0083] The delay control signal is a digital code (such as a multi-bit binary number) output by the digital processing unit. The value of the delay control signal determines the delay amount of the adjustable delay unit. Increasing the value of this signal generally increases the delay, while decreasing it decreases the delay, thereby enabling fine-tuning of the phase of the sub-clock signal CLK_target to be corrected.

[0084] From the aforementioned derivation, it is known that: Net1 = K T1, where T1 is a known reference clock period. Net2=K T2, where T2 is the actual measured pulse width.

[0085] For an N-channel interleaved system, if the sub-clock signal to be corrected, CLK_target, is the clock of the i-th channel, its ideal phase difference with respect to the reference clock signal, CLK_ref, is: .

[0086] Under ideal, error-free conditions, the theoretical value of T2 should be T2_ideal = T1 - At this point, the theoretical value of Net2 is Net2_ideal = K. (T1- ).

[0087] The digital processing unit first calculates the deviation between the measured value of Net2 and its theoretical value Net2_ideal: ΔNet = Net2 - Net2_ideal.

[0088] Since Net2=K T2 and the actual value of T2 is T2_actual = T1- - Substituting the values, we get:

[0089] ΔNet=K [(T1- - )-(T1- )]=-K .

[0090] Therefore, the size of ΔNet is proportional to the phase error. The absolute value of the value, whose sign (positive / negative) indicates the phase error. The direction (i.e., whether CLK_target is ahead or behind).

[0091] The digital processing unit updates the digital code of the delay control signal (denoted as D_ctrl) according to the value of ΔNet and a preset algorithm. For example, if ΔNet > +δ (δ is a positive number close to zero, representing the error dead zone), it is determined that the phase is lagging and the delay needs to be reduced; therefore, D_ctrl is decreased by one step (e.g., D_ctrl = D_ctrl - 1). If ΔNet < -δ, it is determined that the phase is leading and the delay needs to be increased; therefore, D_ctrl is increased by one step (e.g., D_ctrl = D_ctrl + 1). If -δ ≤ ΔNet ≤ +δ, it is determined that the phase error is within the set error range, and D_ctrl remains unchanged.

[0092] S109. Respond to the delay control signal and adjust the transmission delay of the sub-clock signal to be corrected in order to correct the phase of the sub-clock signal to be corrected.

[0093] Specifically, this step can be performed by an adjustable delay unit integrated into the sub-clock signal path to be corrected. The adjustable delay unit can be a digitally controlled variable delay line. For example, it includes a main signal path with one or more parallel capacitor networks controlled by switches. Each capacitor branch consists of a capacitor element and a switching element (such as a MOS transmission gate) connected in series. The on / off states of all switches are uniformly controlled by a decoder, whose input is the delay control signal.

[0094] When an increase in delay is required (causing clock phase lag), the delay control signal connects more capacitor branches through the decoder, thereby increasing the total load capacitance and increasing the transmission delay.

[0095] When it is necessary to reduce delay (by making the clock phase lead), the delay control signal disconnects part of the capacitor branch, reduces the total load capacitance, and thus shortens the transmission delay.

[0096] Each time the adjustable delay unit updates its configuration based on a new delay control signal, the phase of the sub-clock signal to be corrected is adjusted. Subsequently, the system restarts the phase measurement and calculation process (i.e., the aforementioned calibration step), generating a new delay control signal. This cycle repeats, forming a negative feedback loop, until the measured phase error is less than a preset threshold range. At this point, the delay control signal will remain stable, indicating that the phase calibration of this channel is complete.

[0097] The multiphase clock generation and correction method for interleaved analog-to-digital converters provided in this invention generates multiphase clock signals by directly designing traces of different lengths on the package substrate or PCB, eliminating the need for on-chip high-frequency phase-locked loops or off-chip high-frequency clock sources required in traditional solutions. This avoids the huge power consumption and additional chip area caused by active circuits such as PLLs, and also reduces the dependence on external high-speed clock components, achieving a low-cost, low-power clock generation scheme. The phase difference information is encoded as the width difference of two pulse width control signals, and the differential voltage signal is integrated and quantized by an integrator controlled by chopping technology. Subsequently, by performing differential summation operations on the positive and negative polarity digital codes and the negative polarity digital code, the inherent offset voltage and low-frequency noise of analog circuits such as integrators and analog-to-digital converters can be accurately canceled, thereby extracting a pure digital quantity that is only proportional to the phase error. The entire calibration process constitutes a complete digital feedback loop. The system can detect the phase error in real time and automatically generate delay control signals to adjust the adjustable delay units on the clock path, dynamically correcting the clock phase. This process can continue while the ADC is operating normally (background calibration), without interrupting signal conversion or depending on a specific input signal. It can track and compensate for phase changes caused by process deviations, temperature drift, and device aging in real time, thereby maintaining the phase uniformity of the multiphase clock in a long-term and stable manner.

[0098] In some embodiments, the first calibration period includes M chopping cycles of the chop signal, and the second calibration period includes M chopping cycles of the chop signal. M is an integer greater than or equal to 1. That is, the number of chopping cycles included in the first calibration period is the same as the number of chopping cycles included in the second calibration period.

[0099] Figure 4 This is a flowchart illustrating another method for generating and correcting a multiphase clock in an interleaved analog-to-digital converter, as provided in an embodiment of the present invention. Figure 4 As shown, the multiphase clock generation and correction method includes:

[0100] S201 provides a single fixed-frequency input clock signal.

[0101] S202. The input clock signal is transmitted through signal transmission paths with different physical lengths to generate multiple sub-clock signals with different phases.

[0102] S203, Generate a first pulse width control signal and a second pulse width control signal that are related to the actual phase difference between the reference clock signal and the sub-clock signal to be corrected.

[0103] S204. When the chopper signal is at the first level, control the chopper switch to output the first differential voltage signal; when the chopper signal is at the second level, control the chopper switch to output the second differential voltage signal.

[0104] Specifically, the first differential voltage signal is equal to the difference between the positive reference voltage and the negative reference voltage, and the second differential voltage signal is equal to the difference between the negative reference voltage and the positive reference voltage. The first and second differential voltage signals have equal amplitudes but opposite polarities.

[0105] The first level and the second level refer to two logic states of the chopper signal, which are inverses of each other. For example, the first level is high (logic '1'), and the second level is low (logic '0'); and vice versa.

[0106] Figure 5 This is a schematic diagram of a chopper switch provided in an embodiment of the present invention. Figure 5 As shown, the first input terminal of the chopper switch is connected to the positive reference voltage Vrefp, the second input terminal is connected to the negative reference voltage Vrefn, the first output terminal is connected to the positive input terminal IP of the integrator, and the second output terminal is connected to the negative input terminal IN of the integrator. Its operating logic is as follows:

[0107] When the chopper signal is at the first level (e.g., high level), the first switch S1 and the fourth switch S4 are closed, and the second switch S2 and the third switch S3 are open. The positive reference voltage Vrefp is connected to the positive input terminal IP of the integrator through the first switch S1. The negative reference voltage Vrefn is connected to the negative input terminal IN of the integrator through the fourth switch S4. At this time, the chopper switch outputs the first differential voltage signal.

[0108] When the chopper signal flips to the second level (e.g., low level), the second switch S2 and the third switch S3 are closed, and the first switch S1 and the fourth switch S4 are open. The positive reference voltage Vrefp is connected to the negative input terminal IN of the integrator through the second switch S2. The negative reference voltage Vrefn is connected to the positive input terminal IP of the integrator through the third switch S3. At this time, the chopper switch outputs the second differential voltage signal.

[0109] S205. During the positive polarity phase of each chopping cycle in the first calibration period, in response to the first pulse width control signal, the first differential voltage signal is connected to the integrator for integration, and the integration result is converted from analog to digital to obtain a positive polarity digital code; during the negative polarity phase of each chopping cycle in the first calibration period, in response to the first pulse width control signal, the second differential voltage signal is connected to the integrator for integration, and the integration result is converted from analog to digital to obtain a negative polarity digital code.

[0110] Specifically, all positive and negative digital codes obtained during the first calibration period constitute the first set of digital codes; and the total number of positive digital codes is equal to the total number of negative digital codes.

[0111] Assume the first calibration period comprises three complete chopping cycles (i.e., M=3). During the positive polarity phase of each chopping cycle, in response to the first pulse width control signal PWM1, the first differential voltage signal is integrated once and converted by the ADC to obtain a positive polarity digital code. During the negative polarity phase of each chopping cycle, in response to the first pulse width control signal PWM1, the second differential voltage signal is integrated once and converted by the ADC to obtain a negative polarity digital code.

[0112] Therefore, after the first calibration period ends, the first set of digital codes obtained will contain the following six specific digital codes: {P1, N1, P2, N2, P3, N3}. Here, P1, P2, and P3 represent the positive polarity digital codes obtained in the first, second, and third chopping cycles, respectively. N1, N2, and N3 represent the negative polarity digital codes obtained in the first, second, and third chopping cycles, respectively. This set of digital codes {P1, N1, P2, N2, P3, N3} constitutes the first set of digital codes.

[0113] S206. During the positive polarity phase of each chopping cycle in the second calibration period, in response to the second pulse width control signal, the first differential voltage signal is connected to the integrator for integration, and the integration result is converted from analog to digital to obtain a positive polarity digital code; during the negative polarity phase of each chopping cycle in the second calibration period, in response to the second pulse width control signal, the second differential voltage signal is connected to the integrator for integration, and the integration result is converted from analog to digital to obtain a negative polarity digital code.

[0114] Specifically, all positive and negative digital codes obtained during the second calibration period constitute the second set of digital codes; and the total number of positive digital codes is equal to the total number of negative digital codes.

[0115] Assume the second calibration period also contains 3 chopping cycles. During the positive polarity phase of each chopping cycle, the first differential voltage signal is integrated once in response to the second pulse width control signal PWM2. During the negative polarity phase of each chopping cycle, the second differential voltage signal is integrated once in response to the second pulse width control signal PWM2, resulting in a negative polarity digital code.

[0116] Therefore, after the second calibration period ends, the second set of digital codes obtained will contain the following six specific digital codes {A1, B1, A2, B2, A3, B3} (using letters A and B as examples to distinguish them from the first set of digital codes). Wherein, A1, A2, and A3 represent the positive polarity digital codes obtained in the first, second, and third chopping cycles, respectively. B1, B2, and B3 represent the negative polarity digital codes obtained in the first, second, and third chopping cycles, respectively.

[0117] S207. Calculate the first net integral result based on the first set of digital codes, and calculate the second net integral result based on the second set of digital codes.

[0118] S208. Determine the phase error of the sub-clock signal to be corrected based on the difference between the first net integral result and the second net integral result, and output the delay control signal corresponding to the phase error.

[0119] Specifically, the difference between the first net integral result and the second net integral result is compared with a preset threshold to determine the phase error of the sub-clock signal to be corrected.

[0120] The preset threshold corresponds to the difference in net integral results between the theoretical phase difference between the sub-clock signal to be corrected and the reference clock signal.

[0121] S209. Respond to the delay control signal and adjust the transmission delay of the sub-clock signal to be corrected in order to correct the phase of the sub-clock signal to be corrected.

[0122] Figure 6 This is a flowchart illustrating another method for generating and correcting a multiphase clock in an interleaved analog-to-digital converter, as provided in an embodiment of the present invention. Figure 6 As shown, the multiphase clock generation and correction method includes:

[0123] S301 provides a single fixed-frequency input clock signal;

[0124] S302. The input clock signal is transmitted through signal transmission paths with different physical lengths to generate multiple sub-clock signals with different phases.

[0125] S303, Generate a first pulse width control signal and a second pulse width control signal that are related to the actual phase difference between the reference clock signal and the sub-clock signal to be corrected;

[0126] S304 generates a chopper signal to control the chopper switch to periodically output differential voltage signals that are opposite to each other.

[0127] S305 generates a reset signal synchronized with the edge of the chopping signal.

[0128] Specifically, the reset signal is used to reset the integrator during the first calibration period and / or the second calibration period.

[0129] The reset signal is a short pulse signal used to force the integrator's output state to a known initial level (typically zero potential or common-mode level). This can be achieved by connecting a switch controlled by this signal in parallel across the integrator's feedback capacitor. When the reset signal is active, the switch closes, the capacitor is short-circuited and discharged, and the integrator output is reset.

[0130] The edge of a chopper signal refers to the moment when the chopper signal changes direction, usually referring to its rising edge or falling edge.

[0131] Synchronization refers to the timing of the reset signal generation being aligned with or maintaining a fixed timing relationship with the edge of the chopping signal.

[0132] The integrator performs continuous-time integration of the differential voltage signal. Without periodic reset, its output voltage may accumulate over multiple cycles of continuous integration, eventually exceeding the amplifier's linear output range (i.e., saturation), leading to measurement failure. The reset signal returns the integrator output voltage to zero after each (or every few) chopping cycles, ensuring it always operates within the linear region. Simultaneously, the digital processing unit following the ADC processes the ADC conversion results according to the timing of the reset signal rst. For Sigma-delta ADCs, this signal is used to reset the digital filter.

[0133] S306. During the first calibration period, in response to the first pulse width control signal, the differential voltage signal is connected to the integrator for integration, and the integration result is converted from analog to digital to obtain the first set of digital codes.

[0134] S307. During the second calibration period, in response to the second pulse width control signal, the differential voltage signal is connected to the integrator for integration, and the integration result is converted from analog to digital to obtain the second set of digital codes.

[0135] S308. Calculate the first net integral result based on the first set of digital codes, and calculate the second net integral result based on the second set of digital codes;

[0136] S309. Determine the phase error of the sub-clock signal to be corrected based on the difference between the first net integral result and the second net integral result, and output the delay control signal corresponding to the phase error.

[0137] S310, responds to the delay control signal, adjusts the transmission delay of the sub-clock signal to be corrected, so as to correct the phase of the sub-clock signal to be corrected.

[0138] Based on the same inventive concept, embodiments of the present invention also provide a multiphase clock generation and correction circuit for an interleaved analog-to-digital converter. Figure 7 This is a schematic diagram of the structure of a multiphase clock generation and correction circuit for an interleaved analog-to-digital converter provided in an embodiment of the present invention. Figure 7 As shown, the multiphase clock generation and correction circuit includes:

[0139] The clock distribution module 10 is used to receive a single fixed-frequency input clock signal and output multiple sub-clock signals with different phases through multiple transmission paths of different physical lengths.

[0140] Phase calibration module 20 is used to perform phase calibration on at least one sub-clock signal to be corrected. The phase calibration module includes:

[0141] The clock logic control unit 201 is used to receive a reference clock signal and a sub-clock signal to be corrected, and to output a first pulse width control signal and a second pulse width control signal.

[0142] The chopper switch 202 is used to periodically output differential voltage signals that are opposite to each other under the control of the chopper signal.

[0143] Integrator 203;

[0144] A connection switch K1 is connected between the output of the chopper switch unit and the differential input terminal of the integrator. It is used to respond to the first pulse width control signal during the first calibration period and to respond to the second pulse width control signal during the second calibration period, thereby selectively connecting the differential voltage signal to the integrator.

[0145] The analog-to-digital converter 204 is connected to the output of the integrator 203 and is used to convert the integrated voltage into digital code.

[0146] The digital processing unit 205 is connected to the output of the analog-to-digital converter and is used to calculate a first net integral result based on a first set of digital codes obtained during a first calibration period, and to calculate a second net integral result based on a second set of digital codes obtained during a second calibration period; to determine the phase error of the sub-clock signal to be corrected based on the difference between the first net integral result and the second net integral result, and to output a delay control signal corresponding to the phase error.

[0147] The adjustable delay unit 206 is set on the transmission path of the sub-clock signal to be corrected, and is used to adjust the transmission delay of the sub-clock signal to be corrected in response to the delay control signal.

[0148] Specifically, Figure 8 This is a timing diagram of the control signals for various control switches provided in an embodiment of the present invention. For example... Figure 8 As shown, the connection switch K1 between the chopper switch 202 and the integrator 203 is controlled by the first pulse width control signal PWM1 or the second pulse width control signal PWM2, and the sampling switch K2 between the integrator 203 and the analog-to-digital converter 204 is controlled by the integral sampling control signal.

[0149] The reset signal and chopper signal are also generated by the clock logic control unit 202. The following is an example illustrating the clock logic control unit.

[0150] The first calibration period consists of M chopping signal cycles (i.e., M chopping cycles). Within each chopping cycle, due to the switching of the chopping signal level, it includes a positive polarity phase and a negative polarity phase. During the first calibration period, the system consistently uses the first pulse width control signal PWM1 as the integration window control signal. Therefore, within each chopping cycle, in response to two valid pulses of the first pulse width control signal PWM1 (occurring during the positive and negative polarity phases respectively), two complete integration-sampling conversion cycles are sequentially triggered, ultimately obtaining a positive polarity digital code and a negative polarity digital code.

[0151] Specifically, the integral sampling control signal between the integrator 203 and the analog-to-digital converter 204 is divided into an integral stage and an ADC sampling and conversion stage within half a chopping cycle.

[0152] Integration Phase: When the first pulse width control signal PWM1 is at an active level (e.g., high level), the connection switch K1 is closed, and the integrator integrates the differential voltage signal corresponding to the current chopped phase. The integration duration is determined by the pulse width T1 of the first pulse width control signal PWM1. At this time, the integration sampling control signal is at an inactive level, causing the sampling switch K2 to open, isolating the integrator 203 from the analog-to-digital converter 204.

[0153] ADC sampling and conversion stage: When the first pulse width control signal PWM1 becomes invalid (e.g., low level), the connection switch K1 is opened, the integrator 203 stops integrating, and its output voltage enters the holding state. At this time, the integration sampling control signal jumps to an active level, controlling the sampling switch K2 to close, and the holding voltage output by the integrator 203 is connected to the analog-to-digital converter 204 for sampling and quantization, thereby obtaining a digital code.

[0154] After a sampling conversion operation is completed and before the next pulse width control signal PWM1 arrives, a reset signal synchronized with the chopping signal edge becomes active, resetting the output voltage of integrator 203 to its initial state, preparing for the next integration-sampling conversion cycle. Throughout the entire second calibration period, the above process remains completely consistent, except that the system switches to using the second pulse width control signal PWM2 as the integration window control signal, thereby performing the integration operation with a pulse width T2.

[0155] Figure 9 This is a schematic diagram of an adjustable delay unit provided in an embodiment of the present invention. Figure 9 As shown, the adjustable delay unit 206 includes a first delay unit U1, a second delay unit U2, and multiple parallel capacitor branches connected between the first delay unit U1 and the second delay unit U2.

[0156] Each capacitor branch includes a capacitor C1 and a switch K3 connected in series;

[0157] The delay control signal is used to control the on / off state of switch K3 in each capacitor branch, so as to adjust the phase of the sub-clock signal to be corrected by changing the total capacitance connected to the transmission path of the sub-clock signal to be corrected.

[0158] Specifically, the delay control signal D_ctrl is a multi-bit digital code used to control the on / off state of the switches in each capacitor branch.

[0159] The total delay of the circuit is mainly determined by the total load capacitance C_total of the capacitor network. The total load capacitance C_total is equal to the sum of the capacitance values ​​of all capacitor branches that are in the conducting state.

[0160] When the value of the delay control signal D_ctrl increases, the decoding circuit will connect more capacitor branches, increasing the total load capacitance C_total. This increases the signal transmission delay, causing the output clock phase to lag.

[0161] Conversely, when the delay control signal D_ctrl decreases, the decoding circuit will disconnect some capacitor branches, reducing the total load capacitance C_total, decreasing the transmission delay, and causing the output clock phase to advance.

[0162] Assume the delay control signal D_ctrl is a 6-bit signal with an adjustable range of 0-63. The initial value is set to the middle value of 31, that is, the original delay control signal D_ctrl_old = 31.

[0163] If the digital processing unit 205 determines that CLK_target is ahead and requires an additional delay, its output new delay control signal D_ctrl_new = original delay control signal D_ctrl_old + 1 = 32. The adjustable delay unit responds to this new value by connecting the capacitor combination corresponding to code value 32 in its decoding circuit, making the total load capacitance C_total slightly larger than before (code value 31). Therefore, the transmission delay of the sub-clock signal CLK_target to be corrected increases by a small step (e.g., 0.1 ps), and its phase is corrected backward (in the lag direction) by a small step.

[0164] If the digital processing unit 205 determines that the sub-clock signal CLK_target to be corrected is lagging and reduces the delay, then its output new delay control signal D_ctrl_new = D_ctrl_old - 1 = 30. The adjustable delay unit responds, switching to the capacitor combination corresponding to code value 30, and the total load capacitance C_total decreases. The transmission delay of the sub-clock signal CLK_target to be corrected is reduced, and its phase is corrected forward (in the leading direction).

[0165] After the phase is corrected, the system will re-execute the above steps to measure the new phase error. If the phase error is still outside the set error range, the delay control signal D_ctrl will continue to be adjusted; if the phase error is within the set error range, the delay control signal D_ctrl will remain unchanged, and the calibration will be complete.

[0166] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for generating and correcting a multiphase clock in an interleaved analog-to-digital converter, characterized in that, The method comprises: providing a single fixed frequency input clock signal; transmitting the input clock signal through signal transmission paths with different physical lengths to generate a plurality of sub-clock signals with different phases, the plurality of sub-clock signals being respectively used to drive a plurality of sub-ADC channels of an interleaved analog-to-digital converter; performing closed-loop phase calibration on at least one to-be-corrected sub-clock signal by taking one of the plurality of sub-clock signals as a reference clock signal, the closed-loop phase calibration comprising: generating first and second pulse width control signals related to an actual phase difference between the reference clock signal and the to-be-corrected sub-clock signal; generating a chopping signal to control a chopping switch to periodically output differential voltage signals that are opposite to each other; in a first calibration period, in response to the first pulse width control signal, connecting the differential voltage signals to an integrator for integration, and performing analog-to-digital conversion on the integration result to obtain a first group of digital codes; in a second calibration period, in response to the second pulse width control signal, connecting the differential voltage signals to the integrator for integration, and performing analog-to-digital conversion on the integration result to obtain a second group of digital codes; calculating a first net integration result according to the first group of digital codes, and calculating a second net integration result according to the second group of digital codes; determining a phase error of the to-be-corrected sub-clock signal according to the difference between the first net integration result and the second net integration result, and outputting a delay control signal corresponding to the phase error; in response to the delay control signal, adjusting the transmission delay of the to-be-corrected sub-clock signal to correct the phase of the to-be-corrected sub-clock signal.

2. The interleaved analog-to-digital converter multiphase clock generation and correction method of claim 1, wherein, The step of controlling the chopping switch to periodically output differential voltage signals that are opposite to each other comprises: when the chopping signal is at a first level, controlling the chopping switch to output a first differential voltage signal equal to the difference between a positive reference voltage and a negative reference voltage; when the chopping signal is at a second level, controlling the chopping switch to output a second differential voltage signal equal to the difference between the negative reference voltage and the positive reference voltage; wherein the second level is opposite to the first level.

3. The interleaved analog-to-digital converter multiphase clock generation and correction method of claim 2, wherein, The first calibration period comprises M chopping periods of the chopping signal; M is an integer greater than or equal to 1. The step of, in the first calibration period, in response to the first pulse width control signal, connecting the differential voltage signals to an integrator for integration, and performing analog-to-digital conversion on the integration result to obtain a first group of digital codes comprises: in a positive polarity phase of each chopping period of the first calibration period, in response to the first pulse width control signal, connecting the first differential voltage signal to the integrator for integration, and performing analog-to-digital conversion on the integration result to obtain a positive polarity digital code; in a negative polarity phase of each chopping period of the first calibration period, in response to the first pulse width control signal, connecting the second differential voltage signal to the integrator for integration, and performing analog-to-digital conversion on the integration result to obtain a negative polarity digital code; All positive polarity digital codes and all negative polarity digital codes obtained in the first calibration period form the first group of digital codes; and the total number of the positive polarity digital codes is equal to the total number of the negative polarity digital codes.

4. The method of polyphase clock generation and correction for interleaved analog-to-digital converters according to claim 2 or 3, characterized in that, The second calibration period comprises M chopping periods of the chopping signal; M is an integer greater than or equal to 1; The step of, in the second calibration period, integrating the differential voltage signal into the integrator in response to the second pulse width control signal and performing analog-digital conversion on the integration result to obtain a second group of digital codes comprises: In a positive polarity phase of each chopping period of the second calibration period, a first differential voltage signal is integrated into the integrator in response to the second pulse width control signal, and analog-digital conversion is performed on the integration result to obtain a positive polarity digital code; In a negative polarity phase of each chopping period of the second calibration period, a second differential voltage signal is integrated into the integrator in response to the second pulse width control signal, and analog-digital conversion is performed on the integration result to obtain a negative polarity digital code; All positive polarity digital codes and all negative polarity digital codes obtained in the second calibration period form the second group of digital codes; and the total number of the positive polarity digital codes is equal to the total number of the negative polarity digital codes.

5. The interleaved analog-to-digital converter multiphase clock generation and correction method of claim 1, wherein, The steps of calculating a first net integration result according to the first group of digital codes and calculating a second net integration result according to the second group of digital codes comprise: The sum of all positive polarity digital codes in the first group of digital codes is subtracted by the sum of all negative polarity digital codes to obtain the first net integration result; The sum of all positive polarity digital codes in the second group of digital codes is subtracted by the sum of all negative polarity digital codes to obtain the second net integration result.

6. The interleaved analog-to-digital converter multiphase clock generation and correction method of claim 1, wherein, The step of determining the phase error of the to-be-corrected sub-clock signal according to the difference between the first net integration result and the second net integration result comprises: The difference between the first net integration result and the second net integration result is compared with a preset threshold to determine the phase error of the to-be-corrected sub-clock signal; The preset threshold corresponds to a net integration result difference value corresponding to a theoretical phase difference between the to-be-corrected sub-clock signal and the reference clock signal.

7. The method of claim 1, wherein the method further comprises: generating a plurality of phase-locked clocks for the interleaved analog-to-digital converter; and modifying the plurality of phase-locked clocks based on the plurality of phase-locked clocks and the plurality of phase-locked clock signals. The number of chopping periods included in the first calibration period is the same as the number of chopping periods included in the second calibration period.

8. The interleaved analog-to-digital converter multiphase clock generation and correction method of claim 1, wherein, In the closed-loop phase calibration process, further comprising generating a reset signal synchronized with the edge of the chopping signal; the reset signal is used to reset the integrator in the first calibration period and / or the second calibration period.

9. A circuit for generating and correcting a multiphase clock for an interleaved analog-to-digital converter, comprising: comprise: a clock distribution module configured to receive an input clock signal of a single fixed frequency and output a plurality of sub-clock signals of different phases via a plurality of transmission paths of different physical lengths; a phase calibration module configured to calibrate at least one to-be-corrected sub-clock signal, the phase calibration module comprising: a clock logic control unit configured to receive a reference clock signal and the to-be-corrected sub-clock signal and output a first pulse width control signal and a second pulse width control signal; A chopper switch is configured to periodically output differential voltage signals in opposite phases under control of a chopping signal; An integrator; A connection switch is connected between an output of the chopper switch unit and a differential input of the integrator, and is configured to selectively connect the differential voltage signals to the integrator in response to the first pulse width control signal during a first calibration period and in response to the second pulse width control signal during a second calibration period; An analog-to-digital converter is connected to an output of the integrator, and is configured to convert the integrated voltage into digital codes; A digital processing unit is connected to an output of the analog-to-digital converter, and is configured to calculate a first net integration result based on a first set of digital codes obtained during the first calibration period, to calculate a second net integration result based on a second set of digital codes obtained during the second calibration period, to determine a phase error of the to-be-corrected sub-clock signal according to a difference between the first net integration result and the second net integration result, and to output a delay control signal corresponding to the phase error; An adjustable delay unit is arranged in a transmission path of the to-be-corrected sub-clock signal, and is configured to adjust a transmission delay of the to-be-corrected sub-clock signal in response to the delay control signal.

10. The interleaved analog-to-digital converter multiphase clock generation and correction circuit of claim 9, wherein, The adjustable delay unit includes a first delay unit, a second delay unit, and a plurality of parallel capacitor branches connected between the first delay unit and the second delay unit; Each capacitor branch includes a capacitor and a switch connected in series; The delay control signal is used to control on-off states of the switches in the capacitor branches, so as to adjust the phase of the to-be-corrected sub-clock signal by changing a total capacitance connected in the transmission path of the to-be-corrected sub-clock signal.

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