Coding method, decoding method and device

Abstract

The invention relates to the technical field of communication, in particular to a coding method and device and a decoding method and device. The method can be applied to the IEEE 802.11 ax standard, the 802.11 be standard, the 802.11 bn standard and the like and other standards of the IEEE 802.11 series, such as the 802.15 standard, the 802.11 bf standard, the IMMW standard or the star flash standard and the like. The method comprises the following steps: a first site obtains information bits, performs LDPC coding on the information bits based on a check matrix, obtains coded bits, and outputs a sequence. And after obtaining the to-be-decoded information, the second station performs LDPC decoding in combination with the check matrix to obtain information bits. The code length corresponding to the check matrix is 7776, the code rate corresponding to the check matrix is 2 / 3, and the expansion factor of the check matrix is 162. The check matrix can be better matched with a longer code length, and the coding and decoding performance is improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, and an apparatus. Background Technology

[0002] The Institute of Electrical and Electronics Engineers (IEEE) 802.11n / ac / ax / be and other wireless local area network (WLAN) transmission standards primarily focus on improving user experience in high-bandwidth scenarios (such as 60 GHz), including increasing average user throughput and energy efficiency of battery-powered devices. High-bandwidth scenarios require high-speed and reliable transmission of data, video, and other services on limited frequency and power resources, thus necessitating highly reliable and efficient channel coding and decoding schemes.

[0003] In the field of channel coding, concatenated codes (such as turbo codes) and low-density parity-check (LDPC) codes are currently the two most mature and widely used channel coding methods, both of which have performance close to the Shannon limit. Compared with concatenated codes, LDPC codes have the following advantages: good error performance without the need for a deep interleaver; better frame error rate performance; significantly reduced error levels; decoding is not grid-based; supports parallel decoding; and has low decoding latency. Therefore, LDPC codes have become the standard channel coding scheme for low-frequency short-range WLAN communication systems such as IEEE 802.11n / ac / ax.

[0004] How to further improve the performance of LDPC codes is an urgent issue to be addressed. Summary of the Invention

[0005] This application provides an encoding method, a decoding method, and an apparatus that can improve the performance of LDPC codes.

[0006] In a first aspect, embodiments of this application provide an encoding method applied to a first site, the first site including a Wi-Fi device, or a chip or functional module disposed in the Wi-Fi device, the method comprising:

[0007] The information bits are LDPC encoded according to the parity check matrix to obtain the encoded bits. The code rate corresponding to the parity check matrix is ​​2 / 3 and the code length is 7776. The encoded bits are then output.

[0008] In this embodiment, the parity check matrix supports a code length of 7776 and a code rate of 2 / 3, enabling the first station to support LDPC encoding with a code length of 7776 and a code rate of 2 / 3. This results in stronger error control performance for the first station and improves the performance of the LDPC code. Simultaneously, using LDPC encoding can also improve the transmission reliability of the wireless transmission system and the data transmission reliability of the Wi-Fi system.

[0009] Secondly, embodiments of this application provide a decoding method, the method being applied to a second site, the second site including a Wi-Fi device, or a chip or functional module disposed within the Wi-Fi device, the method comprising:

[0010] Input the information to be decoded; perform LDPC decoding on the information to be decoded according to the parity check matrix. The code rate corresponding to the parity check matrix is ​​2 / 3 and the code length corresponding to the parity check matrix is ​​7776.

[0011] In this embodiment, the parity-check matrix supports a code length of 7776 and a code rate of 2 / 3, enabling the second station to support LDPC decoding with a code length of 7776 and a code rate of 2 / 3. This results in stronger error control performance for the second station and improves the performance of the LDPC code. Furthermore, using LDPC encoding can also improve the transmission reliability of the wireless transmission system and the data transmission reliability of the Wi-Fi system.

[0012] In one possible implementation, combining the first or second aspect, the expansion factor of the parity check matrix is ​​162.

[0013] The check matrix is ​​a 16-row, 48-column matrix, and by using an expansion factor of 162, the check matrix can be made to match the code length.

[0014] The matrix corresponding to the information bits in the parity check matrix is ​​the first 32 columns of the 48-column matrix, and the matrix corresponding to the parity bits in the parity check matrix is ​​the last 16 columns of the 48-column matrix.

[0015] In conjunction with the first or second aspect, in one possible implementation, the verification matrix includes a submatrix, which is a 2x2 matrix containing two elements greater than or equal to 0, and the two elements greater than or equal to 0 satisfy a modulo operation relationship.

[0016] The above modulo operation relationship satisfies either the condition that the two elements greater than or equal to 0 are the same, or the difference between the two elements greater than or equal to 0 is 81.

[0017] In conjunction with the first or second aspect, in one possible implementation, the check matrix corresponds to the base check matrix, the check matrix having the same number of rows as the base check matrix, and the check matrix having the same number of columns as the base check matrix.

[0018] If the code length corresponding to the basic parity check matrix is ​​3888, the code rate corresponding to the basic parity check matrix is ​​2 / 3, and the expansion factor of the basic parity check matrix is ​​81.

[0019] In conjunction with the first or second aspect, in one possible implementation, the parity check matrix corresponds to the basic parity check matrix, including:

[0020] The first element in the parity check matrix and the second element in the basic parity check matrix satisfy a modulo operation relationship, which is: the first element is the same as the second element, or the first element = the second element + 81 (or the difference between the first element and the second element is 81); where the position of the first element in the parity check matrix is ​​the same as the position of the second element in the basic parity check matrix, the first element is the element in the parity check matrix corresponding to the information bit, and the second element is the element in the basic parity check matrix corresponding to the information bit, and both the first element and the second element are greater than or equal to 0.

[0021] In this embodiment of the application, the verification matrix is ​​obtained through the basic verification matrix, which allows the verification matrix to reuse the encoding and decoding architecture of the basic verification matrix as much as possible, thereby reducing the implementation complexity.

[0022] In conjunction with the first or second aspect, in one possible implementation, the parity check matrix corresponds to the basic parity check matrix, including:

[0023] The third element in the parity check matrix is ​​the same as the fourth element in the basic parity check matrix; the third element is in the same position as the fourth element in the basic parity check matrix. The third element is the element in the parity check matrix corresponding to the information bit, and the fourth element is the element in the basic parity check matrix corresponding to the information bit. Both the third and fourth elements are less than 0.

[0024] In conjunction with the first or second aspect, in one possible implementation, the parity check matrix corresponds to the basic parity check matrix, including:

[0025] The matrix corresponding to the parity bit in the parity check matrix is ​​the same as the matrix corresponding to the parity bit in the basic parity check matrix.

[0026] In this embodiment of the application, by maintaining the same matrix of parity bits, the fast and efficient coding algorithm of the original WLAN LDPC can be maintained.

[0027] For details regarding the specific verification matrices involved in the first and second aspects, please refer to the third aspect; they will not be elaborated upon here.

[0028] Thirdly, embodiments of this application provide a verification matrix, which is any one of the following matrices:

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[0102]

[0103] Fourthly, embodiments of this application provide a first site for executing the method in the first aspect or any possible implementation. The first site includes modules for executing the method in the first aspect or any possible implementation.

[0104] Fifthly, embodiments of this application provide a second site for performing the method in the second aspect or any possible implementation. The second site includes modules for performing the method in the second aspect or any possible implementation.

[0105] In a sixth aspect, embodiments of this application provide a communication device, which includes a processor and a transceiver. The processor is used to execute the processing steps in the method described in the first to second aspects or any possible implementations above, and the transceiver is used to execute the transmission and reception steps or input and output steps in the method described in the first to second aspects or any possible implementations above.

[0106] In a seventh aspect, embodiments of this application provide a communication device including a logic circuit and an interface, wherein the logic circuit and the interface are coupled to enable the communication device to implement the method described in the first aspect to the second aspect or any possible implementation.

[0107] Eighthly, embodiments of this application provide a computer-readable storage medium for storing a computer program that, when run on a communication device, causes the methods described in the first to second aspects or any possible implementation thereof to be executed.

[0108] Ninthly, embodiments of this application provide a computer program product that, when run on a communication device, causes the methods described in the first to second aspects or any possible implementation thereof to be executed.

[0109] In a tenth aspect, embodiments of this application provide a communication system including a first station and a second station. The first station is used to perform the method as described in the first aspect or any possible implementation, and the second station is used to perform the method as described in the second aspect or any possible implementation. Attached Figure Description

[0110] Figures 1a to 1c This is a schematic diagram of the architecture of the communication system provided in the embodiments of this application;

[0111] Figure 2a This is a schematic diagram of the parity check matrix H of the LDPC code;

[0112] Figure 2b It corresponds to Figure 2a Tanner diagram;

[0113] Figure 3a It is the parity check matrix corresponding to a code length of 1944 bits;

[0114] Figure 3b Taking Z=4 as an example, the circulant permutation matrix (CPM) when i=0, the CPM when i=1, the CPM when i=2, and the CPM when i=3;

[0115] Figure 4 This is a flowchart illustrating the communication method provided in an embodiment of this application;

[0116] Figure 5 This is a schematic diagram of LDPC encoding provided in an embodiment of this application;

[0117] Figure 6 This is a schematic diagram of the verification matrix provided in an embodiment of this application;

[0118] Figure 7a and Figure 7b This is the basic parity check matrix with a code length of 3888 bits and R = 2 / 3 provided in the embodiments of this application;

[0119] Figure 8 This is a schematic diagram illustrating two options for satisfying the modulo operation relationship provided in the embodiments of this application;

[0120] Figure 9 This is a schematic diagram of the tree structure provided in an embodiment of this application;

[0121] Figure 10 This is a schematic diagram of a communication device provided in an embodiment of this application;

[0122] Figure 11 This is another schematic diagram of the communication device provided in the embodiments of this application;

[0123] Figure 12 This is another structural schematic diagram of the communication device provided in the embodiments of this application. Detailed Implementation

[0124] To facilitate understanding of the technical solution of this application, the application will be further described below with reference to the accompanying drawings.

[0125] The terms "first" and "second," etc., used in the specification, claims, and drawings of this application are used only to distinguish different objects and not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0126] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0127] In this application, "at least one (item)" refers to one or more, "more than one" refers to two or more, "at least two (items)" refers to two or three or more, and "and / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. "Or" indicates that there can be two relationships, such as only A exists and only B exists; when A and B are not mutually exclusive, it can also mean that there are three relationships, such as only A exists, only B exists, and both A and B exist simultaneously. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items. For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c".

[0128] The following describes the communication system involved in the embodiments of this application.

[0129] The technical solutions provided in this application can be applied to wireless local area network (WLAN) systems, such as Wi-Fi. For example, the methods provided in this application can be applied to the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series standards, such as the 802.11be standard, the 802.11bn standard (also known as Wi-Fi 8, or ultra-high reliability (UHR) or ultra-high reliability and throughput (UHRT)), or next-generation standards of the 802.11bn standard, or standards supporting ambient power (AMP). The technical solutions provided in this application can also be applied to wireless personal area networks (WPANs) based on integrated millimeter wave (IMMW) and ultra-wideband (UWB) technologies. The methods provided in the embodiments of this application can be applied to the IEEE 802.15 series standards, such as the 802.15.4a, 802.15.4z, or 802.15.4ab standards, or future UWB WPAN standards. The technical solutions provided in the embodiments of this application can also be applied to the Spark Link or NearLink standards. The technical solutions provided in the embodiments of this application can also be applied to the following communication systems, for example, Internet of Things (IoT) systems, vehicle-to-everything (V2X, where X can represent anything), device-to-device (D2D), narrowband Internet of Things (NB-IoT) systems, long-term evolution (LTE) systems, 5th-generation (5G) communication systems, and new communication systems that will emerge in future communication developments.For example, V2X can include vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), vehicle-to-pedestrian (V2P), or vehicle-to-network (V2N) communication.

[0130] WLAN systems can provide high-speed, low-latency transmission. As WLAN application scenarios continue to evolve, WLAN systems will be applied to more scenarios or industries, such as the Internet of Things industry, the Internet of Vehicles industry, the banking industry, enterprise offices, stadiums and exhibition halls, concert halls, hotel rooms, dormitories, hospital wards, classrooms, shopping malls, squares, streets, production workshops and warehouses, etc. Of course, devices that support WLAN communication or sensing (such as access points or sites) can be sensor nodes in smart cities (such as smart water meters, smart electricity meters, and smart air monitoring nodes), smart devices in smart homes (such as smart cameras, projectors, displays, televisions, speakers, refrigerators, and washing machines), nodes in the Internet of Things (IoT), entertainment terminals (such as wearable devices for augmented reality (AR) and virtual reality (VR), smart devices in smart offices (such as printers, projectors, loudspeakers, and speakers), vehicle-to-everything (V2X) devices, infrastructure in daily life scenarios (such as vending machines, self-service navigation kiosks in supermarkets, self-service checkout machines, and self-service ordering machines), and equipment in large sports and music venues.

[0131] Although the embodiments of this application primarily use WLAN as an example, especially networks applied to the IEEE 802.11 series of standards, the various aspects involved in the embodiments of this application can be extended to other networks employing various standards. For example, Bluetooth, high-performance radio LAN (HIPERLAN) (a wireless standard similar to the IEEE 802.11 standard), and wide area network (WAN) or other networks now known or developed in the future.

[0132] In one possible implementation, the method provided in this application embodiment can be implemented by a communication device in a communication system. For example, the communication device can be an access point (AP) or a station (STA).

[0133] An Access Point (AP) is a device with wireless communication capabilities that supports communication, sensing, or power transmission using WLAN standards. It has the function of communicating or sensing with other devices in a WLAN network (such as non-access point stations (non-APSTAs) or other access points). Alternatively, an access point acts as a bridge connecting wired and wireless networks, primarily connecting various wireless network clients together and then connecting the wireless network to an Ethernet network. In a WLAN system, an access point can be called an Access Point Station (AP STA). This wireless communication device can be a complete device or a chip, processing system, or functional module installed within a complete device. Devices with these chips, processing systems, or functional modules can implement the methods and functions of the embodiments described in this application under the control of the chips, processing systems, or functional modules. The AP in the embodiments of this application is a device that provides services to non-AP STAs and can support 802.11 series standards or subsequent standards. For example, an access point can be an access point for terminals (such as mobile phones) to enter a wired (or wireless) network, mainly deployed in homes, buildings, and parks, with a typical coverage radius of tens to hundreds of meters; it can also be deployed outdoors. For example, an AP can be a communication server, router, switch, bridge, or other communication entity; APs can include various forms of macro base stations, micro base stations, repeater stations, etc.

[0134] A Station-Style (STA) is a device with wireless communication capabilities that supports communication, sensing, or power transmission using WLAN standards. It has the ability to communicate, sense, or transmit power with other non-AP STAs or access points in a WLAN network. In a WLAN system, a station can be called a non-access point station (non-AP STA). For example, an STA is any user communication device that allows a user to communicate with an AP (Access Point) or sense or transmit power, and thus communicate with the WLAN. This wireless communication device can be a complete device, or it can be a chip, processing system, or functional module installed in a complete device. Devices with these chips, processing systems, or functional modules can implement the methods and functions of the embodiments of this application under the control of the chips, processing systems, or functional modules. For example, an STA can be a wireless communication chip, a wireless sensor, or a wireless communication terminal, and can also be referred to as a user. Furthermore, an STA can be a mobile phone supporting Wi-Fi communication, a tablet computer supporting Wi-Fi communication, a set-top box supporting Wi-Fi communication, a smart TV supporting Wi-Fi communication, a smart wearable device supporting Wi-Fi communication, an in-vehicle communication device supporting Wi-Fi communication, and a computer supporting Wi-Fi communication.

[0135] For example, the communication systems to which the methods provided in this application can be applied may include access points and stations. For instance, this application can be applied to scenarios of communication or sensing between APs and STAs, between APs, or between STAs in a WLAN, and this application does not limit this. Optionally, an AP can communicate or sense with a single STA, or an AP can communicate or sense with multiple STAs simultaneously. Specifically, communication or sensing between an AP and multiple STAs can be further divided into downlink transmission where the AP simultaneously sends signals to multiple STAs, and uplink transmission where multiple STAs send signals to the AP. The communication between APs and STAs, between APs, and between STAs can support WLAN communication standards, which may include the IEEE 802.11 series of standards, such as the 802.11bn standard, and of course, standards after 802.11bn.

[0136] Figures 1a to 1c This is a schematic diagram of the architecture of a communication system provided in an embodiment of this application. The communication system may include one or more APs and one or more STAs. Figure 1a The diagram illustrates two access points, such as AP1 and AP2, and three stations, such as STA1, STA2, and STA3. As an example, the method provided in this application embodiment can be applied to data communication or sensing between an AP and one or more STAs, such as... Figure 1a The communication between AP1 and STA1 shown is as follows: Figure 1b The communication between the AP and STA shown is as follows: Figure 1c The illustrated AP communicates, senses, or transmits power with STA1, STA2, and STA3 respectively. As another example, the method provided in this application embodiment can be applied to communication between APs, such as... Figure 1a The example illustrates communication or sensing between AP1 and AP2. As another example, the method provided in this application embodiment can be applied to communication or sensing between STAs, such as... Figure 1a The communication or sensing between STA2 and STA3 is shown.

[0137] Figures 1a to 1c The use of STA (station) as a mobile phone and AP (access point) as a router is merely an example and does not imply limitation on the types of AP and STA in the embodiments of this application. Furthermore, Figures 1a to 1c The number of APs and STAs shown are merely examples. In a specific implementation, the number of APs or STAs may be more or less, and this application does not limit this.

[0138] From the perspectives of transmitting and receiving signals, the first station described below can be understood as a communication device that transmits signals, and the second station can be understood as a communication device that receives signals. Alternatively, the first station can also be called the transmitting end or encoding end, and the second station can also be called the receiving end or decoding end. The aforementioned signals can be encoded bits, or signals obtained by processing encoded bits, etc.

[0139] From the perspective of different devices, as an example, the first site can be an access point (AP), and the second site can be a non-AP STA. As another example, both the first and second sites can be non-AP STAs or both can be APs. As yet another example, the first site can be a non-AP STA, and the second site can be an AP. The specific forms of the first and second sites will not be listed here.

[0140] This application embodiment describes the method provided by the first station and the second station as both sides. However, during the transmission of signals, the first station and the second station can also forward the signals through other devices, such as forwarding the signals between the first station and the second station through a forwarding device. This application embodiment does not limit other devices besides the first station and the second station.

[0141] Before introducing the methods involved in the embodiments of this application, the relevant concepts of LDPC codes involved in the embodiments of this application are introduced below.

[0142] LDPC codes are linear block codes, and their parity-check matrix is ​​a sparse matrix. The number of zero elements in the parity-check matrix of an LDPC code is far greater than the number of non-zero elements; in other words, the row and column weights of the parity-check matrix are very small compared to the code length of the LDPC code.

[0143] In 1981, Tanner represented the codewords of LDPC codes graphically, calling this a Tanner graph (or factor graph or number graph). Tanner graphs correspond one-to-one with parity-check matrices. A Tanner graph consists of two types of nodes: the first type represents codeword symbols and is called variable nodes; the second type is parity-check nodes, representing parity constraints, with each node representing a single parity constraint.

[0144] Figure 2a This is a schematic diagram of the parity check matrix H of the LDPC code. Figure 2a In the middle, {V i} represents the set of variable nodes, {C i} represents the set of check nodes. Each row of the check matrix H represents a check equation, and each column represents a code character. Figure 2aIn this diagram, there are 8 variable nodes and 4 check nodes. If a code character is included in the corresponding check equation, a line can be used to connect the involved bit nodes and check nodes to obtain a Tanner diagram.

[0145] Figure 2b It corresponds to Figure 2a The Tanner plot. The Tanner plot represents the parity-check matrix of the LDPC code. Figure 2a For example, for a parity check matrix H of size 4 rows and 8 columns, the Tanner graph contains two types of nodes: 8 variable nodes and 4 parity nodes. The 8 variable nodes correspond to the 8 columns of the parity check matrix H, and the 4 parity nodes correspond to the 4 rows of the parity check matrix H. A cycle in the Tanner graph consists of interconnected nodes. The cycle starts and ends at one of these nodes and visits each node only once.

[0146] LDPC codes include quasi-cyclic (QC) LDPC (QC-LDPC) codes. QC-LDPC codes are a widely used type of structured LDPC codes. Due to the unique structure of their parity-check matrix, they can be encoded using simple feedback shift registers, which effectively solves the encoding complexity problem of LDPC codes.

[0147] For a code length of 648 bits, 1296 bits, or 1944 bits, four different coding rates are supported for each code length: 1 / 2, 2 / 3, 3 / 4, and 5 / 6. The parity check matrix is ​​different for each code length and coding rate, but the parity bit portion (i.e., the matrix corresponding to the parity bits, or parity check square matrix) in the parity check matrix has the same structure for different code lengths or coding rates.

[0148] Figure 3a It is the parity check matrix corresponding to a code length of 1944 bits. Figure 3a The following are examples of parity-check matrices corresponding to four different coding rates: 1 / 2, 2 / 3, 3 / 4, and 5 / 6. Each coding rate corresponds to a separate parity-check matrix. A code length of 1944 bits can also be referred to as a 1944-bit code length, a code length of 1944, or a code length of 1944.

[0149] Figure 3a The "-" in the matrix indicates a Z*Z matrix consisting entirely of zeros. Figure 3a The elements greater than or equal to 0 in the matrix represent the circulant permutation matrix (CPM) of the Z*Z identity matrix. This CPM can be represented by P... iLet i represent the element greater than or equal to 0. 0 ≤ i ≤ Z⁻¹. i can be called the cyclic shift value, the number of cyclic shifts (e.g., the number of bits cyclically shifted to the right in an identity matrix), or the CPM coefficient, etc. The specific name for i is not limited in this application. Z represents the expansion factor. It is understood that... Figure 3a The "-" in the text can also be represented by "-1", meaning that "-" and "-1" in this application can be substituted for each other.

[0150] The spread factor Z and the code length N satisfy the following relationship: N = Z * (number of columns in the parity-check matrix). Figure 3a For example, the parity check matrix has 24 columns, meaning N = 24 * Z. Whether N = 648, N = 1296, or N = 1944, the parity check matrix still has 24 columns. The relationship between Z and N shown here is just an example; for a 48-column parity check matrix, N = Z * 48.

[0151] For example, N = 1944, Z = 81. When i = 1, P1 represents the CPM of the 81*81 identity matrix after rotating one position to the right. The CPM is shown below:

[0152]

[0153] Figure 3b Taking Z=4 as an example, the CPM when i=0, the CPM when i=1, the CPM when i=2, and the CPM when i=3. Figure 3b The CPM shown is merely an example; the CPM for other Z*Z identity matrices in this application embodiment can be referenced as follows. Figure 3a or Figure 3b The principle shown yields the final P. i This will not be elaborated upon further below.

[0154] Optionally, the code rate can be selected by the transmission system based on the link adaptive modulation and coding scheme (MCS). Optionally, the code length can be determined by the data bit length (also known as the information bit length), the total number of coded bits, and the PPDU encoding parameters. The PPDU encoding parameters include the relationship between the data bit length, the total number of coded bits, and the code length. Thus, the station can select a parity check matrix from the 12 parity check matrices based on the given code length and code rate.

[0155] The following describes the methods involved in the embodiments of this application.

[0156] Because LDPC codes can improve the transmission reliability of wireless transmission systems, they have been widely used in WLAN standards. To further improve the data transmission reliability of Wi-Fi systems, current or next-generation standards may consider longer LDPC code lengths, thereby providing the encoding module with stronger error control performance.

[0157] Therefore, this application provides a new parity check matrix that can be applied to longer code lengths. This parity check matrix can be applied to a code length of 7776 bits, thus achieving stronger error control performance. A code length of 7776 bits can also be referred to as a 4x-LDPC code length or 4x LDPC, etc. That is, 7776 bits is four times the LDPC code length of 1944.

[0158] The embodiments of this application design a parity check matrix based on the basic parity check matrix, which can not only be applied to longer code lengths and achieve excellent performance, but also reuse the original WLAN LDPC code encoding and decoding architecture as much as possible. For example, the modifications to the existing LDPC encoding module and LDPC decoding module are small, reducing the implementation complexity of LDPC encoding and decoding.

[0159] In the embodiments of this application, the matrices shown below may represent parity-check matrices, or be referred to as prototypes of parity-check matrices, or matrix prototypes of the parity-check matrices, or matrix prototypes for codeword block length N, or parent matrices, etc. The specific names of the matrices involved in the embodiments of this application are not limited thereto. For ease of description, the following description uses parity-check matrices as an example.

[0160] In this embodiment of the application, the code length can also be referred to as a codeword block length or codeword length, etc. The specific name of the code length is not limited in this embodiment of the application. For ease of description, the code length will be used as an example in the following description.

[0161] In this embodiment, Z can be referred to as the subblock size, expansion factor, or lift factor, etc. The specific name of Z is not limited in this embodiment. For ease of description, Z will be referred to as the expansion factor in the following explanation.

[0162] Optionally, since the number of columns in each matrix shown below is 48, N = Z * 48. For ease of understanding, different letter parameters are used to represent different meanings in the embodiments of this application, such as N representing code length, Z representing expansion factor, and R representing code rate. However, the letter parameters corresponding to each meaning are only examples and are not intended to limit the embodiments of this application.

[0163] Figure 4 This is a flowchart illustrating the communication method provided in an embodiment of this application. The communication method involves an encoding process and a decoding process. Figure 4 The process related to encoding can be called the encoding method, and the process related to decoding can be called the decoding method. For explanations of the first and second stations, please refer to the above text; they will not be elaborated upon here. Figure 4 As shown, the method includes:

[0164] 401. The first station performs LDPC encoding on the information bits according to the parity check matrix to obtain the encoded bits. The code rate corresponding to the parity check matrix is ​​2 / 3, and the code length corresponding to the parity check matrix is ​​7776.

[0165] The encoded bits include parity bits. For R = 2 / 3 and N = 7776, the number of information bits in a 7776-bit code length can be 7776 * 2 / 3 = 5184. Alternatively, it can be 32 * 162 = 5184. 32 represents the number of columns in the parity matrix corresponding to the information bits, and 162 is the spread factor.

[0166] As an example, the number of information bits can be equal to 5184.

[0167] As another example, the number of information bits can be less than 5184. The first station can fill the information bits with a certain number of 0s, and then delete these 0s after LDPC encoding. This operation of filling the information bits with a certain number of 0s at the first station and then deleting these 0s after encoding can be called a shortening operation.

[0168] As another example, the number of information bits is greater than 5184. The first station can divide this information bit into multiple codewords, and the number of information bits carried by each codeword can be less than or equal to 5184. Optionally, the above-mentioned shortening operation and the operation of processing into multiple codewords can be combined with each other, and the embodiments of this application do not limit this.

[0169] When using orthogonal frequency division multiplexing (OFDM) technology, the encoded information bits need to be placed into an integer number of OFDM symbols, and the encoded bits also need to be placed into an exact integer number of LDPC codewords. Before the first station performs LDPC encoding, the minimum number of OFDM symbols N required for this transmission is determined. SYM According to N SYM Calculate the total number of coded bits N that can be stored in all OFDM symbols, based on the current coding and modulation scheme (such as the modulation order and code rate indicated by the MCS). TCB For example, N TCB =N CBPS *N SYM N CBPS N represents the number of coded bits that can be stored in each OFDM symbol. SYM This represents the number of OFDM symbols. For example, the first station uses N... TCB The number of information bits is selected by choosing the code length used in the current transmission and the required number of codewords N. CW This example illustrates how the first station determines the code length based on PPDU encoding parameters. These PPDU encoding parameters can include a code length greater than 1944, such as a code length of 7776 bits. Alternatively, the first station can directly determine its code length, which can be 7776 bits. The specific method by which the first station determines the code length is not limited in this embodiment.

[0170] When there are not enough information bits to fill the information bit portion of an LDPC codeword, the first station can perform a shortening operation before LDPC encoding.

[0171] Figure 5 This is a schematic diagram of LDPC encoding provided in an embodiment of this application. Figure 5 Three LDPC codewords are shown as an example. The length of each LDPC codeword is equal to the code length. For example... Figure 5As shown, 501 indicates that the first station obtains the payload bits to be encoded (information bits as shown in the embodiments of this application). 502 indicates that the first station calculates the LDPC code length and the number of codewords. 503 indicates that the first station can perform a shortening operation on the payload bits. 504 indicates that the first station uses the payload bits and shortened 0 bits to generate parity bits. 505 indicates that the first station discards shortening 0 bits. The above descriptions regarding shortening operations are merely examples. Further explanations regarding shortening operations can be found in relevant standards, etc., and this application embodiment does not limit the scope of the descriptions.

[0172] Optionally, the first station can punch holes in the encoded parity bits to obtain a higher code rate or a shorter code length.

[0173] The code rate can be determined based on the MCS adaptively selected by the link. For example, the code rate R is determined based on the channel information between the first and second stations. The specific method for determining the code rate R is not limited in this application embodiment. As an example, the MCS can be issued by the AP. As another example, the MCS can be determined by the first station. For example, the first station sends an MCS to the second station, and the second station receives the MCS and learns the code rate R based on it. As yet another example, the MCS is determined by the second station. For example, the second station sends an MCS to the first station, and the first station receives the MCS and learns the code rate R based on it. The specific interaction process of the MCS is not limited in this application embodiment.

[0174] In this embodiment, the parity check matrix is ​​a 16-row, 48-column matrix. The expansion factor of the parity check matrix is ​​162.

[0175] The check matrix includes a submatrix, which is a 2x2 matrix. Each submatrix contains two elements greater than or equal to 0 that satisfy a modulo operation. Alternatively, the two elements on opposite diagonals of the submatrix satisfy a modulo operation, or the two elements on opposite anti-diagonals of the submatrix satisfy a modulo operation.

[0176] For example, if the two elements in the submatrix are element a and element b, then element a = element b % (Z / 2). That is, element a = element b, or element a = element b + 81. Here, elements a and b are the elements in the check matrix other than "-1" (or "-"), meaning that elements a and b are both greater than or equal to 0. Optionally, the elements in the submatrix other than elements a and b are -1 (or "-").

[0177] Further details regarding the parity check matrix can be found below, but will not be elaborated upon here.

[0178] 402. The first station outputs the encoded bits.

[0179] For example, the encoded bits are output from the LDPC encoding module of the first station. Optionally, the encoded bits can undergo further processing, and the first station transmits the processed signal through the channel. This signal can be referred to as the signal corresponding to the encoded bits. Figure 4 As shown, the first station can transmit signals corresponding to the encoded bits through the channel.

[0180] Correspondingly, the second station receives signals transmitted through the channel from the first station.

[0181] 403. Obtain the information to be decoded at the second station.

[0182] Optionally, the second station obtains the aforementioned information to be decoded from the signal it receives from the first station.

[0183] 404. The second station performs LDPC decoding on the information to be decoded based on the parity check matrix.

[0184] The decoding methods used by the second station include, but are not limited to, hard-decision decoding, soft-decision decoding, or hybrid decoding methods. Through LDPC decoding, the second station can obtain the information bits.

[0185] As an example, the second station can determine the code length based on the PPDU encoding parameters, which is 7776. As another example, the second station can receive indication information from the first station, indicating the code length used by the first station, such as 7776. The specific method by which the second station determines the code length is not limited in this embodiment.

[0186] The method for determining the bitrate at the second site is described in step 401, and will not be repeated here.

[0187] In this embodiment of the application, steps 401 to 402 can be implemented by an LDPC encoding module, such as the first station including an LDPC encoding module. Steps 403 and 404 can be implemented by an LDPC decoding module, such as the second station including an LDPC decoding module.

[0188] The verification matrix provided in this application embodiment can be applied to a code length of 7776, thereby improving the transmission reliability and performance of the system.

[0189] The following is an introduction Figure 4 The verification matrix involved.

[0190] As one possible implementation, this application provides a verification matrix, which is any one of the following matrices 1 to 40:

[0191] Matrix 1:

[0192]

[0193] Matrix 2:

[0194]

[0195] Matrix 3:

[0196]

[0197]

[0198] Matrix 4:

[0199]

[0200] Matrix 5:

[0201]

[0202] Matrix 6:

[0203]

[0204] Matrix 7:

[0205]

[0206] Matrix 8:

[0207]

[0208]

[0209] Matrix 9:

[0210]

[0211] Matrix 10:

[0212]

[0213] Matrix 11:

[0214]

[0215]

[0216] Matrix 12:

[0217]

[0218] Matrix 13:

[0219]

[0220] Matrix 14:

[0221]

[0222]

[0223] Matrix 15:

[0224]

[0225] Matrix 16:

[0226]

[0227] Matrix 17:

[0228]

[0229]

[0230] Matrix 18:

[0231]

[0232] Matrix 19:

[0233]

[0234] Matrix 20:

[0235]

[0236]

[0237] Matrix 21:

[0238]

[0239] Matrix 22:

[0240]

[0241] Matrix 23:

[0242]

[0243] Matrix 24:

[0244]

[0245] Matrix 25:

[0246]

[0247]

[0248] Matrix 26:

[0249]

[0250] Matrix 27:

[0251]

[0252] Matrix 28:

[0253]

[0254]

[0255] Matrix 29:

[0256]

[0257] Matrix 30:

[0258]

[0259] Matrix 31:

[0260]

[0261]

[0262] Matrix 32:

[0263]

[0264] Matrix 33:

[0265]

[0266] Matrix 34:

[0267]

[0268]

[0269] Matrix 35:

[0270]

[0271] Matrix 36:

[0272]

[0273] Matrix 37:

[0274]

[0275]

[0276] Matrix 38:

[0277]

[0278] Matrix 39:

[0279]

[0280]

[0281] Matrix 40:

[0282]

[0283] As another possible implementation, this application also provides a method for designing a parity check matrix. In a specific implementation, the communicating parties may not execute the design method described below, but instead save the parity check matrix designed by the design method, or save extended indication information, or save cyclic shift values, etc. The design method described below can obtain matrices 1 to 40 shown above. Although 40 parity check matrices are shown above as an example, other parity check matrices determined according to the design method shown in this application also fall within the protection scope of this application. The design method is as follows:

[0284] The parity-check matrix corresponds to the base parity-check matrix. In other words, the parity-check matrix is ​​determined based on the base parity-check matrix. The base parity-check matrix has a code length of 3888, a code rate of 2 / 3, and an expansion factor of 81. That is, the base parity-check matrix has the same number of rows and columns as the parity-check matrix. For example, if the parity-check matrix is ​​a 16*48 matrix, the base parity-check matrix is ​​also a 16*48 matrix. It's important to understand that the 16*48 matrix shown here is merely an example; in a concrete implementation, the 16*48 matrix can be expanded using cyclic shift values ​​and an expansion factor to obtain a matrix of size 16Z*48Z.

[0285] The parity check matrix corresponds to the basic parity check matrix and satisfies at least one of the following:

[0286] (1) The first element Z1(i,j) in the parity check matrix and the second element Z(i,j) in the basic parity check matrix satisfy the modulo operation relationship. That is, Z1(i,j) and Z(i,j) can satisfy: Z(i,j)=Z1(i,j)%(Z / 2). In other words, Z1(i,j)=Z(i,j), or Z1(i,j)=Z(i,j)+(Z / 2). Z is the expansion factor of the parity check matrix, such as Z=162.

[0287] Alternatively, Z1(i,j) and Z(i,j) can satisfy the following: Z(i,j) = Z1(i,j)%(Z0), where Z0 is the expansion factor 81 of the basic parity-check matrix.

[0288] In this matrix, the first element is the element in the parity check matrix corresponding to the information bit, and the second element is the element in the basic parity check matrix corresponding to the information bit. The position of the first element in the parity check matrix (e.g., the i-th row and j-th column) is the same as the position of the second element in the basic parity check matrix (e.g., the i-th row and j-th column). Both the first and second elements are greater than or equal to 0, meaning the first element is the cyclic shift value in the parity check matrix, and the second element is the cyclic shift value in the basic parity check matrix.

[0289] For example, if Z(i,j) = 61, then Z1(i,j) = 61, or Z1(i,j) = 61 + (162 / 2) = 142.

[0290] In this embodiment, Z(i,j) and Z1(i,j) satisfy a nested relationship, i.e., a modulo operation relationship exists between them. This allows the proposed parity check matrix with a code length of 7776 to minimize modifications to existing LDPC encoding and decoding modules in the Wi-Fi system, reducing the complexity of the encoding and decoding implementation. Furthermore, by determining the parity check matrix based on the basic parity check matrix, the existing LDPC encoding module can be reused when the first station performs LDPC encoding, and the existing LDPC decoding module can be reused when the second station performs LDPC decoding. This embodiment reduces modifications to the LDPC encoding and decoding modules while ensuring encoding and decoding performance.

[0291] (2) The third element in the parity check matrix is ​​the same as the fourth element in the basic parity check matrix. The third element is the element in the parity check matrix corresponding to the information bit, and the fourth element is the element in the basic parity check matrix corresponding to the information bit. Both the third and fourth elements are less than 0.

[0292] For example, if the element in the i-th row and j-th column of the matrix corresponding to the information bit in the basic parity check matrix is ​​less than 0 (i.e., "-1" or "-"), then the element in the i-th row and j-th column of the matrix corresponding to the information bit in the parity check matrix will also be less than 0.

[0293] (3) The matrix corresponding to the parity bit in the parity check matrix is ​​the same as the matrix corresponding to the parity bit in the basic parity check matrix.

[0294] Since the expansion factor of the parity check matrix is ​​162 and the expansion factor of the basic parity check matrix is ​​81, when (3) is satisfied, the size of the CPM represented by the element in the matrix corresponding to the parity bit in the parity check matrix changes from the original Z0*Z0 (expansion factor Z0 of the basic parity check matrix) to Z*Z, that is, from 81*81 to 162*162.

[0295] Figure 6 This is a schematic diagram of the verification matrix provided in an embodiment of this application. Figure 3a Taking R=5 / 6 as an example, the matrix corresponding to the parity bits in the parity check matrix is ​​as follows: Figure 6 The square matrix within the box contains matrices that, excluding the matrices within the box, are the matrices in the parity check matrix corresponding to the information bits.

[0296] In this embodiment, the matrix corresponding to the parity bit in the parity check matrix is ​​the same as the matrix corresponding to the parity bit in the basic parity check matrix, which can maintain the fast and efficient coding algorithm of WLAN LDPC.

[0297] Figure 7a and Figure 7b This is the basic parity check matrix with a code length of 3888 bits and R = 2 / 3 provided in the embodiments of this application. The parity check matrices shown in matrices 1 to 20 above can be for... Figure 7a The basic parity check matrix shown is used to determine this. The parity check matrices shown in matrices 21 to 40 above can be used for... Figure 7b The basic parity check matrix shown is used to determine this.

[0298] Figure 7a The elements in the matrix corresponding to the information bits in the basic parity check matrix shown above satisfy (1) and (2) above with the elements in the matrix corresponding to the information bits in the parity check matrices shown in matrices 1 to 20. The matrix corresponding to the parity bits in the basic parity check matrix and the matrix corresponding to the parity bits in the parity check matrices shown in matrices 1 to 20 satisfy (3) above. Figure 7b Similarly, this will not be elaborated upon here.

[0299] Optionally, the aforementioned basic parity-check matrix can be determined based on the parity-check matrix corresponding to a code length of 1944 bits and a code rate of 2 / 3. That is, the aforementioned basic parity-check matrix can be determined based on... Figure 3aThe parity-check matrix corresponding to R=2 / 3 shown is determined. Figure 3a The expansion factor of each of the parity-check matrices shown is 81.

[0300] In one possible implementation, based on the fact that the check matrix and the basic check matrix satisfy the above (1) to (3), the embodiments of this application also provide a design method. Based on the design method shown below, the check matrix with better performance can be effectively screened out, thereby enhancing the performance of the check matrix.

[0301] To ensure the above modular operation relationship, each cyclic shift value in the parity check matrix has two choices: if Z(i,j) = s, then Z1(i,j) = s (remains unchanged) or Z1(i,j) = s + (Z / 2). Figure 8 The small squares in the diagram represent the values ​​of Z(i,j). Option A (Opt A) means Z1(i,j) = s (remaining unchanged), and option B (Opt B) means Z1(i,j) = s + (Z / 2).

[0302] For Z1(i,j), to choose Opt A or Opt B, you can expand Z1(i,j) using a tree expansion method and choose the one with the greater depth. A diagram illustrating the tree expansion is shown below. Figure 9 As shown, circles represent variable nodes, and squares represent verification nodes. The deeper the expanded tree, the fewer short cycles the resulting matrix contains, and short cycles negatively impact performance. Expanding each variable node according to the tree, the depth of each item Opt A or Opt B in the corresponding matrix may differ, resulting in different cycle structures in the Tanner graph corresponding to the overall verification matrix. Therefore, this embodiment comprehensively considers the local and overall cycle structure of the matrix, designing all non-zero elements based on tree expansion to ensure that the Tanner graph corresponding to the first verification matrix has a good cycle structure.

[0303] In one possible implementation, both communicating parties store cyclic shift values. For example, they can store each cyclic shift value in the parity check matrix. Optionally, when the code length is 7776, both parties obtain the parity check matrix based on their respective stored cyclic shift values ​​and perform encoding and decoding based on this matrix. Optionally, when the code length is 3888, both parties can obtain the basic parity check matrix based on the aforementioned modulo operation relationship. Again, both parties store each cyclic shift value in the basic parity check matrix. Optionally, when the code length is 7776, both parties obtain the parity check matrix based on the aforementioned modulo operation relationship. By storing cyclic shift values, both parties can obtain parity check matrices of two code lengths, saving storage space.

[0304] In one possible implementation, the communicating parties store extended indication information, which indicates whether the modulo operation relationship between Z(i,j) and Z1(i,j) is Z1(i,j) = Z(i,j) or Z1(i,j) = Z(i,j) + (Z / 2).

[0305] As an example, the extended indication information can be a bitmap, where bits in the bitmap indicate whether the modulo operation relationship between Z(i,j) and Z1(i,j) at the corresponding position of that bit is Z1(i,j) = Z(i,j) or Z1(i,j) = Z(i,j) + (Z / 2). For example, if the value of a bit is 0, the modulo operation relationship corresponding to that bit is Z1(i,j) = Z(i,j). As another example, if the value of a bit is 1, it indicates that the modulo operation relationship corresponding to that bit is Z1(i,j) = Z(i,j) + (Z / 2). The specific relationship between the bits in the bitmap and their corresponding positions is not limited in the embodiments of this application.

[0306] As another example, the extended indication information can be in the form of a binary matrix, the size of which can be the same as the size of the matrix corresponding to the information bits in the parity check matrix. This binary matrix may include elements 0 and 1. If element 0 is located in the i-th row and j-th column of the binary matrix, element 0 can represent the modulo operation relationship between Z1(i,j) and Z(i,j) corresponding to the position of element 0 as Z1(i,j) = Z(i,j). Similarly, if element 1 is located in the i-th row and j-th column of the binary matrix, this element 1 can represent the modulo operation relationship between Z1(i,j) and Z(i,j) corresponding to the position of element 1 as Z1(i,j) = Z(i,j) + (Z / 2).

[0307] The various verification matrices provided in the embodiments of this application can achieve significant performance improvements, while also achieving a good trade-off between performance and complexity.

[0308] The above implementation methods can be individual embodiments, or they can be combined with each other.

[0309] The following describes the communication device provided in the embodiments of this application.

[0310] This application divides the communication device into functional modules according to the above-described method embodiments. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware or as software functional modules. It should be noted that the module division in this application is illustrative and represents only one logical functional division; other division methods may be used in actual implementation. The following will combine... Figures 10 to 12 The communication device of the embodiments of this application is described in detail.

[0311] Figure 10 This is a schematic diagram of a communication device provided in an embodiment of this application, such as... Figure 10 As shown, the communication device includes a processing module 1001 and a transceiver module 1002. The transceiver module 1002 can implement corresponding communication functions, and the processing module 1001 is used to implement corresponding processing functions. The transceiver module 1002 can also be referred to as an interface, a communication interface, or a communication module, etc.

[0312] In some embodiments of this application, the communication device can be used to perform the actions performed by the first station in the above method embodiments. In this case, the first station can be the Wi-Fi device itself or a chip or functional module configurable in the device. The transceiver module 1002 is used to perform the transceiver-related operations of the first station in the above method embodiments, and the processing module 1001 is used to perform the processing-related operations of the first station in the above method embodiments.

[0313] For example, the processing module 1001 is used to acquire information bits and perform LDPC encoding on the information bits based on the parity check matrix to obtain encoded bits; the transceiver module 1002 is used to output the encoded bits.

[0314] Optionally, the processing module 1001 can also be used to perform other processing on the encoded bits; the transceiver module 1002 can also be used to send or output the signal after other processing.

[0315] Reuse Figure 10 In other embodiments of this application, the communication device can be used to perform the actions performed by the second station in the above method embodiments. In this case, the communication device can be the Wi-Fi device itself or a chip or functional module configurable in the device. The transceiver module 1002 is used to perform the transceiver-related operations of the second station in the above method embodiments, and the processing module 1001 is used to perform the processing-related operations of the second station in the above method embodiments.

[0316] Optionally, the transceiver module 1002 is used to receive or input signals transmitted through the channel; the processing module 1001 can be used to process the signal to obtain information to be decoded.

[0317] For example, the transceiver module 1002 can be used to input information to be decoded; the processing module 1001 can perform LDPC decoding on the information to be decoded based on the parity check matrix.

[0318] For example, the transceiver module 1002 described above can be an antenna module. Alternatively, the transceiver module 1002 can be an input / output module. Optionally, in the above embodiments, the communication device may further include a storage module, which can be used to store instructions and / or data. The processing module 1001 can read the instructions and / or data from the storage module to enable the communication device to implement the aforementioned method embodiments. For example, the storage module can store the parity check matrix shown above, or it can be used to store CPM coefficients or extended indication information, etc., in the parity check matrix shown above.

[0319] For specific explanations of terms or steps in the above embodiments, please refer to the descriptions in the above method embodiments, which will not be detailed here.

[0320] It is understandable that the module division in the above-mentioned device is merely a logical functional division. Each function can correspond to a functional module, or two or more functions can be integrated into one functional module. In actual implementation, all or some modules can be integrated into one physical entity, or they can be distributed across different physical entities. Furthermore, the above-mentioned functional modules can be implemented in hardware, software, or a combination of both.

[0321] In one example, the functional unit in any of the above devices may be one or more integrated circuits configured to implement the above methods, such as: one or more application-specific integrated circuits (ASICs), or one or more central processing units (CPUs), one or more microcontroller units (MCUs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms.

[0322] The communication device according to the embodiments of this application has been described above. The following describes the possible product forms of the communication device. Any device possessing the above-described... Figure 10 Any form of the communication device described herein falls within the protection scope of the embodiments of this application. The following description is merely illustrative and does not limit the product form of the communication device in the embodiments of this application to this.

[0323] In one possible implementation, Figure 10In the communication device shown, the processing module 1001 can be one or more processors, and the transceiver module 1002 can be a transceiver, or the transceiver module 1002 can also be a transmitting module and a receiving module. The transmitting module can be a transmitter, and the receiving module can be a receiver. The transmitting module and the receiving module are integrated into one device, such as a transceiver. In the embodiments of this application, the processor and the transceiver can be coupled, etc., and the connection method between the processor and the transceiver is not limited in the embodiments of this application. In the process of executing the above method, the process of sending information in the above method can be the process of the processor outputting the above information. When outputting the above information, the processor outputs the above information to the transceiver so that the transceiver can transmit it. After the above information is output by the processor, it may need to undergo other processing before reaching the transceiver. Similarly, the process of receiving information in the above method can be the process of the processor receiving the input above information. When the processor receives the input information, the transceiver receives the above information and inputs it into the processor. Furthermore, after the transceiver receives the above information, the above information may need to undergo other processing before being input into the processor.

[0324] Figure 11 This is another structural schematic diagram of the communication device provided in the embodiments of this application. For example... Figure 11 As shown, the communication device 110 includes one or more processors 1120 and transceivers 1110.

[0325] In some embodiments of this application, the communication device can be used to perform the steps, methods, or functions performed by the first station described above, such as the processor 1120 being used to perform... Figure 10 The transceiver 1110 can be used to perform the functions or steps implemented by the processing module 1001 shown. Figure 10 The transceiver module 1002 shown illustrates the functions or steps implemented by this module. For detailed information on the processor 1120 and transceiver 1110, please refer to [link / reference needed]. Figure 10 Alternatively, the method embodiments shown above will not be described in detail here.

[0326] In other embodiments of this application, the communication device is used to perform the steps, methods, or functions performed by the second station described above, such as the processor 1120 being used to perform... Figure 10 The transceiver 1110 can be used to perform the functions or steps implemented by the processing module 1001 shown. Figure 10 The transceiver module 1002 shown illustrates the functions or steps implemented by this module. For detailed information on the processor 1120 and transceiver 1110, please refer to [link / reference needed]. Figure 10 Alternatively, the method embodiments shown above will not be described in detail here.

[0327] exist Figure 11In various implementations of the communication apparatus shown, the transceiver may include a receiver for performing a receiving function (or operation) and a transmitter for performing a transmitting function (or operation). The transceiver is also used to communicate with other devices / appliances via a transmission medium.

[0328] Optionally, the communication device 110 may further include one or more memories 1130 for storing program instructions and / or data. The memories 1130 are coupled to the processor 1120. The coupling in this embodiment is an indirect coupling or communication connection between communication devices, units, or modules, and can be electrical, mechanical, or other forms, used for information exchange between the communication devices, units, or modules. The processor 1120 may operate in conjunction with the memories 1130. The processor 1120 may execute program instructions stored in the memories 1130. Optionally, at least one of the aforementioned memories may be included in the processor.

[0329] This application embodiment does not limit the specific connection medium between the transceiver 1110, processor 1120, and memory 1130. This application embodiment... Figure 11 The memory 1130, processor 1120, and transceiver 1110 are connected via a bus 1140, and the bus is in Figure 11 The connections between other components are shown in bold and are for illustrative purposes only, not as limiting information. The bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, Figure 11 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0330] In the embodiments of this application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules within the processor.

[0331] In this application embodiment, the memory may include, but is not limited to, non-volatile memory such as hard disk drive (HDD) or solid-state drive (SSD), random access memory (RAM), erasable programmable read-only memory (EPROM), read-only memory (ROM), or compact disc read-only memory (CD-ROM), etc. Memory is any storage medium capable of carrying or storing program code in the form of instructions or data structures, and capable of being read and / or written by a computer (such as the communication device shown in this application), but is not limited to this. The memory in this application embodiment may also be a circuit or any other device capable of implementing storage functions, used to store program instructions and / or data.

[0332] The processor 1120 is mainly used to process communication protocols and communication data, control the entire communication device, execute software programs, and process the data of the software programs. The memory 1130 is mainly used to store software programs and data. The transceiver 1110 may include control circuitry and an antenna. The control circuitry is mainly used for converting baseband signals to radio frequency signals and processing radio frequency signals. The antenna is mainly used for transmitting and receiving radio frequency signals in the form of electromagnetic waves. Input / output devices, such as touchscreens, displays, and keyboards, are mainly used to receive user input data and output data to the user.

[0333] When the communication device is powered on, the processor 1120 can read the software program in the memory 1130, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 1120 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit processes the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 1120. The processor 1120 converts the baseband signal into data and processes the data.

[0334] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0335] The communication device shown in the embodiments of this application may also have a higher... Figure 11This application does not limit the use of other components or other related elements. The methods performed by the processor and transceiver shown above are merely examples; the specific steps performed by the processor and transceiver can be found in the methods described above.

[0336] In another possible implementation Figure 10 In the communication device shown, the processing module 1001 can be one or more logic circuits, and the transceiver module 1002 can be an input / output interface, or a communication interface, or an interface circuit, or an interface, etc. Alternatively, the transceiver module 1002 can also be a transmitting module and a receiving module. The transmitting module can be an output interface, and the receiving module can be an input interface. The transmitting module and the receiving module are integrated into one module, such as an input / output interface.

[0337] Figure 12 This is another structural schematic diagram of the communication device provided in the embodiments of this application. For example... Figure 12 As shown, Figure 12 The communication device shown includes logic circuit 1201 and interface 1202. That is, the processing module 1001 can be implemented using logic circuit 1201, and the transceiver module 1002 can be implemented using interface 1202. The logic circuit 1201 can be a chip, processing circuit, integrated circuit, or system-on-chip (SoC) chip, etc., and the interface 1202 can be a communication interface, input / output interface, pins, etc. For example, Figure 12 Taking the aforementioned communication device as an example, the chip includes a logic circuit 1201 and an interface 1202.

[0338] In this embodiment, the logic circuit and the interface can also be coupled to each other. The specific connection method between the logic circuit and the interface is not limited in this embodiment. For example, the logic circuit 1201 can be used to perform... Figure 10 The processing module 1001 shown implements the functions or steps, and the interface 1202 can be used to execute such functions or steps. Figure 10 The transceiver module 1002 shown illustrates the functions or steps implemented by this module. For detailed information on the logic circuit 1201 and interface 1202, please refer to [link / reference needed]. Figure 10 Alternatively, the method embodiments shown above will not be described in detail here.

[0339] The communication device shown in the embodiments of this application can implement the method provided in the embodiments of this application in hardware form, or it can implement the method provided in the embodiments of this application in software form, etc., and the embodiments of this application do not limit it in this way.

[0340] This application also provides a communication system, which includes a first station and a second station, and the first station and the second station can be used to perform the methods in any of the foregoing embodiments.

[0341] In addition, this application also provides a computer program for implementing the operations and / or processes performed by various communication devices in the method provided in this application.

[0342] This application also provides a computer-readable storage medium storing computer code that, when executed on a computer (such as the various communication devices shown above), causes the computer to perform the operations and / or processes performed by the various communication devices in the method provided in this application.

[0343] This application also provides a computer program product, which includes computer code or a computer program that, when run on a computer (such as the various communication devices shown above), causes the operations and / or processes performed by each execution in the method provided in this application to be executed.

[0344] In the embodiments provided in this application, it should be understood that the disclosed systems, communication devices, and methods can be implemented in other ways. For example, the communication device embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, communication devices, or modules, or it may be an electrical, mechanical, or other form of connection.

[0345] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the technical effects of the solutions provided in the embodiments of this application.

[0346] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0347] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. An encoding method characterized by comprising: The method comprises: performing low-density parity-check (LDPC) encoding on information bits according to a check matrix, to obtain encoded bits, the check matrix corresponding to a code rate of 2 / 3, the check matrix corresponding to a code length of 7776, and the check matrix corresponding to an extension factor of 162; outputting the encoded bits.

2. A decoding method, comprising: The method comprises: inputting to-be-decoded information; performing low-density parity-check (LDPC) decoding on the to-be-decoded information according to a check matrix, the check matrix corresponding to a code rate of 2 / 3, the check matrix corresponding to a code length of 7776, and the check matrix corresponding to an extension factor of 162.

3. The method according to claim 1 or 2, characterized in that, The check matrix comprises a sub-matrix, the sub-matrix being a 2-row and 2-column matrix, the sub-matrix comprising two elements greater than or equal to 0, and the two elements satisfying a modulo operation relationship.

4. The method according to any one of claims 1 to 3, characterized in that, The check matrix is any one of the following matrices: or 5. The method according to any one of claims 1 to 4, characterized in that, The check matrix corresponds to a base check matrix, the base check matrix corresponding to a code length of 3888, the base check matrix corresponding to a code rate of 2 / 3, and the base check matrix corresponding to an extension factor of 81.

6. The method of claim 5, wherein, The check matrix corresponds to a base check matrix, and comprises: a first element in the check matrix and a second element in the base check matrix satisfy a modulo operation relationship, the modulo operation relationship satisfying that the first element is the same as the second element or the first element is equal to a sum of the second element and 81; wherein a position of the first element in the check matrix is the same as a position of the second element in the base check matrix, the first element being an element in a matrix corresponding to information bits in the check matrix, the second element being an element in a matrix corresponding to information bits in the base check matrix, and the first element and the second element being greater than or equal to 0.

7. The method according to claim 5 or 6, characterized in that, The check matrix corresponds to a base check matrix, and comprises: a third element in the check matrix is the same as a fourth element in the base check matrix; wherein a position of the third element in the check matrix is the same as a position of the fourth element in the base check matrix, the third element being an element in a matrix corresponding to information bits in the check matrix, the fourth element being an element in a matrix corresponding to information bits in the base check matrix, and the third element and the fourth element being less than 0.

8. The method of claim 5, wherein, The check matrix corresponds to a base check matrix, and comprises: a matrix corresponding to check bits in the check matrix is the same as a matrix corresponding to check bits in the base check matrix.

9. A communications device, characterized by The apparatus comprises a module for performing the method of any one of claims 1-8.

10. A communications device, characterized by The apparatus comprises a processor and a transceiver coupled to cause the communication apparatus to implement the method of any one of claims 1-8.

11. A communications device, characterized by The apparatus comprises a logic circuit and an interface coupled to cause the communication apparatus to implement the method of any one of claims 1-8.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program, which is executed by a communication apparatus to cause the method of any one of claims 1-8 to be implemented.

13. A computer program product, characterised in that, The computer program product, when executed by a computer, causes the method of any of claims 1-8 to be performed.

14. A communication system, characterized by comprising a first station for performing the method of any of claims 1, 3-8 and a second station for performing the method of any of claims 2-8.

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