Dual-polarization reconfigurable photoelectric logic device based on alpha-In2Se3 / WSe2 heterostructure and preparation method thereof
By utilizing the dual-polarized reconfigurable optoelectronic logic device with an α-In2Se3/WSe2 heterostructure and combining source-drain bias voltage and gate voltage, low power consumption and high integration of CMOS logic circuits are achieved. This solves the problems of single function and multi-dimensional control in existing technologies and is suitable for photonic computing chips and logic operation units.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-05
- Publication Date
- 2026-03-17
AI Technical Summary
Existing CMOS logic circuits have high power consumption, existing optoelectronic logic devices have limited functionality and cannot be reconfigured, and traditional ferroelectric heterojunctions lack multi-dimensional control capabilities, making it difficult to meet the requirements of edge computing devices for ultra-low power consumption and high integration.
By employing an α-In2Se3/WSe2 heterostructure, the in-plane and out-of-plane polarization of the two-dimensional material is synergistically controlled through a combination of source/drain bias and gate voltage to form a heterojunction, enabling dynamic switching between photovoltaic and photoconductive modes. The fabrication methods include mechanical exfoliation and physical dry transfer techniques.
It enables dynamic, non-volatile switching between NAND and OR logic functions of the same device, improves the adaptability and integration of hardware circuits, has a photocurrent switching ratio greater than 103, is compatible with low-temperature fabrication processes, and is suitable for photonic computing chips and logic operation units.
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Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, specifically to a dual-polarized reconfigurable optoelectronic logic device based on an α-In2Se3 / WSe2 heterostructure and its fabrication method. Background Technology
[0002] With the rapid development of technologies such as the Internet of Things (IoT) and edge computing, higher demands are being placed on the power consumption, integration, and functional flexibility of data processing hardware. Optoelectronic logic devices, as key units for realizing integrated optoelectronic computing, have become a research focus. However, current optoelectronic logic device technology still faces technological bottlenecks.
[0003] First, optoelectronic logic circuits based on traditional silicon-based CMOS technology have significant inherent limitations. Due to the physical scaling limits of transistors and static power consumption issues, the static power consumption of existing CMOS logic circuits typically reaches the milliwatt level, the operation speed is limited by RC delay, and there are challenges in increasing integration density, making it difficult to meet the urgent needs of edge computing devices for ultra-low power consumption and high integration.
[0004] Secondly, while optoelectronic logic devices based on two-dimensional materials have shown potential in size reduction in recent years, their functional limitation is a prominent issue. These devices can typically only implement a single fixed logic function and require a continuous external power supply, making it impossible to achieve dynamic reconfiguration of logic functions on a single device.
[0005] Furthermore, while traditional ferroelectric heterojunctions exhibit certain non-volatile characteristics in photoelectric modulation, their modulation mechanisms have significant shortcomings. They can only achieve single-dimensional modulation of the photoresponse through out-of-plane polarization, lacking multi-degree-of-freedom coordinated modulation capabilities, which limits the flexibility and diversity of logic function switching. Simultaneously, the fabrication of traditional oxide ferroelectric materials often requires high-temperature processes, which are incompatible with the low-temperature integration processes of two-dimensional material devices, thus restricting their application in novel optoelectronic chips.
[0006] Therefore, we propose a dual-polarized reconfigurable optoelectronic logic device based on the α-In2Se3 / WSe2 heterostructure and its fabrication method to alleviate or solve the above problems.
[0007] The information disclosed above in this background section is only for enhancing the understanding of the background section of this invention, and therefore may include prior art that is not known to those skilled in the art. Summary of the Invention
[0008] To address the aforementioned technical problems, this invention provides a dual-polarized reconfigurable optoelectronic logic device based on an α-In2Se3 / WSe2 heterostructure and its fabrication method, thereby solving one of the problems in the prior art, such as high power consumption of CMOS logic circuits, single function and inability to reconfigure existing optoelectronic logic devices, and lack of multi-dimensional control capabilities in traditional ferroelectric heterojunctions.
[0009] To achieve the above objectives, the present invention provides a dual-polarized reconfigurable optoelectronic logic device, comprising:
[0010] Substrate;
[0011] A gate dielectric layer is disposed on the substrate;
[0012] Two-dimensional WSe2 photosensitive layer;
[0013] A two-dimensional α-In2Se3 ferroelectric layer, wherein the two-dimensional WSe2 photosensitive layer and the two-dimensional α-In2Se3 ferroelectric layer are stacked to form a heterojunction through van der Waals interactions;
[0014] The source and drain electrodes are electrically connected to the heterojunction and are used to apply source and drain bias voltages.
[0015] The gate electrode, used to apply the gate voltage, is located between the substrate and the gate dielectric layer, forming a bottom gate structure;
[0016] The source-drain bias voltage is used to regulate the in-plane ferroelectric polarization state of the two-dimensional α-In2Se3 ferroelectric layer, and the gate voltage is used to regulate its out-of-plane ferroelectric polarization state. By coordinating the combination of the source-drain bias voltage and the gate voltage, the photoelectric response mode of the device can be switched non-volatilely, thereby realizing different Boolean logic functions.
[0017] Preferably, the different Boolean logic functions include NAND logic and OR logic.
[0018] Preferably, the switching of the photoelectric response mode includes switching between photovoltaic mode and light guiding mode;
[0019] When the device is configured to operate in photovoltaic mode, it performs NAND logic functions accordingly.
[0020] When the device is configured to operate in photoconductor mode, it performs the corresponding OR logic function.
[0021] Preferably, in the photovoltaic mode, the threshold for determining the output logic state is 1pA of photocurrent; in the photoconductor mode, the threshold for determining the output logic state is -20nA of photocurrent.
[0022] Preferably, the device follows a polarization-optical response quantitative model: I sc = k1V dp+ k2V gp + I0;
[0023] Where k1 and k2 are response coefficients related to material and interface properties, and I0 is the baseline current.
[0024] Preferably, the photocurrent switching ratio of the device is greater than 10. 3 .
[0025] A method for fabricating a dual-polarized reconfigurable optoelectronic logic device includes the following steps:
[0026] A gate dielectric layer is formed on the substrate;
[0027] Two-dimensional WSe2 and two-dimensional α-In2Se3 sheets were obtained by mechanical exfoliation.
[0028] Using a physical dry transfer technique, the two-dimensional WSe2 sheet and the two-dimensional α-In2Se3 sheet are stacked on the gate dielectric layer to form a van der Waals heterojunction;
[0029] Source and drain electrodes are patterned and fabricated on the heterojunction. The patterning of the source and drain electrodes is performed using electron beam lithography. The electrode material is gold and the thickness is 50 nm.
[0030] A photonic computing chip integrating multiple dual-polarized reconfigurable optoelectronic logic devices as described in any one of claims 1-6.
[0031] A logic operation unit, using a single dual-polarized reconfigurable opto-logic device as described in any one of claims 1-6, achieves the same function as a logic gate circuit composed of multiple complementary metal-oxide-semiconductor transistors by applying different combinations of source-drain bias voltages and gate voltages.
[0032] Compared with the prior art, the beneficial effects of the present invention are:
[0033] This invention utilizes the in-plane and out-of-plane biaxial ferroelectric properties of α-In2Se3 to enable dynamic and non-volatile switching between different Boolean logic functions such as NAND and OR by simply changing the combination of applied source-drain bias voltage and gate voltage. This overcomes the limitation of single-function optoelectronic logic devices made of existing two-dimensional materials and improves the adaptability of hardware circuits.
[0034] This invention achieves independent and coordinated control of the in-plane and out-of-plane degrees of freedom of ferroelectric polarization in a single device, enabling more effective manipulation of the band structure and built-in electric field of the heterojunction, thereby realizing the switching between two different working mechanisms: photovoltaic mode and photoconductive mode.
[0035] In this invention, based on the non-volatile switching of α-In₂Se₃ ferroelectric domains, the device, after being configured for a specific logic function, maintains its functional state even after the control voltage is removed. Furthermore, the device exhibits a performance higher than 10... 3 The photocurrent switching ratio ensures a sufficiently large noise margin between logic states "0" and "1", providing a guarantee for logic operations.
[0036] The mechanical stripping and dry transfer technology used in this invention avoids the high-temperature preparation process required for traditional ferroelectric oxide heterojunctions, and can achieve high-quality van der Waals heterojunction preparation at low temperatures, with better compatibility with mainstream semiconductor processes.
[0037] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the invention will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of the structure of the dual-polarized reconfigurable optoelectronic logic device of the present invention.
[0039] Figure 2 This is a schematic diagram illustrating the polarization-induced band structure modulation of the present invention.
[0040] Figure 3 This is a schematic diagram illustrating the switching of NAND and OR logic output values according to the present invention.
[0041] Figure 4 This is a schematic diagram of the single-device NAND logic gate symbol of the present invention.
[0042] Figure 5 This is a schematic diagram of the CMOS-based NAND logic circuit of the present invention. Detailed Implementation
[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. It should be noted that the drawings are schematic and not illustrated to scale. For clarity and convenience, the relative sizes and proportions of the parts shown in the drawings have been exaggerated or reduced in size. Any size is only illustrative and not limiting.
[0044] Example 1: A dual-polarization reconfigurable optoelectronic logic device based on an α-In2Se3 / WSe2 heterojunction, such as... Figure 1 As shown, it includes:
[0045] Substrate: A heavily doped silicon wafer is used, which also serves as the back gate electrode.
[0046] Gate dielectric layer; a silicon dioxide layer formed on a silicon substrate.
[0047] Heterojunction; formed by stacking a two-dimensional WSe2 photosensitive layer and a two-dimensional α-In2Se3 ferroelectric layer through van der Waals forces.
[0048] Electrodes; gold (Au) electrodes are used as the source and drain electrodes.
[0049] The working principle of this embodiment: This device utilizes the biaxial ferroelectricity of α-In₂Se₃, both in-plane and out-of-plane. Its in-plane polarization is controlled by source-drain bias, and its out-of-plane polarization is controlled by gate voltage. The synergistic effect of these two polarization states allows for non-volatile reconstruction of the heterojunction's band structure, such as... Figure 2 As shown, this allows the device to switch between photovoltaic mode and photoconductive mode, thereby enabling different Boolean logic functions.
[0050] Example 2: A method for fabricating a dual-polarization reconfigurable optoelectronic logic device, comprising the following steps:
[0051] A heavily doped silicon wafer with SiO2 grown on its surface was selected as the starting substrate.
[0052] Thin-layer materials were obtained from bulk WSe2 and α-In2Se3 crystals using a mechanical exfoliation method.
[0053] Stacking is performed using a physical dry transfer technique;
[0054] Transfer the WSe2 sheet to a predetermined location on the target SiO2 / Si substrate;
[0055] Then, the α-In2Se3 sheet was transferred onto the fixed WSe2 layer to form an α-In2Se3 / WSe2 van der Waals heterostructure;
[0056] On the formed heterojunction, the source and drain electrode patterns are defined by electron beam lithography, and gold is deposited as the electrode material with a thickness of 50 nm.
[0057] Implementation 3: Perform optoelectronic testing on the fabricated device. The realization of the logic function depends on the coordinated control of the α-In2Se3 dual polarization. The NAND logic function realizes the photovoltaic mode. Applying the gate voltage sets the out-of-plane polarization of α-In2Se3 to a specific state.
[0058] In this configuration, the device operates in photovoltaic mode, generating a very small short-circuit photocurrent. Input signal definition:
[0059] Input 1 (source-drain bias): +2V is defined as logic "0", and 0V is defined as logic "1".
[0060] Input 2 (gate voltage): -80 V is defined as logic "0", and 0 V is defined as logic "1".
[0061] Output (short-circuit photocurrent): > 1 pA is determined as logic "0", < 1 pA is determined as logic "1".
[0062] The OR logic function implements photoconductive mode, adjusting the gate voltage to set the out-of-plane polarization of α-In2Se3 to another state. In this configuration, the device operates in photoconductive mode, generating a large negative photocurrent. The input signal definitions are the same as in NAND mode.
[0063] Output (short-circuit photocurrent): < -20 nA is determined as logic "1", > -20 nA is determined as logic "0".
[0064] In summary, by changing the combination of gate voltage and source-drain bias, the device can be dynamically reconfigured between the two logic functions mentioned above, such as... Figure 3 The test data is shown.
[0065] Example 4: Performance testing was conducted on the device in this example. The results show that the photocurrent on / off ratio of the device is greater than 10. 3 .
[0066] The short-circuit photocurrent of the device and the modulation voltage follow a quantitative relationship: I sc = k1V dp + k2V gp + I0, the model provides a theoretical basis for the precise design and control of devices.
[0067] like Figure 4 As shown, a single device of this invention can implement the function of a NAND gate. For example... Figure 5 As shown, traditional CMOS processes require multiple transistors to achieve the same function, which demonstrates that the present invention can significantly reduce the number of transistors and improve integration density.
[0068] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0069] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A dual-polarized reconfigurable optoelectronic logic device, characterized in that, Comprising: a substrate; a gate dielectric layer disposed on the substrate; a two-dimensional WSe2 photoactive layer; a two-dimensional α-In2Se3 ferroelectric layer, the two-dimensional WSe2 photoactive layer and the two-dimensional α-In2Se3 ferroelectric layer are stacked by van der Waals interaction to form a heterojunction; a source electrode and a drain electrode electrically connected to the heterojunction for applying a source-drain bias; a gate electrode for applying a gate voltage, located between the substrate and the gate dielectric layer, forming a bottom gate structure; wherein the source-drain bias is used to regulate the in-plane ferroelectric polarization state of the two-dimensional α-In2Se3 ferroelectric layer, and the gate voltage is used to regulate the out-of-plane ferroelectric polarization state thereof; By synergistically regulating the combination of the source-drain bias and the gate voltage, the photoelectric response mode of the device can be non-volatile switched, thereby realizing different Boolean logic functions.
2. The dual-polarization reconfigurable optoelectronic logic device of claim 1, wherein: The different Boolean logic functions include NAND logic and OR logic.
3. The dual-polarization reconfigurable optoelectronic logic device of claim 1, wherein: The switching of the photoelectric response mode includes switching between photovoltaic mode and photoconductive mode; When the device is configured to work in photovoltaic mode, the NAND logic function is executed; When the device is configured to work in photoconductive mode, the OR logic function is executed.
4. The dual-polarized reconfigurable optoelectronic logic device of claim 3, wherein: In the photovoltaic mode, the determination threshold of the output logic state is photocurrent 1pA; in the photoconductive mode, the determination threshold of the output logic state is photocurrent-20nA.
5. The dual-polarization reconfigurable optoelectronic logic device of claim 1, wherein, The device follows a polarization-light response quantitative model: I sc = k1V dp + k2V gp + I0; Wherein, k1 and k2 are response coefficients related to material and interface characteristics, and I0 is the baseline current.
6. The dual-polarization reconfigurable optoelectronic logic device of claim 1, wherein, The opto-current switching ratio of the device is greater than 10 3 .
7. The method of claim 1-6, wherein the method further comprises, Comprising the following steps: forming a gate dielectric layer on the substrate; obtaining two-dimensional WSe2 flakes and two-dimensional α-In2Se3 flakes by mechanical exfoliation method respectively; stacking the two-dimensional WSe2 flakes and the two-dimensional α-In2Se3 flakes on the gate dielectric layer to form a van der Waals heterojunction by physical dry transfer technology; patterning and preparing a source electrode and a drain electrode on the heterojunction, the patterning of the source electrode and the drain electrode is completed by electron beam lithography technology, the electrode material is gold, and the thickness is 50nm.
8. A photonic computing chip, characterized by Integrated with multiple bipolar reconfigurable optoelectronic logic devices as claimed in any one of claims 1-6.
9. A logic operation unit, characterized by comprising: Using a single bipolar reconfigurable optoelectronic logic device as claimed in any one of claims 1-6, the same function as a logic gate circuit composed of multiple complementary metal oxide semiconductor transistors can be realized by applying different combinations of source-drain bias and gate voltage.