Preparation method of LED chip and LED chip

Abstract

The invention discloses a preparation method of an LED chip and the LED chip, and relates to the technical field of light emitting diodes, a stacking structure is firstly formed, the stacking structure comprises a first substrate and an epitaxial lamination layer located on one side of the first substrate, and after mesa etching is carried out on the epitaxial lamination layer, a mesa and a groove are formed in the side, away from the first substrate, of the epitaxial lamination layer; then, n photoresist layers are formed on the side, away from the first substrate, of the epitaxial laminated layer, n is larger than or equal to 2, the n photoresist layers are exposed and developed, each photoresist layer is provided with an opening, the orthographic projection of the opening in the plane where the first substrate is located is located in the orthographic projection of the groove in the plane where the first substrate is located, and n is larger than or equal to 2; the n-layer photoresist layer is provided with a first photoetching pattern at the groove, and deep etching is carried out on the epitaxial lamination layer to form an isolation channel; the edge of the table top is covered by the thickened n photoresist layers, so that the edge of the table top is protected from being over-etched, an insulating layer deposited on the edge of the table top subsequently is smooth, and the reliability of the LED chip is improved.

Description

Technical Field

[0001] This application relates to the field of light-emitting diode technology, and in particular to a method for fabricating an LED chip and the LED chip itself. Background Technology

[0002] With the rapid development of light-emitting diode (LED) technology, LED display and lighting applications have undergone tremendous changes. People's continuous pursuit of display performance such as high resolution, high color gamut, and high color saturation has made Mini RGB backlight and direct-view LED chips a hot topic in research and development. As LED chips become smaller and smaller, the requirements for their reliability are also getting higher and higher.

[0003] In the LED chip fabrication process, the epitaxial stack is typically first etched to form mesa and grooves. Then, deep etching is performed within the grooves formed by the mesa etching to create isolation channels, achieving electrical isolation between different LED chips. Specifically, the deep etching process involves: coating the entire surface with a photoresist layer; creating isolation channel openings within the grooves corresponding to the mesa etching in the photoresist layer; and then deeply etching the exposed epitaxial stack to form the isolation channels.

[0004] However, in existing LED chip fabrication methods, during the deep etching of the isolation channel, the photoresist layer at the mesa edge is easily etched away completely, and further over-etched to the mesa edge, causing abnormal appearance at the mesa edge. This results in an uneven insulating layer deposited in the abnormal area at the mesa edge, which is prone to cracks, leading to reduced reliability of the LED chip. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a method for fabricating an LED chip and an LED chip, which protects the edges of the mesa formed by mesa etching from over-etching during deep etching of isolation channels, thereby improving the reliability of the LED chip.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] In a first aspect, this application provides a method for fabricating an LED chip, comprising:

[0008] A stacked structure is formed, the stacked structure including a first substrate and an epitaxial stack located on one side of the first substrate, the epitaxial stack including a first type semiconductor layer, an active layer and a second type semiconductor layer stacked in a direction away from the first substrate, the side of the epitaxial stack away from the first substrate having a groove, the groove exposing a portion of the first type semiconductor layer;

[0009] n photoresist layers, n≥2, are formed on the side of the epitaxial stack away from the first substrate. The n photoresist layers are exposed and developed so that each photoresist layer has an opening. The orthographic projection of the opening onto the plane of the first substrate is located within the orthographic projection of the groove onto the plane of the first substrate. This results in the n photoresist layers having a first photolithographic pattern at the groove. The first photolithographic pattern exposes a portion of the first type semiconductor layer.

[0010] Using the n-layer photoresist layer with the first photolithographic pattern as a mask, the epitaxial stack is deeply etched to form an isolation channel, which penetrates the epitaxial stack.

[0011] Remove the n photoresist layers.

[0012] Optionally, in the n photoresist layers, along the direction away from the first substrate, the opening of the (i+1)th photoresist layer is located inside the opening of the i-th photoresist layer, 1≤i≤n-1.

[0013] Optionally, the step of forming n photoresist layers on the side of the epitaxial stack opposite to the first substrate, where n ≥ 2, and exposing and developing the n photoresist layers to make each photoresist layer have an opening, includes:

[0014] After each photoresist layer is formed on the side of the epitaxial stack away from the first substrate, the photoresist layer is exposed and developed to give the opening, and then the next photoresist layer is formed so that each photoresist layer has the opening.

[0015] Optionally, in the n-layer photoresist layer, along the direction away from the first substrate, the opening of the (j+1)-th photoresist layer exposes the opening of the j-th photoresist layer, 1≤j≤n-1.

[0016] Optionally, the step of forming n photoresist layers on the side of the epitaxial stack opposite to the first substrate, where n ≥ 2, and exposing and developing the n photoresist layers to make each photoresist layer have an opening, includes:

[0017] On the side of the epitaxial stack away from the first substrate, n photoresist layers are first formed, and along the direction away from the first substrate, the insensitivity of each photoresist layer is sequentially enhanced.

[0018] Along the direction close to the first substrate, n photoresist layers are exposed and developed sequentially, with the exposure time and development time of each photoresist layer increasing sequentially, so that each photoresist layer has the opening.

[0019] Alternatively, along the direction close to the first substrate, the n photoresist layers are exposed and developed once, such that each photoresist layer has the opening.

[0020] Optional, n=2 or 3.

[0021] Optionally, forming the stacked structure includes:

[0022] Provide a second substrate;

[0023] An etching stop layer and the epitaxial stack are sequentially formed on one side of the second substrate. The epitaxial stack includes a second type semiconductor layer, the active layer, and a first type semiconductor layer stacked in a direction away from the second substrate.

[0024] Provide the first substrate, bond the epitaxial stack to the first substrate from the side of the epitaxial stack opposite to the second substrate, and remove the second substrate and the etching stop layer;

[0025] At least the second type semiconductor layer and the active layer are subjected to mesa etching to form the stacked structure.

[0026] Optionally, the method for fabricating the LED chip further includes:

[0027] A first electrode is formed in the groove, and the first electrode is in contact with the first type of semiconductor layer; and a second electrode is formed on the side of the second type of semiconductor layer opposite to the first substrate.

[0028] Optionally, the LED chip includes at least two LED chips; the isolation channel divides the epitaxial stack into at least two sub-epitaxy stacks, with one sub-epitaxy stack corresponding to one LED chip;

[0029] The method for preparing the LED chip further includes:

[0030] An insulating dielectric layer is formed on the entire surface, and the insulating dielectric layer is etched to form a through-hole.

[0031] A bridging metal is prepared on the side of the insulating dielectric layer opposite to the first substrate. One end of the bridging metal is electrically connected to the first electrode of one of the LED chips through a first through-hole, and the other end of the bridging metal is electrically connected to the second electrode of another adjacent LED chip through another first through-hole, so that the adjacent LED chips are connected in series.

[0032] A distributed Bragg reflector dielectric layer is formed on the entire surface, and the distributed Bragg reflector dielectric layer and the insulating dielectric layer are etched to form a through-hole.

[0033] A first pad and a second pad are formed on the side of the distributed Bragg reflector layer away from the first substrate. The first pad is electrically connected to the independent first electrode in the LED chip connected in series through a second via. The second pad is electrically connected to the independent second electrode in the LED chip connected in series through another second via.

[0034] Secondly, this application also provides an LED chip, which is prepared using the method described in any of the above-mentioned methods.

[0035] Compared with existing technologies, the above technical solution has the following advantages:

[0036] The LED chip fabrication method provided in this application first forms a stacked structure, which includes a first substrate and an epitaxial stack located on one side of the first substrate. The epitaxial stack includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer stacked along a direction away from the first substrate. After mesa etching, the epitaxial stack has a mesa and a groove on the side away from the first substrate, with the groove exposing a portion of the first-type semiconductor layer. Then, n photoresist layers, n≥2, are formed on the side of the epitaxial stack away from the first substrate. These n photoresist layers are exposed and developed so that each photoresist layer has an opening, and the orthographic projection of the opening of each photoresist layer onto the plane of the first substrate lies within the orthographic projection of the groove onto the plane of the first substrate. This results in the n photoresist layers having a first photolithographic pattern at the groove, with the first photolithographic pattern exposing a portion of the first-type semiconductor layer. Since the orthographic projection of the opening of each photoresist layer onto the plane of the first substrate lies within the groove... The first photolithographic pattern of the n-layer photoresist layer at the groove is located within the orthogonal projection of the first substrate plane. Therefore, the first photolithographic pattern is also located within the orthogonal projection of the groove on the first substrate plane. In other words, the first photolithographic pattern is located within the groove along the direction perpendicular to the first substrate plane. Furthermore, the opening of the first type semiconductor layer exposed by the first photolithographic pattern is the opening of the isolation channel. Thus, using the n-layer photoresist layer with the first photolithographic pattern as a mask, the epitaxial stack is deeply etched to form the isolation channel. The isolation channel penetrates the epitaxial stack, achieving electrical isolation between different LED chips. At the same time, during the deep etching of the isolation channel, the edge of the mesa and the sidewall of the groove are covered by the thickened n-layer photoresist layer, which can protect the edge of the mesa from over-etching and ensure that the edge of the mesa has a good step morphology, so as to facilitate the smoothing of the insulating layer subsequently deposited on the edge of the mesa and improve the reliability of the LED chip.

[0037] Furthermore, this application uses a thicker photoresist layer covering the edge of the mesa to protect the edge of the mesa from over-etching abnormalities during the deep etching of the isolation channel. As a result, the distance between the sidewall of the groove formed by the mesa etching and the sidewall of the isolation channel formed by the deep etching can be smaller, which is beneficial to increasing the light-emitting area corresponding to the mesa of the LED chip and improving the luminous efficiency of the LED chip. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of a local cross-sectional structure corresponding to the normal mesa etching and isolation channel deep etching during the LED chip fabrication process.

[0040] Figure 2 This is a schematic diagram of a local cross-sectional structure corresponding to the etching anomaly that appeared at the edge of the surface after the isolation channel was deeply etched during the LED chip fabrication process.

[0041] Figure 3 This is a schematic flowchart illustrating a method for fabricating an LED chip according to an embodiment of this application.

[0042] Figure 4 This is a schematic diagram of a partial cross-sectional structure after mesa etching in the method for fabricating an LED chip provided in this application embodiment;

[0043] Figures 5a-5c A partial cross-sectional structural diagram of a deep etching process for an isolation channel in the LED chip fabrication method provided in this application embodiment;

[0044] Figures 6a-6c This is a partial cross-sectional structural diagram of another isolation channel deep etching process step in the LED chip fabrication method provided in the embodiments of this application.

[0045] Figure 7 This is a partial cross-sectional view of the LED chip fabrication method provided in this application embodiment after the isolation channel has been deeply carved.

[0046] Figures 8a-8d This is a partial cross-sectional structural diagram of the process steps corresponding to the formation of the stacked structure in the LED chip fabrication method provided in the embodiments of this application;

[0047] Figure 9A schematic diagram of the photomask pattern etched on the mesa in the LED chip fabrication method provided in this application embodiment;

[0048] Figure 10 This is a schematic diagram of the photomask pattern deeply etched in the isolation channel in the LED chip fabrication method provided in the embodiments of this application;

[0049] Figure 11 These are schematic diagrams of various photomask patterns used in the LED chip fabrication method provided in the embodiments of this application.

[0050] Explanation of reference numerals in the attached figures:

[0051] Stacked structure 100; first substrate 10; epitaxial stack 20; first type semiconductor layer 21; active layer 22; second type semiconductor layer 23; mesa; groove T1; photoresist layer 30; opening K1; first photoresist layers 30A, 30C; second photoresist layers 30B, 30D; first opening K1A; second opening K1B; third opening K1D; fourth opening K1C; second substrate 11; etching stop layer 12; bonding dielectric layer 13; first electrode M1; second electrode M2; insulating dielectric layer PV; first via Q1; bridging metal L1; distributed Bragg reflector dielectric layer DBR; second via Q2; first pad PAD1; second pad PAD2; sub-epitaxy stack 201. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0054] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the accompanying drawings illustrating the device structure may be partially enlarged, not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0055] Figure 1 The diagram shows a partial cross-sectional structure following normal mesa etching and deep etching of isolation channels during the fabrication of an LED chip. Figure 1 As shown, in the LED chip fabrication process, a stacked structure 100 is first formed. The stacked structure 100 includes a first substrate 10 and an epitaxial stack 20 located on one side of the first substrate 10. The epitaxial stack 20 includes a first type semiconductor layer 21, an active layer 22, and a second type semiconductor layer 23 stacked in a direction away from the first substrate 10. The epitaxial stack 20 is etched by mesa etching to form a mesa and a groove T1. The groove T1 penetrates the second type semiconductor layer 23 and the active layer 22, exposing a portion of the first type semiconductor layer 21. Subsequently, a deep etching of the isolation channel ISO is performed in the groove T1 formed by the mesa etching. Specifically, a photoresist layer is coated on the entire surface, and an isolation channel opening is opened in the groove T1 formed by the mesa etching corresponding to the photoresist layer, thereby deeply etching the epitaxial stack 20 exposed by the isolation channel opening to form the isolation channel ISO.

[0056] However, as described in the background section, in existing LED chip fabrication methods, during the deep etching of the isolation channel, the photoresist layer at the mesa edge is easily etched cleanly, and further over-etched to the mesa edge, causing abnormal appearance at the mesa edge. This results in an uneven insulating layer deposited in the abnormal area at the mesa edge, which is prone to cracks, leading to reduced reliability of the LED chip.

[0057] The inventors discovered that this is because, during the photoresist coating for deep etching of the isolation channel, the step-like morphology of the mesa edge makes the photoresist coating at the mesa edge relatively thin. After hard baking, the photoresist at the mesa edge further flows into a smooth, gradually changing small-angle slope morphology, resulting in the photoresist thickness at the mesa edge becoming even thinner. As a result, after deep etching of the isolation channel, it is easy to clean the photoresist at the mesa edge and further etch to the mesa edge, causing abnormal appearance at the mesa edge. Figure 2 This diagram illustrates a local cross-sectional structure corresponding to an over-etching anomaly at the edge of the mesa surface during the LED chip fabrication process, where the isolation channel is deeply etched. The over-etching anomaly region at the edge of the mesa surface is shown in the diagram. Figure 2 As shown in the rectangle with the midpoint line; the insulating layer subsequently deposited in the abnormal area at the edge of the platform will be uneven and prone to cracks, leading to a decrease in the reliability of the LED chip.

[0058] Especially for red LED chips, since the total thickness of the epitaxial stack of red LED chips is relatively large, the depth of the groove T1 formed after the epitaxial stack of red LED chips after mesa etching is relatively deep (generally 3μm-8μm), and the depth of the isolation channel ISO formed after deep etching is even deeper (generally 5μm-13μm). This makes it easy for the isolation channel to be over-etched to the edge of the mesa at the same time during deep etching.

[0059] To solve the above problems, the inventors proposed, as follows: Figure 2 As shown, the minimum distance d between the sidewall of the groove T1 and the sidewall of the isolation channel ISO can be increased, but this will sacrifice the area of ​​the mesa, that is, reduce the light-emitting area of ​​the LED chip, thereby reducing the luminous efficiency of the LED chip.

[0060] In view of this, embodiments of this application provide a method for fabricating an LED chip. Figure 3 The diagram illustrates a flow chart of a method for fabricating an LED chip according to an embodiment of this application. Figure 3 As shown, the method for fabricating this LED chip includes:

[0061] S1: As Figure 4 As shown, a stacked structure 100 is formed. The stacked structure 100 includes a first substrate 10 and an epitaxial stack 20 located on one side of the first substrate 10. The epitaxial stack 20 includes a first type semiconductor layer 21, an active layer 22 and a second type semiconductor layer 23 stacked in a direction away from the first substrate 10. The epitaxial stack 20 has a groove T1 on the side away from the first substrate 10, and the groove T1 exposes a portion of the first type semiconductor layer 21.

[0062] In this process, the epitaxial stack 20 undergoes mesa etching to form a mesa and a groove T1. The groove T1 penetrates the second type semiconductor layer 23 and the active layer 22, exposing the first type semiconductor layer 21.

[0063] Optionally, the groove T1 can penetrate the second type semiconductor layer 23 and the active layer 22, and stop at the surface of the first type semiconductor layer 21 away from the first substrate 10, thereby exposing part of the first type semiconductor layer 21; or, the groove T1 can also penetrate the second type semiconductor layer 23, the active layer 22 and part of the first type semiconductor layer 21, thereby exposing part of the first type semiconductor layer 21.

[0064] S2: As Figure 5b and Figure 6bAs shown, n photoresist layers 30, n≥2, are formed on the side of the epitaxial stack 20 away from the first substrate 10. These n photoresist layers 30 are exposed and developed so that each photoresist layer 30 has an opening K1. The orthographic projection of the opening K1 of each photoresist layer 30 onto the plane of the first substrate 10 is located within the orthographic projection of the groove T1 onto the plane of the first substrate 10. Thus, these n photoresist layers 30 have a first photolithographic pattern W1 at the groove T1. The first photolithographic pattern W1 exposes the first type semiconductor layer 21.

[0065] S3: As Figure 5c and Figure 6c As shown, using an n-layer photoresist layer 30 with a first photolithographic pattern W1 as a mask, the epitaxial stack 20 is deeply etched to form an isolation channel ISO, which penetrates the epitaxial stack 20.

[0066] S4: As Figure 7 As shown, n layers of photoresist 30 are removed.

[0067] It should be noted that this application does not limit the order of coating, exposure and development of the n photoresist layers 30 formed on the side of the epitaxial stack 20 away from the first substrate 10, as long as each photoresist layer 30 has an opening K1, and the orthographic projection of the opening K1 of each photoresist layer 30 onto the plane of the first substrate 10 is located within the orthographic projection of the groove T1 onto the plane of the first substrate 10.

[0068] It is understandable that, such as Figure 5b and Figure 6b As shown, since the orthographic projection of the opening K1 of each photoresist layer 30 onto the plane of the first substrate 10 lies within the orthographic projection of the groove T1 onto the plane of the first substrate 10, the orthographic projection of the first photolithographic pattern W1 of these n photoresist layers 30 at the groove T1 also lies within the orthographic projection of the groove T1 onto the plane of the first substrate 10. In other words, along the direction perpendicular to the plane of the first substrate 10, the first photolithographic pattern W1 lies within the groove T1, and the opening of the exposed portion of the first type semiconductor layer 21 of the first photolithographic pattern W1 is the isolation channel opening. Therefore, as... Figure 5c and Figure 6c As shown, using an n-layer photoresist layer 30 with a first photolithographic pattern W1 as a mask, an isolation channel ISO is formed by deep etching of the epitaxial stack 20. The isolation channel ISO penetrates the epitaxial stack 20 to achieve electrical isolation between different LED chips.

[0069] Meanwhile, since n photoresist layers 30 are formed on the side of the epitaxial stack 20 away from the first substrate 10, the orthographic projection of the opening K1 of each photoresist layer 30 onto the plane of the first substrate 10 lies within the orthographic projection of the groove T1 onto the plane of the first substrate 10. Furthermore, the orthographic projection of the first photolithographic pattern W1 of these n photoresist layers 30 at the groove T1 also lies within the orthographic projection of the groove T1 onto the plane of the first substrate 10. Therefore, during the deep etching of the isolation channel, the edge of the mesa and the sidewall of the groove T1 are covered by the thickened n photoresist layers, thus protecting the edge of the mesa from over-etching. Specifically, after the deep etching of the isolation channel but before removing the photoresist, such as... Figure 5c and Figure 6c As shown, the edges of the mesa and the sidewalls of the groove T1 are still covered with photoresist; after removing the photoresist, as... Figure 7 As shown, the edges of the mesa are not over-etched and have a good step morphology, which facilitates the smoothing of the insulating layer subsequently deposited on the mesa edges and improves the reliability of the LED chip.

[0070] Furthermore, this application uses a thicker photoresist layer covering the edge of the mesa to protect the edge of the mesa from over-etching abnormalities during the deep etching of the isolation channel. As a result, the distance between the sidewall of the groove formed by the mesa etching and the sidewall of the isolation channel formed by the deep etching can be smaller, which is beneficial to increasing the light-emitting area corresponding to the mesa of the LED chip and improving the luminous efficiency of the LED chip.

[0071] Optionally, in some embodiments of this application, such as Figure 5b As shown, in the n-layer photoresist layer 30, along the direction away from the first substrate 10, the opening K1 of the (i+1)th photoresist layer 30 is located within the opening K1 of the ith photoresist layer 30, 1≤i≤n-1; thus, the opening K1 of the nth photoresist layer 30 furthest from the first substrate 10 is the smallest and most inwardly recessed, serving as the isolation channel opening for the exposed portion of the first type semiconductor layer 21. The edge of the mesa and the sidewall of the groove T1 are covered by the thickened n-layer photoresist layer, and the first photolithographic pattern W1 of the n-layer photoresist layer 30 at the groove T1 is an inverted trapezoidal stepped pattern; subsequently, as... Figure 5c As shown, after deep etching of the isolation channel but before removing the photoresist, the edges of the mesa and the sidewalls of the groove T1 are still covered with photoresist. Furthermore, the morphology of the isolation channel ISO formed by deep etching is similar to that of the first lithographic pattern W1, i.e., the isolation channel ISO is approximately inverted trapezoidal, and the inclination angle α of the sidewalls of the isolation channel ISO relative to the horizontal direction is relatively small. After further removal of the photoresist, as... Figure 7 As shown, an isolation channel with a relatively small sidewall inclination angle is obtained, and the edge of the Mesa platform is not over-etched, exhibiting a good step morphology.

[0072] In order to form Figure 5b The first photolithographic pattern W1 shown, optionally, in step S2, forms n photoresist layers 30, n≥2, on the side of the epitaxial stack 20 facing away from the first substrate 10, and exposes and develops the n photoresist layers 30 so that each photoresist layer 30 has an opening K1, including:

[0073] S21: As Figure 5a and Figure 5b As shown, after each photoresist layer 30 is formed on the side of the epitaxial stack 20 away from the first substrate 10, the photoresist layer 30 is exposed and developed so that the photoresist layer 30 has an opening K1, and then the next photoresist layer 30 is formed so that each photoresist layer 30 has an opening K1.

[0074] Taking the formation of two photoresist layers 30 on the side of the epitaxial stack 20 facing away from the first substrate 10, i.e., n=2, as an example. Specifically, let's first... Figure 5a As shown, a first photoresist layer 30A is coated on the side of the epitaxial stack 20 away from the first substrate 10. The first photoresist layer 30A is exposed and developed, so that the first photoresist layer 30A exposes and develops an opening K1 (first opening K1A) in the groove T1; then as... Figure 5b As shown, a second photoresist layer 30B is coated on the side of the first photoresist layer 30A away from the first substrate 10. The second photoresist layer 30B is exposed and developed, so that the second photoresist layer 30B is exposed and developed within the first opening K1A to form an opening K1 (second opening K1B). That is, the opening K1 (first opening K1A) of the first photoresist layer 30A is larger, and the opening K1 (second opening K1B) of the second photoresist layer 30B is smaller than the opening K1 (first opening K1A) of the first photoresist layer 30A. Thus, the coating, exposure and development of two photoresist layers 30 are completed on the side of the epitaxial stack 20 away from the first substrate 10.

[0075] It is understandable that, since the (i+1)th photoresist layer 30 covers the opening K1 of the i-th photoresist layer 30 along the direction away from the first substrate, and the opening K1 of the (i+1)th photoresist layer 30 is exposed and developed within the opening K1 of the i-th photoresist layer 30, the opening K1 of the n-th photoresist layer 30, which is furthest from the first substrate 10, is the smallest and most recessed, serving as the isolation channel opening of the exposed portion of the first type semiconductor layer 21.

[0076] It is also understandable that by using the method of exposing and developing each photoresist layer 30 to form an opening K1, the first photolithographic pattern W1 of the n photoresist layers 30 as a whole at the groove T1 is an inverted trapezoidal stepped pattern, specifically as follows: Figure 5b As shown; subsequently, using the n-layer photoresist layer with the first photolithographic pattern W1 as a mask, the epitaxial stack 20 is deeply etched to form isolation channels ISO, as follows. Figure 5c and Figure 7 As shown, the shape of the isolation channel ISO is similar to that of the first lithographic pattern W1, that is, the isolation channel ISO is approximately inverted trapezoidal, and the inclination angle α of the sidewall of the isolation channel ISO relative to the horizontal direction is relatively small.

[0077] Furthermore, it can be understood that since the opening K1 of the nth photoresist layer 30 furthest from the first substrate 10 is the opening of the isolation channel corresponding to these n photoresist layers 30, that is, the nth photoresist layer 30 is the mask layer for the actual deep etching of the isolation channel, and the other photoresist layers 30 are mainly to protect the edge of the mesa from over-etching, the thickness of the nth photoresist layer 30 can be set to be relatively large, and the thickness of the other photoresist layers 30 can be relatively thin. For example, if n=2, then the thickness of the second photoresist layer 30B can be greater than the thickness of the first photoresist layer 30A.

[0078] It should be noted that when the method of exposing and developing each photoresist layer 30 to form an opening K1 is adopted, each photoresist layer 30 can be the same photoresist layer or different photoresist layers, depending on the specific situation.

[0079] Alternatively, in some embodiments of this application, such as Figure 6b As shown, in the n-layer photoresist layer 30, along the direction away from the first substrate 10, the opening K1 of the (j+1)th photoresist layer 30 exposes the opening K1 of the j-th photoresist layer 30, 1≤j≤n-1; thus, the opening K1 of the first photoresist layer 30 closest to the first substrate 10 is the smallest and most recessed, serving as the isolation channel opening for the exposed portion of the first type semiconductor layer 21. The edge of the mesa and the sidewall of the groove T1 are covered by the thickened n-layer photoresist layer, and the first photolithographic pattern W1 of the n-layer photoresist layer 30 at the groove T1 is an inverted trapezoidal stepped pattern; then as... Figure 6c As shown, after deep etching of the isolation channel but before removing the photoresist, the edges of the mesa and the sidewalls of the groove T1 are still covered with photoresist. Furthermore, the morphology of the isolation channel ISO formed by deep etching is similar to that of the first lithographic pattern W1, i.e., the isolation channel ISO is approximately inverted trapezoidal, and the inclination angle α of the sidewalls of the isolation channel ISO relative to the horizontal direction is relatively small. After further removal of the photoresist, as... Figure 7 As shown, an isolation channel with a relatively small sidewall inclination angle is obtained, and the edge of the Mesa platform is not over-etched, exhibiting a good step morphology.

[0080] In order to form Figure 6bThe first photolithographic pattern W1 shown, optionally, in step S2, forms n photoresist layers 30, n≥2, on the side of the epitaxial stack 20 facing away from the first substrate 10, and exposes and develops the n photoresist layers 30 so that each photoresist layer 30 has an opening K1, including:

[0081] S22: As Figure 6a As shown, n photoresist layers 30 are first formed on the side of the epitaxial stack 20 away from the first substrate 10, and the insensitivity of each photoresist layer 30 is sequentially enhanced along the direction away from the first substrate 10.

[0082] S23: As Figure 6a and Figure 6b As shown, n photoresist layers 30 are exposed and developed sequentially along the direction close to the first substrate 10, and the exposure time of each photoresist layer 30 increases sequentially, and the development time of each photoresist layer 30 increases sequentially, so that each photoresist layer 30 has an opening K1.

[0083] Taking the formation of two photoresist layers 30 on the side of the epitaxial stack 20 facing away from the first substrate 10, i.e., n=2, as an example. Specifically, let's first... Figure 6a As shown, a first photoresist layer 30C and a second photoresist layer 30D are sequentially coated on the side of the epitaxial stack 20 facing away from the first substrate 10. The sensitizing effect of the second photoresist layer 30D is stronger than that of the first photoresist layer 30C. It is understood that photoresist is a photosensitive polymer material that undergoes chemical changes (such as changes in solubility) under specific wavelengths of light. The sensitizing effect of photoresist refers to enhancing its sensitivity to specific wavelengths of light by adding specific chemical substances (sensitizers). The second photoresist layer 30D has stronger insensitivity, making it more sensitive to exposure and development. The portion of the second photoresist layer 30D corresponding to the opening can be developed in a shorter time after exposure and in a shorter development time. The first photoresist layer 30C has weaker insensitivity, making it less sensitive to exposure and development. The portion of the first photoresist layer 30C corresponding to the opening needs to be developed in a longer time after exposure and in a longer development time.

[0084] Then, as Figure 6a As shown, after a short exposure time to the portion corresponding to the opening in the second photoresist layer 30D, development is performed within a short development time, resulting in the second photoresist layer 30D having an opening K1 (the third opening K1D). The orthographic projection of the third opening K1D onto the plane of the first substrate 10 lies within the orthographic projection of the groove T1 onto the plane of the first substrate 10, and the third opening K1D is relatively large; for example... Figure 6bAs shown, after a relatively long exposure time is performed on the portion of the first photoresist layer 30C corresponding to the opening, and then development is performed within a relatively long development time, so that the first photoresist layer 30C has an opening K1 (fourth opening K1C). The orthographic projection of the fourth opening K1C onto the plane of the first substrate 10 is located within the orthographic projection of the third opening K1D onto the plane of the first substrate 10. Thus, the coating, exposure, and development of two photoresist layers 30 are completed on the side of the epitaxial stack 20 away from the first substrate 10.

[0085] It is understandable that, since the opening K1 of the (j+1)th photoresist layer 30 exposes the opening K1 of the jth photoresist layer 30 along the direction away from the first substrate, that is, the opening K1 of the (j+1)th photoresist layer 30 is larger than the opening K1 of the jth photoresist layer 30, the opening K1 of the first photoresist layer 30 closest to the first substrate 10 is the smallest and the most recessed, serving as the isolation channel opening of the exposed portion of the first type semiconductor layer 21.

[0086] It is also understandable that by first forming n photoresist layers 30 with progressively increasing insensitivity along the direction away from the first substrate, and then sequentially exposing and developing the n photoresist layers 30 along the direction closer to the first substrate, the resulting n photoresist layers 30 will also form an inverted trapezoidal stepped pattern W1 at the groove T1. Specifically, as shown... Figure 6b As shown; subsequently, using the n-layer photoresist layer with the first photolithographic pattern W1 as a mask, the epitaxial stack 20 is deeply etched to form isolation channels ISO, as follows. Figure 6c and Figure 7 As shown, the shape of the isolation channel ISO is similar to that of the first lithographic pattern W1, that is, the isolation channel ISO is approximately inverted trapezoidal, and the inclination angle α of the sidewall of the isolation channel ISO relative to the horizontal direction is relatively small.

[0087] Furthermore, it can be understood that since the opening K1 of the first photoresist layer 30 closest to the first substrate 10 is the opening of the isolation channel corresponding to these n photoresist layers 30, that is, the first photoresist layer 30 is the mask layer for the actual deep etching of the isolation channel, and the other photoresist layers 30 are mainly to protect the edge of the mesa from over-etching, the thickness of the first photoresist layer 30 can be set to be relatively large, and the thickness of the other photoresist layers 30 can be relatively thin. For example, if n=2, the thickness of the first photoresist layer 30C can be greater than the thickness of the second photoresist layer 30D.

[0088] It should be noted that when exposing and developing the portion of the (j+1)th photoresist layer 30 corresponding to the opening, a portion of the jth photoresist layer 30 may also be exposed and developed. However, since the insensitivity of the jth photoresist layer 30 is poor, the impact on the jth photoresist layer 30 is minimal.

[0089] Furthermore, in step S22, when n photoresist layers 30 are first formed on the side of the epitaxial stack 20 away from the first substrate 10, considering that the insensitivity of each photoresist layer 30 increases sequentially along the direction away from the first substrate 10, step S23 can also be replaced by:

[0090] S24: Along the direction close to the first substrate 10, n photoresist layers 30 are exposed and developed once, so that each photoresist layer 30 has an opening K1.

[0091] In other words, if the n photoresist layers 30, whose inductance increases sequentially along the direction away from the first substrate, are exposed for a sufficient time and developed for a sufficient time, then along the direction closer to the first substrate, the opening K1 of each photoresist layer 30 decreases sequentially. That is, the opening K1 of the (j+1)th photoresist layer 30 exposes the opening K1 of the jth photoresist layer 30. However, the first photolithographic pattern W1 formed by the n photoresist layers 30 as a whole at the groove T1 may not be as good as... Figure 6b The regularity shown leads to variations in the sidewall shape of the isolation channel ISO.

[0092] Alternatively, in some embodiments of this application, after forming n photoresist layers 30 on the side of the epitaxial stack 20 away from the first substrate 10 (without considering the difference in insensitivity), the n photoresist layers can be directly exposed and developed once, so that each photoresist layer 30 has an opening K1, thereby making the n photoresist layers 30 have a first photolithographic pattern W1 of the exposed portion of the first type semiconductor layer 21 at the groove, and the orthographic projection of the opening K1 of each photoresist layer 30 and the first photolithographic pattern W1 on the plane where the first substrate 10 is located is located within the orthographic projection of the groove T1 on the plane where the first substrate 10 is located. In this way, when performing deep etching of the isolation channel, the edge of the mesa can be protected by a thicker photoresist, so that the edge of the mesa is not over-etched. However, due to the increased thickness of the n-layer photoresist layer 30, and the limitations of the exposure and development process, after the n-layer photoresist layer 30 undergoes one exposure and one development, the sidewall of the first photolithographic pattern W1 formed at the groove T1 will have a larger angle relative to the horizontal direction, which in turn makes the sidewall of the isolation channel ISO have a larger angle a relative to the horizontal direction.

[0093] In many cases, it is required that the angle α of the sidewall of the isolation channel ISO relative to the horizontal direction be relatively small. For example, red LED chips enable LED displays to have a higher color rendering index, a wider color gamut, and better color reproduction. To match a certain driver power supply design, red high-voltage LED chips are made by connecting two or more LED chips in series to form a multi-cell chip. This requires bridging metal to cross the groove T1 and the isolation channel ISO to connect adjacent LED chips. Therefore, the angle α of the sidewall of the isolation channel ISO relative to the horizontal direction must be small, and the angle of the sidewall of the groove T1 relative to the horizontal direction must also be small, preferably controlled within 50°, to achieve good coverage of the bridging metal on the stepped channel formed by the groove T1 and the isolation channel ISO, ensuring the high reliability of the bridging metal in the red high-voltage LED chip.

[0094] The method described above, which involves forming n photoresist layers 30 on the side of the epitaxial stack 20 away from the first substrate 10 (ignoring differences in insensitivity), and then directly exposing and developing the n photoresist layers once, so that each photoresist layer 30 has an opening K1, thereby creating a first photolithographic pattern W1 of the first type semiconductor layer 21 exposed at the groove, can prevent over-etching of the edges of the mesa, but may not meet the requirement that the angle α of the sidewall of the isolation channel ISO is relatively small relative to the horizontal direction. Figures 5a-5c as well as Figures 6a-6c The method shown can simultaneously satisfy the requirements that the edge of the mesa is not over-etched and that the sidewall of the isolation channel ISO has a smaller angle α relative to the horizontal direction.

[0095] In the above embodiments, n can be any positive integer greater than or equal to 2. Preferably, n=2 or 3, and more preferably, n=2. This is because there is an overlay error between two adjacent photoresist layers. Sufficient overlay spacing needs to be left between two adjacent photoresist layers to ensure the process window. The more photoresist layers used, the more necessary it is to appropriately increase the minimum distance between the sidewall of the groove T1 and the sidewall of the isolation channel ISO in order to achieve the goal that the orthographic projection of the opening K1 of each photoresist layer 30 on the plane of the first substrate is located within the orthographic projection of the groove T1 on the plane of the first substrate, and that the first lithographic image W1 formed by the n photoresist layers 30 as a whole on the groove T1 is an inverted trapezoidal step pattern. This sacrifices a portion of the light-emitting area of ​​the mesa.

[0096] Based on any of the above embodiments, optionally, in some embodiments of this application, step S1 forming the stacked structure 100 includes:

[0097] S11: As Figure 8a As shown, a second substrate 11 is provided.

[0098] Optionally, the second substrate 11 is a GaAs substrate.

[0099] S12: As Figure 8a As shown, an etching stop layer 12 and an epitaxial stack 20 are sequentially formed on one side of the second substrate 11. The epitaxial stack 20 includes a second type semiconductor layer 23, an active layer 22 and a first type semiconductor layer 21 stacked in a direction away from the second substrate 11.

[0100] S13: As Figures 8b-8d As shown, a first substrate 10 is provided, and the epitaxial stack 20 is bonded to the first substrate 10 from the side of the epitaxial stack 20 away from the second substrate 11, and the second substrate 11 and the etch stop layer 12 are removed.

[0101] Specifically, a bonding dielectric layer 13 is first deposited on the side of the epitaxial stack 20 away from the second substrate 11. The bonding dielectric layer 13 can be a dielectric film such as SiO2 or Si3N4, and the thickness range can be 1μm-20μm.

[0102] Then, as Figure 8b As shown, the epitaxial stack 20 and the first substrate 10 are bonded together at a certain temperature and pressure from the side of the epitaxial stack 20 away from the second substrate 11. The first substrate 10 can be a substrate such as sapphire or silicon carbide.

[0103] After that, as Figure 8c As shown, the second substrate 11 is removed by wet etching. Since the etching stop layer 12 in the epitaxial structure can prevent the etching solution from continuing to etch the epitaxial stack 20 below, the epitaxial stack 20 below the etching stop layer 12 is not affected.

[0104] Next, as Figure 8d As shown, the corrosion stop layer 12 is then removed by wet etching.

[0105] S14: As Figure 4 As shown, at least the second type semiconductor layer 23 and the active layer 22 are subjected to mesa etching to form a stacked structure 100.

[0106] Specifically, a photoresist layer is formed on the side of the epitaxial stack 20 opposite to the first substrate 10, and this photoresist layer is exposed and developed to create a mesa etched pattern, thereby performing mesa etching on the epitaxial stack 20. For better understanding, Figure 9 The image shows the photomask pattern etched on the mesa in the LED chip fabrication method provided in this application embodiment. The diagonal stripe area is an opaque area, corresponding to the mesa formed by the mesa etching, and the blank area is a transparent area, corresponding to the groove T1 formed by the mesa etching.

[0107] Accordingly, Figure 10The image shows a photomask pattern for deep etching of isolation channels in the LED chip fabrication method provided in this application embodiment. The grid area is an opaque area, corresponding to the part that is not deeply etched, and the blank area is a transparent area, corresponding to the part that is deeply etched to form the isolation channel ISO.

[0108] Figure 11 The illustrations show various photomask patterns used in the LED chip fabrication method provided in this application embodiment, wherein the corresponding LED chip portions are labeled. (Refer to...) Figure 11 As shown, after the isolation channel deep etching is completed, the LED chip fabrication method provided in this application embodiment may further include:

[0109] S5: A first electrode M1 is formed in the groove T1, and the first electrode M1 is in contact with the first type semiconductor layer 21; and a second electrode M2 ​​is formed on the side of the second type semiconductor layer 23 away from the first substrate 10.

[0110] Specifically, a first electrode M1 is prepared on the surface of the first semiconductor layer 21 exposed in the groove T1 by metal evaporation and metal stripping processes, and an ohmic contact is formed between the first semiconductor layer 21 and the first electrode M1 by metal fusion process. The fusion temperature is generally 300℃-600℃ and the fusion time is 10min-60min.

[0111] Similarly, a second electrode M2 ​​is prepared on the surface of the second type semiconductor layer 23 away from the first substrate 10 by metal evaporation and metal stripping processes, and an ohmic contact is formed between the second type semiconductor layer 23 and the second electrode M2 ​​by metal fusion process. The fusion temperature is generally 200℃-500℃ and the fusion time is 2min-30min.

[0112] Further optional, in some embodiments of this application, reference is made to Figure 7 and Figure 11 As shown, an LED chip may include at least two LED chips; the isolation channel ISO divides the epitaxial stack 20 into at least two sub-epitaxy stacks 201, with one sub-epitaxy stack 201 corresponding to one LED chip; the method for fabricating the LED chip provided in this application embodiment may further include:

[0113] S6: Form an insulating dielectric layer PV across the entire surface, and etch the insulating dielectric layer PV to form a through-hole Q1.

[0114] S7: A bridging metal L1 is prepared on the side of the insulating dielectric layer PV away from the first substrate 10. One end of the bridging metal L1 is electrically connected to the first electrode M1 of an LED chip through a first through hole Q1, and the other end of the bridging metal L1 is electrically connected to the second electrode M2 ​​of another adjacent LED chip through another first through hole Q1, so that the adjacent LED chips are connected in series.

[0115] S8: The distributed Bragg reflector dielectric layer DBR is formed on the entire surface, and the distributed Bragg reflector dielectric layer DBR and the insulating dielectric layer PV are etched to form a through-hole Q2.

[0116] S9: A first pad PAD1 and a second pad PAD2 are formed on the side of the distributed Bragg reflector layer DBR away from the first substrate 10. The first pad PAD1 is electrically connected to the independent first electrode M1 in the LED chip connected in series through a second through hole Q2. The second pad PAD2 is electrically connected to the independent second electrode M2 ​​in the LED chip connected in series through another second through hole Q2.

[0117] Thus, an LED chip with at least two LED chips connected in series can be obtained. The LED chip emits light from one side of the first substrate 10. The distributed Bragg reflector layer (DBR) can reflect the light emitted by the active layer 22 that is directed away from the first substrate 10 toward the side of the first substrate 10.

[0118] Accordingly, this application also provides an LED chip, which is prepared using the method provided in any of the above embodiments. This LED chip can be a red high-voltage LED chip. The specific structure of this LED chip can be referred to in the foregoing embodiments, and will not be repeated here.

[0119] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0120] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of fabricating an LED chip, characterized by, The application comprises: forming a stack structure, the stack structure comprising a first substrate and an epitaxial stack located on one side of the first substrate, the epitaxial stack comprising a first-type semiconductor layer, an active layer and a second-type semiconductor layer stacked in a direction away from the first substrate, the epitaxial stack having a groove on the side thereof away from the first substrate, the groove exposing part of the first-type semiconductor layer; forming n layers of photoresist on the side of the epitaxial stack away from the first substrate, n≥2, and exposing and developing the n layers of photoresist so that each layer of the photoresist has an opening, the orthogonal projection of the opening on the plane of the first substrate being located within the orthogonal projection of the groove on the plane of the first substrate, so that the n layers of photoresist have a first photoetching pattern at the groove, the first photoetching pattern exposing part of the first-type semiconductor layer; using the n layers of photoresist having the first photoetching pattern as a mask, performing deep etching on the epitaxial stack to form an isolation channel, the isolation channel penetrating the epitaxial stack; removing the n layers of photoresist.

2. The method of claim 1, wherein the LED chip is prepared by a method comprising: In the n layers of photoresist, the opening of the i+1th layer of photoresist is located within the opening of the ith layer of photoresist in the direction away from the first substrate, 1≤i≤n-1.

3. The method of claim 2, wherein the LED chip is prepared by a method comprising: The forming of the n layers of photoresist on the side of the epitaxial stack away from the first substrate, n≥2, and the exposing and developing of the n layers of photoresist so that each layer of the photoresist has an opening, comprises: after forming each layer of the photoresist on the side of the epitaxial stack away from the first substrate, exposing and developing the layer of photoresist so that the layer of photoresist has the opening, and then forming the next layer of photoresist so that each layer of the photoresist has the opening.

4. The method of claim 1, wherein the LED chip is prepared by a method comprising: In the n layers of photoresist, the opening of the j+1th layer of photoresist exposes the opening of the jth layer of photoresist in the direction away from the first substrate, 1≤j≤n-1.

5. The method of claim 4, wherein the LED chip is prepared by a method comprising: The forming of the n layers of photoresist on the side of the epitaxial stack away from the first substrate, n≥2, and the exposing and developing of the n layers of photoresist so that each layer of the photoresist has an opening, comprises: n layers of photoresist are first formed on the side of the epitaxial stack away from the first substrate, and the photosensitivity of each layer of the photoresist is sequentially enhanced in the direction away from the first substrate; n layers of photoresist are sequentially exposed and developed in the direction approaching the first substrate, and the exposure time of each layer of the photoresist is sequentially increased, and the developing time of each layer of the photoresist is sequentially increased, so that each layer of the photoresist has the opening; or, n layers of photoresist are exposed and developed once in the direction approaching the first substrate, so that each layer of the photoresist has the opening.

6. The method of claim 1-5, wherein, n=2 or 3.

7. The method of claim 1-5, wherein The forming of the stack structure comprises: providing a second substrate; forming an etching stop layer and the epitaxial stack in sequence on the side of the second substrate, the epitaxial stack comprising the second-type semiconductor layer, the active layer and the first-type semiconductor layer stacked in a direction away from the second substrate; providing the first substrate, bonding the epitaxial stack to the first substrate from the side of the epitaxial stack away from the second substrate, and removing the second substrate and the etching stop layer; at least mesa etching the second-type semiconductor layer and the active layer to form the stacked structure.

8. The method of claim 1-5, wherein, The method for preparing the LED chip further comprises: forming a first electrode in the recess, the first electrode being in contact with the first-type semiconductor layer, and forming a second electrode on the side of the second-type semiconductor layer away from the first substrate.

9. The method for preparing an LED chip according to claim 8, characterized in that, The LED chip comprises at least two LED chiplets, and the isolation channel separates the epitaxial stack into at least two sub-epitaxial stacks, one of the sub-epitaxial stacks corresponding to one of the LED chiplets. The method for preparing the LED chip further comprises: forming an insulating medium layer on the whole surface and etching the insulating medium layer to form a first through hole; forming a bridging metal on the side of the insulating medium layer away from the first substrate, one end of the bridging metal being electrically connected to the first electrode of one of the LED chiplets through the first through hole, and the other end of the bridging metal being electrically connected to the second electrode of another adjacent LED chiplet through another first through hole, so that the adjacent LED chiplets are connected in series; forming a distributed Bragg reflection medium layer on the whole surface and etching the distributed Bragg reflection medium layer and the insulating medium layer to form a second through hole; forming a first pad and a second pad on the side of the distributed Bragg reflection medium layer away from the first substrate, the first pad being electrically connected to the first electrode of an independent LED chiplet in series connection through the second through hole, and the second pad being electrically connected to the second electrode of an independent LED chiplet in series connection through another second through hole.

10. An LED chip, characterized by The LED chip is prepared by the method of any one of claims 1-9. The LED chip is prepared by the method of any one of claims 1-9.

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