Write-time memory fault processing method and device, terminal and storage medium

Abstract

This invention discloses a method, apparatus, terminal, and storage medium for handling write-time memory faults, belonging to the field of memory. The method includes: when executing a memory unrepairable fault handling method, determining whether it is a memory synchronization fault; if it is a memory synchronization fault, obtaining the context register information of the interrupted process and obtaining the value of the program counter; determining the address of the interrupted instruction; based on the interrupted instruction address, reading the binary code corresponding to the interrupted instruction and parsing the opcode in the binary code; determining whether the currently interrupted process is in a write operation phase based on the opcode parsing result; if it is in a write operation phase, determining that a write-time memory fault has occurred; when using anonymous mapping, allocating a new physical page frame and replacing the original faulty physical page frame with the new physical page frame; identifying all page table entries involved in the original faulty physical page frame; and replacing the original information in all page table entries with the new physical page frame information.

Description

Technical Field

[0001] This invention relates to the field of memory fault technology, and in particular to a method, apparatus, terminal, and storage medium for handling write-time memory faults. Background Technology

[0002] Memory failures are among the most common and impactful error types in modern servers. To address this challenge, the industry has designed highly complex RAS (Reliability, Availability, and Serviceability) systems. The implementation of a RAS system requires collaboration across hardware, firmware, a unified and extensible firmware interface, and various layers of the operating system. At the hardware and firmware levels, the RAS system first performs a preliminary classification based on the characteristics of the failures, providing a coarse-grained processing framework for the hardware. This allows the operating system to intervene at a higher level, enabling more detailed and precise classification and handling of failures based on its own management mechanisms.

[0003] In existing technologies, to address memory failures and meet the aforementioned RAS (Recovery and Sustainability) principles, methods such as unmapping and terminating processes are typically employed to prevent processes from accessing corrupted faulty data and to avoid the spread of faulty data within the system, which could cause wider contamination.

[0004] In the process of realizing this invention, the inventors discovered the following technical problem: when a process encounters a memory failure while performing a write operation, the data to be written may not have been persisted to the storage medium. The traditional approach of terminating the process indiscriminately is an overly aggressive processing strategy. Directly terminating the process will result in the permanent loss of this part of the data, which cannot meet the data integrity requirements. Summary of the Invention

[0005] This invention provides a method, apparatus, terminal, and storage medium for handling write-time memory faults, in order to solve the technical problem that existing solutions for memory faults cannot meet data integrity requirements.

[0006] In a first aspect, embodiments of the present invention provide a method for handling write-time memory faults, including:

[0007] When executing the memory failure repair handling method, determine whether it is a memory synchronization failure;

[0008] In the event of a memory synchronization failure, the context register information of the interrupted process is obtained, and the value of the program counter is obtained from the context register information.

[0009] The address of the interrupted instruction is determined using the value of the program counter. Based on the obtained address of the interrupted instruction, the binary code corresponding to the interrupted instruction is read, and the opcode in the binary code is parsed.

[0010] Based on the result of parsing the opcode, determine whether the currently interrupted process is in the write operation phase. If it is in the write operation phase, determine that a write-time memory failure has occurred.

[0011] Use the interrupt context to obtain the last-level page table entry, and determine whether it is an anonymous mapping based on the last-level page table entry;

[0012] When mapping anonymously, a new physical page frame is allocated, and the original faulty physical page frame is replaced with the new physical page frame.

[0013] The last-level page table entry is used to determine all page table entries involved in the original faulty physical page frame;

[0014] Replace the original faulty physical page frame information in all page table entries with new physical page frame information.

[0015] Furthermore, the allocation of a new physical page frame, and the replacement of the original faulty physical page frame with the new physical page frame, includes:

[0016] Delete the original faulty physical page frame and exit the write-time memory fault exception handling task;

[0017] A page fault is triggered using the memory management unit, and a new physical page frame is allocated.

[0018] The new physical page frame information is written into the page table entry used by the process corresponding to the memory fault to replace the faulty page information.

[0019] Furthermore, the step of using the last-level page table entry to determine all page table entries involved in the original faulty physical page frame includes:

[0020] When a page fault is triggered by one of the associated processes in the faulty physical page frame, the new physical page frame information is associated in the page table entry used by the associated process based on the page fault triggered by the associated process.

[0021] Furthermore, the allocation of a new physical page frame, the replacement of the original faulty physical page frame with the new physical page frame, and the determination of all page table entries related to the original faulty physical page frame using the last-level page table entries; and the replacement of the original faulty physical page frame information in all page table entries with the new physical page frame information, including:

[0022] Allocate a new physical page frame;

[0023] Obtain the virtual address obtained during the write-time memory fault exception handling task, and find all page table entries associated with the faulty physical page frame based on the virtual address, wherein each page table entry corresponds to a process that shares the physical page frame;

[0024] Modify the atomic physical page frame field in all page table entries to the new physical page frame information.

[0025] Furthermore, the method also includes:

[0026] Exit from the memory fault exception handling task and return to the context of the process corresponding to the write-time memory fault. When accessing the virtual address using the memory management unit, the new physical page frame information is obtained, and the exception is no longer triggered.

[0027] The interrupted write operation instruction was successfully executed to write data to a healthy physical memory address, ensuring that other processes sharing the healthy physical memory address do not experience page faults or page errors.

[0028] Furthermore, the method also includes:

[0029] The memory page management structure corresponding to the faulty physical page is marked as poisoned to permanently isolate the faulty physical page in the system's memory allocation and management mechanism.

[0030] Furthermore, the step of obtaining the last-level page table entry using the interrupt context includes:

[0031] The interrupted process is determined based on the interruption context, the physical page frame number used is determined based on the interrupted process, and the page management structure corresponding to the physical page frame number is obtained.

[0032] The virtual page address corresponding to the physical page is obtained by using the preset structure field information in the page management structure;

[0033] The last-level page table entry is obtained based on the virtual page address and the base address of the process's virtual memory page table.

[0034] Secondly, embodiments of the present invention also provide a write-time memory fault handling apparatus, comprising:

[0035] The judgment module is used to determine whether the memory synchronization failure is the cause when the memory cannot be repaired fault handling method is executed.

[0036] The acquisition module is used to acquire the context register information of the interrupted process when a memory synchronization failure occurs, and to acquire the value of the program counter from the context register information;

[0037] The parsing module is used to determine the address of the interrupted instruction using the value of the program counter, read the binary code corresponding to the interrupted instruction based on the obtained address of the interrupted instruction, and parse the opcode in the binary code.

[0038] The write operation phase determination module is used to determine whether the currently interrupted process is in the write operation phase based on the parsing result of the opcode. If it is in the write operation phase, it determines that a write-time memory failure has occurred.

[0039] An anonymous mapping determination module is used to obtain the last-level page table entry using the interrupt context, and determine whether it is an anonymous mapping based on the last-level page table entry.

[0040] The first replacement module is used to allocate a new physical page frame when mapping anonymously, and replace the original faulty physical page frame with the new physical page frame.

[0041] The page table entry determination module is used to determine all page table entries involved in the original faulty physical page frame using the last-level page table entries.

[0042] The second replacement module is used to replace the original faulty physical page frame information in all page table entries with new physical page frame information.

[0043] Thirdly, embodiments of the present invention also provide a terminal, including:

[0044] One or more processors;

[0045] Storage device for storing one or more programs.

[0046] When the one or more programs are executed by the one or more processors, the one or more processors implement the write-time memory fault handling method as described in any of the above embodiments.

[0047] Fourthly, embodiments of the present invention also provide a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform the write-time memory fault handling method provided in the above embodiments.

[0048] The write-time memory fault handling method, apparatus, terminal, and storage medium provided in this invention, when executing a memory unrepairable fault handling method, determines whether it is a memory synchronization fault; when it is a memory synchronization fault, obtains the context register information of the interrupted process and obtains the value of the program counter from the context register information; uses the value of the program counter to determine the address of the interrupted instruction, reads the binary code corresponding to the interrupted instruction based on the obtained address of the interrupted instruction, and parses the opcode in the binary code; determines whether the currently interrupted process is in the write operation stage based on the parsing result of the opcode, and if it is in the write operation stage, determines that a write-time memory fault has occurred; uses the interrupt context to obtain the last-level page table entry, and determines whether it is an anonymous mapping based on the last-level page table entry; when it is an anonymous mapping, allocates a new physical page frame, and uses the new physical page frame to replace the original faulty physical page frame; uses the last-level page table entry to determine all page table entries involved in the original faulty physical page frame; and replaces the original faulty physical page frame information in all page table entries with the new physical page frame information. When a memory failure occurs, it can determine whether it is a synchronous failure and further determine whether the memory failure occurred during a write operation. If it is determined to be during a write operation, it is further determined whether it is an anonymous mapping. If it is an anonymous mapping, a new physical page frame is created. Due to the unrecoverable data characteristics of anonymous mapping, the physical page is directly replaced, and all associated page table entries are updated, achieving complete isolation of the failed page. The originally corrupted data is no longer referenced, and the new physical page ensures the success of the write operation. It can prevent data loss and process termination, allowing the system to continue execution without being aware of the failure. It can achieve seamless repair of memory write failures while ensuring data write integrity. Attached Figure Description

[0049] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0050] Figure 1 This is a flowchart illustrating the write-time memory fault handling method provided in Embodiment 1 of the present invention;

[0051] Figure 2 This is a flowchart illustrating the write-time memory fault handling method provided in Embodiment 2 of the present invention;

[0052] Figure 3 This is a schematic diagram of the write-time memory fault handling device provided in Embodiment 3 of the present invention;

[0053] Figure 4 This is a schematic diagram of the terminal provided in Embodiment 4 of the present invention. Detailed Implementation

[0054] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0055] Example 1

[0056] Figure 1 This is a flowchart illustrating the write-time memory fault handling method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where a write-time memory fault occurs. The method can be executed by a write-time memory fault handling device and specifically includes the following steps:

[0057] Step 110: When executing the memory failure repair method, determine whether it is a memory synchronization failure. If it is a memory synchronization failure, obtain the context register information of the interrupted process and obtain the value of the program counter from the context register information.

[0058] Operating systems, adhering to the design principles of reliability, availability, and maintainability, have already undertaken the task of hierarchical management of hardware-reported memory faults. The above has become an industry-recognized standard specification, particularly the mature implementations of RAS mechanisms by processor manufacturers such as Intel. These solutions are universally applicable and widely adopted as design specifications. Therefore, this embodiment and subsequent optimizations aim to achieve lossless write-time memory fault handling while meeting the aforementioned specifications.

[0059] For example, when memory failures occur, such as hard failures like damaged memory chips or soft failures like those caused by cosmic rays, existing technologies implement extensive error detection functions in multiple internal modules of the processor to ensure that the processor reaches the target reliability level. Therefore, various existing mechanisms can be used to identify the existence of a memory failure and attempt to repair it. The above process can serve as a method for handling memory failures that cannot be repaired. When the system executes this method, it determines whether the failure is a memory synchronization failure. For example, synchronization failures are directly detected by components on the CPU, such as the Instruction Fetch Unit (IFU) or Data Cache Unit (DCU), while asynchronous failures are generally detected by components on the Memory Controller (MC). For example, memory access operations initiated by system tasks exist in memory as read / write instructions, and the data pointed to by the target address also exists in memory. During the CPU's pipeline operations of address fetching, decoding, and execution, instruction fetching and data read / write operations occur. Memory faults occurring during this process are synchronous faults. Unlike CPU-initiated memory access operations, asynchronous faults refer to faults caused by configuring the memory controller hardware during memory inspection to directly initiate memory access operations. For instance, detection components can be used to determine whether a fault is synchronous. For example, memory faults detected using IFU and DCU can be identified as synchronous faults, and the corresponding fault level and physical page frame can be registered in the Machine Check Architecture (MCA) registers.

[0060] Because the fault level is uncorrectable, the MCA triggers a Machine Check Exception Error (MCEERR) synchronization exception and sends it to the CPU. This process interrupts the process performing a write operation, the system enters an interrupt context environment, obtains the context register information of the interrupted process, and then looks up the program counter value in the context register. For example, determining whether the fault handling mode is firmware-first or kernel-local-first will determine how the process context is obtained. If firmware-first, the context information filled with firmware needs to be parsed from the hardware error source table conforming to the APEI specification; if kernel-local-first, it is directly parsed from the structpt_regs structure in the interrupt entry point.

[0061] Step 120: Determine the address of the interrupted instruction using the value of the program counter; based on the obtained address of the interrupted instruction, read the binary code corresponding to the interrupted instruction and parse the opcode in the binary code; determine whether the currently interrupted process is in the write operation stage based on the parsing result of the opcode; if it is in the write operation stage, determine that a write-time memory failure has occurred.

[0062] For example, the specific address of the interrupted instruction can be determined based on the program counter value. Based on the obtained address of the interrupted instruction, the corresponding binary code is read, and the opcode within the code is parsed. By determining whether the parsed opcode belongs to the store instruction category, it can be determined whether the currently interrupted process is in the write operation phase. By parsing the program counter (PC) to obtain the instruction address and then parsing the instruction binary code (Opcode), it is possible to accurately identify whether the current process is in the write operation phase. This avoids false positives; fault tolerance is only triggered when the CPU is actually performing a write operation, ensuring that the system does not unnecessarily interfere with read operations or non-critical instructions.

[0063] Step 130: Obtain the last-level page table entry using the interrupt context, and determine whether it is an anonymous mapping based on the last-level page table entry.

[0064] Memory mapping methods are mainly divided into file mapping and anonymous mapping. Anonymous mapping, such as the process's heap and stack, is private memory and cannot be directly restored from the disk. For example, one can start by examining the virtual memory region VMA pointed to by the last-level page table entry PTE: by checking the vm_file pointer of the VMA, if it is an anonymous mapping, the pointer vma->vm_file == NULL, that is, if it is a null value, then it can be determined to be an anonymous mapping.

[0065] Step 140: When mapping for anonymity, allocate a new physical page frame and replace the original faulty physical page frame with the new physical page frame.

[0066] For example, a page table entry consists of a physical page frame number (PFN) and a page operation attribute, where the PFN currently corresponds to a faulty page frame. Accordingly, the frame number of the currently faulty page frame needs to be replaced with the frame number of a newly allocated physical page frame, so that accessing the virtual memory address no longer maps to the faulty page frame.

[0067] In this embodiment, the process may include: deleting the existing faulty physical page frame and exiting the write-time memory fault handling task; triggering a page fault using the memory management unit and allocating a new physical page frame; and writing the new physical page frame information to replace the faulty page information in the page table entry used by the process corresponding to the memory fault. Using this method, the faulty physical page frame can be deleted, allowing the process to jump to the normal write-time memory fault handling task, which then triggers a page fault using the memory management unit and allocates a new physical page frame. This method conforms to the RAS (Real-Time Memory Fault) rule-compliant memory fault handling mechanism, and the new physical page frame information can be written to the page table entry used by the process corresponding to the memory fault to replace the faulty page information.

[0068] Step 150: Use the last-level page table entry to determine all page table entries involved in the original faulty physical page frame, and replace the original faulty physical page frame information in all page table entries with new physical page frame information.

[0069] Since multiple processes may use the same physical page frame information, the above method can only resolve errors caused by the process currently causing the fault using the physical page frame, but it cannot resolve errors caused by other processes using the same physical page frame. Therefore, in this embodiment, it is also necessary to replace the information of the physical page frame in other page table entries.

[0070] For example, determining all page table entries involved in the original faulty physical page frame using the page table entries may include: when one of the associated processes in the faulty physical page frame triggers a page fault, as the page fault is triggered by the associated process, the new physical page frame information is associated in the page table entry used by that associated process. Since page faults only occur in the current process accessing the address, if the physical page is shared by 10 processes, only the interrupted process will trigger a page fault and obtain a new page. The process tables of the other 9 processes still point to the cleared physical page frame. Therefore, according to the method provided in the above steps, when a memory fault is triggered by one of the processes, the write-time memory fault handling task needs to be exited; a page fault is triggered using the memory management unit, and the new physical page frame information is written to the page table entry used by the process corresponding to the memory fault to replace the faulty page information. In this way, when each shared process uses the faulty physical page frame, its related page table entries can be updated so that the shared process can use the newly allocated physical page frame and write the corresponding data. This avoids the loss of currently calculated data, thereby improving data integrity.

[0071] This embodiment determines whether a memory synchronization failure is occurring during the execution of the memory failure handling method. If a memory synchronization failure is detected, the context register information of the interrupted process is obtained, and the program counter value is retrieved from the context register information. The address of the interrupted instruction is determined using the program counter value. Based on the obtained interrupted instruction address, the binary code corresponding to the interrupted instruction is read, and the opcode in the binary code is parsed. The parsing result of the opcode determines whether the currently interrupted process is in a write operation phase. If it is in a write operation phase, a write-time memory failure is identified. The last-level page table entry is retrieved using the interrupt context, and it is determined whether the last-level page table entry is an anonymous mapping. If it is an anonymous mapping, a new physical page frame is allocated, and the new physical page frame replaces the original faulty physical page frame. The last-level page table entry is used to determine all page table entries involved in the original faulty physical page frame. The original faulty physical page frame information in all page table entries is replaced with the new physical page frame information. When a memory failure occurs, it can determine whether it is a synchronous failure and further determine whether the memory failure occurred during a write operation. If it is determined to be during a write operation, it is further determined whether it is an anonymous mapping. If it is an anonymous mapping, a new physical page frame is created. Due to the unrecoverable data characteristics of anonymous mapping, the physical page is directly replaced, and all associated page table entries are updated, achieving complete isolation of the failed page. The originally corrupted data is no longer referenced, and the new physical page ensures the success of the write operation. It can prevent data loss and process termination, allowing the system to continue execution without being aware of the failure. It can achieve seamless repair of memory write failures while ensuring data write integrity.

[0072] In a preferred embodiment of this example, the method may further include the following steps: exiting the memory fault handling task and returning to the context of the process corresponding to the write-time memory fault; accessing the virtual address using the memory management unit to obtain the new physical page frame information, thus preventing further exceptions; pointing to the interrupted write operation instruction and successfully executing the write operation instruction to write data to a healthy physical memory address, ensuring that other processes sharing the healthy physical memory address do not experience faults or page faults. By exiting the fault handling task and returning to the process context, the system no longer interrupts the execution flow of the process being written to. The interrupted write operation instruction can be redirected, thus continuing execution naturally; obtaining the new physical page frame information through the memory management unit (MMU) and re-executing the write instruction ensures that data is written to healthy physical memory. This not only ensures that the data of the current write operation is not lost but also maintains the integrity of the memory data structure. This effectively improves the system's fault tolerance, data reliability, and business continuity.

[0073] In another preferred embodiment of this example, the method may further include the following step: marking the memory page management structure corresponding to the faulty physical page as poisoned, so as to permanently isolate the faulty physical page in the system's memory allocation and management mechanism. For example, the page management structure corresponding to the faulty physical page can be marked with the HW Poison attribute to identify it as a poisoned page, thereby permanently isolating the page from the system's memory allocation and management mechanism. This achieves the most thorough and secure fault-tolerant handling of memory defects.

[0074] Example 2

[0075] Figure 2 This is a flowchart illustrating the write-time memory fault handling method provided in Embodiment 2 of the present invention. This embodiment is an optimization based on the above embodiment. It allocates a new physical page frame, replaces the original faulty physical page frame with the new physical page frame, and uses the last-level page table entry to determine all page table entries involved in the original faulty physical page frame. The original faulty physical page frame information in all page table entries is replaced with new physical page frame information. Specifically, the optimization involves: allocating a new physical page frame; obtaining the virtual address acquired during the write-time memory fault exception handling task; searching for all page table entries associated with the faulty physical page frame based on the virtual address, wherein each page table entry corresponds to a process sharing the physical page frame; and modifying the atomic physical page frame field in all page table entries to the new physical page frame information.

[0076] See Figure 2 The write-time memory fault handling method includes:

[0077] Step 210: When executing the memory failure repair method, determine whether it is a memory synchronization failure. If it is a memory synchronization failure, obtain the context register information of the interrupted process and obtain the value of the program counter from the context register information.

[0078] Step 220: Determine the address of the interrupted instruction using the value of the program counter; based on the obtained address of the interrupted instruction, read the binary code corresponding to the interrupted instruction and parse the opcode in the binary code.

[0079] Step 230: Determine whether the currently interrupted process is in the write operation phase based on the parsing result of the opcode. If it is in the write operation phase, determine that a write-time memory fault has occurred. Obtain the last-level page table entry using the interrupt context and determine whether it is an anonymous mapping based on the last-level page table entry.

[0080] For example, obtaining the last-level page table entry using the interrupt context may include: determining the interrupted process based on the interrupt context; determining the physical page frame number used by the interrupted process based on the interrupted process; and obtaining the page management structure corresponding to the physical page frame number; obtaining the virtual page address corresponding to the physical page using preset structure field information in the page management structure; and obtaining the last-level page table entry based on the virtual page address and the process's virtual memory page table base address. Using the above method, the last-level page table entry used to trigger the current fault can be accurately obtained.

[0081] Step 240: When mapping anonymously, allocate a new physical page frame.

[0082] In this embodiment, it is not necessary to delete the physical page frames that caused the fault in advance.

[0083] Step 250: Obtain the virtual address obtained during the write-time memory fault exception handling task, and search for all page table entries associated with the faulty physical page frame based on the virtual address, wherein each page table entry corresponds to a process that shares the physical page frame.

[0084] The write-time fault handling method provided in the above embodiments requires two exception handling processes: low-level memory fault handling and page fault handling, resulting in low processing efficiency. Furthermore, it requires separate processing for each process using the faulty physical page frame, which is a distributed processing approach, further reducing efficiency. Therefore, this embodiment adopts an alternative processing method: the virtual address corresponding to the current write-time memory fault handling task is used to determine the corresponding faulty physical page frame, and then this faulty physical page frame is used to find all page table entries using that physical memory. Since each process has its own page table entries, and these page table entries correspond to the same physical page frame, all page table entries associated with that physical page frame can be obtained.

[0085] Step 260: Modify the atomic physical page frame field in all page table entries to the new physical page frame information.

[0086] By using the above method for atomic modifications, only the relationships in all page table entries are changed. This prevents other processes from getting bogged down in memory fault handling and page fault handling tasks again, ensuring that normal writes can be performed even in the event of a memory error. This improves the efficiency of memory error handling.

[0087] This embodiment optimizes the process by allocating a new physical page frame, replacing the original faulty physical page frame with the new physical page frame, and using the last-level page table entries to determine all page table entries related to the original faulty physical page frame. Specifically, it involves: allocating a new physical page frame; obtaining the virtual address acquired during the write-time memory fault handling task; searching for all page table entries associated with the faulty physical page frame based on the virtual address, where each page table entry corresponds to a process sharing the physical page frame; and modifying the atomic physical page frame field in all page table entries to the new physical page frame information. This ensures the complete removal of faulty pages. All processes using this page no longer point to the faulty page but to the new healthy page, completely eliminating the potential problems caused by shared physical page frames remaining even after a single process repairs them. It also improves the efficiency of handling anonymous mapped write-time memory faults.

[0088] Example 3

[0089] Figure 3 This is a schematic diagram of the write-time memory fault handling device provided in Embodiment 3 of the present invention. See also... Figure 3 The write-time memory fault handling device includes:

[0090] The judgment module 310 is used to determine whether it is a memory synchronization failure when executing the memory failure repair handling method;

[0091] The acquisition module 320 is used to acquire the context register information of the interrupted process when a memory synchronization failure occurs, and to acquire the value of the program counter from the context register information;

[0092] The parsing module 330 is used to determine the address of the interrupted instruction using the value of the program counter, read the binary code corresponding to the interrupted instruction based on the obtained address of the interrupted instruction, and parse the opcode in the binary code.

[0093] The write operation phase determination module 340 is used to determine whether the currently interrupted process is in the write operation phase based on the parsing result of the opcode. If it is in the write operation phase, it determines that a write-time memory failure has occurred.

[0094] Anonymous mapping determination module 350 is used to obtain the last-level page table entry using the interrupt context, and determine whether it is an anonymous mapping based on the last-level page table entry.

[0095] The first replacement module 360 ​​is used to allocate a new physical page frame when mapping anonymously, and replace the original faulty physical page frame with the new physical page frame.

[0096] Page table entry determination module 370 is used to determine all page table entries involved in the original faulty physical page frame using the last-level page table entry;

[0097] The second replacement module 380 is used to replace the original faulty physical page frame information in all page table entries with new physical page frame information.

[0098] The write-time memory fault handling device provided in this embodiment determines whether a memory synchronization fault is occurring when executing a memory unrepairable fault handling method. If a memory synchronization fault is occurring, it obtains the context register information of the interrupted process and retrieves the program counter value from the context register information. It uses the program counter value to determine the address of the interrupted instruction, reads the binary code corresponding to the interrupted instruction based on the obtained address, and parses the opcode in the binary code. Based on the opcode parsing result, it determines whether the currently interrupted process is in a write operation phase. If it is in a write operation phase, a write-time memory fault is determined. It uses the interrupt context to obtain the last-level page table entry and determines whether it is an anonymous mapping. If it is an anonymous mapping, it allocates a new physical page frame and replaces the original faulty physical page frame with the new physical page frame. It uses the last-level page table entry to determine all page table entries involved in the original faulty physical page frame and replaces the original faulty physical page frame information in all page table entries with the new physical page frame information. When a memory failure occurs, it can determine whether it is a synchronous failure and further determine whether the memory failure occurred during a write operation. If it is determined to be during a write operation, it is further determined whether it is an anonymous mapping. If it is an anonymous mapping, a new physical page frame is created. Due to the unrecoverable data characteristics of anonymous mapping, the physical page is directly replaced, and all associated page table entries are updated, achieving complete isolation of the failed page. The originally corrupted data is no longer referenced, and the new physical page ensures the success of the write operation. It can prevent data loss and process termination, allowing the system to continue execution without being aware of the failure. It can achieve seamless repair of memory write failures while ensuring data write integrity.

[0099] Based on the above embodiments, the first replacement module includes:

[0100] The deletion unit is used to delete the original faulty physical page frame and exit the write-time memory fault exception handling task.

[0101] The allocation unit is used to trigger a page fault using the memory management unit and allocate a new physical page frame;

[0102] The writing unit is used to write the new physical page frame information to replace the faulty page information in the page table entry used by the process corresponding to the memory fault.

[0103] Based on the above embodiments, the page table entry determination module includes:

[0104] An allocation unit is used to allocate a new physical page frame.

[0105] The lookup unit is used to obtain the virtual address obtained during the write-time memory fault exception handling task, and to find all page table entries associated with the faulty physical page frame based on the virtual address, wherein each page table entry corresponds to a process that shares the physical page frame;

[0106] Accordingly, the second replacement module includes:

[0107] The modification unit is used to modify the atomic physical page frame field in all page table entries to the new physical page frame information.

[0108] Based on the above embodiments, the device further includes:

[0109] The exit module is used to exit from the memory fault exception handling task and return the context of the process corresponding to the memory fault that occurred. When accessing the virtual address using the memory management unit, the new physical page frame information is obtained and the exception is no longer triggered.

[0110] The execution module is used to point to the interrupted write operation instruction, and to successfully execute the write operation instruction to write data to a healthy physical memory address, so that other processes sharing the healthy physical memory address will not experience failures or page faults.

[0111] Based on the above embodiments, the page table entry determination module includes:

[0112] The page management structure acquisition module is used to determine the interrupted process based on the interruption context, determine the physical page frame number used based on the interrupted process, and acquire the page management structure corresponding to the physical page frame number.

[0113] The virtual page address acquisition module is used to obtain the virtual page address corresponding to the physical page by utilizing the preset structure field information in the page management structure;

[0114] The module for obtaining the last-level page table entry is used to obtain the last-level page table entry based on the virtual page address and the base address of the process's virtual memory page table.

[0115] The write-time memory fault handling device provided in the embodiments of the present invention can execute the write-time memory fault handling method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0116] Example 4

[0117] Figure 4 This is a schematic diagram of the structure of a terminal configured with Jailhouse Hypervisor, provided in Embodiment 4 of the present invention. Figure 4 A block diagram is shown of an exemplary terminal 12 suitable for implementing embodiments of the present invention. Figure 4 The terminal 12 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0118] like Figure 4 As shown, terminal 12 is presented in the form of a general-purpose computing terminal. The components of terminal 12 may include, but are not limited to: one or more processors or processing units 16, system memory 28, and bus 18 connecting different system components (including system memory 28 and processing unit 16).

[0119] Bus 18 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. For example, these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0120] Terminal 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by terminal 12, including volatile and non-volatile media, removable and non-removable media.

[0121] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache 32. Terminal 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write non-removable, non-volatile magnetic media (… Figure 4 Not shown; usually referred to as a "hard drive"). Although Figure 4 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 via one or more data media interfaces. System memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0122] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in system memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 42 typically perform the functions and / or methods described in the embodiments of the present invention.

[0123] Terminal 12 can also communicate with one or more external devices 14 (e.g., keyboard, pointing terminal, display 24, etc.), and with one or more terminals that enable a user to interact with terminal 12, and / or with any terminal (e.g., network card, modem, etc.) that enables terminal 12 to communicate with one or more other computing terminals. This communication can be performed via input / output (I / O) interface 22. Furthermore, terminal 12 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 20. As shown, network adapter 20 communicates with other modules of terminal 12 via bus 18. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with terminal 12, including but not limited to: microcode, terminal drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0124] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the write-time memory fault handling method provided in the embodiments of the present invention.

[0125] Example 5

[0126] Embodiment 5 of the present invention also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform any of the write-time memory fault handling methods provided in the above embodiments.

[0127] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0128] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0129] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0130] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or terminal. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0131] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for handling write-time memory faults, characterized in that, include: When executing the memory failure repair handling method, determine whether it is a memory synchronization failure; In the event of a memory synchronization failure, the context register information of the interrupted process is obtained, and the value of the program counter is obtained from the context register information. The address of the interrupted instruction is determined using the value of the program counter. Based on the obtained address of the interrupted instruction, the binary code corresponding to the interrupted instruction is read, and the opcode in the binary code is parsed. Based on the result of parsing the opcode, determine whether the currently interrupted process is in the write operation phase. If it is in the write operation phase, determine that a write-time memory failure has occurred. Use the interrupt context to obtain the last-level page table entry, and determine whether it is an anonymous mapping based on the last-level page table entry; When mapping anonymously, a new physical page frame is allocated, and the original faulty physical page frame is replaced with the new physical page frame. The last-level page table entry is used to determine all page table entries involved in the original faulty physical page frame; Replace the original faulty physical page frame information in all page table entries with new physical page frame information.

2. The method according to claim 1, characterized in that, The allocation of a new physical page frame, and the replacement of the original faulty physical page frame with the new physical page frame, includes: Delete the original faulty physical page frame and exit the write-time memory fault exception handling task; A page fault is triggered using the memory management unit, and a new physical page frame is allocated. The new physical page frame information is written into the page table entry used by the process corresponding to the memory fault to replace the faulty page information.

3. The method according to claim 2, characterized in that, The step of using the last-level page table entry to determine all page table entries involved in the original faulty physical page frame includes: When a page fault is triggered by one of the associated processes in the faulty physical page frame, the new physical page frame information is associated in the page table entry used by the associated process based on the page fault triggered by the associated process.

4. The method according to claim 1, characterized in that, The process involves allocating a new physical page frame, replacing the original faulty physical page frame with the new physical page frame, and using the last-level page table entry to determine all page table entries involved in the original faulty physical page frame. Replace the existing faulty physical page frame information in all page table entries with new physical page frame information, including: Allocate a new physical page frame; Obtain the virtual address obtained during the write-time memory fault exception handling task, and find all page table entries associated with the faulty physical page frame based on the virtual address, wherein each page table entry corresponds to a process that shares the physical page frame; Modify the atomic physical page frame field in all page table entries to the new physical page frame information.

5. The method according to claim 3 or 4, characterized in that, The method further includes: Exit from the memory fault exception handling task and return to the context of the process corresponding to the write-time memory fault. When accessing the virtual address using the memory management unit, the new physical page frame information is obtained, and the exception is no longer triggered. The interrupted write operation instruction was successfully executed to write data to a healthy physical memory address, ensuring that other processes sharing the healthy physical memory address do not experience page faults or page errors.

6. The method according to claim 5, characterized in that, The method further includes: The memory page management structure corresponding to the faulty physical page is marked as poisoned to permanently isolate the faulty physical page in the system's memory allocation and management mechanism.

7. The method according to claim 1, characterized in that, The step of obtaining the last-level page table entry using the interrupt context includes: The interrupted process is determined based on the interruption context, the physical page frame number used is determined based on the interrupted process, and the page management structure corresponding to the physical page frame number is obtained. Using the pre-defined structure field information in the page management structure, the virtual page address corresponding to the physical page is obtained; The last-level page table entry is obtained based on the virtual page address and the base address of the process's virtual memory page table.

8. A write-time memory fault handling device, characterized in that, include: The judgment module is used to determine whether the memory synchronization failure is the cause when the memory cannot be repaired fault handling method is executed. The acquisition module is used to acquire the context register information of the interrupted process when a memory synchronization failure occurs, and to acquire the value of the program counter from the context register information; The parsing module is used to determine the address of the interrupted instruction using the value of the program counter, read the binary code corresponding to the interrupted instruction based on the obtained address of the interrupted instruction, and parse the opcode in the binary code. The write operation phase determination module is used to determine whether the currently interrupted process is in the write operation phase based on the parsing result of the opcode. If it is in the write operation phase, it determines that a write-time memory failure has occurred. An anonymous mapping determination module is used to obtain the last-level page table entry using the interrupt context, and determine whether it is an anonymous mapping based on the last-level page table entry. The first replacement module is used to allocate a new physical page frame when mapping anonymously, and replace the original faulty physical page frame with the new physical page frame. The page table entry determination module is used to determine all page table entries involved in the original faulty physical page frame using the last-level page table entries. The second replacement module is used to replace the original faulty physical page frame information in all page table entries with new physical page frame information.

9. A terminal, characterized in that, include: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the write-time memory fault handling method as described in any one of claims 1-7.

10. A storage medium containing computer-executable instructions, characterized in that, The computer-executable instructions, when executed by a computer processor, are used to perform the write-time memory fault handling method as described in any one of claims 1-7.

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