MOSFET Saturation Current Physical Modeling and Layout Optimization Method and System

Abstract

This invention discloses a method and system for physical modeling and layout optimization of MOSFET saturation current. The methods include: based on effective mobility extraction technology and quasi-ballistic transport theory, impedance is decomposed into ballistic injection impedance and channel scattering impedance, thereby constructing a high-precision MOSFET saturation current physical model. The extracted physical parameters, after modifying the compact model, enable accurate prediction of the saturation current. Furthermore, an initial layout is constructed based on the modeling scheme, and the thermal failure boundary of the MOSFET device saturation current physical model is defined using thermal signature criteria. Then, based on this thermal failure boundary, geometric constraints are applied to the initial layout to generate a multi-finger parallel layout structure that suppresses self-heating effects. Overall, the solution provided by this invention significantly reduces the prediction bias of the compact model and significantly reduces the risk of large-signal linearity degradation in low-temperature drivers and low-noise amplifiers, providing reliable assurance for design.

Description

Technical Field

[0001] This invention relates to the field of semiconductor microelectronics technology, and in particular to a method and system for physical modeling and layout optimization of MOSFET saturation current. Background Technology

[0002] As solid-state quantum computing technology scales up, to address the "wiring bottleneck" (including thermal load and signal delay) caused by the massive cabling between room-temperature controlled devices and milliKelvin (mK) temperature-range quantum chips, the industry has reached a consensus: the analog front-end and control circuitry (Cryo-CMOS) must be moved down to the 4K (Kelvin) or first-stage cold block (approximately 50K) temperature range of the cryo-cooler. However, industry-standard PDKs (Process Design Kits) are typically calibrated only within the range of -40°C to 125°C. When the operating temperature of CMOS (Complementary Metal-Oxide-Semiconductor) devices drops below 50K, existing design methodologies face severe physical challenges.

[0003] 1. Physical failure of current modeling in the saturation region.

[0004] In cryogenic environments (below 50K), compact models (such as BSIM and PSP) often have prediction errors exceeding 20% ​​for the saturation current. BSIM is the Berkeley short-channel insulated-gate field-effect transistor model, and PSP is a high-precision, industry-standard MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) model based on surface potential. The core reason for this is the change in the fundamental physical mechanism and the failure of the parameter extraction method.

[0005] (1.1) Velocity Overshoot: At low temperatures, phonon scattering is drastically suppressed, and the mean free path of charge carriers increases significantly. In short-channel devices, carrier transport enters a quasi-ballistic mode, exhibiting a significant velocity overshoot phenomenon, with the actual velocity far exceeding the steady-state saturation velocity. The traditional drift-diffusion model forces clamping of the saturation velocity, severely underestimating the saturation drive capability of advanced process nodes.

[0006] (1.2) Source-to-drain contact nonlinearity leads to extraction failure: At low temperatures, carrier freezing occurs in the highly doped source / drain regions, causing Fermi level shift and depletion layer widening at the contact interface. The contact characteristics degenerate from a tunneling-dominated ohmic contact at room temperature to a barrier-bound Schottky-like contact. This leads to parasitic series resistance... The voltage is no longer constant and exhibits strong voltage nonlinearity. Traditional parameter extraction methods (such as the Y-function method) rely on the assumption that "the contact resistance in the linear region is constant." At low temperatures, this assumption no longer holds, leading to significant deviations in mobility and threshold voltage extracted from linear region data. This parameter bias introduced from the linear region causes severe distortion in the model's prediction of the saturation region current, failing to accurately describe the device's low-temperature transport characteristics.

[0007] 2. Output admittance collapse caused by self-heating effect.

[0008] Another major challenge in low-temperature, high-power circuit design is severe thermal nonlinearity:

[0009] (2.1) Thermal properties "frozen": According to Debye's Law, the specific heat capacity C of silicon materials is... p With temperature T 3 The temperature decreases regularly (i.e., the cube of temperature T). At 4K, silicon has extremely low thermal inertia, and even a small fluctuation in power consumption can cause a drastic local lattice temperature rise.

[0010] (2.2) Output admittance collapse: For wide-channel devices, internal heat is difficult to dissipate. As the drain-source voltage increases... Increased power density leads to higher lattice temperature and drastic thermal degradation of mobility. This manifests in electrical characteristics as a significant slowdown in the rate of increase of leakage current with voltage, resulting in decreased output admittance. The admittance decays rapidly with increasing power consumption and approaches zero (i.e., admittance collapses). This nonlinearity... Suppression is the main cause of the degradation of large-signal linearity (P1dB, IIP3) of low-temperature LNAs (low-noise amplifiers) and drivers, where P1dB is the 1dB compression point and IIP3 is the third-order input cutoff point.

[0011] Therefore, there is an urgent need to develop a new solution to address the problems of existing compact models failing to model the saturation region due to source-end contact nonlinearity, and wide-channel devices experiencing significant suppression of output admittance (admittance collapse) due to self-heating effects at deep low temperatures, which leads to circuit linearity degradation.

[0012] In view of this, the present invention is hereby proposed. Summary of the Invention

[0013] The purpose of this invention is to provide a method and system for physical modeling and layout optimization of MOSFET saturation current, which provides a reliable simulation model and structural design basis for low-temperature quantum computing control circuits (such as low-noise amplifiers and drivers), and can significantly reduce the risk of large-signal linearity degradation.

[0014] The objective of this invention is achieved through the following technical solution:

[0015] A physical modeling method for MOSFET saturation current, comprising:

[0016] The raw current and voltage data of a CMOS device are obtained by measuring it in a temperature range below a set temperature; where CMOS is a complementary metal-oxide semiconductor.

[0017] Based on the effective mobility extraction technology in the linear region, the original voltage is preprocessed to extract the source series resistance and the threshold voltage in the linear region. Based on the threshold voltage in the linear region, the threshold voltage in the saturation region is extracted using the subthreshold characteristic. The source potential is then corrected by combining the source series resistance and the original current to obtain the effective overdrive voltage in the saturation region.

[0018] Based on quasi-ballistic transport theory and combined with the effective overdrive voltage in the saturation region, a physical model of MOSFET saturation current for CMOS devices is constructed. The MOSFET saturation current physical model includes ballistic injection impedance and channel scattering impedance. The MOSFET is a metal-oxide-semiconductor field-effect transistor.

[0019] The physical model of MOSFET saturation current is linearized, and the effective injection velocity and scattering parameters are extracted through regression calculations, thereby correcting the compact model.

[0020] A layout optimization method, comprising:

[0021] Based on the aforementioned physical modeling method for MOSFET saturation current, a physical model of MOSFET saturation current for the current CMOS device is constructed, and an initial CMOS device layout is constructed using the physical model of MOSFET saturation current for the current CMOS device.

[0022] Using thermal signature technology, drain-source current and drain-source voltage data of CMOS devices with different communication lengths L and widths W are measured under deep inversion conditions. Thermal signature maps are constructed to identify thermal failure boundaries caused by the failure of the physical model of MOSFET saturation current due to self-heating effect.

[0023] Based on the thermal failure boundary, the initial CMOS device layout is optimized through geometric constraints to ensure that the current CMOS device operates within the effective physical range.

[0024] A MOSFET saturation current physical modeling system is provided to implement the aforementioned MOSFET saturation current physical modeling method, comprising: a raw data extraction unit for measuring a CMOS device in a temperature range below a set temperature to obtain raw current and voltage data; wherein, CMOS is a complementary metal-oxide-semiconductor.

[0025] The effective overdrive voltage extraction unit is used to preprocess the original voltage based on the effective mobility extraction technology in the linear region, and extract the source series resistance and the threshold voltage in the linear region; based on the threshold voltage in the linear region, the threshold voltage in the saturation region is extracted using the subthreshold characteristic, and the source potential is corrected by combining the source series resistance and the original current to obtain the effective overdrive voltage in the saturation region.

[0026] The model building unit is used to construct a physical model of the MOSFET saturation current of CMOS devices based on quasi-ballistic transport theory and combined with the effective overdrive voltage in the saturation region; wherein, the MOSFET saturation current physical model includes ballistic injection impedance and channel scattering impedance, and the MOSFET is a metal-oxide-semiconductor field-effect transistor.

[0027] The compact model correction unit is used to linearize the MOSFET saturation current physical model and extract the effective injection velocity and scattering parameters through regression calculation, thereby correcting the compact model.

[0028] A layout optimization system for implementing the aforementioned layout optimization method, comprising:

[0029] The model and initial layout building unit is used to build the MOSFET saturation current physical model of the current CMOS device, and to build the initial CMOS device layout using the MOSFET saturation current physical model of the current CMOS device.

[0030] The thermal failure boundary identification unit is used to measure the drain-source current and drain-source voltage data of CMOS devices with different communication lengths L and widths W under deep inversion conditions using thermal signature technology, and to construct a thermal signature map to identify the thermal failure boundary of the MOSFET saturation current physical model failure caused by self-heating effect.

[0031] The layout optimization unit is used to optimize the initial CMOS device layout based on thermal failure boundaries and geometric constraints, so that the current CMOS device operates within the effective physical range.

[0032] As can be seen from the technical solution provided by the present invention, based on the effective mobility extraction technology and quasi-ballistic transport theory, the impedance is decomposed into ballistic injection impedance and channel scattering impedance, thereby constructing a high-precision MOSFET saturation current physical model. After the extracted physical parameters are used to correct the compact model, accurate prediction of the saturation current can be achieved. Furthermore, based on the MOSFET saturation current physical modeling scheme, an initial layout is constructed, and the thermal failure boundary of the MOSFET device saturation current physical model is defined by combining the thermal signature criterion. Then, based on the thermal failure boundary, the initial layout is geometrically constrained to generate a multi-finger parallel layout structure that suppresses self-heating effects. Overall, the solution provided by the present invention significantly reduces the prediction bias of the compact model and can significantly reduce the risk of large-signal linearity degradation in low-temperature drivers and low-noise amplifiers, providing reliable assurance for design. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A flowchart illustrating a physical modeling method for MOSFET saturation current provided in an embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram of the framework of a MOSFET saturation current physical modeling method provided in an embodiment of the present invention.

[0036] Figure 3 This is a schematic diagram of the first-level regression provided in an embodiment of the present invention.

[0037] Figure 4 This is a schematic diagram of the second-level regression provided in an embodiment of the present invention.

[0038] Figure 5 This is a schematic diagram of the third-level regression provided in an embodiment of the present invention.

[0039] Figure 6 This is a flowchart of a layout optimization method provided in an embodiment of the present invention.

[0040] Figure 7 This is a schematic diagram of constructing a thermal signature map according to an embodiment of the present invention.

[0041] Figure 8 This is a schematic diagram of the test data analysis process provided in an embodiment of the present invention.

[0042] Figure 9This is a schematic diagram of the analysis process after determining the thermal failure boundary, as provided in an embodiment of the present invention.

[0043] Figure 10 This is a schematic diagram of a MOSFET saturation current physical modeling system provided in an embodiment of the present invention.

[0044] Figure 11 This is a schematic diagram of a layout optimization system provided in an embodiment of the present invention. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0046] First, the following explanations are provided for the terms that may be used in this article:

[0047] The terms "comprising," "including," "containing," "having," or other similar semantic descriptions should be interpreted as non-exclusive inclusion. For example, including a technical feature element (such as raw material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, device, step, process, method, reaction conditions, processing conditions, parameter, algorithm, signal, data, product or article of manufacture, etc.) should be interpreted as including not only the expressly listed technical feature element, but also other technical feature elements that are not expressly listed and are well-known in the art.

[0048] This invention provides a method and system for physical modeling and layout optimization of MOSFET saturation current. It is a compact modeling and layout optimization solution for cryogenic (less than 50 K) environments, primarily addressing the core challenges of simulation model distortion and linearity degradation of high-power devices in superconducting / spin quantum computing readout and control circuit design. Contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Unless otherwise specified, specific conditions in the embodiments of this invention are performed according to conventional conditions or manufacturer recommendations. Reagents or instruments used in the embodiments of this invention, unless otherwise specified, are commercially available products.

[0049] Example 1

[0050] This invention provides a physical modeling method for MOSFET saturation current, such as... Figure 1 As shown, it mainly includes the following steps:

[0051] Step 11: Extraction of raw data.

[0052] In this embodiment of the invention, the CMOS device is measured at a temperature range below a set temperature to obtain raw current and voltage data; wherein, CMOS is a complementary metal-oxide semiconductor.

[0053] Step 12: Extract the effective overdrive voltage.

[0054] In this embodiment of the invention, based on the effective mobility extraction technology in the linear region, the original voltage is preprocessed to extract the source series resistance. With the threshold voltage of the linear region Subsequently, the subthreshold characteristic was used to further extract the threshold voltage of the saturation region. By combining the source series resistance with the original current to correct the source potential, an effective overdrive voltage in the saturation region can be obtained. .

[0055] In this embodiment of the invention, the subthreshold characteristic is used to extract the threshold voltage of the saturation region. In addition, by combining the source series resistance to correct the source potential, the effective overdrive voltage in the saturation region is obtained, including:

[0056] (1) Utilizing the horizontal offset of the subthreshold curves in the linear and saturation regions Calculate the threshold voltage in the saturation region: ;in, The threshold voltage for the saturation region. This is the threshold voltage for the linear region.

[0057] (2) Correcting the source potential by combining the source series resistance To obtain the effective overdrive voltage in the saturation region:

[0058] ;

[0059] in, This is the effective overdrive voltage in the saturation region; This is the drain-source current in the saturation region, which belongs to the original current; This is the gate-source voltage, which is the original voltage. This is the source series resistor.

[0060] In this embodiment of the invention, the effective mobility extraction technique for the linear region can refer to existing solutions, such as the Chinese invention patent "Method, System, Device and Storage Medium for Mobility Extraction in Low-Temperature CMOS" with authorization publication number CN120688425B. The implementation process of extracting the threshold voltage of the saturation region using subthreshold characteristics can refer to existing solutions, such as the Chinese invention patent application "Method and System for Extracting Microscopic Parameters of Low-Temperature CMOS Carrier MFP" with publication number CN121410490A.

[0061] Step 13: Construct a physical model of the MOSFET saturation current of a CMOS device.

[0062] In this embodiment of the invention, a physical model of MOSFET saturation current of CMOS devices is constructed based on quasi-ballistic transport theory and combined with the effective overdrive voltage in the saturation region; wherein, the physical model of MOSFET saturation current includes ballistic injection impedance and channel scattering impedance, and MOSFET is a metal oxide semiconductor field-effect transistor.

[0063] In this embodiment of the invention, the MOSFET saturation region characteristics of CMOS devices are modeled based on quasi-ballistic transport theory. The total transport impedance Z of the MOSFET saturation region is divided into ballistic injection impedance and channel scattering impedance, expressed as:

[0064] ;

[0065] in, To inject impedance into the ballistic trajectory, Channel scattering impedance; For effective migration rate, Here, is the capacitance per unit area of ​​the gate oxide layer, W is the channel width of the CMOS device, and L is the channel length of the CMOS device. This is the effective overdrive voltage in the saturation region; For effective injection speed.

[0066] Step 14: Compact model correction.

[0067] In this embodiment of the invention, the physical model of MOSFET saturation current is linearized, and the effective injection velocity and scattering parameters are extracted through regression calculation, thereby correcting the saturation velocity parameters in the compact model.

[0068] (1) Linearization method.

[0069] Effective migration rate Determined by both surface roughness scattering and Coulomb scattering, it can be expressed as:

[0070] ;

[0071] in, and All are scattering parameters. The surface roughness scattering parameter in the saturation region. denoted as Coulomb scattering parameter in the saturation region, and B is the power-law parameter calculated based on the effective mobility extraction technique in the linear region.

[0072] Combining the above equation, the physical model of MOSFET saturation current is linearized through algebraic transformation, and expressed as:

[0073] .

[0074] (2) Regression calculation.

[0075] Define the dependent variable H, the independent variable X, and the slope term. With intercept term :

[0076] ;

[0077] ;

[0078] ;

[0079] .

[0080] The effective injection velocity and scattering parameters are extracted through the following multi-level linear regression operation:

[0081] First-level regression: Based on obtaining the effective overdrive voltage in the saturation region , with the original current (i.e., the drain-source current in the saturation region) For CMOS devices with different channel lengths L, linear fitting was performed on the dependent variable H and the independent variable X to obtain the corresponding slope terms. With intercept term .

[0082] Second-order regression: Based on slope term The slope term is fitted to the relationship between the channel length L of the CMOS device and the CMOS device channel length L. Surface roughness scattering parameters in the saturation region With effective injection speed .

[0083] Third-level regression: Based on intercept term The relationship between the channel length L of the CMOS device and the intercept term is fitted. Coulomb scattering parameters in the saturation region .

[0084] By modifying the compact model using the extracted effective injection velocity and scattering parameters, accurate prediction of saturation current can be achieved.

[0085] To more clearly demonstrate the technical solution and its effects provided by the present invention, the method provided by the embodiments of the present invention will be described in detail below with reference to specific examples.

[0086] To address the shortcomings of existing technologies, this invention provides a method that, based on the accurate extraction of parameters in the linear region, further decouples the transport mechanism in the saturation region. Specifically, based on quasi-ballistic transport theory, this invention constructs a physical model of impedance in the saturation region (a physical model of saturation current), and decouples the extraction of ballistic injection velocity and scattering parameters through a multi-level linear regression algorithm, thereby significantly improving the prediction accuracy of the cryogenic compact model. Figure 2 The diagram illustrates the overall framework and flow of this method.

[0087] I. Data preprocessing and baseline parameter extraction.

[0088] This step aims to provide accurate fundamental parameters for subsequent impedance analysis in the saturation region through a systematic process. Based on the physical characteristics at low temperatures (e.g., 4 K), the effective overdrive voltage in the saturation region is determined:

[0089] ;

[0090] in, This is the effective overdrive voltage in the saturation region; This represents the drain-source current in the saturation region (which is part of the raw current data). This is the gate-source voltage (which belongs to the raw voltage data). For source series resistance, This is the threshold voltage for the saturation region.

[0091] In one embodiment, the source series resistance in the above equation Total parasitic resistance extracted from the linear region Based on the symmetry assumption The estimation was obtained. In other embodiments, if significant asymmetry exists at the source-drain contacts (e.g., difference in lightly doped drain (LDD) implantation), it can be independently extracted via source-drain interchange measurements or Kelvin test structures. This parameter is introduced to control the gate-source voltage applied to the external port. The correction is made to map it to the effective overdrive voltage of the saturation region of the actual control source barrier.

[0092] In this embodiment of the invention, CMOS devices can be measured at deep cryogenic temperatures to obtain raw data. The data is then preprocessed using effective mobility extraction techniques to extract baseline parameters (effective overdrive voltage in the saturation region). This refers to the drain-source current, which typically includes the drain-source current in the linear region. With saturation region drain-source current .

[0093] 1. Extraction of threshold voltage in the linear region.

[0094] A linear region source-drain total resistance model is constructed using the shift-and-ratio method. A model for enhancing resistance is constructed using the nth derivative. ,in, The symbol represents the nth-order partial derivative, and the subscript i indicates the i-th device. The above operation effectively suppresses series resistance and strong-field polynomial terms that are independent of the gate voltage. Subsequently, a long-channel reference device is selected as the reference device, and a baseline model is constructed. Then construct the ratio function. :

[0095] ;

[0096] in, This represents the voltage offset.

[0097] The optimal voltage offset that minimizes the standard deviation of the ratio function is found through an optimization algorithm. Thus, the threshold voltage of the linear region of the CMOS device is obtained. , This is the threshold voltage of the reference device.

[0098] 2. Decomposition of strong and weak field scattering components and extraction of power-law parameters.

[0099] Under low-temperature conditions, carrier mobility is mainly limited by Coulomb scattering at low fields and surface roughness scattering at high fields. The total resistance model in the linear region is decomposed into weak-field and strong-field components, and the effective overdrive voltage in the linear region is defined. :

[0100] ;

[0101] in, This is a geometric scaling factor related to the channel length L of the CMOS device. For total parasitic resistance, Where is the capacitance per unit area of ​​the gate oxide layer, and W is the channel width of the CMOS device. This represents the strong field component in the total resistance model of the linear region. Indicates the discrete geometric scaling factor in the linear region resistance model. The weak field component after that, The power-law parameter B and amplitude A were extracted through linear fitting.

[0102] Those skilled in the art will understand that the calculation method for the effective overdrive voltage in the linear region is the same as that for the effective overdrive voltage in the saturation region. However, the current in the linear region is much smaller than that in the saturation region. Therefore, the formula... It can be ignored.

[0103] In addition, to simplify the calculation, a merging magnitude parameter is introduced. At this point, the weak field component can be simply represented as... In a directly proportional form.

[0104] 3. Extraction of total parasitic resistance based on residual function.

[0105] To separate source-drain parasitic resistances, a residual function is defined. Using the introduced merging amplitude parameter Subtract the known weak field components from the total resistance model in the linear region:

[0106] ;

[0107] At this point, the residual function only includes the total parasitic resistance. With strong field weight.

[0108] Since the strong field component is proportional to the channel length L of the CMOS device, while the total parasitic resistance... Approximating a constant, a linear regression is performed on the residual function of CMOS devices with different channel lengths with respect to the channel length L. The intercept of this regression is the total parasitic resistance. .

[0109] Total parasitic resistance Source series resistor series resistor with drain Series composition, i.e. Based on the symmetry assumption of the device structure (assuming that the two series resistors are equal, i.e.) The source series resistance is extracted as follows: .

[0110] 4. Calculation of threshold voltage in the saturation region.

[0111] Considering the leakage-induced barrier reduction (DIBL) effect, the horizontal offset of the subthreshold curves in the linear and saturation regions is used. Calculate the threshold voltage in the saturation region: ;in, The threshold voltage for the saturation region. This is the threshold voltage for the linear region.

[0112] II. Impedance Analysis and Modeling in the Saturation Region

[0113] This step establishes a physical picture of cryogenic quasi-ballistic transport, including cryogenic quasi-ballistic transport physics analysis, impedance decomposition and model construction, model linearization, parameter decoupling and multi-level linear regression extraction, providing a theoretical basis for impedance modeling. Addressing the physical characteristics of acoustic phonon scattering freezing and optical phonon scattering localization under cryogenic conditions, this invention establishes an impedance physics model dominated by source-end "kT layer" (inversion layer) scattering.

[0114] 1. The physical mechanism of quasi-ballistic transport.

[0115] Under low-temperature conditions, carrier transport exhibits significant quasi-ballistic characteristics:

[0116] (1) Acoustic phonon scattering is significantly suppressed: Under low temperature conditions, lattice thermal vibration is weakened, the probability of acoustic phonon scattering is greatly reduced, and the mean free path of charge carriers is significantly increased.

[0117] (2) Localization of optical phonon scattering: Free carriers in the kT layer have not yet been accelerated to the optical phonon emission threshold (~60meV). Near the source barrier of interest (virtual source region), the current is less sensitive to optical phonon scattering; although scattering may occur in the high field region at the drain, it mainly affects energy relaxation rather than the injection of confined current.

[0118] (3) Scattering characteristics dominated by the kT layer at the source: The effective mobility characterizes the scattering in the kT layer on the source side, which determines the injection efficiency. This invention utilizes this physical mechanism to decompose the transport in the saturation region into a series impedance physical model of the injection process and the scattering process.

[0119] 2. Construction of the impedance physical model (i.e., the MOSFET saturation current physical model mentioned above).

[0120] Based on the above physical mechanism, the following impedance physical model is established:

[0121] (1) Impedance decomposition and model construction.

[0122] Based on the physical characteristics of modern nanoscale transistors, the saturation region characteristics of the device are modeled using quasi-ballistic transport theory. Unlike the drift-diffusion model of traditional long-channel devices, this theory introduces the concept of a "virtual source," decomposing the total transport impedance Z in the saturation region into a series of ballistic injection impedance and channel scattering impedance.

[0123] .

[0124] In the above formula:

[0125] Injecting impedance into the ballistics , among them For effective injection speed, as an engineering equivalent parameter, it uniformly characterizes the source-end barrier injection capability. It should be noted that this parameter, through equivalent absorption, simultaneously incorporates the intrinsic thermal injection limit and the combined limitation of current imposed by the low-temperature source-end non-ohmic contact (Schottky barrier / impurity freezing).

[0126] Channel scattering impedance This impedance originates from lattice scattering, impurity scattering, and surface roughness scattering experienced by charge carriers during channel transport. This impedance, as an equivalent scattering term, reverts to the traditional drift-diffusion law in the long-channel limit, while in the short-channel limit it is used to characterize distributed scattering events within the channel; the formula... The effective mobility is proportional to the channel length L, indicating that as the channel length increases, the scattering probability increases, and the device behavior gradually reverts to that of traditional long-channel devices.

[0127] (2) Characterization of scattering mechanism.

[0128] In the low-temperature quasi-ballistic region, the effective mobility within the kT layer is determined by both surface roughness (SR) scattering and Coulomb (CB) scattering. Based on the research results of mobility analysis in the linear region, the following scattering model is adopted:

[0129] ;

[0130] in, and All are scattering parameters. The surface roughness scattering parameter in the saturation region. denoted as Coulomb scattering parameter in the saturation region; B is a power-law parameter calculated based on the effective mobility extraction technique. In one implementation, it can directly inherit the value extracted in the linear region; in another implementation, it allows refitting in the regression of data in the saturation region to improve accuracy.

[0131] (3) Model linearization.

[0132] Combining the two formulas mentioned above, and through algebraic transformations, we can rearrange them into a standard linear regression form. The specific linearized equations are as follows:

[0133] ;

[0134] Where: dependent variable Independent variable Slope term Intercept term .

[0135] The above form clearly separates the slope term and the intercept term, and is dimensionally consistent, laying a solid mathematical foundation for subsequent multi-level regression extraction.

[0136] 3. Parameter decoupling and extraction.

[0137] This step utilizes a multi-level linear regression strategy to achieve precise decoupling and extraction of physical parameters.

[0138] First-level regression (device-level extraction): Based on the corrected original data of the saturation region, linear fitting is performed on the dependent variable H and the independent variable X for CMOS devices with different channel lengths L, and the corresponding slope terms are fitted. With intercept term .like Figure 3 As shown, the fitting process is illustrated for different channel lengths L, R 2 A commonly used statistical indicator for evaluating the quality of linear fit is a value closer to 1, which generally indicates a better fit. Figure 3 Average R 2 (Avg R) 2 A value greater than 0.999 indicates that the data points closely match the fitted line.

[0139] Second-level regression (decoupling effective injection rate from surface roughness): based on slope term The slope term is fitted to the relationship between the channel length L of the CMOS device and the CMOS device channel length L. Surface roughness scattering parameters in the saturation region With effective injection speed .like Figure 4 As shown, the intercept item is displayed. The relationship between the channel length L and the measured value is shown, where the circular nodes represent measured values, the lines are linearly fitted straight lines, and R... 2 =0.9959, which indicates that the linear fit is of excellent quality.

[0140] Third-order regression (Coulomb scattering parameter decoupling): based on the intercept term The relationship between the channel length L of the CMOS device and the intercept term is fitted. Coulomb scattering parameters in the saturation region .like Figure 5 As shown, the slope term is displayed. The relationship between the channel length L and the measured value is shown, where the square nodes represent measured values, the lines are linear fit lines, and R... 2 =0.9929, representing an excellent linear fit, defined as... , Figure 5 The parameters are given. and Examples.

[0141] 4. Compact model correction.

[0142] Extracted effective injection rate Surface roughness scattering parameters in the saturation region Coulomb scattering parameters in the saturation region By substituting the quasi-ballistic current formula or writing it into the model card, the parameters of the compact model can be corrected, thereby achieving accurate prediction of the saturation current.

[0143] Example 2

[0144] This invention provides a layout optimization method, such as... Figure 6 As shown, it mainly includes the following steps:

[0145] Step 61: Based on the method provided in the foregoing embodiments, construct a physical model of the MOSFET saturation current of the current CMOS device, and use the physical model of the MOSFET saturation current of the current CMOS device to construct an initial CMOS device layout.

[0146] In this embodiment of the invention, the current CMOS device is the CMOS device to be optimized for layout, which can be selected by the user according to actual needs, and the invention does not impose any restrictions.

[0147] Step 62: Using hot signature technology, under deep inversion conditions of the device (generally taking the absolute value of the corresponding drain-source voltage), (At the maximum value) Measure the drain-source current and drain-source voltage data of CMOS devices with different communication lengths L and widths W, and construct a thermal signature map to identify the thermal failure boundary of the MOSFET saturation current physical model failure caused by self-heating effect.

[0148] Step 63: Based on the thermal failure boundary, optimize the initial CMOS device layout through geometric constraints so that the current CMOS device operates within the effective physical range.

[0149] The layout optimization method provided in this invention utilizes thermal signature technology to define the thermal failure boundary of the MOSFET saturation current physical model. By identifying the thermal failure region of the MOSFET saturation current physical model, a no-entry criterion is provided for subsequent layout optimization; considering that the model construction scheme has already been described in detail above, it will not be repeated here. The following mainly describes the preferred implementation methods for the subsequent two steps.

[0150] 1. Thermal failure boundary determination based on hot signature.

[0151] (1) Define thermal characteristic parameters:

[0152] ;

[0153] ;

[0154] in, Normalized output admittance (unit: mS / μm). Ms represents the normalized power density (unit: mW / μm), and both are thermal characteristic parameters. Ms stands for millisiemens, and mW stands for milliwatt; W is the channel width of the CMOS device. This is the drain-source current. This is the drain-source voltage. The symbol represents the partial derivative.

[0155] In this embodiment of the invention, the above-mentioned normalized power consumption density This method is suitable for comparing device families with the same process node, the same channel length L, and similar layout contact / metal coverage conditions. When comparing devices with different L values, the power per unit active area (P / Area) can be used as a thermal load indicator. Calculation notes: Due to noise in measured data, sliding window smoothing differentiation or local polynomial regression can be used for calculation. .

[0156] (2) Constructing thermal signature maps: Using the measured drain-source current and drain-source voltage data, and calculating the corresponding thermal signature maps respectively. and and with The horizontal axis is... Using the vertical axis, plot a family of curves for CMOS devices with different channel widths.

[0157] (3) Failure Judgment (Thermal Failure Boundary Detection of MOSFET Saturation Current Physical Model): When using the MOSFET saturation current physical model for specific circuit simulation and optimization design, thermal failure judgment needs to be performed on the corresponding CMOS device geometry (such as channel width W) in the circuit. This is to avoid severe self-heating effects caused by insufficient heat conduction when the CMOS device operates at low temperatures, which could lead to a decrease in the prediction accuracy of the MOSFET saturation current physical model or even failure, causing the actual circuit performance to deviate from the simulation design. Specifically, a CMOS device with a set channel width can be selected as the baseline. For the current CMOS device, based on its channel width, the corresponding family of curves of the CMOS device is read. If its normalized output admittance is... In the same If the drop in the baseline exceeds a preset threshold, the current CMOS device is determined to have entered the thermal failure zone, and the corresponding channel size needs to be further optimized (e.g., split into multiple parallel connections).

[0158] In this embodiment of the invention, a narrow-channel device can be selected as the reference line, for example, W = 0.25μm.

[0159] For example, 70% can be set as a preset threshold; of course, 70% is just an example value. In practical applications, this threshold can be determined by inversely calculating from the linearity indicators of the circuit design (such as P1dB, IIP3), the upper limit of allowable temperature rise, or the model prediction error tolerance.

[0160] It should be noted that, in this embodiment of the invention, CMOS devices with different channel lengths and widths are obtained under deep inversion conditions (generally, the absolute value of the corresponding drain-source voltage is taken). (at the maximum value) (i.e., drain-source current and drain-source voltage data), construct a thermal signature map, and use this as the basis for determining whether the MOSFET saturation current physical model falls into the thermal failure region.

[0161] The specific physical mechanism lies in the fact that, based on Debye's law, the specific heat capacity of silicon materials in a low-temperature vacuum environment... Relative to temperature The relationship is at an extremely low level. When the device enters the saturation region, the drain-source current increases significantly, leading to a surge in power consumption. Due to the severe heat dissipation bottleneck in the low-temperature vacuum environment, and the low specific heat capacity, the device is extremely sensitive to heat accumulation, resulting in the actual operating temperature of the active region being much higher than the ambient temperature. This significant self-heating effect renders the physical model of the extracted saturation current no longer applicable to the actual set temperature.

[0162] (4) Based on the failure determination results, determine the maximum gate width that maintains the accuracy of the MOSFET saturation current physical model, and denote it as the thermal failure boundary. .

[0163] 2. Layout optimization to suppress self-heating effect.

[0164] In this embodiment of the invention, a margin coefficient is introduced to account for engineering reliability margin. Define design rule thresholds ;in, To design a rule threshold, layout optimization is performed based on the design rule threshold; for example, a threshold can be taken as... .

[0165] Based on the above design rule threshold Geometric constraints are applied to the initial CMOS device layout to force the CMOS device to operate within the effective physical region of the model. Specifically:

[0166] (1) In the initial CMOS device layout, the total gate width of the CMOS device is decomposed into N parallel finger structures, and the width of each finger is constrained. .

[0167] In a preferred embodiment, it is possible to select To maximize the effective injection speed per unit width .

[0168] (2) Set the finger spacing in the initial CMOS device layout. ;in, To set the coefficients, the sensitivity analysis of the finger spacing or the thermal diffusion length of the thermal signature spectrum is used to determine the coefficients, which aims to block thermal crosstalk between adjacent fingers by utilizing the substrate thermal diffusion effect. This indicates the minimum value allowed by the design rule check.

[0169] For example, it can be set .

[0170] (3) In the initial CMOS device layout, the active regions of the source and drain are connected to the substrate ground ring through the bottom metal to build a low thermal resistance heat dissipation channel.

[0171] The above-mentioned solutions in the embodiments of the present invention have the following main advantages: (A1) Quantitative thermal management and layout linearity optimization: transforming implicit self-heating risks into quantifiable design rule thresholds. (A2) Improved circuit performance: This solution is expected to significantly reduce the risk of large-signal linearity degradation of cryogenic drivers and LNAs, providing reliable assurance for the design.

[0172] To visually demonstrate the effects of this invention, an example is provided below.

[0173] 1. Physical modeling and thermal failure boundary delineation.

[0174] First, based on the MOSFET saturation current physical modeling method, impedance analysis of the saturation region of the process test structure under 4K environment is performed to extract the physical parameters of the CMOS device. , , ), and corrected the compact model.

[0175] Subsequently, a hot signature graph is constructed, such as Figure 7 As shown. Test data indicates that, Figure 8 As shown, when the device width W = 1.0 μm, The retention rate is approximately 75%, which is still within a controllable range and is labeled as Critical / Stable. However, when the width increases to W = 5.0μm, the retention rate drops to 60%, which is below the set example failure threshold (70%), and is therefore judged as a failure and labeled as Failed.

[0176] like Figure 9 The image shows an analysis example after determining the thermal failure boundary. Based on this analysis, the thermal failure boundary of the model is determined. ≈1.2μm. To ensure design redundancy, this embodiment sets a design rule threshold. If the application scenario is switched to 20K or other temperature ranges, the aforementioned process must be recalibrated.

[0177] 2. Layout guidance parameters and structure optimization.

[0178] For total grid width For a 64μm qubit driver circuit, this embodiment generates an optimized layout structure according to the following rules:

[0179] (1) Geometric splitting rules: Set the width of a single finger In this embodiment, the following is selected: This value is much smaller than This divides the total width of 64μm into 128 parallel finger units. This number of divisions is based solely on... The calculation examples provided do not constitute a limitation on the number of fingers.

[0180] (2) Thermal isolation parameters: set the finger spacing This blocks thermal crosstalk.

[0181] (3) Vertical heat dissipation network: Construct a high-density contact hole and substrate grounding ring.

[0182] Based on the above examples, the following conclusions can be drawn:

[0183] Based on the construction of thermal signature maps and thermal failure boundary verification, the above layout structure significantly suppresses the local thermal accumulation effect that leads to output admittance collapse by constructing efficient heat dissipation channels. Theoretical derivation shows that, under the same power consumption, this structure can prevent the device from entering the strong nonlinear region (i.e., prevent...). (Excessive attenuation). This directly suppresses the nonlinear change in output impedance, thereby stabilizing the circuit gain and ensuring that the linearity of the low-temperature drive circuit under large signal swing can be accurately predicted by the established quasi-ballistic model, thus effectively solving the design problem of severe "model-to-measurement" distortion in the existing technology.

[0184] Through the above description of the embodiments, those skilled in the art can clearly understand that the above embodiments can be implemented by software, or by using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions of the above embodiments can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, mobile hard drive, etc.), including several instructions to cause a computer device (such as a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0185] Example 3

[0186] This invention also provides a MOSFET saturation current physical modeling system, which is mainly used to implement the method provided in Embodiment 1 above, such as... Figure 10 As shown, the system mainly includes:

[0187] The raw data extraction unit is used to measure CMOS devices in a temperature range below a set temperature to obtain raw current and voltage data; wherein, CMOS is complementary metal-oxide semiconductor.

[0188] The effective overdrive voltage extraction unit is used to preprocess the original voltage based on the effective mobility extraction technology in the linear region, and extract the source series resistance and the threshold voltage in the linear region; based on the threshold voltage in the linear region, the threshold voltage in the saturation region is extracted using the subthreshold characteristic, and the source potential is corrected by combining the source series resistance and the original current to obtain the effective overdrive voltage in the saturation region.

[0189] The model building unit is used to construct a physical model of the MOSFET saturation current of CMOS devices based on quasi-ballistic transport theory and combined with the effective overdrive voltage in the saturation region; wherein, the MOSFET saturation current physical model includes ballistic injection impedance and channel scattering impedance, and the MOSFET is a metal-oxide-semiconductor field-effect transistor.

[0190] The compact model correction unit is used to linearize the MOSFET saturation current physical model and extract the effective injection velocity and scattering parameters through regression calculation, thereby correcting the compact model.

[0191] Since the main technical details of this system have been described in detail in previous embodiments, they will not be repeated here.

[0192] Those skilled in the art will understand that, for the sake of convenience and brevity, the above division of functional units is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the system can be divided into different functional units to complete all or part of the functions described above.

[0193] Example 4

[0194] This invention also provides a layout optimization system, which is mainly used to implement the method provided in Embodiment 2 above, such as... Figure 11 As shown, the system mainly includes:

[0195] The model and initial layout building unit is used to build the MOSFET saturation current physical model of the current CMOS device, and to build the initial CMOS device layout using the MOSFET saturation current physical model of the current CMOS device.

[0196] The thermal failure boundary identification unit is used to measure the drain-source current and drain-source voltage data of CMOS devices with different communication lengths L and widths W under deep inversion conditions using thermal signature technology, and to construct a thermal signature map to identify the thermal failure boundary of the MOSFET saturation current physical model failure caused by self-heating effect.

[0197] The layout optimization unit is used to optimize the initial CMOS device layout based on thermal failure boundaries and geometric constraints, so that the current CMOS device operates within the effective physical range.

[0198] Since the main technical details of this system have been described in detail in previous embodiments, they will not be repeated here.

[0199] Those skilled in the art will understand that, for the sake of convenience and brevity, the above division of functional units is used as an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the system can be divided into different functional units to complete all or part of the functions described above.

[0200] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A physical modeling method for MOSFET saturation current, characterized in that, include: The raw current and voltage data of a CMOS device are obtained by measuring it in a temperature range below a set temperature; where CMOS is a complementary metal-oxide semiconductor. Based on the effective mobility extraction technique in the linear region, the original voltage is preprocessed to extract the source series resistance and the threshold voltage of the linear region. Based on the threshold voltage of the linear region, the threshold voltage of the saturation region is extracted using subthreshold characteristics. The source potential is then corrected by combining the source series resistance and the original current to obtain the effective overdrive voltage in the saturation region. This includes utilizing the horizontal offset between the subthreshold curves of the linear and saturation regions. Calculate the threshold voltage in the saturation region: ;in, The threshold voltage for the saturation region. The threshold voltage in the linear region; the source potential is corrected by combining the source series resistance. To obtain the effective overdrive voltage in the saturation region: ;in, This is the effective overdrive voltage in the saturation region; This is the drain-source current in the saturation region, which belongs to the original current; This is the gate-source voltage, which is the original voltage. The source series resistor; Based on quasi-ballistic transport theory and combined with the effective overdrive voltage in the saturation region, a physical model of MOSFET saturation current for CMOS devices is constructed. The MOSFET saturation current physical model includes ballistic injection impedance and channel scattering impedance. The MOSFET is a metal-oxide-semiconductor field-effect transistor. The physical model of MOSFET saturation current is linearized, and the effective injection velocity and scattering parameters are extracted through regression calculation, thereby correcting the compact model.

2. The physical modeling method for MOSFET saturation current according to claim 1, characterized in that, The physical model of MOSFET saturation current for CMOS devices, constructed based on quasi-ballistic transport theory and combined with effective overdrive voltage in the saturation region, includes: Based on quasi-ballistic transport theory, the saturation region characteristics of CMOS devices are modeled, and the total transport impedance Z in the MOSFET saturation region is divided into ballistic injection impedance and channel scattering impedance, expressed as: ； in, To inject impedance into the ballistic trajectory, Channel scattering impedance; For effective migration rate, Let W be the capacitance per unit area of ​​the gate oxide layer, W be the channel width of the CMOS device, and L be the channel length of the CMOS device. This is the effective overdrive voltage in the saturation region; For effective injection speed.

3. The physical modeling method for MOSFET saturation current according to claim 2, characterized in that, The linearization of the MOSFET saturation current physical model includes: Effective migration rate Determined by both surface roughness scattering and Coulomb scattering, it can be expressed as: ； in, and All are scattering parameters. The scattering parameters are the surface roughness parameters in the saturation region. Here, denoted as Coulomb scattering parameter in the saturation region, and B is the power-law parameter calculated based on the effective mobility extraction technique in the linear region. Combining the above equation, the physical model of MOSFET saturation current is linearized through algebraic transformation, and expressed as: ； in, This is the drain-source current in the saturation region, which is the original current.

4. The MOSFET saturation current physical modeling method according to claim 3, characterized in that, The extraction of effective injection velocity and scattering parameters through regression calculation includes: Define the dependent variable H, the independent variable X, and the slope term. With intercept term : ； ； ； ； The effective injection velocity and scattering parameters are extracted through the following multi-level linear regression operation: First-level regression: Based on obtaining the effective overdrive voltage and original current in the saturation region, linear fitting is performed on the dependent variable H and the independent variable X for CMOS devices with different channel lengths L, and the corresponding slope terms are fitted. With intercept term ; Second-order regression: Based on slope term The slope term is fitted to the relationship between the channel length L of the CMOS device and the CMOS device channel length L. Surface roughness scattering parameters in the saturation region With effective injection speed ; Third-level regression: Based on intercept term The relationship between the channel length L of the CMOS device and the intercept term is fitted. Coulomb scattering parameters in the saturation region .

5. A layout optimization method, characterized in that, include: Based on the method described in any one of claims 1 to 4, a physical model of the MOSFET saturation current of the current CMOS device is constructed, and an initial CMOS device layout is constructed using the physical model of the MOSFET saturation current of the current CMOS device. Using thermal signature technology, drain-source current and drain-source voltage data of CMOS devices with different communication lengths L and widths W are measured under deep inversion conditions. Thermal signature maps are constructed to identify thermal failure boundaries caused by the failure of the physical model of MOSFET saturation current due to self-heating effect. Based on the thermal failure boundary, the initial CMOS device layout is optimized through geometric constraints to ensure that the current CMOS device operates within the effective physical range.

6. The layout optimization method according to claim 5, characterized in that, The method of using thermal signature technology to identify the thermal failure boundary of the MOSFET saturation current physical model failure due to self-heating effect includes: Define thermal characteristic parameters: ； ； in, For normalized output admittance, Both are normalized power density parameters and thermal characteristic parameters; W is the channel width of the CMOS device. This is the drain-source current. This is the drain-source voltage. The sign for partial derivatives; Constructing a thermal signature map: Calculate the corresponding thermal signature using the measured drain-source current and drain-source voltage data. and and with The horizontal axis is... Using the vertical axis, plot a family of curves for CMOS devices with different channel widths; Failure determination: Select a CMOS device with a defined channel width as the baseline. For the current CMOS device, read the corresponding family of curves based on its channel width. If its normalized output admittance... In the same If the drop in the baseline exceeds a preset threshold, the current CMOS device is determined to have entered the thermal failure zone. Based on the failure assessment results, the maximum gate width that maintains the accuracy of the MOSFET saturation current physical model is determined and denoted as the thermal failure boundary. .

7. The layout optimization method according to claim 6, characterized in that, The optimization of the initial CMOS device layout based on thermal failure boundaries and geometric constraints includes: Introducing margin coefficient Define design rule thresholds ;in, To design the rule threshold, layout optimization is performed based on the design rule threshold: In the initial CMOS device layout, the total gate width of the CMOS device is decomposed into N parallel finger-like structures, and the width of each finger is constrained. ; In the initial CMOS device layout, the finger spacing is set as follows: ;in, The coefficients are determined by sensitivity analysis of the finger spacing or thermal diffusion length of the thermal signature spectrum. This indicates the minimum value allowed by the design rule check; In the initial CMOS device layout, the source and drain active regions are connected to the substrate ground ring via a contact hole array and a bottom metal layer.

8. A physical modeling system for MOSFET saturation current, characterized in that, To implement the method according to any one of claims 1 to 4, comprising: The raw data extraction unit is used to measure CMOS devices in a temperature range below a set temperature to obtain raw current and voltage data; wherein, CMOS is complementary metal-oxide semiconductor. The effective overdrive voltage extraction unit is used to preprocess the original voltage based on the effective mobility extraction technology in the linear region, and extract the source series resistance and the threshold voltage in the linear region; based on the threshold voltage in the linear region, the threshold voltage in the saturation region is extracted using the subthreshold characteristic, and the source potential is corrected by combining the source series resistance and the original current to obtain the effective overdrive voltage in the saturation region. The model building unit is used to construct a physical model of the MOSFET saturation current of CMOS devices based on quasi-ballistic transport theory and combined with the effective overdrive voltage in the saturation region; wherein, the MOSFET saturation current physical model includes ballistic injection impedance and channel scattering impedance, and the MOSFET is a metal-oxide-semiconductor field-effect transistor. The compact model correction unit is used to linearize the MOSFET saturation current physical model and extract the effective injection velocity and scattering parameters through regression calculation, thereby correcting the compact model.

9. A layout optimization system, characterized in that, To implement the method according to any one of claims 5 to 7, comprising: The model and initial layout building unit is used to build the MOSFET saturation current physical model of the current CMOS device, and to build the initial CMOS device layout using the MOSFET saturation current physical model of the current CMOS device. The thermal failure boundary identification unit is used to measure the drain-source current and drain-source voltage data of CMOS devices with different communication lengths L and widths W under deep inversion conditions using thermal signature technology, and to construct thermal signature maps to identify the thermal failure boundary of the MOSFET saturation current physical model failure caused by self-heating effect. The layout optimization unit is used to optimize the initial CMOS device layout based on thermal failure boundaries and geometric constraints, so that the current CMOS device operates within the effective physical range.

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