Integrated circuit automatic generation method based on circuit topological structure perception

Abstract

The invention discloses an integrated circuit automatic generation method and system based on circuit topological structure perception, a server and a storage medium. The method comprises the steps that an integrated circuit population to be subjected to simulation testing is determined; performing performance simulation on individuals in the integrated circuit population; judging whether a termination condition is met or not according to the performance evaluation result; if yes, outputting an individual with an optimal performance evaluation result as a circuit parameter configuration scheme; if not, individuals with the performance superior to the specified standard are screened out from the integrated circuit population to serve as parent individuals; segmenting the coding vectors of the parent individuals according to drive stage division, and selecting corresponding drive stage coding segments of different parent individuals for exchange to generate cross progenies; determining an adjustment priority of each component in the coding vector of the cross progeny, and adjusting the coding components with different priorities according to a preset rule of matching the priorities to generate a variation progeny; and performing performance simulation by taking the variation offspring as a new generation of integrated circuit population.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to an automated integrated circuit generation method, system, server, and storage medium based on circuit topology awareness. Background Technology

[0002] In the field of integrated circuit design, as chip manufacturing processes continue to evolve and circuit functionality becomes increasingly complex, the constraints on performance indicators such as timing, power consumption, and area of ​​target circuits are becoming more and more stringent. The traditional design mode that relies on engineers' experience to manually adjust MOS transistor parameters and driver stage configuration has problems such as low efficiency, limited parameter optimization dimensions, and difficulty in balancing multiple performance constraints. It can no longer meet the needs of automated and high-precision design of large-scale integrated circuits. Therefore, automated generation methods of integrated circuit parameters based on intelligent optimization technologies such as evolutionary algorithms have become a key research focus in the industry.

[0003] Currently, mainstream automated optimization schemes for integrated circuit parameters are based on general evolutionary algorithms (such as genetic algorithms and particle swarm optimization). These methods abstract integrated circuit parameters into general encoded vectors and iteratively optimize through operations such as random crossover and mutation, relying on global random search to find the optimal solution. This approach is detached from knowledge of circuit design, and is prone to blindly adjusting critical path parameters that determine the core performance of the circuit. This leads to frequent performance drops or non-physical implementation issues in mutated offspring, a high proportion of ineffective iterations, and low optimization efficiency.

[0004] Therefore, reducing the proportion of invalid iterations and improving the efficiency and practicality of automated integrated circuit parameter generation are problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide an automated generation method, system, server and storage medium for integrated circuits based on circuit topology awareness. This method deeply integrates circuit topology characteristics and process rule constraints into the evolutionary algorithm. By performing differentiated optimization operations on the encoding vector, it can reduce the proportion of invalid iterations and improve the efficiency and practicality of automated generation of integrated circuit parameters.

[0006] In a first aspect, embodiments of this application provide an automated integrated circuit generation method based on circuit topology awareness, comprising: The population of integrated circuits to be simulated and tested is determined; the population of integrated circuits is a set of encoded vectors used to describe the parameters of the integrated circuits, generated based on the topology information and performance constraints of the target circuit; the topology information includes driver level partitioning; Performance simulations were performed on individuals within the integrated circuit population to obtain performance evaluation results for the associated performance constraints. Determine whether the termination conditions are met based on the performance evaluation results; If satisfied, output the individual with the best performance evaluation result as the circuit parameter configuration scheme; If the performance is not met, individuals with performance superior to the specified standard are selected from the integrated circuit population as parent individuals based on the performance evaluation results. Based on the driver-level partitioning, the encoding vectors of the parent individuals are segmented, and the corresponding driver-level encoding segments of different parent individuals are selected and swapped to generate crossover offspring. The adjustment priority of each component in the encoding vector of the crossover offspring is determined, and the encoding components with different priorities are adjusted according to the preset rules of matching priority to generate mutated offspring. The mutated offspring are used as a new generation of integrated circuit population, and the step of performing performance simulation on all individuals within the integrated circuit population is performed.

[0007] In one embodiment, the adjustment priority of each component in the coding vector of the crossover descendant is determined, and the coding components with different priorities are adjusted according to a preset rule of matching priority, including: Based on the performance simulation results, identify the critical and non-critical paths of the circuit corresponding to the cross-descendant; The coding components of the critical path are adjusted according to a first rule, and the coding components of the non-critical path are adjusted according to a second rule. Mutant offspring are generated based on the adjusted coding components. The adjustment step size of the first rule is smaller than that of the second rule.

[0008] In one embodiment, the encoded components of the critical path are adjusted according to a first rule, including: Extract the current parameter values, path identification information, and path delay values ​​of the MOS transistor encoded components of the critical path; Calculate the difference between the path delay value and the delay threshold in the performance constraint; The corresponding adjustment coefficient is determined based on the difference; wherein the difference is positively correlated with the adjustment coefficient. Multiply the current parameter value by the adjustment coefficient to obtain the first adjustment step size; The coded components of the critical path are adjusted to reduce latency based on the first adjustment step size, thereby generating the adjusted critical path coded components.

[0009] In one embodiment, the encoded components of the non-critical path are adjusted according to a second rule, including: Extract the current parameter values ​​of the MOS transistor encoding components of the non-critical path and the performance redundancy of the path; The second adjustment step size is determined based on the performance redundancy; wherein the performance redundancy is positively correlated with the second adjustment step size. The coded components of the non-critical path are randomly adjusted according to the second adjustment step size to generate the adjusted coded components of the non-critical path.

[0010] In one embodiment, after randomly adjusting the encoded components of the non-critical path according to the second adjustment step size, the method further includes: Verify whether the adjusted parameters conform to the preset process rules; The parameters that pass the verification are used as the adjusted non-critical path coding components.

[0011] In one embodiment, determining the population of integrated circuits to be simulated includes: Obtain the topology information and performance constraints of the target circuit; the topology information includes the MOS transistor connection relationships and driver stage division; A circuit parameter encoding vector is constructed based on the topology information; the encoding vector includes the width and length parameters, relative size scaling factor, and drive strength level identifier corresponding to the MOS transistors and drive stages in the topology. Based on the performance constraints, the value range of each component of the encoding vector is determined, and an initial population composed of the encoding vector is generated as the integrated circuit population.

[0012] In one embodiment, determining whether the termination condition is met based on the performance evaluation result includes: Calculate the deviation between the individual with the best performance evaluation result and the performance constraints; Determine the current iteration number; Calculate the change in evaluation result of the individual with the best performance evaluation result within the most recent consecutive preset algebras; If any preset condition is met, the termination condition is determined to be met; the preset conditions include: the deviation value does not exceed a preset deviation threshold, the number of iterations reaches a preset maximum number of iterations, and the change in the evaluation result does not exceed a preset change threshold.

[0013] Secondly, embodiments of this application provide an automated integrated circuit generation system based on circuit topology awareness, comprising: A population determination module is used to determine the population of integrated circuits to be simulated and tested; the integrated circuit population is a set of encoded vectors generated based on the topology information and performance constraints of the target circuit, used to describe the parameters of the integrated circuit; the topology information includes driver level partitioning; The performance simulation module is used to perform performance simulation on individuals within the integrated circuit population and obtain performance evaluation results of associated performance constraints. The termination judgment module is used to determine whether the termination condition is met based on the performance evaluation result; if it is met, the configuration output module is triggered; if it is not met, the parent filtering module is triggered. The configuration output module is used to output the individual with the best performance evaluation result as the circuit parameter configuration scheme. The parent selection module is used to select individuals with performance superior to a specified standard from the integrated circuit population as parent individuals based on the performance evaluation results. The crossover generation module is used to segment the encoding vector of the parent individual according to the driving level partition, and select the corresponding driving level encoding segments of different parent individuals to exchange, thereby generating crossover offspring. The mutation generation module is used to determine the adjustment priority of each component in the encoding vector of the crossover offspring, adjust the encoding components with different priorities according to the preset rules of matching priority, and generate mutated offspring; the mutated offspring are used as a new generation of integrated circuit population to trigger the performance simulation module.

[0014] Thirdly, embodiments of this application provide a server, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the program, it implements the steps of the automated generation method for integrated circuits based on circuit topology awareness.

[0015] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, characterized in that, when the program is executed by a processor, it implements the steps of the automated integrated circuit generation method based on circuit topology awareness.

[0016] This application provides an automated integrated circuit generation method based on circuit topology awareness. It acquires an integrated circuit population generated according to the topology information and performance constraints of the target circuit, ensuring that the circuit corresponding to each encoding vector conforms to both architectural logic and performance feasibility. Then, it performs performance simulation on individuals within the population and obtains evaluation results. If the performance evaluation results meet the termination conditions, it outputs the individual with the best performance evaluation result as the circuit parameter configuration scheme. This individual has passed population evolution screening and performance constraint verification and can be used as a feasible circuit parameter configuration scheme. If the performance evaluation results do not meet the termination conditions, it selects high-quality individuals based on the performance evaluation results, retaining high-quality genes in the population to provide a high-starting-point parent for subsequent crossover and mutation, and then uses this as a driving force. The system is divided into segments, and the corresponding driver-level coding segments of different parent generations are swapped. This not only accurately integrates the performance advantages of different parent generations at specific driver levels, but also avoids random crossover from disrupting the internal parameter synergy of the driver level. It ensures that the crossover offspring conform to the circuit topology logic. Priorities are assigned based on the weight of the parameters' impact on performance, and differentiated adjustments are made to reduce the waste of resources from blind mutations. Mutated offspring are generated and used as a new population for cyclical simulation. Each generation inherits the superior features of the previous generation and explores new parameter combinations, gradually breaking through the local optimum trap and bringing the population performance closer to the global optimum. Multiple rounds of simulation evaluation and evolutionary screening ensure that the final output scheme has both optimal performance and stable deployment capability, which can be directly adapted to the engineering requirements of integrated circuit design, reducing R&D costs and tape-out risks.

[0017] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0018] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart illustrating an automated integrated circuit generation method based on circuit topology awareness provided in an embodiment of this application is shown. Figure 2 This illustration shows a schematic diagram of an automated integrated circuit generation system based on circuit topology awareness, provided in an embodiment of this application. Figure 3 A schematic diagram of the structure of a server computer system provided in an embodiment of this application is shown. Detailed Implementation

[0019] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present application will now be described in detail with reference to the accompanying drawings and embodiments. Although the embodiments of this application provide method operation instruction steps as shown in the following embodiments or drawings, more or fewer operation instruction steps may be included in the method based on conventional or non-inventive effort. In steps where there is no logically necessary causal relationship, the execution order of these steps is not limited to the execution order provided in the embodiments of this application. In actual processing or when the device executes, the method may be executed sequentially or in parallel according to the method shown in the embodiments or drawings.

[0021] Example 1: This embodiment proposes an automated integrated circuit generation method based on circuit topology awareness. Please refer to [link / reference]. Figure 1 , Figure 1 A flowchart illustrating the automated integrated circuit generation method based on circuit topology awareness provided in this embodiment is shown. Figure 1 As shown, the method mainly includes: Step 101: Determine the population of integrated circuits to be simulated and tested.

[0022] Determine the population of integrated circuits to be used for simulation testing, i.e., the set of candidate design schemes.

[0023] An integrated circuit population is generated based on the topological information and performance constraints of the target circuit. The integrated circuit population is represented as a set of coded vectors. Each vector converts the adjustable parameters of the circuit (such as transistor aspect ratio, driver unit size, wiring parameters, etc.) into a numerical sequence that can be recognized by a computer through specific coding rules.

[0024] The core basis for generating this population includes two aspects: first, the topological structure information of the target circuit, namely the module connection relationship and hierarchical architecture (especially the driver level partitioning, such as the cascaded structure of multi-level buffers and the distribution rules of units with different drive strengths), which determine the basic architecture for the realization of circuit functions; second, performance constraints, namely the performance boundaries that the circuit must meet (such as maximum delay, power consumption limit, area constraints, etc.). By using the architectural rules limited by the topology and the boundary conditions of performance constraints as the basis for generation, it is ensured that the circuit design corresponding to each encoding vector in the population not only meets the architectural requirements for the realization of basic functions, but also falls within the feasible performance parameter range.

[0025] Step 102: Perform performance simulation on individuals within the integrated circuit population to obtain performance evaluation results of associated performance constraints.

[0026] For each individual within the integrated circuit population (i.e., the circuit design corresponding to each coding vector), multi-dimensional performance simulation tests are performed using electronic design automation (EDA) simulation tools (such as SPICE, Spectre, etc.) to obtain its actual performance data (such as delay, power consumption, area, noise margin, etc.) under preset operating conditions (such as typical process corners, voltage, and temperature combinations). These performance data are then compared with pre-set performance constraints (such as delay ≤ 5ns, power consumption ≤ 10mW, area ≤ 1000μm). 2 Correlation analysis is performed to generate quantitative evaluation results that include the actual values ​​of each performance index, the deviation from the constraints, and whether the constraints are met. Actual performance data obtained through simulation (rather than theoretical estimates) reflects the circuit's performance under operating conditions, avoiding misjudgments caused by a disconnect between parameter combinations and actual performance, and achieving accurate performance quantification.

[0027] For example, the evaluation results for an individual might be a delay of 4.8 ns (meeting the constraint), a power consumption of 11.2 mW (exceeding the constraint by 1.2 mW), and an area of ​​950 μm. 2 (Constraints are satisfied).

[0028] Step 103: Determine whether the termination condition is met based on the performance evaluation results; if it is met, proceed to step 104; if it is not met, proceed to step 105.

[0029] Step 104: Output the individual with the best performance evaluation result as the circuit parameter configuration scheme.

[0030] Step 105: Based on the performance evaluation results, select individuals from the integrated circuit population whose performance is superior to the specified standard as parent individuals.

[0031] The merging of steps 103 to 105 will be described here.

[0032] The current performance evaluation result is verified based on the preset termination conditions. This embodiment does not limit the specific rules for setting the termination conditions; they can be set according to the needs of the actual application scenario. Optionally, a termination condition can be set based on three indicators: the deviation between the optimal individual and the performance constraints, the number of iterations, and the change in the evaluation result.

[0033] Specifically, it includes the following sub-steps: calculating the deviation between the individual with the best performance evaluation result and the performance constraints (such as the actual difference between core indicators such as latency and power consumption and the constraint threshold); determining the current iteration number; and calculating the change in the evaluation result of the individual with the best performance evaluation result in the most recent consecutive preset number of generations.

[0034] If any of the preset conditions are met, the termination condition is determined to be met; the preset conditions include: the deviation value does not exceed the preset deviation threshold, the number of iterations reaches the preset maximum number of iterations, and the change in the evaluation result does not exceed the preset change threshold.

[0035] The termination condition, through a combination of multi-dimensional conditions, can establish a balance between achieving the target performance, controlling computational resources, and maximizing optimization efficiency, avoiding optimization inaccuracies or resource waste caused by a single condition. This embodiment only uses this termination condition as an example for introduction; the setting of other termination conditions can refer to the introduction of this embodiment, and will not be repeated here.

[0036] If the termination condition is met, it indicates that the optimization has achieved the expected goal (such as finding a solution that meets all constraints and has the best performance). Then, step 104 is executed, and the individual with the best performance evaluation result in the population (i.e. the circuit parameter configuration with the best overall performance) is output as the final circuit parameter configuration scheme.

[0037] If the termination condition is not met, it indicates that there is still room for optimization. Then, proceed to step 105, and set clear screening criteria based on the performance evaluation results, such as performance indicators being better than the average level of the population and the satisfaction of key constraints being higher than a certain threshold. Select high-quality individuals that meet the criteria from the current population as parent individuals. By selecting high-quality individuals as parents, and by retaining the parameter combination features with better performance, we can provide evolutionary advantages for the next generation of the population, promote the overall performance of the population to develop in a better direction, avoid the low optimization efficiency caused by randomly generating new individuals, and at the same time significantly improve the convergence speed.

[0038] Step 106: Based on the driver-level partitioning, segment the encoding vector of the parent individual, and select the corresponding driver-level encoding segments of different parent individuals to exchange, generating crossover offspring.

[0039] Based on the driver level division rules of the target circuit, the selected parent individuals (high-quality circuit parameter encoding vectors) are split into multiple independent encoding segments according to the parameter range corresponding to the driver level. For example, if the circuit is divided into 3 levels of driver units, the encoding vector is split into the first level driver parameter segment, the second level driver parameter segment, and the third level driver parameter segment.

[0040] Subsequently, the coding segments corresponding to the same driving level are selected and exchanged between different parent individuals. For example, the second-level driving coding segment of parent A is swapped with the second-level driving coding segment of parent B. Through this corresponding hierarchical directional exchange, a new coding vector with the high-quality parameter features of different parents is generated, which is called the crossover offspring.

[0041] The partitioning of driver levels in integrated circuits is based on key topology designs for circuit function implementation (such as multi-level drivers needing to meet rules like signal timing matching and progressive load driving capability). The parameters of each driver level (such as transistor aspect ratio and cell size) form a cohesive whole. In this step, driver level segmentation and crossover are performed to achieve the reorganization of high-quality parameters while preserving the rationality of the circuit topology. This ensures that the offspring inherit the advantages of the parent generation while conforming to the basic logic of circuit function implementation. Different parent generations may have performance advantages in different driver levels. For example, parent A may have the best latency in its first-level driver, while parent B may have the best power consumption in its second-level driver. The exchange of corresponding driver level coding segments can accurately combine these advantageous features into the same offspring, achieving performance complementarity between latency and power consumption advantages, and accelerating the overall performance improvement of the population.

[0042] Step 107: Determine the adjustment priority of each component in the coding vector of the crossover offspring, adjust the coding components with different priorities according to the preset rules of matching priority, and generate mutated offspring; take the mutated offspring as the new generation of integrated circuit population, and jump to step 102.

[0043] For the coding vector of the crossover descendants, the adjustment priority of each component is first determined based on the influence weight of each coding component (adjustable parameters of an individual circuit, such as transistor aspect ratio, driver stage cell size, wiring width, etc.) on the target performance constraints (such as delay, power consumption, area), combined with the circuit topology (such as the core driver cell parameters having higher priority than auxiliary cells in driver stage partitioning). For example, the core driver stage aspect ratio, which plays a decisive role in delay, is set to the highest priority, while the wiring spacing of auxiliary cells, which has a negligible impact on area, is set to a low priority.

[0044] Then, modifications are executed according to the preset adjustment rules based on priority, with higher priority components having smaller adjustment ranges than lower priority components. High-priority components are adjusted with small amplitude and high precision, such as ±3% to ±5% parameter increments, to avoid damaging core performance; lower-priority components can be adjusted with larger amplitudes or assigned random values ​​within a limited range, such as ±10% to ±15% fluctuations, to explore more design space and ultimately generate new encoding vectors with better performance or more parameter diversity, i.e., mutated offspring.

[0045] High-priority parameters correspond to key factors affecting performance constraints. For example, when latency is not met, driver-level parameters are adjusted first. Targeted adjustments can directly address bottlenecks, avoid ineffective mutations that consume resources, and accelerate the convergence of the population towards the performance target. Meanwhile, small adjustments to core parameters can avoid functional failures or precipitous performance drops caused by parameter mutations, ensuring that mutated offspring conform to circuit topology rules and basic performance requirements. At the same time, wide-range adjustments to low-priority parameters can retain the possibility of exploring new parameter combinations (avoiding the population getting trapped in local optima) without affecting the core optimization direction, achieving a balance between precise optimization and space exploration, and improving the global optimality of the final solution.

[0046] The mutated offspring individuals generated through mutation are integrated into a new generation of integrated circuit population. Then, the process jumps back to step 102, where the mutated offspring from the previous evolutionary round serve as the starting point for the next round of optimization, undergoing performance simulation verification again. The evaluation results are used again to determine whether the termination condition is met, or to further screen parent generations and generate new crossover and mutated offspring, forming a cyclical iterative optimization loop. Each generation of the population inherits the superior parameter characteristics of the previous generation, while simultaneously exploring the unknown design space through new mutations, allowing the population performance to gradually approach the global optimum through multiple iterations.

[0047] Based on the above introduction, the integrated circuit automated generation method based on circuit topology awareness provided in this embodiment obtains an integrated circuit population generated according to the topology information and performance constraints of the target circuit, ensuring that the circuit corresponding to each encoding vector conforms to the architectural logic and is within the performance feasible range. Then, performance simulation is performed on individuals within the population to obtain evaluation results. If the performance evaluation result meets the termination condition, the individual with the best performance evaluation result is output as the circuit parameter configuration scheme. This individual has passed population evolution screening and performance constraint verification and can be used as a feasible circuit parameter configuration scheme. If the performance evaluation result does not meet the termination condition, high-quality individuals are selected based on the performance evaluation result, retaining high-quality genes in the population to provide a high-starting-point parent generation for subsequent crossover and mutation. The driver level is then used as the segmentation basis. The corresponding driver level coding segments of different parents are swapped. This can not only accurately integrate the performance advantages of different parents in a specific driver level, but also avoid random crossover from destroying the internal parameter coordination of the driver level. This ensures that the crossover offspring conform to the circuit topology logic. Priorities are divided according to the weight of the parameter's impact on performance, and differentiated adjustments are made to reduce the waste of resources from blind mutation. Mutated offspring are generated and used as a new population for cyclic simulation. Each generation inherits the superior features of the previous generation and explores new parameter combinations, gradually breaking through the local optimum trap and making the population performance approach the global optimum. Multiple rounds of simulation evaluation and evolutionary screening ensure that the final output scheme has both optimal performance and stable implementation capability. It can be directly adapted to the engineering requirements of integrated circuit design, reducing R&D costs and tape-out risks.

[0048] Example 2: The above embodiments do not limit the rules for adjusting the coding components of the crossover offspring. To resolve the contradiction between stability and exploration in mutation operations, this embodiment proposes an adjustment method. Step 107 determines the adjustment priority of each component in the coding vector of the crossover offspring, and adjusts the coding components with different priorities according to the preset rules of matching priority. Specifically, it can be executed according to the following sub-steps: Step 71: Identify the critical and non-critical paths of the circuit corresponding to the cross descendants based on the performance simulation results.

[0049] The critical path is the core support for circuit performance (such as delay and timing convergence). If its parameters are significantly adjusted, it may destroy the high-quality performance characteristics formed by the crossover offspring (such as the critical path that originally met the timing constraints causing delay to exceed the limit due to parameter mutation). On the other hand, the non-critical path has a limited impact on the core performance constraints. If only a small adjustment is made, it is difficult to explore new parameter combinations through mutation, which may cause the population to fall into a local optimum.

[0050] In this embodiment, when generating mutated offspring, the critical paths that play a decisive role in the overall performance of the circuit corresponding to the crossover offspring are first identified through performance simulation results. For example, the signal transmission path that determines the maximum delay of the circuit may significantly affect the overall timing if its parameters change slightly. In contrast, the non-critical paths that have a weaker impact on performance, such as redundant logic or auxiliary function paths, have limited impact on the core performance constraints due to parameter fluctuations.

[0051] In this embodiment, the evaluation criteria and evaluation indicators for critical paths and non-critical paths are not limited, and can be set according to the needs of actual application scenarios.

[0052] Step 72: Adjust the coding components of the critical path according to the first rule, and adjust the coding components of the non-critical path according to the second rule, and generate mutated offspring based on the adjusted coding components.

[0053] The coding components corresponding to the critical path (such as the aspect ratio of the transistors and the size of the driving unit on the path) are adjusted using the first rule, and the coding components corresponding to the non-critical path are adjusted using the second rule, ultimately forming a variant offspring that balances performance stability and design exploration.

[0054] Among them, the adjustment step size of the first rule is smaller than that of the second rule. The first rule is a small and precise adjustment of ±2% to ±3%; the second rule is an adjustment of a larger magnitude of ±10% to ±15% or a random change within a limited range.

[0055] Small step size adjustments on critical paths can avoid the damage to the core performance of the circuit caused by parameter mutations, ensure that mutated offspring inherit the high-quality performance foundation of crossover offspring, and reduce the risk of performance degradation caused by mutations; large step size adjustments on non-critical paths can more effectively break through the limitations of local parameter combinations, explore potential optimization directions, and introduce new performance improvement possibilities for the population.

[0056] The coding component adjustment method provided in this embodiment can make each round of mutation more closely match the actual needs of circuit performance improvement, thereby accelerating the convergence of the population to the global optimal solution.

[0057] Example 3: In Example 2, the specific rules for the first rule used to adjust the coding components of critical paths and the second rule used to adjust the coding components of non-critical paths are not limited. This example introduces an adjustment method for the first and second rules to adapt to different types of paths and achieve precise matching of adjustment intensity with optimization needs.

[0058] Specifically, a method for adjusting the coded components of the critical path according to the first rule can be performed according to the following sub-steps: Step 721: Extract the current parameter values, path identification information, and path delay values ​​of the MOS transistor encoding components of the critical path.

[0059] From the performance simulation results of the crossover descendant coding vector and the corresponding circuit, three types of core information are accurately extracted: First, the current parameter values ​​of the MOS transistor coding components on the critical path, that is, the specific parameter values ​​of the corresponding MOS transistor in the coding vector, such as the actual values ​​of adjustable parameters such as aspect ratio, threshold voltage, and gate oxide thickness; Second, path identification information, which is the feature data used to uniquely distinguish the critical path, such as the sequence of modules included in the path, the logic unit numbers of the start and end points, and the timing constraint type, to ensure accurate location of the target path in multi-critical-path scenarios; Third, the path delay value, which is the actual signal transmission delay of the critical path measured through performance simulation, and is the direct basis for evaluating whether its performance meets the standards.

[0060] Step 722: Calculate the difference between the path delay value and the delay threshold in the performance constraints.

[0061] Step 723: Determine the corresponding adjustment coefficient based on the difference.

[0062] The merging of steps 722 and 723 will be described here.

[0063] If the critical path delay exceeds the limit by too much, a small adjustment may not be enough to bring the delay to the target within a limited number of iterations, resulting in low optimization efficiency. If the delay is only slightly exceeded, an excessive adjustment may reduce the delay too much, but cause other performance indicators (such as a surge in power consumption due to increased transistor size or area exceeding the limit) to deteriorate. To address this, this embodiment binds the difference to the adjustment coefficient, so that the adjustment intensity is precisely adapted to the performance gap, achieving on-demand adjustment.

[0064] Specifically, first calculate the difference between the actual path delay value of the critical path and the preset delay threshold (such as the maximum allowable delay of the circuit) in the performance constraints. If the delay value is greater than the threshold, the difference is positive, representing the delay overshoot; if it is less than the threshold, the difference is negative, representing the delay redundancy.

[0065] Then, the corresponding adjustment coefficient is determined based on the absolute value of this difference. For example, the coefficient is 1.1 when the difference is 5ns and 1.03 when the difference is 1ns. The difference and the adjustment coefficient are positively correlated, that is, the more the delay exceeds the limit (the larger the difference), the larger the adjustment coefficient; the less the delay exceeds the limit (the smaller the difference), the smaller the adjustment coefficient.

[0066] Step 724: Multiply the current parameter value by the adjustment coefficient to obtain the first adjustment step size.

[0067] Step 725: Based on the first adjustment step size, perform targeted adjustment on the coding components of the critical path to reduce latency, and generate the adjusted critical path coding components.

[0068] The merging of steps 724 and 725 will be described here.

[0069] Based on the current parameter values ​​(such as transistor aspect ratio, drive strength, etc.) of the MOS transistor encoding components on the critical path, multiply them by the adjustment coefficient determined in the previous stage based on the delay difference to obtain the first adjustment step size, that is, the specific magnitude of parameter adjustment. For example, when the current aspect ratio is 10μm / 0.5μm and the adjustment coefficient is 1.05, the step size corresponds to an increment of 0.5μm, and the new parameter value is 10.5μm / 0.5μm.

[0070] Subsequently, based on this step size, the coding components of the critical path are modified in a targeted manner. All adjustments are aimed at reducing path delay. For example, the on-resistance is reduced and the driving capability is enhanced by increasing the width-to-length ratio of the MOS transistor, or the switching delay is reduced by adjusting the threshold voltage, thereby generating the adjusted critical path coding components.

[0071] This adjustment method uses the positive correlation between latency difference and adjustment coefficient to ensure that the adjustment of critical path parameters is precisely matched to the performance gap, avoiding under- or over-optimization. At the same time, with the goal of reducing latency, combined with a step size that is suitable for the current parameters, it can efficiently optimize the performance of the critical path while taking into account the overall performance balance.

[0072] A method for adjusting the encoded components of non-critical paths according to the second rule can be performed by the following sub-steps: Step 726: Extract the current parameter values ​​of the MOS transistor encoding components of non-critical paths and the performance redundancy of the paths.

[0073] Step 727: Determine the second adjustment step size based on performance redundancy.

[0074] The merging of steps 726 and 727 will be described here.

[0075] Although non-critical paths do not determine the core performance of the circuit, they have optimization potential. In this embodiment, the current parameter values ​​of the MOS transistor encoding components on the non-critical paths (such as the actual values ​​of aspect ratio, drive strength, etc.) and the performance redundancy of the path are first extracted, that is, the difference between the actual performance indicators and the constraints, such as the margin for delay below the threshold and the space for power consumption below the upper limit, reflecting the degree of redundancy in the path performance.

[0076] The second adjustment step size is determined based on the magnitude of the performance redundancy. For example, when the redundancy is 50%, the step size is set to ±15%, and when the redundancy is 10%, the step size is set to ±3%. The performance redundancy is positively correlated with the second adjustment step size. The higher the path performance redundancy (the larger the margin), the larger the adjustment step size; the lower the redundancy (the smaller the margin), the smaller the adjustment step size.

[0077] Redundancy-based step size design ensures that modifications to non-critical path parameters are always within the safe boundaries of performance constraints, avoiding new performance bottlenecks caused by adjustments. Without affecting the core performance of the critical path, the redundancy space of the non-critical path is used for targeted optimization, achieving overall improvement in indicators such as circuit area and power consumption, and enhancing the overall cost-effectiveness of the design solution.

[0078] Step 728: Randomly adjust the coding components of non-critical paths according to the second adjustment step size to generate adjusted non-critical path coding components.

[0079] Based on the determined second adjustment step size, the coding components of non-critical paths are randomly modified within the step size range. For example, when the step size is ±10%, the parameter values ​​may be randomly increased by 8% or decreased by 5%, and finally the adjusted non-critical path coding components are generated.

[0080] Random adjustments can break through the limitations of fixed patterns and explore more potential high-quality parameter combinations. The second adjustment step size has been limited to a safety boundary based on redundancy to avoid over-adjustment that could turn non-critical paths into new performance bottlenecks.

[0081] Furthermore, after randomly adjusting the coding components of the non-critical path according to the second adjustment step size in step 728, it is possible to verify whether the adjusted parameters conform to the preset process rules. Then, only the parameters that pass the verification are used as the adjusted non-critical path coding components. By introducing preset process rules to verify the adjusted parameters, only parameters that fully conform to the process rules are retained as the final adjusted non-critical path coding components, and invalid adjustment results that violate the rules are eliminated, ensuring that the parameter adjustment results have both performance rationality and manufacturing feasibility. Of course, this step can also be omitted, and this embodiment does not limit this.

[0082] Example 4: The integrated circuit population is generated based on the topology information and performance constraints of the target circuit. However, the generation method is not limited in the above embodiments. To improve the overall automation level, this embodiment proposes a generation method. Step 101, determining the integrated circuit population in the integrated circuit population to be simulated and tested, can be automatically generated according to the following sub-steps: Step 11: Obtain the topology information and performance constraints of the target circuit.

[0083] Topology information includes MOSFET connections and driver stage partitioning; First, obtain the core basic information of the target circuit (design target circuit), including the topological structure information that defines the circuit functional architecture (including the connection logic relationship between MOS transistors and the driver stage division to ensure effective signal transmission), as well as the performance constraints of the design target (such as delay upper limit, power consumption threshold, area limit, etc.).

[0084] Step 12: Construct circuit parameter encoding vectors based on topology information.

[0085] Using topology information as a blueprint, the adjustable key parameters in the circuit are transformed into structured encoded vectors. The vectors not only contain the width and length parameters directly corresponding to each MOS transistor (which determine the transistor's driving capability), but also incorporate relative size ratio coefficients that reflect the size coordination between driving stages (to ensure performance matching of multi-level driving units) and driving strength level identifiers that identify the driving capability level (corresponding to driving configurations for different load requirements), thus achieving a one-to-one mapping between parameters and circuit structure.

[0086] Step 13: Determine the value range of each component of the encoding vector based on performance constraints, and generate an initial population composed of encoding vectors as the integrated circuit population.

[0087] Based on performance constraints, a reasonable range of values ​​is set for each component of the encoding vector (such as aspect ratio and scaling factor) (e.g., aspect ratio not exceeding 50, driving strength level not less than 3). Based on this range of values, multiple compliant encoding vectors are randomly generated to form an initial population, which serves as the population of integrated circuits to be simulated and tested.

[0088] This integrated circuit population generation method constructs encoding vectors based on topology, fully covering key parameters of MOS transistors and driver stages. This ensures that the initial population individuals conform to the circuit functional architecture, avoiding invalid structural designs from the source. At the same time, by combining performance constraints to limit the range of parameter values, out-of-bounds individuals are screened out in advance, which can reduce the waste of subsequent simulation resources and lay a high-quality starting point for iterative optimization.

[0089] Example 5: This embodiment provides an automated integrated circuit generation system based on circuit topology awareness, such as... Figure 2 As shown, the system mainly includes: a population determination module 201, a performance simulation module 202, a termination judgment module 203, a configuration output module 204, a parent selection module 205, a crossover generation module 206, and a mutation generation module 207.

[0090] Among them, the population determination module 201 is used to determine the population of integrated circuits to be simulated and tested; the integrated circuit population is a set of encoded vectors generated based on the topology information and performance constraints of the target circuit, used to describe the parameters of the integrated circuit; the topology information includes driver level partitioning; The performance simulation module 202 is used to perform performance simulation on individuals within the integrated circuit population and obtain performance evaluation results of associated performance constraints. The termination judgment module 203 is used to determine whether the termination condition is met based on the performance evaluation result; if it is met, the configuration output module 204 is triggered; if it is not met, the parent filtering module 205 is triggered. The configuration output module 204 is used to output the individual with the best performance evaluation result as the circuit parameter configuration scheme. The parent selection module 205 is used to select individuals with performance superior to a specified standard from the integrated circuit population as parent individuals based on the performance evaluation results. The crossover generation module 206 is used to segment the encoding vector of the parent individual according to the driver level partition, and select the corresponding driver level encoding segments of different parent individuals to exchange and generate crossover offspring. The mutation generation module 207 is used to determine the adjustment priority of each component in the encoding vector of the crossover offspring, and adjust the encoding components with different priorities according to the preset rules of matching priority to generate mutated offspring; the mutated offspring are used as a new generation of integrated circuit population to trigger the performance simulation module 202.

[0091] It should be noted that the integrated circuit automated generation system based on circuit topology awareness provided in this embodiment and the integrated circuit automated generation method based on circuit topology awareness provided in the above embodiments can be referred to each other, and the repeated parts will not be repeated in this embodiment.

[0092] In the integrated circuit automated generation system based on circuit topology awareness provided in this embodiment, the population determination module generates encoding vectors based on the topology, ensuring the rationality of the circuit structure from the source; the crossover generation module exchanges encoding segments in a driver-level direction, accurately integrating the advantages of the parent generation while avoiding structural failure; the mutation generation module adjusts parameters based on priority differentiation, achieving precise optimization of critical paths and efficient exploration of non-critical paths; combined with quantitative evaluation of performance simulation, multi-dimensional control of termination judgment, and preservation of high-quality genes by parent generation selection, the system can not only avoid subjective biases caused by human intervention throughout the process, but also accelerate the convergence of the population to the optimal performance through directed evolution. The final output circuit parameter configuration scheme has structural feasibility, superior performance, and engineering practicality, greatly improving the efficiency and quality of automated integrated circuit design.

[0093] Example 6: The following is for reference. Figure 3 , Figure 3 A schematic diagram of the structure of a computer system suitable for implementing the server of the present application is shown.

[0094] like Figure 3 As shown, the computer system includes a central processing unit (CPU) 301, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 302 or programs loaded from storage section 308 into random access memory (RAM) 303. RAM 303 also stores various programs and data required for the system's operating instructions. CPU 301, ROM 302, and RAM 303 are interconnected via bus 304. Input / output (I / O) interface 305 is also connected to bus 304.

[0095] The following components are connected to I / O interface 305: an input section 306 including a keyboard, mouse, etc.; an output section 307 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 308 including a hard disk, etc.; and a communication section 309 including a network interface card such as a LAN card, modem, etc. The communication section 309 performs communication processing via a network such as the Internet. Drive 310 is also connected to I / O interface 305 as needed. Removable media 311, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 310 as needed so that computer programs read from them can be installed into storage section 308 as needed.

[0096] Specifically, according to embodiments of this application, the flowchart above refers to... Figure 1The described process can be implemented as a computer software program. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowchart. In such an embodiment, the computer program contains program code for performing the methods shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via communication section 309, and / or installed from removable medium 311. When the computer program is executed by central processing unit (CPU) 301, it performs the functions defined in the system of this application.

[0097] It should be noted that the computer-readable medium shown in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operational instructions of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two connected blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified functions or operational instructions, or using a combination of dedicated hardware and computer instructions.

[0099] The units or modules described in the embodiments of this application can be implemented in software or hardware. The described units or modules can also be located in a processor. The names of these units or modules do not, in certain circumstances, constitute a limitation on the unit or module itself.

[0100] In another aspect, this application also provides a computer-readable storage medium, which may be included in the server described in the above embodiments, or may exist independently and not assembled into the server. The aforementioned computer-readable storage medium stores one or more programs that, when used by one or more processors, execute the data balancing method described in this application.

[0101] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the foregoing disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for automated generation of integrated circuits based on circuit topology awareness, characterized in that, include: Determine the population of integrated circuits to be simulated and tested; The integrated circuit population is a set of encoded vectors used to describe the parameters of the integrated circuit, generated based on the topology information and performance constraints of the target circuit; the topology information includes driver level partitioning. Performance simulations were performed on individuals within the integrated circuit population to obtain performance evaluation results for the associated performance constraints. Determine whether the termination conditions are met based on the performance evaluation results; If satisfied, output the individual with the best performance evaluation result as the circuit parameter configuration scheme; If the performance is not met, individuals with performance superior to the specified standard are selected from the integrated circuit population as parent individuals based on the performance evaluation results. Based on the driver-level partitioning, the encoding vectors of the parent individuals are segmented, and the corresponding driver-level encoding segments of different parent individuals are selected and swapped to generate crossover offspring. The adjustment priority of each component in the encoding vector of the crossover offspring is determined, and the encoding components with different priorities are adjusted according to the preset rules of matching priority to generate mutated offspring. The mutated offspring are used as a new generation of integrated circuit population, and the step of performing performance simulation on all individuals within the integrated circuit population is performed.

2. The method as described in claim 1, characterized in that, Determine the adjustment priority of each component in the encoding vector of the crossover descendant, and adjust the encoding components of different priorities according to a preset rule of matching priority, including: Based on the performance simulation results, identify the critical and non-critical paths of the circuit corresponding to the cross-descendant; The coding components of the critical path are adjusted according to a first rule, and the coding components of the non-critical path are adjusted according to a second rule. Mutant offspring are generated based on the adjusted coding components. The adjustment step size of the first rule is smaller than that of the second rule.

3. The method as described in claim 2, characterized in that, The encoded components of the critical path are adjusted according to the first rule, including: Extract the current parameter values, path identification information, and path delay values ​​of the MOS transistor encoded components of the critical path; Calculate the difference between the path delay value and the delay threshold in the performance constraint; The corresponding adjustment coefficient is determined based on the difference; wherein the difference is positively correlated with the adjustment coefficient. Multiply the current parameter value by the adjustment coefficient to obtain the first adjustment step size; The coded components of the critical path are adjusted to reduce latency based on the first adjustment step size, thereby generating the adjusted critical path coded components.

4. The method as described in claim 2, characterized in that, The encoded components of the non-critical paths are adjusted according to the second rule, including: Extract the current parameter values ​​of the MOS transistor encoding components of the non-critical path and the performance redundancy of the path; The second adjustment step size is determined based on the performance redundancy; wherein the performance redundancy is positively correlated with the second adjustment step size. The coded components of the non-critical path are randomly adjusted according to the second adjustment step size to generate the adjusted coded components of the non-critical path.

5. The method as described in claim 4, characterized in that, After randomly adjusting the encoded components of the non-critical path according to the second adjustment step size, the method further includes: Verify whether the adjusted parameters conform to the preset process rules; The parameters that pass the verification are used as the adjusted non-critical path coding components.

6. The method as described in claim 1, characterized in that, The process of determining the population of integrated circuits to be simulated includes: Obtain the topology information and performance constraints of the target circuit; the topology information includes the MOS transistor connection relationships and driver stage division; A circuit parameter encoding vector is constructed based on the topology information; the encoding vector includes the width and length parameters, relative size scaling factor, and drive strength level identifier corresponding to the MOS transistors and drive stages in the topology. Based on the performance constraints, the value range of each component of the encoding vector is determined, and an initial population composed of the encoding vector is generated as the integrated circuit population.

7. The method as described in claim 1, characterized in that, The step of determining whether the termination condition is met based on the performance evaluation result includes: Calculate the deviation between the individual with the best performance evaluation result and the performance constraints; Determine the current iteration number; Calculate the change in evaluation result of the individual with the best performance evaluation result within the most recent consecutive preset algebras; If any preset condition is met, the termination condition is determined to be met; the preset conditions include: the deviation value does not exceed a preset deviation threshold, the number of iterations reaches a preset maximum number of iterations, and the change in the evaluation result does not exceed a preset change threshold.

8. An automated integrated circuit generation system based on circuit topology awareness, characterized in that, include: Population determination module, used to determine the population of integrated circuits to be simulated and tested; The integrated circuit population is a set of encoded vectors used to describe the parameters of the integrated circuit, generated based on the topology information and performance constraints of the target circuit; the topology information includes driver level partitioning. The performance simulation module is used to perform performance simulation on individuals within the integrated circuit population and obtain performance evaluation results of associated performance constraints. The termination judgment module is used to determine whether the termination condition is met based on the performance evaluation result. If the conditions are met, the configuration output module is triggered. If the conditions are not met, the parent filtering module will be triggered; The configuration output module is used to output the individual with the best performance evaluation result as the circuit parameter configuration scheme. The parent selection module is used to select individuals with performance superior to a specified standard from the integrated circuit population as parent individuals based on the performance evaluation results. The crossover generation module is used to segment the encoding vector of the parent individual according to the driving level partition, and select the corresponding driving level encoding segments of different parent individuals to exchange, thereby generating crossover offspring. The mutation generation module is used to determine the adjustment priority of each component in the encoding vector of the crossover offspring, and adjust the encoding components with different priorities according to the preset rules of matching priority to generate mutated offspring. The mutated offspring are used as a new generation of integrated circuit population to trigger the performance simulation module.

9. A server, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the method as described in any one of claims 1 to 7.

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