Miller clamping circuit and power tube driving device

Abstract

The invention provides a Miller clamping circuit and a power tube driving device, and relates to the technical field of integrated circuits. The Miller clamping circuit comprises a clamping tube, a clamping tube control module, a logic control module and a switched capacitor module. The logic control module generates a logic control signal based on the grid voltage of the power tube, the control signal of the pull-up driving tube and the control signal of the pull-down driving tube, and then the clamping tube control module conducts the clamping tube based on the logic control signal and the control signal of the pull-down driving tube when the bridge circuit is in a crosstalk state; at the moment, the switched capacitor module generates induction current according to the control signal of the pull-down driving tube and the grid voltage of the power tube so as to adjust the conduction time of the clamping tube. On the basis, the Miller clamping circuit with the self-adaptive capability is provided, the change rate of the grid voltage of the power tube during turn-off is sampled, and self-adaptive adjustment of the turn-on time of the clamping tube along with crosstalk change is achieved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a Miller clamping circuit and a power transistor driving device. Background Technology

[0002] With the widespread application of wide-bandgap semiconductor devices such as silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs), their high-speed switching characteristics in bridge circuits have brought significant performance improvements. However, the high-speed switching process of SiC MOSFETs can cause bridge arm crosstalk problems, leading to false turn-on of complementary transistors or even gate breakdown. Drive protection technology for power semiconductor devices has a significant impact on circuit reliability and device lifespan.

[0003] In power electronic systems, active Miller clamping technology serves as an effective gate protection method. When crosstalk voltage appears at the gate of a power transistor (such as an IGBT or MOSFET), it establishes a low-impedance path to ground by controlling the conduction of the clamping transistor. This technology effectively prevents mis-conduction or gate breakdown due to excessive crosstalk voltage, and is therefore widely used in the drive circuits of various power transistors. The clamping capability of this technology on the gate voltage of the power transistor directly affects the power consumption performance of the entire circuit and the lifespan of the power transistor. However, since the magnitude of crosstalk voltage dynamically changes with operating conditions in practical applications, existing technologies lack a way to adaptively control the conduction time of the clamping transistor based on the crosstalk voltage magnitude. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a Miller clamping circuit with adaptive capability, which achieves adaptive adjustment of the clamping transistor's on-time as crosstalk changes by sampling the rate of change of the gate voltage of the power transistor during turn-off.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, the present invention provides a Miller clamping circuit applied to a bridge circuit, the bridge circuit including at least a power transistor, a pull-up driving transistor, and a pull-down driving transistor; the Miller clamping circuit includes: a clamping transistor, a clamping transistor control module, a logic control module, and a switched capacitor module; the clamping transistor control module is connected to the gate of the clamping transistor, the switched capacitor module is connected to the drain of the clamping transistor and the gate of the clamping transistor; the source of the clamping transistor is grounded; the output terminal of the logic control module is connected to the input terminal of the clamping transistor control module; the gate voltage of the power transistor is used to characterize the real-time gate voltage of the power transistor; The logic control module is used to generate logic control signals based on the gate voltage of the power transistor, the control signal of the pull-up drive transistor, and the control signal of the pull-down drive transistor. The clamping transistor control module is used to turn on the clamping transistor when the bridge circuit is in a crosstalk state, based on the logic control signal and the control signal of the pull-down drive transistor. The switched capacitor module is used to generate induced current based on the control signal of the pull-down drive transistor and the gate voltage of the power transistor, so as to adjust the conduction time of the clamping transistor.

[0006] Optionally, the clamping transistor control module includes a pull-down unit and a drive unit; the input terminal of the drive unit is used to receive logic control signals; the first input terminal of the pull-down unit is used to receive control signals for the pull-down drive transistor; the second input terminal of the pull-down unit is used to receive logic control signals; the output terminals of the pull-down unit and the drive unit are both connected to the gate of the clamping transistor. The driving unit is used to adjust the gate voltage of the clamping transistor based on logic control signals to change the on / off state of the clamping transistor. The pull-down unit is used to provide a low-impedance path for the clamping transistor when it is in the off state.

[0007] Optionally, the driving unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the source of the first PMOS transistor and the source of the second PMOS transistor are both used to receive the supply voltage; the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded; the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor and is used to receive logic control signals; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the second PMOS transistor, and the gate of the second NMOS transistor; the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the clamping transistor. When the logic control signal is high, the second PMOS transistor and the first NMOS transistor are turned on. When the logic control signal is low, the first PMOS transistor and the second NMOS transistor are turned on.

[0008] Optionally, the pull-down unit includes a second NOT gate, a first NOR gate, a third NOT gate, a fourth NOT gate, and a third NMOS transistor; the input of the second NOT gate is used to receive the control signal of the pull-down driver transistor; the output of the second NOT gate is connected to the first input of the first NOR gate; the second input of the first NOR gate is used to receive the logic control signal; the output of the first NOR gate is connected to the input of the third NOT gate; the output of the third NOT gate is connected to the input of the fourth NOT gate; the output of the fourth NOT gate is connected to the gate of the third NMOS transistor; the source of the third NMOS transistor is grounded; and the drain of the third NMOS transistor is connected to the gate of the clamping transistor. Specifically, the third NMOS transistor is turned off when the logic control signal is high or the control signal of the pull-down drive transistor is low. When the logic control signal is low and the control signal of the pull-down drive transistor is high, the third NMOS transistor is turned on.

[0009] Optionally, the switched capacitor module includes a first capacitor, a field-effect transistor (FET), a first resistor, a second resistor, and a first NOT gate. The first terminal of the first capacitor is connected to the drain of the clamping transistor and is used to receive the gate voltage of the power transistor. The second terminal of the first capacitor is connected to the drain of the FET. The source of the FET is connected to the gate of the clamping transistor. The gate of the FET is connected to the first terminal of the first resistor and the first terminal of the second resistor. The second terminal of the second resistor is grounded. The second terminal of the first resistor is connected to the output terminal of the first NOT gate. The input terminal of the first NOT gate is used to receive the control signal of the pull-down drive transistor. Specifically, when the control signal of the pull-down drive transistor is low, the field-effect transistor is turned on. When the control signal of the pull-down drive transistor is high, the field-effect transistor is turned off.

[0010] Optionally, the logic control module includes a comparison unit and a control unit; the first input terminal of the comparison unit is used to receive the gate voltage of the power transistor; the second input terminal of the comparison unit is used to receive a preset reference voltage; the output terminal of the comparison unit is connected to the first input terminal of the control unit; the second input terminal of the control unit is also used to receive the control signal of the pull-up drive transistor; the third input terminal of the control unit is also used to receive the control signal of the pull-down drive transistor; the output terminal of the control unit is connected to the input terminal of the clamping transistor control module. The comparison unit is used to determine whether the power transistor drive device is in a crosstalk state based on a preset reference voltage and the gate voltage of the power transistor, and to send a comparison signal to the control unit based on the determination result. The control unit is used to generate logic control signals based on the comparison signal, the control signal of the pull-up drive transistor, and the control signal of the pull-down drive transistor.

[0011] Optionally, when the control signal of the pull-up drive transistor is high, the logic control signal is low; When the control signal of the pull-up drive transistor is low and the control signal of the pull-down drive transistor is high, the logic control signal is low. When the control signal of the pull-up drive transistor is low and the control signal of the pull-down drive transistor is low, the comparison signal is low and the logic control signal is low. When the control signal for the pull-up drive transistor is low and the control signal for the pull-down drive transistor is low, the comparison signal is high and the logic control signal is high.

[0012] Optionally, the control unit includes: a latch, a fifth NOT gate, and a second NOR gate; the first input terminal of the latch is connected to the output terminal of the comparison unit; the second input terminal of the latch is used to receive the control signal of the pull-down drive transistor; the output terminal of the latch is connected to the input terminal of the fifth NOT gate; the output terminal of the fifth NOT gate is connected to the first input terminal of the second NOR gate; the second input terminal of the second NOR gate is used to receive the control signal of the pull-up drive transistor; and the output terminal of the second NOR gate is connected to the input terminal of the clamping transistor control module.

[0013] Optionally, the Miller clamp circuit also includes an input clamp module, the input of which is used to receive the gate voltage of the power transistor; the output of the input clamp module is connected to the input of the logic control module. The input clamping module is used to clamp the gate voltage of the power transistor to a preset range to obtain the processed gate voltage of the power transistor. The logic control module is used to generate logic control signals based on the processed gate voltage of the power transistor, the control signal of the pull-up drive transistor, and the control signal of the pull-down drive transistor.

[0014] In a second aspect, the present invention also provides a power transistor driving device, which includes the Miller clamping circuit of any of the first aspects described above.

[0015] The Miller clamping circuit and power transistor driving device provided in this invention have the following advantages: The Miller clamping circuit in this application includes a clamping transistor, a clamping transistor control module, a logic control module, and a switched capacitor module. The clamping transistor control module is connected to the gate of the clamping transistor, and the switched capacitor module is connected to the drain of the clamping transistor. The source of the clamping transistor is grounded. The output terminal of the logic control module is connected to the input terminal of the clamping transistor control module. The logic control module generates a logic control signal based on the gate voltage of the power transistor, the control signal of the pull-up drive transistor, and the control signal of the pull-down drive transistor. Then, the clamping transistor control module turns on the clamping transistor when the bridge circuit is in a crosstalk state based on the logic control signal and the control signal of the pull-down drive transistor. At this time, the switched capacitor module generates an induced current based on the control signal of the pull-down drive transistor and the gate voltage of the power transistor to adjust the conduction time of the clamping transistor. Based on this, this application provides a Miller clamping circuit with adaptive capability, which achieves adaptive adjustment of the clamping transistor conduction time according to crosstalk by sampling the rate of change of the gate voltage of the power transistor during turn-off.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the power transistor driving device provided in an embodiment of the present invention is shown; Figure 2 This shows one of the structural schematic diagrams of the Miller clamping circuit provided in an embodiment of the present invention; Figure 3 This diagram illustrates the structure of a signal acquisition structure in the prior art. Figure 4 The diagram shows a waveform of an abnormal state within one switching cycle in the prior art; Figure 5 A schematic diagram of the structure of the logic control module provided in an embodiment of the present invention is shown; Figure 6 A circuit schematic diagram of the control unit provided in an embodiment of the present invention is shown; Figure 7 A circuit schematic diagram of the comparison unit provided in an embodiment of the present invention is shown; Figure 8 A second schematic diagram of the Miller clamping circuit provided in an embodiment of the present invention is shown; Figure 9 A circuit schematic diagram of the input clamping module provided in an embodiment of the present invention is shown; Figure 10 A schematic diagram of the clamping transistor control module in an embodiment of the present invention is shown; Figure 11 A circuit schematic diagram of the driving unit provided in an embodiment of the present invention is shown; Figure 12 The circuit schematic of the pull-down unit provided in an embodiment of the present invention is shown; Figure 13 A circuit schematic diagram of the switched capacitor module provided in an embodiment of the present invention is shown; Figure 14 A circuit diagram of the Miller clamping circuit provided in an embodiment of the present invention is shown; Figure 15 The experimental data diagram of the Miller clamp circuit provided in this embodiment is shown.

[0019] Icons: 10-Power transistor driver; 100-Miller clamp circuit; 200-Bridge circuit; 101-Clamp transistor control module; 102-Logic control module; 103-Switched capacitor module; 104-Input clamp module; 201-Comparator unit; 202-Control unit; 203-Pull-down unit; 204-Drive unit; INV5 - Fifth NOT gate; NOR2 - Second NOR gate; C1 - First capacitor; LDMOS2 - Field-effect transistor; R1 - First resistor; R2 - Second resistor; INV1 - First NOT gate; LDMOS1 - Clamping transistor; PM1 - First PMOS transistor; PM2 - Second PMOS transistor; NM1 - First NMOS transistor; NM2 - Second NMOS transistor; PM7 - Seventh PMOS transistor; PM8 - Eighth PMOS transistor; PM9 - Ninth PMOS transistor; PM10 - Tenth PMOS transistor; PM11 - Eleventh PMOS transistor; NM 4 - Fourth NMOS transistor; NM5 - Fifth NMOS transistor; NM6 - Sixth NMOS transistor; NM7 - Seventh NMOS transistor; NM8 - Eighth NMOS transistor; NM9 - Ninth NMOS transistor; R3 - Third resistor; R4 - Fourth resistor; R5 - Fifth resistor; R6 - Sixth resistor; INV2 - Second NOT gate; NOR1 - First NOR gate; INV3 - Third NOT gate; INV4 - Fourth NOT gate; NM3 - Third NMOS transistor; NOR3 - Third NOR gate; NOR4 - Fourth NOR gate; EA - Control signal for pull-down drive transistor; EB - Control signal for pull-up drive transistor; CLAMP - Gate voltage of power transistor; LC - Logic control signal. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0022] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0023] Please refer to Figure 1 , Figure 1 A schematic diagram of the power transistor driving device provided in this embodiment is shown. This power transistor driving device 10 is applied to a bridge circuit 200. The power transistor driving device 10 includes at least a Miller clamping circuit 100, and the bridge circuit 200 and the Miller clamping circuit 100 are electrically connected. In this embodiment, the bridge circuit 200 includes at least a power transistor, a pull-up driving transistor, and a pull-down driving transistor. In this embodiment, the Miller clamping circuit 100 can perform clamping adjustment based on the signals and / or voltages generated by the power transistor, pull-up driving transistor, and pull-down driving transistor, achieving adaptive adjustment of the clamping transistor's conduction time as crosstalk changes.

[0024] It should be noted that this embodiment does not limit the specific structure of the bridge circuit described above, and can be any bridge circuit structure, including but not limited to power transistors, pull-up drive transistors, and pull-down drive transistors.

[0025] For details, please refer to Figure 2 , Figure 2 A schematic diagram of the Miller clamping circuit in this embodiment is shown. The Miller clamping circuit 100 includes: a clamping transistor LDMOS1, a clamping transistor control module 101, a logic control module 102, and a switched capacitor module 103. In this embodiment, the clamping transistor control module 101 is connected to the gate of the clamping transistor LDMOS1, and the switched capacitor module 103 is connected to the drain and gate of the clamping transistor LDMOS1; the source of the clamping transistor LDMOS1 is grounded; and the output terminal of the logic control module 102 is connected to the input terminal of the clamping transistor control module 101.

[0026] In this embodiment, the logic control module 102 is used to generate logic control signals based on the gate voltage of the power transistor, the control signal of the pull-up drive transistor, and the control signal of the pull-down drive transistor.

[0027] It should be noted that the power transistor gate voltage CLAMP mentioned above is used to characterize the real-time gate voltage when the power transistor is in the off state.

[0028] The clamping transistor control module 101 is used to turn on the clamping transistor when the bridge circuit is in a crosstalk state based on the logic control signal and the control signal of the pull-down drive transistor.

[0029] The switched capacitor module 103 is used to generate an induced current based on the control signal of the pull-down drive transistor and the gate voltage of the power transistor, so as to adjust the conduction time of the clamping transistor.

[0030] In this embodiment, the control signal EA of the pull-down driver transistor is used to characterize the drive signal V of the pull-down driver transistor. D_L The signal obtained after the delay circuit and inverter; the control signal EB of the pull-up drive transistor is used to characterize the gate signal V of the pull-up drive transistor. D_H The signal obtained after level shifting and inverter. The gate voltage CLAMP of the power transistor is used to characterize the gate voltage of the power transistor in a bridge circuit.

[0031] In this embodiment, the control signal EA of the pull-down drive transistor and the control signal EB of the pull-up drive transistor have a certain timing sequence as the power transistor is turned on.

[0032] In one alternative implementation, if the pull-down driver is a pull-down NMOS transistor and the pull-up driver is a pull-up PMOS transistor, please refer to... Figure 3 , Figure 3 A schematic diagram of a signal acquisition structure in the prior art is shown. This signal acquisition structure is used to extract the control signal EA of the pull-down drive transistor and the control signal EB of the pull-up drive transistor from the bridge circuit.

[0033] Please continue to refer to this. Figure 3 During one sampling period, when the power transistor is turned on, the pull-down NMOS transistor first changes from the on state to the off state. At this time, the control signal EA of the pull-down drive transistor changes from 0 to 1. Then the pull-up PMOS transistor changes from the off state to the on state. At this time, the control signal EB of the pull-up drive transistor changes from 0 to 1, and pulls the gate voltage CLAMP of the power transistor high to VCC.

[0034] Correspondingly, during the power transistor turn-off process, the pull-up PMOS transistor first changes from the on state to the off state. At this time, the control signal EB of the pull-up drive transistor changes from 0 to 1. Then, the pull-down NMOS transistor changes from the off state to the on state. At this time, the control signal EA of the pull-down drive transistor changes from 0 to 1, and pulls the gate voltage CLAMP of the power transistor down to VEE.

[0035] At this point, please refer to Figure 4 , Figure 4The diagram shows a waveform of an abnormal state during a switching cycle in the prior art. It can be seen that when the power transistor is in the off state, crosstalk voltage is prone to occur, and this crosstalk voltage changes dynamically with the operating conditions.

[0036] Based on this, this embodiment provides a Miller clamp circuit with adaptive capability, which can obtain the real-time gate voltage CLAMP of the power transistor by sampling the rate of change of the gate voltage CLAMP when the power transistor is turned off, and combine it with the control signal EA of the pull-down drive transistor and the control signal EB of the pull-up drive transistor to realize the adaptive adjustment of the conduction time of the clamp transistor LDMOS1 as crosstalk changes.

[0037] To determine the high / low level state of its logic control signal LC, please refer to... Figure 5 , Figure 5 This diagram illustrates the structure of the logic control module 102 provided in this embodiment. The logic control module 102 includes a comparison unit 201 and a control unit 202. The first input terminal of the comparison unit 201 is used to receive the gate voltage CLAMP of the power transistor. The second input terminal of the comparison unit 201 is used to receive a preset reference voltage V. N The output of the comparison unit 201 is connected to the first input of the control unit 202; the second input of the control unit 202 is also used to receive the control signal EB of the pull-up drive transistor; the third input of the control unit 202 is also used to receive the control signal EA of the pull-down drive transistor; the output of the control unit 202 is connected to the input of the clamping transistor control module 101.

[0038] The comparison unit 201 is used to determine whether the power transistor drive device is in a crosstalk state based on a preset reference voltage and the gate voltage of the power transistor, and to send a comparison signal to the control unit based on the determination result.

[0039] The control unit 202 is used to generate logic control signals based on the comparison signal, the control signal of the pull-up drive transistor, and the control signal of the pull-down drive transistor.

[0040] This embodiment utilizes the comparison unit 201 based on a preset reference voltage V. N The comparison signal COMP-O is determined by the power transistor gate voltage CLAMP. When the power transistor gate voltage CLAMP is higher than the preset reference voltage V... N If the signal is positive, it indicates the presence of a positive crosstalk voltage, and COMP-O will be at a high level.

[0041] In one optional implementation, a preset reference voltage V is provided. N The voltage can be determined by dividing VDD. It should be noted that this embodiment does not limit the preset reference voltage V. N The specific value can be determined based on actual needs.

[0042] In this embodiment, the logic control signal LC consists of the aforementioned comparison signal COMP-O, the control signal EB of the pull-up driver transistor, and the control signal EA of the pull-down driver transistor, and the following possible states exist: When the control signal EB of the pull-up driver transistor is high, the logic control signal LC is low. When the control signal EB of the pull-up driver transistor is low and the control signal EA of the pull-down driver transistor is high, the logic control signal LC is low. When the control signal EB of the pull-up drive transistor is low and the control signal EA of the pull-down drive transistor is low, the comparison signal COMP-O is low and the logic control signal LC is low. When the control signal EB of the pull-up driver transistor is low and the control signal EA of the pull-down driver transistor is low, the comparison signal COMP-O is high and the logic control signal LC is high.

[0043] That is, when the control signal EB of the pull-up drive transistor is 1, the control unit 202 outputs a logic control signal LC of 0. When the control signal EB of the pull-up drive transistor is 0, the logic control signal LC output by the control unit 202 is the same as the output logic of the latch. That is, when the control signal EA of the pull-down drive transistor is 1, the logic control signal LC is 0 regardless of whether the comparison signal COMP_O is 0 or 1; when the control signal EA of the pull-down drive transistor is 0 and the comparison signal COMP_O is 1, the logic control signal LC is 1; when the control signal EA of the pull-down drive transistor is 0 and the comparison signal COMP_O is 0, the logic control signal LC remains in the previous state.

[0044] Please refer to Figure 6 , Figure 6 The circuit schematic of the control unit provided in this embodiment is shown. In this embodiment, the control unit 202 includes: a latch, a fifth NOT gate INV5, and a second NOR gate NOR2; the first input terminal of the latch is connected to the output terminal of the comparator unit; the second input terminal of the latch is used to receive the control signal EA of the pull-down drive transistor; the output terminal of the latch is connected to the input terminal of the fifth NOT gate INV5; the output terminal of the fifth NOT gate INV5 is connected to the first input terminal of the second NOR gate NOR2; the second input terminal of the second NOR gate NOR2 is used to receive the control signal EB of the pull-up drive transistor; the output terminal of the second NOR gate NOR2 is connected to the input terminal of the clamping transistor control module 101.

[0045] Please continue to refer to this. Figure 6 In this embodiment, the latch is an SR latch composed of a third NOR gate NOR3 and a fourth NOR gate NOR4. The specific connection relationship can be referred to the figure, which will not be repeated here.

[0046] Please refer to Figure 7, Figure 7 The circuit diagram of the comparison unit provided in this embodiment is shown. The comparison unit 201 consists of the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, the fourth NMOS transistor NM4, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the ninth NMOS transistor NM9, and the fifth resistor R5 and the sixth resistor R6. The specific connection relationship can be referred to the figure.

[0047] Specifically, the drain and gate of the fourth NMOS transistor NM4 are connected and receive a 3.7uA current source I. REF The source of the fourth NMOS transistor NM4 is connected to ground, and its gate is connected to the gate of the seventh NMOS transistor NM7. The source of the seventh NMOS transistor NM7 is connected to ground, and its drain is connected to the source of the sixth NMOS transistor NM6 and the source of the eighth NMOS transistor NM8. The gate of the sixth NMOS transistor NM6 is connected to the gate of the seventh PMOS transistor PM7, and its drain is connected to the drain of the seventh PMOS transistor PM7, the drain of the eighth PMOS transistor PM8, the gate of the ninth PMOS transistor PM9, the gate of the eleventh PMOS transistor PM11, and the gate of the ninth NMOS transistor NM9. The eighth NMOS transistor NM8... The gate of the 10th PMOS transistor PM10 is connected to the gate of the 5th resistor R5 and the 6th resistor R6. The drain of the 8th NMOS transistor NM8 is connected to the drain of the 10th PMOS transistor PM10, the drain of the 9th PMOS transistor PM9, and the gate of the 8th PMOS transistor PM8. The sources of the 7th PMOS transistor PM7, the 8th PMOS transistor PM8, the 9th PMOS transistor PM9, and the 10th PMOS transistor PM10 are connected to VDD. The source of the 11th PMOS transistor PM11 is connected to the 5V power supply, and the drain of the 11th PMOS transistor PM11 is connected to the drain of the 9th NMOS transistor NM9 and serves as the output terminal, outputting the comparator signal COMP_0. The source of the 9th NMOS transistor NM9 is connected to the power supply ground.

[0048] Please continue to refer to this. Figure 7 The working principle of the comparison unit 201 in this embodiment can be understood as follows: VDD is divided by resistors R5 and R6 to obtain the preset reference voltage V. N It is then compared with the input power transistor gate voltage CLAMP to output a comparison signal COMP_0.

[0049] Furthermore, to ensure the normal operation of the Miller clamping circuit 100, please refer to... Figure 8 , Figure 8This diagram illustrates another structural schematic of the Miller clamp circuit provided in this embodiment. In this embodiment, the Miller clamp circuit 100 further includes an input clamp module 104. The input terminal of the input clamp module 104 is used to receive the gate voltage CLAMP of the power transistor. The output terminal of the input clamp module 104 is connected to the input terminal of the logic control module 102.

[0050] The input clamping module 104 is used to clamp the power transistor gate voltage CLAMP to a preset range to obtain the processed power transistor gate voltage CLAMP.

[0051] The logic control module 102 is used to generate a logic control signal LC based on the processed power transistor gate voltage CLAMP, the pull-up drive transistor control signal EB, and the pull-down drive transistor control signal EA.

[0052] Please refer to Figure 9 , Figure 9 The circuit diagram of the input clamping module provided in this embodiment is shown. The connection relationship of each structural component of the input clamping module 104 will not be described in detail here. For details, please refer to the specific structural diagram. In addition to the current mirror structure formed by the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the fifth PMOS transistor PM5, and the sixth PMOS transistor PM6, the input clamping module 104 also includes the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the third resistor R3 and the fourth resistor R4.

[0053] The working principle of the input clamping module 104 is as follows: In this embodiment, a bias current is generated on the branch of the fifth PMOS transistor PM5 through a current mirror structure. Simultaneously, I... REF The current flowing through the fourth resistor R4 generates a value I. REF *Voltage of R4.

[0054] Specifically, when CLAMP REF *R4-|V TH-PM3 When |-IR3*R3, the third PMOS transistor PM3 is turned on. At this time, VOUT can be expressed as: ; When CLAMP>I REF *R4+|V TH-PM4 When |+IR3*R3, the fourth PMOS transistor PM4 is turned on. At this time, VOUT can be expressed as: ; When I REF *R4-|V TH-PM3 |-IR3*R3 <VIN<I REF*R4 +|V TH-PM4 When |+IR3*R3, both the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are turned off, and VOUT can be expressed as:​ .

[0055] After the logic control signal LC is determined, please refer to Figure 10 , Figure 10 A schematic diagram of the clamping transistor control module in this embodiment is shown. The clamping transistor control module 101 includes a pull-down unit 203 and a drive unit 204. The input terminal of the drive unit 204 is used to receive a logic control signal LC. The first input terminal of the pull-down unit 203 is used to receive a control signal EA from the pull-down drive transistor. The second input terminal of the pull-down unit 203 is used to receive the logic control signal LC. The output terminals of both the pull-down unit 203 and the drive unit 204 are connected to the gate of the clamping transistor LDMOS1. The driving unit 204 is used to adjust the gate voltage of the clamping transistor LDMOS1 based on the logic control signal LC to change the on / off state of the clamping transistor LDMOS1.

[0056] Pull-down unit 203 is used to provide a low-impedance path for clamp transistor LDMOS1 when clamp transistor LDMOS1 is in the off state.

[0057] Please refer to Figure 11 , Figure 11 The circuit schematic of the driving unit provided in this embodiment is shown. In this embodiment, the driving unit 204 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, and a second NMOS transistor NM2. The first PMOS transistor PM1 and the second PMOS transistor PM2 are used to receive the supply voltage. The sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are grounded. The gate of the first PMOS transistor PM1 is connected to the gate of the first NMOS transistor NM1 and is used to receive the logic control signal LC. The drain of the first PMOS transistor PM1 is connected to the drain of the first NMOS transistor NM1, the gate of the second PMOS transistor PM2, and the gate of the second NMOS transistor NM2. The drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2 and the gate of the clamping transistor LDMOS1.

[0058] Specifically, when the logic control signal LC is high, the second PMOS transistor PM2 and the first NMOS transistor NM1 are turned on, pulling the gate of the clamping transistor LDMOS1 up to VDD; when the logic control signal LC is low, the first PMOS transistor PM1 and the second NMOS transistor NM2 are turned on, pulling the gate of the clamping transistor LDMOS1 down to GND.

[0059] Understandably, in this embodiment, the pull-down unit provides a low-impedance path between the gate and ground of the clamping transistor when the clamping transistor needs to be in the off state, to prevent the clamping transistor from being mis-turned on.

[0060] Please refer to Figure 12 , Figure 12 The circuit schematic of the pull-down unit provided in this embodiment is shown. The pull-down unit 203 includes a second NOT gate INV2, a first NOR gate NOR1, a third NOT gate INV3, a fourth NOT gate INV4, and a third NMOS transistor NM3. The input terminal of the second NOT gate INV2 is used to receive the control signal EA of the pull-down drive transistor. The output terminal of the second NOT gate INV2 is connected to the first input terminal of the first NOR gate NOR1. The second input terminal of the first NOR gate NOR1 is used to receive the logic control signal LC. The output terminal of the first NOR gate NOR1 is connected to the input terminal of the third NOT gate INV3. The output terminal of the third NOT gate INV3 is connected to the input terminal of the fourth NOT gate INV4. The output terminal of the fourth NOT gate INV4 is connected to the gate of the third NMOS transistor NM3. The source of the third NMOS transistor NM3 is grounded. The drain of the third NMOS transistor NM3 is connected to the gate of the clamping transistor LDMOS1.

[0061] Specifically, when the logic control signal LC is high or the control signal EA of the pull-down drive transistor is low, the third NMOS transistor NM3 is turned off.

[0062] When the logic control signal LC is low and the control signal EA of the pull-down drive transistor is high, the third NMOS transistor NM3 is turned on, which is equivalent to adding a low-impedance path between the gate of the clamping transistor LDMOS1 and GND. The resistance value is equal to the equivalent on-resistance Ron_NM3 of the third NMOS transistor NM3.

[0063] Please refer to Figure 13 , Figure 13 The circuit schematic of the switched capacitor module provided in this embodiment is shown. In this embodiment, the switched capacitor module 103 includes a first capacitor C1, a field-effect transistor LDMOS2, a first resistor R1, a second resistor R2, and a first NOT gate INV1. The first terminal of the first capacitor C1 is connected to the drain of the clamping transistor LDMOS1 and is used to receive the gate voltage CLAMP of the power transistor. The second terminal of the first capacitor C1 is connected to the drain of the field-effect transistor LDMOS2. The source of the field-effect transistor LDMOS2 is connected to the gate of the clamping transistor LDMOS1. The gate of the field-effect transistor LDMOS2 is connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2. The second terminal of the second resistor R2 is grounded. The second terminal of the first resistor R1 is connected to the output terminal of the first NOT gate INV1. The input terminal of the first NOT gate INV1 is used to receive the control signal EA of the pull-down drive transistor.

[0064] When the control signal EA of the pull-down drive transistor is low, the field-effect transistor LDMOS2 is turned on. The switched capacitor module 103 is regarded as a capacitor C1 connected in parallel between the drain and gate of the clamp transistor LDMOS1. At this time, an induced current proportional to dCLAMP / dt can be generated by the CLAMP voltage and input to the gate node of the clamp transistor LDMOS1 to charge the gate-source parasitic capacitance CGS of the clamp transistor LDMOS1. The first resistor R1 and the second resistor R2 are connected in series to divide the voltage and prevent the gate of the field-effect transistor LDMOS2 from breaking down.

[0065] It should be noted that in this embodiment, the switched capacitor module 103 adjusts the conduction time of the clamping transistor LDMOS1 by outputting induced current throughout the entire time. Specifically, as the crosstalk (dV) increases, the switching capacitor module 103 adjusts the conduction time of the clamping transistor LDMOS1. DS As / dt) increases, the positive crosstalk voltage (dV) CLAMP As / dt) increases, the conduction time of the clamping transistor LDMOS1 decreases.

[0066] For details, please refer to Figure 14 , Figure 14 The circuit diagram of the Miller clamping circuit provided in this embodiment is shown. The working principle of the Miller clamping circuit 100 in this embodiment is as follows: First, please continue to refer to Figure 4 Before the power transistor is turned on, the control signal EA of the pull-down drive transistor and the control signal EB of the pull-up drive transistor will change from 0 to 1, which turns off the field-effect transistor LDMOS2 in the switched capacitor module 103. At this time, the switched capacitor branch constructed by each device under the switched capacitor module 103 is equivalent to an open circuit. By controlling the third NMOS transistor NM3 in the pull-down unit 203 to turn on, the logic control module 102 outputs the logic control signal LC to a low level, which controls the second NMOS transistor NM2 to turn on through the drive unit 204. At this time, the gate impedance of the clamping transistor LDMOS1 to ground is approximately: R on_NM3 / / R on_NM2 ; Furthermore, since the width-to-length ratio (W / L) of the third NMOS transistor NM3 is much larger than that of the second NMOS transistor NM2, the equivalent on-resistance Ron_NM3 << the equivalent on-resistance Ron_NM2.

[0067] When the power transistor starts conducting, the gate voltage CLAMP begins to rise. At this time, the crosstalk (dV) DS If / dt) is large, it will affect the gate-drain parasitic capacitance C of the clamping transistor LDMOS1. GD An induced current is generated on the circuit. The induced current flows to GND through the low-impedance path formed by the second NMOS transistor NM2 and the second NMOS transistor NM2, in order to prevent the rise time of CLAMP from increasing due to the conduction of clamping transistor LDMOS1.

[0068] Please continue to refer to Figure 4 , it can be seen that when the power transistor is turned off, it can be divided into two stages, namely before the crosstalk appears and after the crosstalk appears.

[0069] Based on this, please continue to refer to Figure 14 , before the forward crosstalk voltage appears, at this time, the control signal EA of the pull-down driving transistor is 0. At this time, the field-effect transistor LDMOS2 is turned on, and the first capacitor C1 is equivalent to being connected in parallel between the drain and the gate of the clamping transistor LDMOS1. Since the pull-down branch controls the third NMOS transistor NM3 to turn off, the impedance of the gate of the clamping transistor LDMOS1 to the ground increases from Ron_NM3 / / Ron_NM2 to Ron_NM2. Since Ron_NM3 << Ron_NM2, at this time, the impedance of the gate of the clamping transistor LDMOS1 to the ground increases significantly.

[0070] When a forward crosstalk voltage appears at the gate of the power transistor, a first induced current I GD and a second induced current I C1 are generated on the first capacitor C1 and the gate-drain parasitic capacitor C CGD of the clamping transistor LDMOS1. The calculation formulas for the first induced current I C1 and the second induced current I CGD can be expressed as: .

[0071] .

[0072] Due to the influence of signal propagation delay and response time, at this time, the comparison unit 201 and the control unit 202 have not completed the detection of the crosstalk voltage. At this time, the output states of the comparison unit 201 and the control unit 202 remain unchanged. The second NMOS transistor NM2 pulls the gate of the clamping transistor LDMOS1 to GND. Therefore, a part of the induced current on the first capacitor C1 and the gate-drain parasitic capacitor C GD of the clamping transistor LDMOS1 flows through the second NMOS transistor NM2 into GND, and the other part of the current charges the gate-source parasitic capacitor CGS of the clamping transistor LDMOS1. The charging current can be expressed as: ; Since the equivalent on-resistance of the second NMOS transistor NM2 is large, more current flows to the gate-source parasitic capacitor C GS of the clamping transistor LDMOS1.

[0073] It can be understood that the conduction process of the clamping transistor LDMOS1 in this embodiment can be regarded as two stages.

[0074] In the first stage, before the crosstalk voltage is generated and the logic control signal LC output by the logic control module 102 changes from 0 to 1, the gate-source capacitance C of the clamping transistor LDMOS1... GS The charging current is coupled through the first capacitor C1 to the CLAMP voltage change rate dV CLAMP / dt is generated by induction, and crosstalk dV CLAMP The larger / dt is, the larger the charging current is, and the V of the clamping transistor LDMOS1 is... GS The faster the rise, the more adaptive the on-time of the clamping transistor LDMOS1 becomes with respect to the CLAMP.

[0075] In the second stage, after the logic control module 102 outputs the logic control signal LC from 0 to 1, the second NMOS transistor NM2 is turned off and the second PMOS transistor PM2 is turned on. The charging current of the gate-source capacitor of the clamping transistor LDMOS1 is mainly provided by the supply voltage VDD. In an optional embodiment, the supply voltage VDD in this embodiment is 5V.

[0076] Please refer to Figure 15 , Figure 15 The experimental data diagram of the Miller clamp circuit provided in this embodiment is shown; with crosstalk (dV) DS As / dt) increases, the positive crosstalk voltage (dV) CLAMP As / dt) increases, the conduction time of the clamping transistor LDMOS1 decreases. If the 0V turn-off condition is used, the conduction time of the clamping transistor LDMOS1 is 3.06ns, 2.90ns, 2.78ns, and 2.58ns respectively under the conditions of crosstalk of 90V / ns, 110V / ns, 130V / ns, and 150V / ns.

[0077] In summary, the Miller clamping circuit in this application includes a clamping transistor, a clamping transistor control module, a logic control module, and a switched capacitor module. The clamping transistor control module is connected to the gate of the clamping transistor, and the switched capacitor module is connected to the drain of the clamping transistor. The source of the clamping transistor is grounded. The output terminal of the logic control module is connected to the input terminal of the clamping transistor control module. Specifically, the logic control module generates a logic control signal based on the gate voltage of the power transistor, the control signal of the pull-up drive transistor, and the control signal of the pull-down drive transistor. Subsequently, the clamping transistor control module conducts the clamping transistor when the bridge circuit is in a crosstalk state based on the logic control signal and the control signal of the pull-down drive transistor. At this time, the switched capacitor module generates an induced current based on the control signal of the pull-down drive transistor and the gate voltage of the power transistor to adjust the conduction time of the clamping transistor.

[0078] Based on this, this application provides a Miller clamping circuit with adaptive capability, which achieves adaptive adjustment of the clamping transistor's on-time as crosstalk changes by sampling the rate of change of the power transistor's gate voltage during turn-off.

[0079] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0080] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0081] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0082] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A Miller clamping circuit applied to a bridge circuit, said bridge circuit comprising at least a power transistor, a pull-up driver transistor, and a pull-down driver transistor, characterized in that, The Miller clamping circuit includes: a clamping transistor, a clamping transistor control module, a logic control module, and a switched capacitor module; the clamping transistor control module is connected to the gate of the clamping transistor, and the switched capacitor module is connected to the drain and gate of the clamping transistor; the source of the clamping transistor is grounded; the output terminal of the logic control module is connected to the input terminal of the clamping transistor control module. The logic control module is used to generate logic control signals based on the power transistor gate voltage, the control signal of the pull-up drive transistor, and the control signal of the pull-down drive transistor; the power transistor gate voltage is used to characterize the real-time gate voltage of the power transistor. The clamping transistor control module is used to turn on the clamping transistor when the bridge circuit is in a crosstalk state based on the logic control signal and the control signal of the pull-down drive transistor. The switched capacitor module is used to generate an induced current based on the control signal of the pull-down drive transistor and the gate voltage of the power transistor, so as to adjust the conduction time of the clamping transistor.

2. The Miller clamping circuit according to claim 1, characterized in that, The clamping transistor control module includes a pull-down unit and a drive unit; the input terminal of the drive unit is used to receive the logic control signal; the first input terminal of the pull-down unit is used to receive the control signal of the pull-down drive transistor; the second input terminal of the pull-down unit is used to receive the logic control signal. The output terminal of the pull-down unit and the output terminal of the drive unit are both connected to the gate of the clamping transistor; The driving unit is used to adjust the gate voltage of the clamping transistor based on the logic control signal to change the on / off state of the clamping transistor. The pull-down unit is used to provide a low-impedance path for the clamping tube when the clamping tube is in the off state.

3. The Miller clamping circuit according to claim 2, characterized in that, The driving unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the source of the first PMOS transistor and the source of the second PMOS transistor are both used to receive the supply voltage; the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded; the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor and is used to receive the logic control signal; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the second PMOS transistor, and the gate of the second NMOS transistor; the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the clamping transistor. When the logic control signal is high, the second PMOS transistor and the first NMOS transistor are turned on. When the logic control signal is low, the first PMOS transistor and the second NMOS transistor are turned on.

4. The Miller clamping circuit according to claim 2, characterized in that, The pull-down unit includes a second NOT gate, a first NOR gate, a third NOT gate, a fourth NOT gate, and a third NMOS transistor; the input of the second NOT gate is used to receive the control signal of the pull-down driving transistor; the output of the second NOT gate is connected to the first input of the first NOR gate; the second input of the first NOR gate is used to receive the logic control signal; the output of the first NOR gate is connected to the input of the third NOT gate; the output of the third NOT gate is connected to the input of the fourth NOT gate; the output of the fourth NOT gate is connected to the gate of the third NMOS transistor; the source of the third NMOS transistor is grounded; and the drain of the third NMOS transistor is connected to the gate of the clamping transistor. Specifically, the third NMOS transistor is turned off when the logic control signal is high or the control signal of the pull-down drive transistor is low. When the logic control signal is low and the control signal of the pull-down drive transistor is high, the third NMOS transistor is turned on.

5. The Miller clamping circuit according to claim 1, characterized in that, The switched capacitor module includes a first capacitor, a field-effect transistor (FET), a first resistor, a second resistor, and a first NOT gate. The first terminal of the first capacitor is connected to the drain of the clamping transistor and is used to receive the gate voltage of the power transistor. The second terminal of the first capacitor is connected to the drain of the FET. The source of the FET is connected to the gate of the clamping transistor. The gate of the FET is connected to the first terminal of the first resistor and the first terminal of the second resistor. The second terminal of the second resistor is grounded. The second terminal of the first resistor is connected to the output terminal of the first NOT gate. The input terminal of the first NOT gate is used to receive the control signal of the pull-down drive transistor. When the control signal of the pull-down drive transistor is low, the field-effect transistor is turned on; When the control signal of the pull-down drive transistor is high, the field-effect transistor is turned off.

6. The Miller clamping circuit according to claim 1, characterized in that, The logic control module includes a comparison unit and a control unit; the first input terminal of the comparison unit is used to receive the gate voltage of the power transistor; the second input terminal of the comparison unit is used to receive a preset reference voltage; the output terminal of the comparison unit is connected to the first input terminal of the control unit; the second input terminal of the control unit is also used to receive the control signal of the pull-up drive transistor; the third input terminal of the control unit is also used to receive the control signal of the pull-down drive transistor; the output terminal of the control unit is connected to the input terminal of the clamping transistor control module. The comparison unit is used to determine whether the power transistor driving device is in a crosstalk state based on the preset reference voltage and the power transistor gate voltage, and to send a comparison signal to the control unit based on the determination result. The control unit is configured to generate the logic control signal based on the comparison signal, the control signal of the pull-up drive transistor, and the control signal of the pull-down drive transistor.

7. The Miller clamping circuit according to claim 6, characterized in that, When the control signal of the pull-up drive transistor is high, the logic control signal is low; When the control signal of the pull-up drive transistor is low and the control signal of the pull-down drive transistor is high, the logic control signal is low. When the control signal of the pull-up drive transistor is low and the control signal of the pull-down drive transistor is low, the comparison signal is low and the logic control signal is low. When the control signal of the pull-up drive transistor is low and the control signal of the pull-down drive transistor is low, the comparison signal is high and the logic control signal is high.

8. The Miller clamping circuit according to claim 6, characterized in that, The control unit includes: a latch, a fifth NOT gate, and a second NOR gate; the first input terminal of the latch is connected to the output terminal of the comparison unit; the second input terminal of the latch is used to receive the control signal of the pull-down drive transistor; the output terminal of the latch is connected to the input terminal of the fifth NOT gate; the output terminal of the fifth NOT gate is connected to the first input terminal of the second NOR gate; the second input terminal of the second NOR gate is used to receive the control signal of the pull-up drive transistor; the output terminal of the second NOR gate is connected to the input terminal of the clamping transistor control module.

9. The Miller clamping circuit according to claim 1, characterized in that, The Miller clamp circuit further includes an input clamp module, the input terminal of which is used to receive the gate voltage of the power transistor; the output terminal of the input clamp module is connected to the input terminal of the logic control module. The input clamping module is used to clamp the gate voltage of the power transistor to a preset range to obtain the processed gate voltage of the power transistor. The logic control module is used to generate logic control signals based on the processed power transistor gate voltage, the control signal of the pull-up drive transistor, and the control signal of the pull-down drive transistor.

10. A power transistor drive device, characterized in that, The power transistor drive device includes the Miller clamping circuit as described in any one of claims 1 to 9.

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