Manufacturing method of system-in-package substrate

Abstract

The invention provides a manufacturing method of a system-in-package substrate, which comprises the following steps of: pasting two copper foils and prepregs together for primary pressing, and pasting rough surfaces of the copper foils with the prepregs to obtain a substrate; performing first-order flash etching, grinding thinning, second-order flash etching and first drilling on the substrate, and performing copper foil etching windowing and second drilling to obtain a perforated substrate; the method comprises the following steps: after carrying out chemical copper plating treatment on a perforated substrate, laying a circuit to form a substrate selectively covering a dry film pattern, then carrying out selective porefilling electroplating, and carrying out third-order flash corrosion, film removal and fourth-order flash corrosion to obtain a substrate to be packaged; and carrying out solder mask treatment on the substrate to be packaged, and then carrying out electrogilding treatment to obtain the packaging substrate. According to the manufacturing method of the system-in-package substrate provided by the invention, the double-sided yield of substrate production can be ensured to reach 99% or above, the overall production cost is relatively high, and meanwhile, the product yield of the system-in-package substrate is effectively ensured.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board manufacturing technology, and in particular to a method for manufacturing a system-in-package substrate. Background Technology

[0002] With the advent of the big data era, the market demand for SIP (System-in-Package) is becoming more and more widespread. In order to shorten the transmission distance between devices, modular integrated packaging will become an industry trend. At the same time, the precision requirements of different devices in the module are also getting higher and higher, and the guarantee of high reliability of the product in different fields of application is also receiving much attention.

[0003] For example, a packaging substrate needs to be manufactured with laser X-holes and electroplated filling, matrix-arranged wire bonding pads, micro-pitch pads, and dense circuitry. The wire bonding pads have an upper dimension ≤60µm, a pad spacing ≥20µm, a dense circuitry area with a line width of 20~40µm, and a line spacing of 20~40µm. Currently, the industry mostly uses mSAP (semi-additive process) processing combined with ultra-thin copper. When the laser X-hole depth is ≥150µm, the current mSAP processing technology cannot meet the requirement that the laser X-hole filling depression is ≤3µm. This invention uses a copper foil (copper thickness 12µm, roughness Rz ≤2.5µm), which is 5~10% cheaper than ultra-thin copper (copper thickness 2µm, roughness Rz ≤0.2µm). In addition, a special copper plating process and grinding process with better cost performance can achieve a laser X-hole filling depression of ≤3µm when the laser X-hole depth is ≥150µm. Summary of the Invention

[0004] Therefore, it is necessary to provide a method for manufacturing a system-in-package substrate to address at least one of the problems mentioned above.

[0005] This invention provides a method for fabricating a system-in-package substrate, comprising the following steps: Two copper foils and a prepreg are bonded together in one pressing process, with the rough surface of the copper foil bonded to the prepreg to obtain a substrate; The substrate is subjected to first-stage flash etching, grinding and thinning, second-stage flash etching and first drilling, and then copper foil etching to open windows and second drilling to obtain a perforated substrate. After chemically plating copper onto the via substrate, circuitry is laid out to form a substrate with selectively covered dry film patterns. Then, selective hole-filling electroplating is performed, followed by third-stage flash etching, film removal, and fourth-stage flash etching to obtain the substrate to be packaged. After solder resist treatment is performed on the substrate to be packaged, the packaged substrate is obtained after electroplating with gold.

[0006] In one embodiment, the copper foil has a copper thickness of 12µm and a roughness Rz≤2.5µm; in the step of bonding the two copper foils and the prepreg together for one pressing, the pressing conditions are: pressing heating rate: ≥10℃ / min, maximum pressing temperature ≥220℃, and maximum pressing pressure ≥400psi.

[0007] In one embodiment, after the step of obtaining the substrate, a PNL (abbreviation for Panel) QR code is provided on the edge of the substrate.

[0008] In one embodiment, in the first-stage flash etching step, the flash etching solution includes H2SO4: 25±3 g / L, H2O2: 8±1.5 g / L, and Cu. 2+ The flash etch rate was 20±4 g / L, the flash etch temperature was 32.5±1℃, and the production rate was V1; the production rate of the second-stage flash etch was 2V1.

[0009] In one embodiment, the step of selectively filling vias plating includes selectively patterning the area of ​​the substrate surface not covered with the resist coating photosensitive film, wherein the depth of the copper pits on the plating surface is less than or equal to 8µm; after the selective via-filling vias plating step, the substrate is further subjected to mechanical polishing so that the depth of the copper pits on the plating surface is less than or equal to 2µm.

[0010] In one embodiment, the steps of performing the third-stage flash etching, film removal, and fourth-stage flash etching include first removing the extended copper generated by mechanical grinding through the third-stage flash etching by using chemical soaking, spraying, and agitation, then removing the selective protective layer on the substrate through the film removal process, and then performing the fourth-stage flash etching to form a first layer pattern and a second layer pattern on the substrate.

[0011] In one embodiment, the step of performing solder resist treatment on the substrate to be packaged includes pretreatment of the surface layer of the substrate, solder resist coating, pre-baking, exposure, development and post-baking, to obtain a substrate with solder resist open in the solder area and solder resist protected in the non-solder area.

[0012] In one embodiment, prior to the step of performing solder resist treatment on the substrate to be packaged, the method further includes performing automated optical inspection on the substrate to be packaged.

[0013] In one embodiment, the electroplating process includes a pre-plating circuit treatment before the electroplating process, in which the substrate is sequentially pre-treated, coated with an anti-plating photosensitive film, exposed and developed to form an electroplating protective pattern.

[0014] In one embodiment, the electroplating gold process includes: electroplating gold on areas of the substrate surface that are not covered by the electroplated gold protective pattern and have electroplated gold lead pads.

[0015] The technical solutions provided in the embodiments of the present invention bring the following beneficial technical effects: The system-in-package substrate manufacturing method provided by the present invention is to produce substrates with different required thicknesses and with more cost-effective special thin copper through lamination. After multiple small-scale base copper thinning processes, the base copper thickness can be reduced. Combined with the improved semi-additive process, the yield of substrate production can be ensured to reach more than 97%, the overall production cost is better, and the product yield of system-in-package substrate is effectively guaranteed.

[0016] Additional aspects and advantages of this application will be set forth in the following sections and will be understood in detail from the following description, or may be learned by specific practice of the invention. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of a method for fabricating a system-in-package substrate according to an embodiment of the present invention; Figure 2 This is a schematic diagram of S100 of the method for fabricating a system-in-package substrate according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structural changes in step S200 of the method for fabricating a system-in-package substrate according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structural changes in step S300 of the method for fabricating a system-in-package substrate according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the structural changes in step S400 of the method for fabricating a system-in-package substrate according to an embodiment of the present invention. Detailed Implementation

[0018] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Possible embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein with reference to the drawings. The embodiments described with reference to the drawings are exemplary and intended to provide a more thorough and complete understanding of the disclosure of the invention, and should not be construed as limiting the invention. Furthermore, detailed descriptions of known techniques may be omitted where such details are not essential to the features of the illustrated invention.

[0019] Those skilled in the art will understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the prior art and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0020] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in the specification of this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that the term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0021] The technical solution of the present invention and how the technical solution solves the above-mentioned technical problems will be described in detail below with specific embodiments.

[0022] This invention provides a method for fabricating a system-in-package substrate, such as... Figures 1-5 As shown, it includes the following steps: S100: Two copper foils and a prepreg are laminated together in one step, with the rough surface of the copper foil bonded to the prepreg to obtain a substrate. Specifically, as shown... Figure 2 As shown, the copper foil has a thickness of 12µm and a surface roughness Rz ≤ 2.5µm. In the step of laminating two copper foils and a prepreg together, the lamination conditions are: lamination heating rate ≥ 10℃ / min, maximum lamination temperature ≥ 220℃, and maximum lamination pressure ≥ 400psi. Additionally, after obtaining the substrate, a PNL QR code is affixed to the edge of the substrate. Referring to production management information, a unique PNL QR code is affixed to the edge of the PNL using a QR code marking machine.

[0023] S200: The substrate undergoes first-stage flash etching, grinding and thinning, second-stage flash etching, and first-stage drilling, followed by copper foil etching for windowing and second-stage drilling to obtain a perforated substrate. Specifically, such as... Figure 3 As shown, in the first-stage flash etching step, the flash etching solution includes H2SO4: 25±3 g / L, H2O2: 8±1.5 g / L, and Cu. 2+The first-stage flash etching process used a copper surface roughening agent (H2SO4) of 20±4 g / L, with a flash etching temperature of 32.5±1℃ and a production rate of V1. The second-stage flash etching process used a production rate of 2V1. After the first-stage flash etching, the copper surface roughened, and the copper thickness was controlled at 8±0.3µm. The grinding and thinning operation was carried out using a dedicated 12-axis grinding machine with ceramic brush wheels: 4 x 1000 grit, 4 x 2000 grit, and 4 x 3000 grit. After grinding and thinning, the copper surface thickness was controlled at 5±0.3µm. The second-stage flash etching was the same as the first-stage flash etching, using conventional MGC CPE-800 flash etching solution with the following production parameters: H2SO4: 25±3 g / L, H2O2: 8±1.5 g / L, Cu... 2+ 20±4 g / L, temperature 32.5±1℃, production speed V2=2·V1. After the second-stage flash etching, the surface copper thickness is controlled at 3±0.3µm. Copper foil etching is performed to create windows, i.e., CFM windowing. The substrate is fabricated through a process of "pretreatment-lamination-exposure-development-etching". Windowing etching is first performed at the laser drilling locations. Laser drilling creates the required vias.

[0024] S300: After chemical copper plating on the via substrate, circuitry is laid out to form a substrate with selectively covered dry film patterns. Then, selective via-filling electroplating is performed, followed by third-stage flash etching, film removal, and fourth-stage flash etching to obtain the substrate to be packaged. For example... Figure 4 As shown, after removing the adhesive residue from the walls of the laser holes on the substrate, a chemical copper plating process (Plated Through Hole, abbreviated as PTH) is performed. Then, the substrate is processed through "pretreatment-lamination-exposure-development" to form a selectively covered dry film pattern, which is formed by covering the photosensitive anti-plating film area. Selective pattern electroplating is performed on the areas of the substrate surface not covered with the photosensitive film. Special pattern electroplating conditions are used, with a current density 10% higher than normal. The normal current density is 9 amps / square foot (i.e., 9 ASF). The entire board is designed with differentiated current efficiency and differentiated current control in multiple zones (e.g., the entire board is divided into upper, middle and lower zones, and three rectifiers are designed with differentiated current efficiency and control current). In order to meet the requirement of ≤5µm in the hole filling of high aspect ratio laser X-holes (laser X-hole depth ≥150µm), the copper thickness of conventional electroplating surface is increased by 30±3µm. The method of this application can achieve a copper thickness increase of only 24±3µm, which can fully meet the technical effect of ≤8µm in the copper depth of the electroplated surface, that is, the depth after selective hole filling electroplating is ≤8µm. Next, selective via filling and leveling are performed: the substrate is mechanically ground on 16 axes (ceramic brush wheels: 800 mesh*4+1000 mesh*4+2000 mesh*4+3000 mesh*4), and the copper thickness after grinding is controlled at 18±3µm (the copper thickness of conventional finished products is 15±3µm). After selective via filling and leveling, the dimple is ≤2µm.

[0025] S400: After solder resist treatment on the substrate to be packaged, gold plating is performed to obtain the packaged substrate.

[0026] The system-in-package substrate manufacturing method provided by the present invention produces substrates with different required thicknesses and more cost-effective special thin copper through lamination. After multiple small-scale base copper thinning processes, the base copper thickness can be reduced. Combined with the improved semi-additive process, the double-sided yield of the substrate production can be ensured to reach more than 99%, the overall production cost is better, and the product yield of the system-in-package substrate is effectively guaranteed.

[0027] In one specific implementation of the present invention, the steps of S300 for performing the third-stage flash etching, film removal, and fourth-stage flash etching further include using a chemical immersion, spraying, and agitation method to first remove the extended copper generated by mechanical grinding through the third-stage flash etching, then remove the selective protective layer on the substrate through a film removal process, and then perform the fourth-stage flash etching to form a first-layer pattern and a second-layer pattern on the substrate. Using a chemical immersion + spraying + agitation method, the copper extended by grinding is first removed through flash etching, then the selective protective layer on the substrate is removed, and then the entire substrate is flash etched a second time to form the first-layer pattern and the second-layer pattern. The wire bonding pads are etched downwards, and the etching spray pressure is 1.4 ± 0.3 Kg / cm². 2 (Standard spray pressure 1.4±0.3Kg / cm) 2 For wire bonding pads, the upper dimension is ≤60µm, the pad spacing is ≥20µm, the line width in dense circuit areas is 20~40µm, and the line spacing is 20~40µm.

[0028] In conjunction with the foregoing embodiments, in another embodiment of the present invention, such as Figure 5 As shown, the steps of performing solder resist treatment on the substrate to be packaged in S400 include pretreatment of the surface layer of the substrate, solder resist coating, pre-baking, exposure, development and post-baking, to obtain a substrate with open solder resist on the surface of the solder area and surface solder resist protection on the non-solder area.

[0029] In conjunction with the foregoing embodiments, in one specific implementation of the present invention, before the solder resist treatment on the substrate to be packaged in S400, an automated optical inspection of the substrate to be packaged is further included. A 100% visual inspection of the circuit layer on the substrate surface is performed, and the scrap coordinates are documented based on the QR code information on the board edge.

[0030] In conjunction with the foregoing embodiments and implementations, in another specific implementation of the present invention, the electroplating gold process in S400 further includes a pre-plating gold circuit processing step, in which the substrate is sequentially pre-treated, coated with an anti-plating photosensitive film, exposed and developed to form an electroplating gold protective pattern.

[0031] In conjunction with the foregoing embodiments and implementations, in yet another specific implementation of the present invention, such as... Figure 5As shown, the electroplating gold process in S400 includes: electroplating gold on areas of the substrate surface that are not covered with the electroplated gold protective pattern and have electroplated gold lead pads. Electroplating gold, often referred to as electroplating gold plating in the industry, is performed on areas of the substrate surface not covered with the photosensitive film and having electroplated gold lead pads. Electroplating conditions include: a 30% reduction in current density compared to normal conditions (current density 9ASF), and the inclusion of dummy gold-plated fingers (6 sets, 20*1mm in size) between factory-shipped samples. After electroplating: matrix-arranged wire bonding pads, with a top dimension of ≤60um, pad spacing ≥20um, and a 10% improvement in nickel thickness consistency.

[0032] The method for fabricating a system-in-package substrate provided by this invention has the following beneficial technical effects: 1. By laminating, special 12um thin copper foil with different thicknesses and more competitive price is produced. The roughness Rz of the special thin copper foil is ≤2.5um.

[0033] 2. Dedicated base copper thinning process: By using dedicated operating parameters and multiple small-batch base copper thinning operations, a base copper thickness of 3.0±0.3um can be achieved after thinning.

[0034] 3. Dedicated base copper thinning combined with mSAP process (modified semi-additive process): double-sided yield ≥99%, wire bonding pad size ≤60um, pad spacing ≥20um; dense circuit area line width 20~40um, line spacing 20~40um.

[0035] 4. Selective hole-filling electroplating combined with selective hole-filling leveling process: The overall copper thickness of the electroplated surface is more than 20% lower than that of the conventional method, and the hole-filling depression of the finished product is ≤2um.

[0036] 5. Professional electroplating operation conditions: By reducing the electroplating current density and laying dummy gold-plated fingers, the consistency of nickel plating thickness of matrix-arranged wire bonding pads is improved by more than 10%.

[0037] 6. Better overall cost: 12um thin copper, copper foil roughness Rz≤2.5um, compared with ultra-thin copper (ultra-thin copper thickness: 2 / 3um) process, the cost is reduced by 5%~10%.

[0038] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0039] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0040] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0041] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for fabricating a system-in-package substrate, characterized in that, Includes the following steps: Two copper foils and a prepreg are bonded together in one pressing process, with the rough surface of the copper foil bonded to the prepreg to obtain a substrate; The substrate is subjected to first-stage flash etching, grinding and thinning, second-stage flash etching and first drilling, and then copper foil etching to open windows and second drilling to obtain a perforated substrate. After chemically plating copper onto the via substrate, circuitry is laid out to form a substrate with selectively covered dry film patterns. Then, selective hole-filling electroplating is performed, followed by third-stage flash etching, film removal, and fourth-stage flash etching to obtain the substrate to be packaged. After solder resist treatment is performed on the substrate to be packaged, the packaged substrate is obtained after electroplating with gold.

2. The method for fabricating a system-in-package substrate according to claim 1, characterized in that, The copper foil has a thickness of 12µm and a roughness Rz≤2.5µm. In the step of bonding two copper foils and a prepreg together for one pressing, the pressing conditions are: pressing heating rate: ≥10℃ / min, maximum pressing temperature ≥220℃, and maximum pressing pressure ≥400psi.

3. The method for fabricating a system-in-package substrate according to claim 1, characterized in that, After obtaining the substrate, a PNL QR code is set on the edge of the substrate.

4. The method for fabricating a system-in-package substrate according to claim 1, characterized in that, In the first-stage flash etching step, the flash etching solution includes H2SO4: 25±3 g / L, H2O2: 8±1.5 g / L, and Cu. 2+ The flash etch rate was 20±4 g / L, the flash etch temperature was 32.5±1℃, and the production rate was V1; the production rate of the second-stage flash etch was 2V1.

5. The method for fabricating a system-in-package substrate according to claim 1, characterized in that, The step of selectively filling the holes includes selectively patterning the area of ​​the substrate surface not covered with the photosensitive film, and the depth of the copper pits on the plated surface is less than or equal to 8µm; after the selective filling the holes step, the substrate is further mechanically polished so that the depth of the copper pits on the plated surface is less than or equal to 2µm.

6. The method for fabricating a system-in-package substrate according to claim 1, characterized in that, The steps of performing the third-stage flash etching, film removal, and fourth-stage flash etching include first removing the extended copper generated by mechanical grinding through the third-stage flash etching by using chemical immersion, spraying, and agitation, then removing the selective protective layer on the substrate through the film removal process, and then performing the fourth-stage flash etching to form the first layer pattern and the second layer pattern on the substrate.

7. The method for fabricating a system-in-package substrate according to claim 1, characterized in that, The step of performing solder resist treatment on the substrate to be packaged includes pretreatment of the surface layer of the substrate, solder resist coating, pre-baking, exposure, development and post-baking, to obtain a substrate with open solder resist on the surface of the solder area and surface solder resist protection on the non-solder area.

8. The method for fabricating a system-in-package substrate according to claim 1, characterized in that, Before the step of performing solder resist treatment on the substrate to be packaged, the method further includes performing automated optical inspection on the substrate to be packaged.

9. The method for fabricating a system-in-package substrate according to claim 1, characterized in that, The process before electroplating gold also includes pre-plating circuit processing, in which the substrate is sequentially pre-treated, coated with an anti-plating photosensitive film, exposed and developed to form an electroplating gold protective pattern.

10. The method for fabricating a system-in-package substrate according to claim 9, characterized in that, The electroplating gold process includes: electroplating gold on the areas of the substrate surface that are not covered by the electroplated gold protective pattern and have electroplated gold lead pads.

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