Printed circuit board, layout method thereof and vehicle

Abstract

The invention discloses a printed circuit board, a layout method thereof and a vehicle, and relates to the technical field of printed circuit board layout. The method comprises the following steps: connecting a capacitor in series on a differential signal line of a physical layer chip; carrying out hollowing processing on the adjacent layer corresponding to the pin bonding pad based on a preset hollowing strategy; carrying out region division on the inner layer of the printed circuit board so as to divide the inner layer into a plurality of different regions; a plurality of backflow via holes are formed beside layer changing via holes of a circuit of the printed circuit board based on a preset setting strategy, and the backflow via holes are used for providing layer changing channels for backflow currents of the circuit on a reference plane when layers of the circuit are changed. By implementing the PCB design measures of capacitor series filtering, pad adjacent layer hollowing, inner layer segmentation and isolation and backflow via hole optimization, the problem that electromagnetic compatibility radiation and conducted emission exceed the standard due to PHY circuit filtering loss, impedance mismatch, power ground noise coupling and unreasonable high-speed signal backflow path in the traditional TBOX design is effectively solved.

Description

Technical Field

[0001] This application relates to the field of printed circuit board layout technology, and more particularly to a method for laying out a printed circuit board, a printed circuit board, and a vehicle. Background Technology

[0002] With the continuous development of vehicle-to-everything (V2X) technology, the Telematics Box (TBOX), as a core component connecting vehicles and external networks, integrates multiple functional units such as cellular communication modules, global navigation satellite system (GNSS) receiver front-ends, and digital circuits (such as main processors and physical layer chips), leading to increasingly severe challenges to its electromagnetic compatibility performance.

[0003] Currently, TBOX's PCB (Printed Circuit Board) layout design has several key defects in terms of electromagnetic compatibility: On the one hand, the grounding system design is too simplified, using only a complete and undivided unified ground plane, which allows high-frequency digital noise and cellular module radio frequency noise to interfere with the entire circuit board without obstruction, especially polluting the simulated ground of the global navigation satellite system and seriously degrading the receiving sensitivity; On the other hand, although some designs attempt to divide the ground plane, due to insufficient dividing gaps or the presence of multiple grounding points, it is very easy to form large-size ground loops. These loops not only pick up low-frequency magnetic field interference like an antenna, but also introduce common-mode interference due to the potential difference between different grounding points. On the other hand, electromagnetic compatibility optimization measures for PHY (Physical Layer) circuits are generally lacking. Differential signal transmission lines lack effective filtering structures, and component pin pads are not designed with impedance compensation. At the same time, the power plane and ground plane are not coordinated to block noise coupling paths, and the return path of high-speed signal lines is not properly optimized when switching layers. Ultimately, this results in TBOX radiated emission and conducted emission indicators generally exceeding the standard by 2-3dB in electromagnetic compatibility design verification and preliminary testing.

[0004] However, most related technologies rely on local remedial measures, such as adding external filters, but fail to fundamentally solve the problem at the level of system architecture and local circuit co-optimization. These technologies suffer from inherent limitations, including high costs, limited improvement effects, and difficulty in adapting to the continuously increasing integration requirements of TBOX. Therefore, how to systematically solve the electromagnetic compatibility emission exceedance problem caused by insufficient PHY circuit filtering, impedance mismatch, power supply-ground noise coupling, and unreasonable high-speed signal return paths, starting from PCB layout design, has become a critical technical bottleneck that urgently needs to be overcome in current TBOX design and engineering. Summary of the Invention

[0005] This application aims to at least partially address one of the technical problems in related technologies. To this end, the first objective of this application is to propose a layout method for a printed circuit board (PCB). The PCB has physical layer chips and pin pads. The layout method includes: connecting capacitors in series on the differential signal lines of the physical layer chips; hollowing out adjacent layers corresponding to the pin pads based on a preset hollowing-out strategy; dividing the inner layers of the PCB into multiple different regions; and setting multiple return vias next to the layer-change vias of the PCB traces based on a preset setting strategy. These return vias provide a layer-change path for the return current of the traces on a reference plane when the traces change layers. This application effectively solves the electromagnetic compatibility (EMC) radiation and conducted emission exceedance problems caused by insufficient PHY circuit filtering, impedance mismatch, power-to-ground noise coupling, and unreasonable high-speed signal return paths in traditional TBOX designs by implementing PCB design measures such as capacitor series filtering, pad adjacent layer hollowing-out, inner layer segmentation and isolation, and return via optimization.

[0006] The second objective of this application is to provide a printed circuit board.

[0007] The third objective of this application is to propose a vehicle.

[0008] To achieve the above objectives, the first aspect of this application proposes a layout method for a printed circuit board. The printed circuit board has a physical layer chip and pin pads. The layout method includes: connecting capacitors in series on the differential signal lines of the physical layer chip; performing hollowing-out processing on the adjacent layers corresponding to the pin pads based on a preset hollowing-out strategy; dividing the inner layers of the printed circuit board into multiple different regions; and setting multiple return vias next to the layer-change vias of the printed circuit board lines based on a preset setting strategy. The return vias are used to provide a layer-change channel for the return current of the lines on a reference plane when the lines change layers.

[0009] According to one embodiment of this application, the differential signal line includes a positive differential signal line and a negative differential signal line. Connecting a capacitor in series on the differential signal line of the physical layer chip includes: connecting the capacitor in series on the positive differential signal line and the negative differential signal line respectively, wherein the series connection position of the capacitor is adjacent to the pin of the physical layer chip, the trace width at both ends of the capacitor is a first spacing, and the spacing between the positive differential signal line and the negative differential signal line is a second spacing.

[0010] According to one embodiment of this application, the preset cutout strategy includes a cutout range, wherein the cutout range is a first distance extending outward from the edge of the pin pad.

[0011] According to one embodiment of this application, a printed circuit board includes a first signal layer, a power layer, a ground layer, and a second signal layer. The inner layer includes a power layer and a ground layer, and multiple different regions include a first region, a second region, a third region, and a fourth region. Dividing the inner layer of the printed circuit board into multiple different regions includes: dividing the power layer into a first region and a second region based on a preset dividing gap; and dividing the ground layer into a third region and a fourth region corresponding to the power layer, using the dividing boundary of the power layer as the dividing boundary of the ground layer.

[0012] According to one embodiment of this application, the first region and the third region are connected by a first decoupling capacitor, and the second region and the fourth region are connected by a second decoupling capacitor, wherein the first decoupling capacitor and the second decoupling capacitor are arranged close to the corresponding chip power supply pins.

[0013] According to one embodiment of this application, the preset setting strategy includes the location information and diameter information of the return via, wherein the location information includes the center distance between the return via and the layer change via.

[0014] According to one embodiment of this application, a cellular communication module, digital circuits, and a global navigation satellite system receiving front-end are also disposed on the printed circuit board. The digital circuits include physical layer chips, and the layout method further includes: arranging the cellular communication module, digital circuits, and global navigation satellite system receiving front-end in partitions on the printed circuit board based on electromagnetic characteristics.

[0015] According to one embodiment of this application, a cellular communication module is arranged in the upper left corner of the printed circuit board, a digital circuit is arranged in the upper right corner of the printed circuit board, and a global navigation satellite system receiving front-end is arranged in the lower right corner of the printed circuit board, wherein the spacing between the cellular communication module, the digital circuit and the global navigation satellite system receiving front-end is not less than a third spacing.

[0016] To achieve the above objectives, a second aspect of this application provides a printed circuit board, which is generated according to the aforementioned printed circuit board layout method.

[0017] To achieve the above objectives, a third aspect of this application provides a vehicle including the aforementioned printed circuit board.

[0018] According to the printed circuit board and its layout method and vehicle of the embodiments of this application, by implementing PCB design measures such as capacitor series filtering, pad adjacent layer cut-out, inner layer segmentation and isolation, and return via optimization, the electromagnetic compatibility radiation and conducted emission exceeding the standard caused by the lack of PHY circuit filtering, impedance mismatch, power supply and ground noise coupling, and unreasonable high-speed signal return path in traditional TBOX design is effectively solved. First, by connecting matching capacitors in series on the differential signal lines of the physical layer chip, high-frequency harmonic noise is effectively suppressed and DC bias interference is blocked, reducing emission noise at the source; second, by precisely cutting out the adjacent layers of the pin pads, the impedance at the pads is compensated, and the overall impedance deviation of the signal path is controlled within ±5Ω, significantly reducing signal reflection (reflection coefficient ≤-20dB) and ensuring the integrity of high-speed signals; third, by coordinating the segmentation of the power and ground planes, the power supply and grounding systems of digital and analog circuits are physically and electrically isolated, cutting off digital noise through The path of coupling from the common plane to sensitive analog circuits (such as the receiver front end of a global navigation satellite system) ensures receiver sensitivity. Finally, return vias are placed next to the line layer change vias to provide the shortest continuous path for return current, reducing the return loop area by more than 70% and fundamentally suppressing electromagnetic interference caused by loop radiation. In addition, this application is entirely achieved through optimization at the PCB layout and routing level, without the need to add any external filtering components or shielding structures. While significantly improving EMC performance and signal quality, it achieves zero increase in hardware cost and zero PCB area occupation. Attached Figure Description

[0019] Figure 1 A flowchart generated for a printed circuit board layout method according to some embodiments of this application; Figure 2 This is a schematic diagram of the structure of a vehicle according to some embodiments of this application. Detailed Implementation

[0020] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0021] The following describes in detail, with reference to the accompanying drawings, the printed circuit board, the layout method thereof, and the vehicle, according to embodiments of this application.

[0022] In some embodiments, a four-layer printed circuit board structure is used as an example for illustration, but this is not intended to limit the scope of this application. Specifically, the printed circuit board includes a first signal layer (top layer), a power layer (inner layer), a ground layer (inner layer), and a second signal layer (bottom layer). Physical layer chips and pin pads are disposed on the printed circuit board. The specific parameters of the printed circuit board are as follows: Board size: 80mm × 60mm; Dielectric material: FR-4 (Flame Retardant 4, flame retardant rating 4), dielectric constant ; Layer thickness: The first signal layer (top layer) is 0.035mm thick, the power layer (inner layer) is 0.07mm thick, the ground layer (inner layer) is 0.07mm thick, and the second signal layer (bottom layer) is 0.035mm thick. Interlayer dielectric thickness: The distance between the first signal layer (top layer) and the power layer (inner layer) is 0.2 mm, the distance between the power layer (inner layer) and the ground layer (inner layer) is 0.3 mm, and the distance between the ground layer and the second signal layer (bottom layer) is 0.2 mm.

[0023] Figure 1 This is a flowchart illustrating a printed circuit board layout method according to some embodiments of this application. (Refer to...) Figure 1 The printed circuit board layout method of this application embodiment may include the following steps: S110 connects a capacitor in series with the differential signal line of the physical layer chip. The capacitance value can be determined according to the actual situation; for example, the capacitance value can be 10pF, and there is no specific limitation here.

[0024] Specifically, after a capacitor is connected in series on the differential signal line of the PHY chip, the capacitor, along with the trace inductance and the physical layer chip input impedance, forms a low-pass filter. The cutoff frequency is set higher than the base frequency (125MHz) of 100Mbps or Gigabit Ethernet signals, and it can effectively suppress high-frequency noise above 200MHz, covering second-order and third-order harmonics. At the same time, the capacitor acts as an AC coupling element, blocking the DC bias voltage difference between the PHY chip and the connected device, and its impedance to a 125MHz signal is approximately 0.13Ω, which can avoid signal attenuation to a certain extent.

[0025] To further illustrate the above embodiments, in this application embodiment, the differential signal lines include positive differential signal lines and negative differential signal lines. Connecting capacitors in series on the differential signal lines of the physical layer chip includes: connecting capacitors in series on both the positive and negative differential signal lines, wherein the series connection of the capacitors is adjacent to the pins of the physical layer chip, the trace width at both ends of the capacitor is a first spacing, and the spacing between the positive and negative differential signal lines is a second spacing. Both the first and second spacings can be determined according to actual conditions; for example, the first spacing can be 0.2mm and the second spacing can be 0.3mm, without specific limitations.

[0026] Specifically, the differential signal lines of the physical layer chip include TXD+ / TXD- and RXD+ / RXD-. TXD+ / TXD- refers to a pair of differential signal lines on the physical layer chip used for transmitting data, and RXD+ / RXD- refers to a pair of differential signal lines on the physical layer chip used for receiving data. TXD+ and RXD+ are positive differential signal lines, while TXD- and RXD- are negative differential signal lines. That is, capacitors are connected in series with TXD+ and TXD- respectively, and capacitors are also connected in series with RXD+ and RXD- respectively. Specifically, capacitors C1 and C2 are connected in series with the TXD+ and TXD- differential pair; capacitors C3 and C4 are connected in series with the RXD+ and RXD- differential pair. The parameters of C1 and C2 must be strictly matched, and the parameters of C3 and C4 must also be strictly matched.

[0027] Furthermore, the capacitors are connected in series near the pins of the physical layer chip to achieve source filtering and impedance control of high-speed differential signals using the shortest path. The trace widths at both ends of the capacitors are a first spacing, which to some extent ensures that signals are not reflected due to abrupt changes in trace width when entering and leaving the capacitors. Specifically, capacitor C1 is near the TXD+ pin of the physical layer chip, capacitor C2 is near the TXD- pin, capacitor C3 is near the RXD+ pin, and capacitor C4 is near the RXD- pin. Moreover, the spacing between the positive and negative differential signal lines is a second spacing; that is, the spacing between TXD+ and TXD-, and the spacing between RXD+ and RXD-, is a second spacing to meet impedance requirements. For example, to meet a 100Ω requirement, the second spacing is set to 0.3mm.

[0028] This application constructs a high-frequency noise suppression and impedance compensation structure located close to the noise source by connecting capacitors in series with the positive and negative differential signal lines, respectively, and precisely controlling the trace width at both ends of the capacitors and the differential pair spacing. This effectively filters out high-order harmonic noise and, to a certain extent, avoids excessive radiated emissions. Simultaneously, the capacitors, as AC coupling components, also eliminate DC bias interference between devices. This effectively solves the core problem of excessive EMC emissions caused by insufficient filtering in the physical layer circuit and impedance mismatch. Furthermore, this optimization is achieved entirely at the PCB layout and routing level, without relying on any external high-cost filtering components or complex modules. While significantly improving EMC (Electromagnetic Compatibility) performance, it minimizes hardware material costs. Additionally, the compact partitioned design adapts to the increased integration requirements of TBOX without occupying additional PCB area.

[0029] S120 performs hollowing-out processing on the adjacent layer corresponding to the pin pad based on a preset hollowing-out strategy.

[0030] Specifically, the PIN pads of the PHY circuit and other high-speed signal-related components can be located on either the first signal layer (top layer) or the second signal layer (bottom layer). If the PIN pad is located on the first signal layer (top layer), the adjacent layer is the power layer, and the power layer is hollowed out based on a preset hollowing-out strategy. If the PIN pad is located on the second signal layer (bottom layer), the adjacent layer is the ground layer, and the ground layer is hollowed out based on a preset hollowing-out strategy. The preset hollowing-out strategy can specify the shape and size of the hollowing-out operation.

[0031] Since the characteristic impedance of a transmission line is proportional to the distance (dielectric thickness) from the signal line to the reference plane of the adjacent layer, the cutout process can instantly increase the effective distance between the signal line and the reference plane of the adjacent layer in the pad area, compensate for the impedance drop caused by the increase in line width at the pad, make the impedance deviation of the entire signal path (including the pad segment) ≤ ±5Ω, approach the target impedance of 100Ω, and reduce impedance mismatch and signal reflection.

[0032] To further illustrate the above embodiments, in this application embodiment, the preset cutout strategy includes a cutout range, wherein the cutout range is a first distance extending outward from the edge of the pin pad. The first distance can be determined according to actual conditions; for example, the first distance can be 0.5mm, and no specific limitation is made here.

[0033] Specifically, if the pin pad is located on the first signal layer (top layer), and the adjacent layer is the power layer, then the power layer area corresponding to the pin pad (the power layer directly below the pin pad) is hollowed out, with the hollowing range being the first distance extended outward from the edge of the pin pad. If the pin pad is located on the second signal layer (bottom layer), and the adjacent layer is the ground layer, then the ground layer area corresponding to the pin pad (the ground layer directly below the pin pad) is hollowed out, with the hollowing range being the first distance extended outward from the edge of the pin pad. This ensures that the distance from the signal line in the pad area to the ground layer increases from 0.2mm to 0.5mm, compensating for the impedance decrease caused by the increase in pad line width. The measured impedance is 98Ω, with a deviation ≤2Ω.

[0034] This application implements a preset cutout strategy to cut out the adjacent layer corresponding to the pin pad. This instantly increases the effective distance between the signal line and the reference plane of the adjacent layer in the pad area, successfully compensating for the local impedance drop caused by the increase in pad area. It strictly controls the impedance deviation of the entire high-speed signal path, including the pad, within ±5Ω, with a measured deviation ≤2Ω, and approaches the target impedance value of 100Ω. It can also significantly reduce the reflection coefficient of high-speed signals (such as 100Mbps / 1Gbps Ethernet signals) to below -20dB during transmission, greatly suppressing signal reflection and waveform distortion, ensuring the signal integrity of high-speed circuits such as the PHY inside the TBOX, and avoiding faults such as data packet loss or communication interruption caused by signal distortion.

[0035] S130 divides the inner layer of the printed circuit board into regions, thereby dividing the inner layer into multiple different regions.

[0036] Specifically, the inner layers of the printed circuit board include a power plane and a ground plane. The power plane is divided into multiple electrically isolated independent areas to accommodate the power supply requirements of different functional units. Simultaneously, the ground plane is divided into multiple corresponding areas to achieve precise control over noise isolation and signal return. Through the coordinated partitioning of the power and ground planes, the cross-regional coupling path of high-frequency noise within the board is blocked from a physical structural perspective, constructing a clear current return path and providing clean power and reference ground for each circuit module.

[0037] To further illustrate the above embodiments, in this application embodiment, the printed circuit board includes a first signal layer, a power layer, a ground layer, and a second signal layer. The inner layer includes a power layer and a ground layer, and multiple different regions include a first region, a second region, a third region, and a fourth region. Dividing the inner layer of the printed circuit board into multiple different regions includes: dividing the power layer into a first region and a second region based on a preset dividing gap; and dividing the ground layer into a third region and a fourth region corresponding to the power layer, using the dividing boundary of the power layer as the dividing boundary of the ground layer. The preset dividing gap can be determined according to actual conditions; for example, the preset dividing gap can be 1 mm, and no specific limitation is made here.

[0038] Specifically, when dividing the inner layers of a printed circuit board (PCB), the power layer and ground layer need to be divided simultaneously to ensure that the division boundaries of the power layer and the ground layer are aligned. Specifically, firstly, the power layer is divided into a first region (analog power) and a second region (digital power) based on a preset division gap. Then, the division boundaries of the power layer are used as the division boundaries of the ground layer to divide the ground layer into a third region (analog ground) and a fourth region (digital ground) corresponding to the power layer.

[0039] In other words, the printed circuit board is divided into analog circuit area and digital circuit area. The analog circuit area includes a first area of ​​power layer (analog power) and a third area of ​​ground layer (analog ground), and the first area (analog power) and the third area (analog ground) are in the same vertical projection area. The digital circuit area includes a second area of ​​power layer (digital power) and a fourth area of ​​ground layer (digital ground), and the second area (digital power) and the fourth area (digital ground) are in another vertical projection area.

[0040] To further illustrate the above embodiments, in this application embodiment, the first region and the third region are connected by a first decoupling capacitor, and the second region and the fourth region are connected by a second decoupling capacitor, wherein the first decoupling capacitor and the second decoupling capacitor are arranged close to the corresponding chip power supply pins.

[0041] For example, the first region (analog power supply) and the third region (analog ground) can be connected via a first decoupling capacitor, wherein the capacitance value of the first decoupling capacitor can be 0.1μF, and the number of first decoupling capacitors can be 10; the second region (digital power supply) and the fourth region (digital ground) can be connected via a second decoupling capacitor, wherein the capacitance value of the second decoupling capacitor can be 0.1μF, and the number of second decoupling capacitors can be 20. Furthermore, the first and second decoupling capacitors are arranged close to the corresponding chip power supply pins.

[0042] The fast switching current (ΔI) generated during the operation of digital circuits creates voltage fluctuations (ΔV = ΔI × Z_PDN, i.e., ground bounce or power supply noise) on their own power distribution network impedance (Z_PDN). Traditional coplanar designs allow this noise to directly pollute analog circuits through the common plane. This application, however, physically isolates analog power supply-analog ground and digital power supply-digital ground, strictly confining digital noise within the digital region and preventing it from entering the analog region through planar coupling, thus ensuring the purity of analog power supply and analog ground.

[0043] S140, based on a preset setting strategy, sets multiple return vias next to the layer-change vias of the printed circuit board, wherein the return vias are used to provide a layer-change channel for the return current of the circuit on the reference plane when the circuit changes layers.

[0044] Specifically, the printed circuit board (PCB) traces can be PHY circuits and other high-speed lines, such as 100Mbps or 1Gbps Ethernet signal lines, PHY chip differential signal lines, etc. Based on a preset setting strategy, multiple return vias can be set next to the layer-change vias on the PCB traces. This provides a low-resistance layer-change path for the return current on the reference plane when the trace changes layers, thus avoiding the formation of large-size return loops after the return path is interrupted, reducing the electromagnetic radiation area and sensitivity to external interference. The preset setting strategy defines the location and diameter information of the return vias.

[0045] To further illustrate the above embodiments, in this application embodiment, the preset setting strategy includes the position information and diameter information of the return via, wherein the position information includes the center distance between the positional relationship between the return via and the layer change via.

[0046] For example, when the differential signal line of the PHY chip changes from the first signal layer (top layer) to the second signal layer (bottom layer), the diameter of the layer-changing via can be 0.3mm, and one return via is provided on each side of the layer-changing via. The diameter of the return via can be 0.3mm, the center distance between the return via and the layer-changing via can be 2.5mm, and the return via directly connects the ground layer (inner layer) and the second signal layer (bottom layer).

[0047] This application provides a low-impedance vertical channel for the return current that is forcibly interrupted during signal layer switching by setting a return via next to the line layer switching via according to a preset strategy. This allows the return current to switch the reference plane synchronously with the signal path, thereby reducing the large loop area formed by the return path detour and significantly reducing the radiating antenna efficiency equivalent to the high-speed switching current.

[0048] Currently, printed circuit board (PCB) layout designs suffer from unreasonable functional zoning. For example, placing cellular communication modules, which are both high-speed digital circuits and high-power radio frequency transmitters, close to digital ICs such as the main processor results in excessively close physical distances between noise sources (digital circuits), strong interference sources (cellular modules), and highly sensitive circuits (Global Navigation Satellite System receiver front-end). This provides pathways for electromagnetic interference to occur through space radiation, power networks, and ground plane coupling, leading to a high system noise floor. Therefore, this application proposes a zoned layout of the cellular communication module, digital circuits, and Global Navigation Satellite System receiver front-end on the PCB based on electromagnetic characteristics to reduce external interference coupling.

[0049] In some embodiments, the printed circuit board is further provided with a cellular communication module, digital circuits and a global navigation satellite system receiving front end, wherein the digital circuits include physical layer chips, and the layout method further includes: arranging the cellular communication module, digital circuits and global navigation satellite system receiving front end in partitions on the printed circuit board based on electromagnetic characteristics.

[0050] Specifically, based on electromagnetic characteristics, the cellular communication module (a high-frequency, high-radiation source) can be placed in an independent area on the edge of the board, supplemented by shielding and impedance matching design, to control its radio frequency radiation and reduce external interference; the digital circuits (including the main processor, the digital part of the physical layer chip, and other high-speed switching noise sources) can be concentrated in the middle of the board or a specific area, and their noise can be limited to this area through complete power / ground plane partitioning; the global navigation satellite system receiver front end (a highly susceptible and sensitive analog circuit) can be placed away from the above noise sources in a clean area on the board, and an independent analog power supply and grounding channel can be provided for it.

[0051] To further illustrate the above embodiments, in this application embodiment, a cellular communication module is arranged in the upper left corner of the printed circuit board, a digital circuit is arranged in the upper right corner of the printed circuit board, and a global navigation satellite system receiving front-end is arranged in the lower right corner of the printed circuit board. The distance between the cellular communication module, the digital circuit, and the global navigation satellite system receiving front-end is not less than a third distance. This third distance can be determined according to actual conditions; for example, it can be 5mm, and no specific limitation is made here.

[0052] Specifically, the cellular communication module can be placed in the upper left corner of the printed circuit board, the digital circuit in the upper right corner, and the global navigation satellite system (GNSS) receiver front-end in the lower right corner. The spacing between the cellular communication module, the digital circuit, and the GNSS receiver front-end should be no less than a third spacing, for example, 6mm between the cellular module and the digital circuit, 5mm between the digital circuit and the GNSS receiver front-end, and 12mm between the cellular module and the GNSS receiver front-end. Furthermore, the GNSS receiver front-end, being an extremely sensitive circuit, is placed at the edge of the printed circuit board, away from the cellular communication module (a strong interference source), to further reduce external interference coupling.

[0053] In summary, this application effectively solves the electromagnetic compatibility radiation and conducted emission exceedance problems caused by the lack of PHY circuit filtering, impedance mismatch, power supply and ground noise coupling, and unreasonable high-speed signal return paths in traditional TBOX designs by implementing PCB design measures such as capacitor series filtering, pad clearance in adjacent layers, inner layer segmentation and isolation, and optimized return vias.

[0054] First, by connecting matching capacitors in series on the differential signal lines of the physical layer chip, high-frequency harmonic noise is effectively suppressed and DC bias interference is blocked, reducing emission noise at its source. Second, by precisely hollowing out the adjacent layers of the pin pads, the impedance at the pads is compensated, and the overall impedance deviation of the signal path is controlled within ±5Ω, significantly reducing signal reflection (reflection coefficient ≤-20dB) and ensuring the integrity of high-speed signals. Third, by coordinating the partitioning of the power and ground planes, physical and electrical isolation is achieved between the power supply and grounding systems of digital and analog circuits, cutting off digital noise transmission. The path of coupling from the common plane to sensitive analog circuits (such as the receiver front end of a global navigation satellite system) ensures receiver sensitivity. Finally, return vias are placed next to the line layer change vias to provide the shortest continuous path for return current, reducing the return loop area by more than 70% and fundamentally suppressing electromagnetic interference caused by loop radiation. In addition, this application is entirely achieved through optimization at the PCB layout and routing level, without the need to add any external filtering components or shielding structures. While significantly improving EMC performance and signal quality, it achieves zero increase in hardware cost and zero PCB area occupation.

[0055] Corresponding to the above embodiments, this application also proposes a printed circuit board.

[0056] The printed circuit board of this application is generated according to the aforementioned printed circuit board layout method.

[0057] It should be noted that the above explanation of the embodiments and beneficial effects of the printed circuit board layout method also applies to the printed circuit boards of the embodiments of this application. To avoid redundancy, they will not be elaborated in detail here.

[0058] Corresponding to the above embodiments, this application also proposes a vehicle 10.

[0059] See Figure 2 As shown, the vehicle 10 of this application includes the aforementioned printed circuit board 100.

[0060] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0061] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0062] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0063] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0064] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0065] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A layout method for a printed circuit board, characterized in that, The printed circuit board has a physical layer chip and pin pads, and the layout method includes: Connect the capacitor in series on the differential signal line of the physical layer chip; Based on a preset hollowing strategy, the adjacent layer corresponding to the pin pad is hollowed out. The inner layer of the printed circuit board is divided into regions to separate the inner layer into multiple different regions; Based on a preset setting strategy, multiple return vias are set next to the layer-change vias of the circuits on the printed circuit board. The return vias are used to provide a layer-change channel for the return current of the circuits on the reference plane when the circuits change layers.

2. The layout method for a printed circuit board according to claim 1, characterized in that, The differential signal lines include positive differential signal lines and negative differential signal lines. Connecting a capacitor in series with the differential signal lines of the physical layer chip includes: The capacitors are connected in series on the positive differential signal line and the negative differential signal line, respectively. The series connection of the capacitors is close to the pins of the physical layer chip. The trace width at both ends of the capacitors is a first spacing, and the spacing between the positive differential signal line and the negative differential signal line is a second spacing.

3. The printed circuit board layout method according to claim 1, characterized in that, The preset cutout strategy includes a cutout range, wherein the cutout range is a first distance extended outward from the edge of the pin pad.

4. The layout method for a printed circuit board according to claim 1, characterized in that, The printed circuit board includes a first signal layer, a power layer, a ground layer, and a second signal layer. The inner layer includes a power layer and a ground layer. The plurality of different regions include a first region, a second region, a third region, and a fourth region. Dividing the inner layer of the printed circuit board into multiple different regions includes: The power layer is divided into regions based on a preset dividing gap, so as to divide the power layer into the first region and the second region; The power layer's partition boundary is used as the ground layer's partition boundary. The ground layer is then divided into regions, namely the third region and the fourth region, which correspond to the power layer.

5. The printed circuit board layout method according to claim 4, characterized in that, The first region and the third region are connected by a first decoupling capacitor, and the second region and the fourth region are connected by a second decoupling capacitor. The first decoupling capacitor and the second decoupling capacitor are arranged close to the corresponding chip power supply pins.

6. The printed circuit board layout method according to claim 4, characterized in that, The preset setting strategy includes the position information and diameter information of the return via, wherein the position information includes the center distance between the return via and the layer-changing via.

7. The layout method for a printed circuit board according to claim 1, characterized in that, The printed circuit board also includes a cellular communication module, digital circuitry, and a global navigation satellite system receiver front-end. The digital circuitry includes the physical layer chip, and the layout method further includes: Based on electromagnetic properties, the cellular communication module, the digital circuit, and the global navigation satellite system receiving front end are arranged in sections on the printed circuit board.

8. The layout method for a printed circuit board according to claim 7, characterized in that, in, The cellular communication module is arranged in the upper left corner of the printed circuit board, the digital circuit is arranged in the upper right corner of the printed circuit board, and the global navigation satellite system receiving front end is arranged in the lower right corner of the printed circuit board. The spacing between the cellular communication module, the digital circuit and the global navigation satellite system receiving front end is not less than a third spacing.

9. A printed circuit board, characterized in that, The printed circuit board is generated according to the layout method of the printed circuit board according to any one of claims 1-8.

10. A vehicle, characterized in that, Including the printed circuit board as described in claim 9.

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