Protected electronic device for preventing damage caused by plasma-assisted process

Abstract

The present disclosure relates to a protective electronic device for preventing damage caused by a plasma-assisted process and a method of manufacturing the same. An electronic device includes a circuit module and a protection module. The circuit module includes a P-N junction between a reference terminal and an electrical node, and a metal connection line coupled to the electrical node and configured to be charged due to an antenna effect. The protection module includes an HV transistor and a capacitor. The capacitor is connected between the electrical node and the HV transistor and is configured to turn on the HV transistor when the electrical node is positively charged due to the antenna effect. Thus, the circuit module is maintained at a potential that does not damage the electronic device.

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims the benefit of priority of Italian Patent Application No. 102024000021052, filed on September 20, 2024, the contents of which are hereby incorporated by reference in its entirety herein to the maximum extent permitted by law. TECHNICAL FIELD

[0003] The present invention relates to an electronic device and a manufacturing method thereof, in particular to a protection device for preventing plasma-induced damages due to charging caused by the antenna effect of a metal layer injecting positive charges into an underlying doped region during a manufacturing process. BACKGROUND

[0004] In the technologies for manufacturing very large scale integration (VLSI) circuits (ICs), the formation of metal lines, in particular metal interconnections, on a semiconductor substrate requires a plurality of plasma-assisted process steps. These process steps include, for example: plasma-assisted deposition steps, such as physical vapor deposition (e.g., of the “sputtering” type), chemical vapor deposition (e.g., of the plasma-enhanced chemical vapor deposition (PECVD) type); and plasma-assisted etching steps, such as reactive ion etching (e.g., of the reactive ion etching (RIE) type).

[0005] These plasma-assisted process steps cause a significant amount of charge to be injected into a doped region located within the semiconductor substrate and connected to a metal region of large size, such as, for example, a metal interconnection line. During these process steps, the metal region actually acts as a charge collector and transfers the collected charge to the above-mentioned doped region. This effect is known as the “antenna effect”.

[0006] Integrated circuits for intelligent power management (e.g., "smart power" integrated circuits) are known in the art. In smart power as well as digital and imaging integrated circuits, a buried region (referred to as a "deep N-well" or "DNW") doped with N-type conductivity extending deep into the substrate is used to insulate analog and / or digital circuit blocks from the substrate to protect these circuit blocks from noise and possible parasitic currents injected into the substrate by the power stage. One drawback resulting from the use of DNWs is that the efficiency of the discharge of accumulated charge during plasma processes to the ground terminal through the substrate is low. This can result in the circuit blocks insulated by the DNW being subjected to voltages high enough to cause damage, in particular to the gate oxide. For example, if the body terminal of a MOS transistor is connected or coupled to the ground terminal and its gate terminal is connected or coupled to a circuit block insulated by a DNW charged during a plasma process, the potential difference between the body and gate terminals of the MOS transistor can cause breakdown of the gate oxide of the MOS transistor. A similar breakdown mechanism of the gate oxide of a MOS transistor can occur in the case where the body terminal is connected to or belongs to a circuit block insulated by a DNW charged during a plasma process and the gate terminal is connected or coupled to the ground terminal.

[0007] Figure 1 A portion of the integrated circuit 1 is schematically illustrated in a lateral cross-sectional view in the xz plane of a tri-axial system of mutually orthogonal axes x, y, z.

[0008] The integrated circuit 1 comprises a solid body 2 which in turn comprises: a substrate 4 of a semiconductor material such as, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN); a patterned oxide layer 5 extending at a first face 4a of the substrate 4 and comprising openings through which portions of the first face 4a of the substrate 4 are exposed; and a dielectric layer 3 extending on the patterned oxide layer 5 in direct contact with the exposed portions of the first face 4a of the substrate 4 and with the patterned oxide layer 5. The substrate 4 has, for example, P-type conductivity. In general, the substrate 4 can comprise one or more structural layers of a semiconductor material (e.g., the same material as that described above for the substrate 4); for example, the one or more structural layers are epitaxially grown.

[0009] The integrated circuit 1 further comprises a first circuit block 6 extending at least partially into the substrate 4 and at least partially into the dielectric layer 3, and a second circuit block 8 extending at least partially into the substrate 4 and at least partially into the dielectric layer 3 laterally and along the x-axis at a distance from the first circuit block 6.

[0010] The first circuit block 6 comprises a first P-type MOS transistor ("P-MOS") 10 located in a first N-type doped region ("first N-well") 12 of the substrate 4, and an N-type MOS transistor ("N-MOS") 14 located in a P-type doped region ("P-well") 16. In a view on the XY plane, the P-well region 16 is entirely surrounded by the first N-well 12, and faces a first face 4a of the substrate 4. The first circuit block 6 further comprises a first N-type doped buried region ("first deep N-well" or "first DNW") 18, which extends buried in the substrate 4 partly within the first N-well 12 and the P-well 16, and partly in a portion between the N-well 12 / P-well 16 and a second face 4b of the substrate 4 (opposite to the first face 4a along the Z axis). The first DNW 18 is thus in direct electrical contact with the first N-well 12 and the P-well 16.

[0011] The first circuit block 6 further comprises four metal interconnections 20 extending into the dielectric layer 3 and in electrical contact with respective doped regions between the first N-well 12 and the P-well 16 at the first face 4a of the substrate 4.

[0012] The metal interconnections 20 are formed from a plurality of metal layers 22(1)-22(N) stacked along the z axis and with portions of the dielectric layer 3 interposed therebetween; vias extend into portions of the dielectric layer 3 between the metal layers 22(1)-22(N), thereby electrically connecting the metal layers 22(1)-22(N) to each other and to the substrate 4. The number N of metal layers is in the range of, for example, 2 to 21, and is equal to 6, for example.

[0013] The second circuit block 8 comprises a second P-type MOS transistor ("second P-MOS transistor") 24 located in a second N-type doped region ("second N-well") 26 of the substrate 4, and a second N-type doped buried region ("second deep N-well" or "second DNW") 28. The second DNW 28 extends buried in the substrate 4 partly within the second N-well 26 and partly within a portion of the substrate 4 between the second N-well 26 and the second face 4b of the substrate 4. The second DNW 28 is thus in electrical contact with the second N-well 26.

[0014] A P-N junction is formed at the interface between the first N-well 12 / first DNW 18 and the substrate 4, which electrically insulates the first circuit block 6 from the substrate 4 when reverse-biased. Similarly, a respective P-N junction is formed at the interface between the second N-well 26 / second DNW 28 and the substrate 4, which electrically insulates the first circuit block 6 from the substrate 4 when reverse-biased.

[0015] The first P-MOS transistor 10, the N-MOS transistor 14 and the second P-MOS transistor 24 comprise in a known manner a respective source terminal 10a, 14a, 24a, a respective drain terminal 10b, 14b, 24b, a respective gate terminal 10c, 14c, 24c and a respective body terminal 10d, 14d, 24d. The gate terminal 10c, 14c, 24c comprises a respective conductive portion 10c', 14c' and 24c' and a respective gate dielectric 10c", 14c" and 24c".

[0016] In the integrated circuit 1, the gate terminal 24c of the second P-MOS transistor 24 is electrically connected to the drain terminal 10b of the first P-MOS transistor 10 and to the drain terminal 14b of the N-MOS transistor 14 by means of a connection 23 provided in a manner known per se (not shown in the figures). Figure 1 The connection 23 is formed in the first metal layer 22(1) in a manner not shown in the figures. Figure 1

[0017] During the manufacture of the metal interconnect 20, the progressively formed part of the metal interconnect 20 acts as a collector of positive charges in a plasma process step after the manufacture of the first metal layer 22(1). The positive charges are transferred from the plasma to the metal interconnect 20 and injected from the metal interconnect 20 into the first circuit block 6. The first DNW 18 prevents the accumulated positive charges from being dispersed towards the substrate 4 and thus towards the ground terminal GND connected to the substrate 4 by insulating the first circuit block 6 from the substrate 4. The resulting accumulation of positive charges within the first circuit block 6 leads to an increase in the potential difference between the first circuit block 6 and the substrate 4.

[0018] In the integrated circuit 1, the second N-well 26 is directly electrically connected to a metal interconnect 20 (not shown in the figures) having a very small area, such as to not inject significant charges. The second N-well 26, and thus the body of the second P-MOS transistor 24, thus remains substantially at the same potential as the substrate 4 and thus close to the ground potential GND. At the same time, the gate terminal 24c of the second P-MOS transistor 24 is connected to the drain terminals 10b and 14b and thus at the potential of the first circuit block 6. If the potential difference between the gate terminal 24c and the body of the second P-MOS transistor 24 exceeds the breakdown threshold of the gate dielectric 24c", the gate dielectric 24c" experiences electrical breakdown, leading to a malfunction of the entire integrated circuit 1.

[0019] ​The breakdown mechanism described above can occur during a plasma assisted process whenever a device located in a first circuit block (here block 8) has a gate terminal driven by a device located in a second circuit block (here block 6), and one of the first and second circuit blocks has a metal structure (here structure 20) that can act as a charge collector, both circuit blocks being insulated from the substrate by a respective deep N-well.

[0020] A known technique to protect the gate dielectric 24c" is to connect in parallel a protection diode between the gate terminal 24c and the base of the transistor 24. The accumulated charge in the first circuit block 6 is discharged into the base of the transistor 24 by the reverse (or forward) current of the protection diode. However, depending on the process parameters, the current of the protection diode can not be sufficient to effectively discharge the accumulated charge, thus not providing adequate protection. Moreover, the protection diode can introduce noise during the operation of the device, thus degrading its performance.

[0021] Therefore, there is a need to provide an electronic device and a method of manufacturing the same, such as to overcome the drawbacks of the prior art. SUMMARY

[0022] In an embodiment, an electronic device comprises: a circuit module; and a protection module. The circuit module comprises: a P-N junction electrically coupled between a reference terminal and an electrical node; and a plurality of metal connection lines electrically coupled to the electrical node and configured to be charged with positive charges due to antenna effect when a plasma process is performed. The protection module comprises: a first transistor having an N-channel, the first transistor having a first conductive terminal and a second conductive terminal and a control terminal; and a capacitive component. The second conductive terminal of the first transistor is electrically coupled to the electrical node, the first conductive terminal of the first transistor is electrically coupled to the reference terminal, and the control terminal of the first transistor is capacitively coupled to the electrical node through the capacitive component.

[0023] In an embodiment, a method of manufacturing an electronic device comprises the steps of: forming a circuit module; and forming a protection module. The step of forming the circuit module comprises: forming a P-N junction electrically coupled between a reference terminal and an electrical node; and forming, by one or more plasma assisted processes, a plurality of metal connection lines electrically coupled to the electrical node and configured to be charged with positive charges due to antenna effect when the one or more plasma assisted processes are performed. The step of forming the protection module comprises: forming a first transistor having an N-channel, the first transistor having a first conductive terminal and a second conductive terminal and a control terminal; and forming a capacitive component. The second conductive terminal of the first transistor is electrically coupled to the electrical node, the first conductive terminal of the first transistor is electrically coupled to the reference terminal, and the capacitive component is formed between the control terminal of the first transistor and the electrical node to electrically couple the control terminal to the electrical node. BRIEF DESCRIPTION OF DRAWINGS

[0024] For a better understanding of the present application, reference will now be made, purely by way of non-limiting example, to some embodiments thereof which are described in the accompanying drawings in which:

[0025] Figure 1 schematically illustrates a portion of an integrated circuit;

[0026] Figure 2A illustrates a circuit diagram of a protection circuit of an integrated circuit according to one embodiment and during a step of a manufacturing process;

[0027] Figure 2B illustrates a circuit diagram of the protection circuit at the end of the manufacturing process; Figure 2A

[0028] Figure 2C illustrates a circuit diagram of another embodiment of a branch of the protection circuit of Figure 2A

[0029] Figure 2D illustrates a circuit diagram of another embodiment of the same branch of the protection circuit of Figure 2C Figure 2A

[0030] Figure 3 schematically illustrates a portion of an integrated circuit comprising the protection circuit of Figure 2A

[0031] Figure 4A illustrates the protection circuit of in a top plan view; Figure 2A

[0032] Figure 4B schematically illustrates an embodiment of a branch of the protection circuit of in a lateral cross-sectional view along the section line I-I of Figure 4A Figure 2A

[0033] Figure 4C schematically illustrates an embodiment of another branch of the protection circuit of in a lateral cross-sectional view along the section line II-II of Figure 4A Figure 2A

[0034] Figure 5A schematically illustrates the protection circuit of in a top plan view; Figure 2B

[0035] Figure 5B schematically illustrates a branch of after the formation of the last level metal interconnects in a lateral cross-sectional view along the section line III-III of Figure 5A Figure 4C ​​​​​​​​​​​​​

[0036] Figure 6A one embodiment of a capacitor of a protection circuit of Figure 2A and Figure 2B is schematically illustrated in a top plan view;

[0037] Figure 6B another embodiment of a capacitor of a protection circuit of Figure 2A and Figure 2B is schematically illustrated in a top plan view;

[0038] Figure 7 schematically illustrates a portion of an integrated circuit comprising a protection circuit according to another embodiment; and

[0039] Figures 8A-8F illustrates manufacturing steps of a portion of the protection circuit shown in Figure 5B DETAILED DESCRIPTION

[0040] Figure 2A Fig. 1 illustrates a circuit diagram of a protection circuit 50 of an integrated circuit 100 according to one embodiment. In particular, the protection circuit 50 is a portion of the integrated circuit 100 and is manufactured simultaneously with the integrated circuit 100.

[0041] Figure 2A Fig. 2 illustrates the protection circuit 50 during a first step of a manufacturing process of the integrated circuit 100.

[0042] The protection circuit 50 is connected to other elements of the integrated circuit 100 at a node 104, as better illustrated below.

[0043] The integrated circuit 100 comprises a diode 102, an anode 102a of which is connected to a ground terminal GND and a cathode 102b of which is connected to the node 104. One or more metal interconnects 20 of the integrated circuit 100 are connected to the node 104. As reference is made to Fig. 1, the metal interconnects 20 are connected to the node 104 at a location of the node 104 which is not covered by the diode 102. Figure 1 ​Said, such metal interconnection 20 acts as a collector of electric charges during the plasma-assisted processes, generating the above-mentioned "antenna effect". The protection circuit 50 further comprises a capacitor 108 having a capacitance C comprised between 0.1 fF and 100 fF, for example equal to 10 fF, and comprising a first terminal coupled to the node 104 through the first metal connection 101 and a second terminal coupled to the gate node 110 through the second metal connection 103. The protection circuit 50 further comprises a high-voltage N-type MOS transistor (hereinafter referred to as "HV-NMOS transistor") 112 of the type known per se, comprising a source terminal 112a coupled to the ground terminal GND through the third metal connection 105, a drain terminal 112b coupled to the node 104 through the fourth metal connection 107, a gate terminal 112c coupled to the gate node 110 through the fifth metal connection 109, and a bulk terminal 112d coupled to the source terminal 112a through the sixth metal connection 111. The HV-NMOS transistor 112 is configured to withstand a maximum bias voltage applied to the gate terminal 112c, for example in the range between 3.6 V and 5.5 V. Moreover, the HV-NMOS transistor 112 is configured to withstand an expected bias voltage of the node 104 during the operating conditions of the integrated circuit, for example up to 100 V or even higher.

[0044] The ground terminal GND is at a reference potential V0, for example equal to 0 V.

[0045] The manufacturing process of the integrated circuit 100, in particular of the metal interconnection 20, comprises deposition steps and mask etching steps of metallic and dielectric materials. Such deposition steps and mask etching steps are carried out by plasma-assisted processes. During each plasma-assisted process, the progressively manufactured portion of the metal interconnection 20 accumulates positive electric charges due to the antenna effect.

[0046] In the presence of the accumulation of positive electric charges, the node 104 is at a potential VI greater than the potential V0. Therefore, there is a voltage drop V D on the P-N junction diode 102, which causes its reverse bias. The reverse bias of the P-N junction diode 102 prevents the dissipation of the accumulated positive electric charges towards the ground terminal GND.

[0047] The first branch 50a of the protection circuit 50 comprises the ground terminal GND, the third metal connection 105, the source terminal 112a, the sixth metal connection 111, the bulk terminal 112d, the gate terminal 112c, the fifth metal connection 109, the gate node 110, the second metal connection 103, the capacitor 108, the first metal connection 101 and the node 104. The HV-NMOS transistor 112 comprises, in a manner known per se, a gate dielectric 112c" (see below with reference to Figure 2) between the gate terminal 112c and the bulk terminal 112d.Figure 3 (Description to be provided) and has a gate capacitance C G On the first branch 50a, the capacitance C of capacitor 108 is equal to the gate capacitance C of HV-NMOS transistor 112. G A voltage divider is formed between them. The capacitance C of capacitor 108 and the gate capacitance C of HV-NMOS transistor 112 are... G The value of is designed or selected such that a voltage drop below the breakdown voltage of the gate dielectric 112c'' is generated across the gate dielectric 112c''. Specifically, the voltage divider causes the voltage drop V between the gate terminal 112c and the source terminal 112a of the HV-NMOS transistor 112 to be denoted as . GS It is the voltage drop V D A certain proportion, between 9 / 10 and 1 / 10, specifically equal to 1 / 2. Similarly, the voltage drop V across the terminals of capacitor 108. C It is the voltage drop V D A certain proportion, which is between 1 / 10 and 9 / 10, and in particular equal to 1 / 2.

[0048] The second branch 50b of the protection circuit 50 includes a ground terminal GND, a third metal connection 105, a source terminal 112a, a drain terminal 112b, a fourth metal connection 107, and a node 104. On the second branch 50b, when charge accumulates at node 104 due to the antenna effect, a voltage drop V is established between the drain terminal 112b and the source terminal 112a of the HV-NMOS transistor 112. DS The voltage drop V DS Equal to voltage drop V D Therefore, the voltage drop V GS It is the voltage drop V DS A certain proportion, which is between 9 / 10 and 1 / 10, and in particular equal to 1 / 2.

[0049] As the amount of positive charge accumulated at node 104 increases, the voltage drop V... D The value of also increases. Therefore, the voltage drop V DS and V GS The value increases. When the voltage drop V... D When the voltage V exceeds a certain value (e.g., between 0.6 V and 5 V) depending on the tolerance of the circuit block to be protected, GS Exceeding the turn-on threshold voltage V of the HV-NMOS transistor 112 TH (Between 0.5 V and 2 V, especially 1 V); thus, the conductive channel of the HV-NMOS transistor 112 is formed. Due to the voltage drop V DS It is positive and greater than the voltage drop V. GSThe HV-NMOS transistor 112 is thus turned on and sustains a current I between the drain terminal 112b and the source terminal 112a ON . The current I ON flows from the node 104, through the fourth metal connection 107, the drain terminal 112b, the source terminal 112a, the third metal connection 105, and is discharged through the ground terminal GND, thereby dissipating the positive charge accumulated at the node 104 and reducing the voltage drop V D . When the voltage drop V D drops below a certain value (for example, between 0.6 V and 2 V, for example equal to 1 V), the voltage drop V GS drops below the threshold voltage V TH of the HV-NMOS transistor 112, which turns off.

[0050] During the plasma-assisted process, the HV-NMOS transistor 112 is configured to turn on when the potential VI of the node 104 exceeds a predetermined value deemed harmful to the integrity of the integrated circuit 100 (for example, VI = 3 V). During the plasma-assisted process, the HV-NMOS transistor 112 is also configured to sustain a current I ON , such as to discharge the node 104, and to turn off when the potential VI of the node 104 drops below said value deemed harmful to the integrity of the integrated circuit 100, without the need to apply an external bias voltage by means of a voltage generator dedicated to this purpose.

[0051] Figure 2C A first branch 50a of the protection circuit 50 is illustrated, in which the intrinsic capacitance of the HV-NMOS transistor 112 is shown. In particular, the branch 50a of the protection circuit 50 comprises a gate-drain intrinsic capacitance C GD connected in parallel with the capacitor 108 between the drain terminal 112b and the gate terminal 112c of the HV-NMOS transistor 112. The capacitance C of the capacitor 108 and the intrinsic capacitance C GD are in parallel to form a capacitance 114 connected between the node 104 and the gate terminal 112c.

[0052] The intrinsic capacitance C GD has a value, for example, between 0.5 fF and 10 fF, in particular equal to 1 fF.

[0053] During the operation of the protection circuit 50, the capacitance 114, previously already referred to with reference to Figure 2AThe capacitor 108 operates similarly to the one described. The capacitor 114 has a higher value than the individual capacitance C of the capacitor 108, thereby facilitating the conduction of the HV-NMOS transistor 112, and the capacitor 114 is particularly suitable for situations where the circuit block to be protected cannot withstand high voltages (e.g., voltages above 0.6 V).

[0054] Branch 50a of the protection circuit 50 also includes the gate-source intrinsic capacitance C. GS and gate-body intrinsic capacitance C GB They are connected in parallel to each other and are respectively connected between the gate terminal 112c and the source terminal 112a, and between the gate terminal 112c and the body terminal 112d. Intrinsic capacitance C GS With intrinsic capacitance C GB The parallel connection between them forms the aforementioned gate capacitance C. G The gate capacitance C G It is connected between the gate terminal 112c and the ground terminal GND and in series with the capacitor 114.

[0055] Figure 2D Another embodiment of the first branch 50a of the protection circuit 50 is illustrated. Figure 2D In the embodiment shown, only intrinsic capacitance C exists between the gate terminal 112c and the drain terminal 112b. GD In this embodiment, capacitor 108, first metal connection 101, and second metal connection 103 are not present. Operation and reference of protection circuit 50. Figure 2A The descriptions are similar. Specifically, the intrinsic capacitance C... GD It operates similarly to the aforementioned capacitor 108. (See reference...) Figure 2D The described embodiments require a small circuit area and are suitable for situations where the circuit block to be protected can withstand high voltages (e.g., up to 2.5 V).

[0056] Figure 2B The illustration shows the second manufacturing step of integrated circuit 100, particularly at the end of the manufacturing process of integrated circuit 100. Figure 2A Protection circuit 50. In Figure 2B In the middle, the protection circuit 50 and Figure 2A The common components of the protection circuit 50 are indicated by the same reference numerals and will not be described further.

[0057] Figure 2BThe protection circuit 50 comprises a seventh metal connection 113 connecting the gate node 110 to the source terminal 112a of the HV-NMOS transistor 112. In one embodiment, the seventh metal connection 113 is formed at least partially within the last metal layer of the metal interconnects 20. For example, the seventh metal connection 113 is formed by short-circuiting portions of the metal interconnects 20 connected to the gate node 110 and to the source terminal 112a, respectively.

[0058] Then, at the end of the manufacturing process of the metal interconnects 20, the seventh metal connection 113 is configured to short-circuit the gate terminal 112c and the source terminal 112a of the HV-NMOS transistor 112. Therefore, in the protection circuit 50, at the end of the manufacturing process, the voltage drop V GS forced to the value equal to 0 V, thus forcing the HV-NMOS transistor 112 into the off state, regardless of the potential value VI of the node 104. Therefore, the HV-NMOS transistor 112 is turned off without the need to apply an external bias voltage to the HV-NMOS transistor 112 by means of a voltage generator dedicated to this purpose. By turning off the HV-NMOS transistor 112 as described above, the node 104 is allowed to reach the operating voltage without undesirably leaking current to the ground terminal GND, and in particular, this voltage can even be higher than the voltage to which the integrated circuit 100 is limited during the process of use.

[0059] It should be noted that the operation of the protection circuit 50 described with reference to Figure 2B is provided independently of whether the first branch 50a of the circuit 50 is according to the embodiment of Figure 2A , Figure 2C or Figure 2D .

[0060] Figure 3 A wider portion of the integrated circuit 100 comprising the protection circuit 50 described with reference to Figures 2A-2B is schematically illustrated. In particular, Figure 3 a lateral cross-sectional view on the xz plane in a three-axial system with mutually orthogonal x, y, z axes, using a mixed graphical representation with structural elements and circuit diagrams, is used to facilitate the representation and the comparison with Figures 2A-2B the portion of the integrated circuit 100.

[0061] The protection circuit 50 is electrically connected to the circuit of the type shown in Figure 1 and formed by the first circuit block 6 and the second circuit block 8 described with reference to Figure 1 , respectively. The first circuit block 6, the second circuit block 8 and the protection circuit 50 as a whole form the integrated circuit 100.

[0062] ReferenceFigure 1 The components of the first circuit block 6 and the second circuit block 8 described in Figure 3 The same reference numerals are used to identify the embodiments, and they will not be described further unless it is appropriate to describe them for a better understanding of the described embodiments.

[0063] Specifically, the integrated circuit 100 includes a solid body 2, which in turn includes a substrate 4, a dielectric layer 3, and a patterned oxide layer 5 extending on a first surface 4a of the substrate 4. More specifically, the dielectric layer 3 includes a stack 203 of dielectric layers (hereinafter also referred to as "dielectric stack 203") extending on the substrate 4 and in direct contact with the first surface 4a of the substrate 4 and the patterned oxide layer 5.

[0064] The patterned oxide layer 5 has an opening through which surface 4a of the substrate 4 is exposed. The patterned oxide layer 5 is formed, for example, by mask oxidation of the substrate 4, deposition of an insulating material (e.g., silicon oxide), or alternatively by an etching step of the substrate 4 and a deposition step in which silicon oxide is deposited in the etched area until the etched area is filled. The thickness of the insulating layer 5 along the z-axis is, for example, between 0.1 µm and 0.5 µm (inclusive), and particularly equal to 0.35 µm.

[0065] The substrate 4 is specifically made of a semiconductor material, such as, for example, silicon (Si), silicon carbide (SiC), etc. The substrate 4 may alternatively be of the SOI ("silicon-on-insulator") type.

[0066] Substrate 4 has, for example, a first conductivity of P-type, wherein the dopant concentration is 1 x 10⁻⁶. 14 at / cm 3 Up to 1x10 18 at / cm 3 Within a certain range, for example, equal to 1x10 15 at / cm 3 In one embodiment, substrate 4 comprises multiple stacked layers, such as multiple layers of semiconductor material. In another embodiment, substrate 4 is a single layer. The thickness of substrate 4 along the z-axis is, for example, between 100 µm and 1000 µm (inclusive of the boundary of this range), particularly equal to 725 µm. Substrate 4 at least partially forms a reference. Figure 2A The described PN junction diode 102 has an anode 102a and is connected to the ground terminal GND. During manufacturing, the substrate 4 is capacitively coupled to a substrate support configured to operate as the ground terminal GND.

[0067] The substrate 4 also includes a first doped region (“first N-well”) 12, a second doped region (“second N-well”) 26, and a third doped region (“third N-well”) 230, which have a second conductivity (e.g., N-type) opposite to the first conductivity, wherein the dopant concentration is 1 x 10⁻⁶. 16 at / cm 3 Up to 1x10 18 at / cm 3 Within a certain range, for example, equal to 1x10 17 at / cm 3 The first N-well 12, the second N-well 26, and the third N-well 230 are spaced a certain distance from each other. The protection circuit 50 includes the third N-well 230.

[0068] The substrate 4 also includes a first ohmic contact region 4c, which is in direct contact with the dielectric stack 203 through a corresponding opening in the patterned oxide layer 5; the first ohmic contact region 4c has a first conductivity (P) and particularly in 1x10 19 at / cm 3 Up to 4x10 20 at / cm 3 Within the range, for example, equal to 2x10 20 at / cm 3 The doping concentration is specified. The first ohmic contact region 4c is configured to form an electrical contact with the substrate 4. The first N-well 12, the second N-well 26, the third N-well 230, and the first ohmic contact region 4c extend towards the first surface 4a and extend into the substrate 4 in depth, terminating within the substrate 4 but not reaching the second surface 4b of the substrate 4. The first N-well 12, the second N-well 26, and the third N-well 230 are in direct physical contact with the dielectric stack 203 through corresponding openings in the patterned oxide layer 5.

[0069] The first N-well 12, the second N-well 26, and the third N-well 230 are respectively laterally defined by the first peripheral portion 12b, the second peripheral portion 26b, and the third peripheral portion 230b, forming corresponding PN junctions with the corresponding portions of the substrate 4.

[0070] The substrate 4 also includes a first buried region (“first DNW”) 18, a second buried region (“second DNW”) 28, and a third buried region (“third DNW”) 234, which extend and are embedded in the substrate 4. Specifically, the third DNW 234 extends partially within the third N-well 230 and partially extends within a portion of the substrate 4 located between the third N-well 230 and the second surface 4b, and is therefore in direct electrical contact with the third N-well 230.

[0071] Specifically, the first DNW 18, the second DNW 28, and the third DNW 234 have a diameter between 1x10. 17at / cm 3 between 1 x 10 20 at / cm 3 and, for example, equal to 1 x 10 19 at / cm 3 corresponding N-type dopant concentration.

[0072] The first, second and third DNWs 18, 28, 234 form respective P-N junctions with respective portions of the substrate 4, which are adjacent to and electrically continuous with the P-N junctions formed between the substrate 4 and the first, second and third N-wells 12, 26, 230. Such P-N junctions electrically insulate the first, second and third N-wells 12, 26, 230 from the substrate 4 when reverse biased.

[0073] In one embodiment, the first N-well 12 comprises a second ohmic contact region 12c having a second conductivity (N) and a dopant concentration higher than the dopant concentration of the N-wells 12, 26, 230, and in particular in the range of 1 x 10 19 at / cm 3 to 4 x 10 20 at / cm 3 , for example equal to 2 x 10 20 at / cm 3 . The second ohmic contact region 12c extends at the face 4a and is in direct contact with the dielectric stack 203 through a respective opening in the insulating layer 5. At least a portion of the first N-well 12 forms the cathode 102b of the P-N junction diode 102. The second ohmic contact region 12c of the first N-well 12 at least partially forms the node 104.

[0074] In embodiments where reference is made to Figure 1 , similarly to what is described with reference to , the first N-well 12 accommodates the source terminal 10a and the drain terminal 10b of the first P-MOS transistor 10 and the second N-well 26 accommodates the source terminal 24a and the drain terminal 24b of the second P-MOS transistor 24. The gate terminals 10c, 24c of the first and second P-MOS transistors 10, 24 respectively comprise respective gate-conductive portions 10c', 24c' and gate dielectrics 10c", 24c" extending into the dielectric stack 203 in a manner known per se.

[0075] The first N-well 12 and the third N-well 230 comprise, respectively, a first doped portion ("first P-well") 16 and a second doped portion ("second P-well") 232, having a first conductivity (P) and having a certain dopant concentration, which is higher than the dopant concentration of the N-wells 12, 230, and in particular in the range of 1 x 1018at / cm3to 1 x 1020at / cm3, for example equal to 1 x 1019at / cm3. 16 at / cm 3 to 1 x 1020at / cm3. 18 at / cm 3 at / cm 17 at / cm 3 .

[0076] The first P-well 16 and the second P-well 232 extend facing the first face 4a and extend in depth into the substrate 4. In a plan view on the xy plane, the first P-well 16 and the second P-well 232 are completely surrounded by the first N-well 12 and the third N-well 230, respectively.

[0077] The first P-well 16 accommodates the source terminal 14a and the drain terminal 14b of the N-MOS transistor 14.

[0078] The second P-well 232 accommodates the source terminal 112a, the drain terminal 112b and the body terminal 112d of the HV-NMOS transistor 112. The gate terminals 14c and 112c of the N-MOS transistor 14 and of the HV-NMOS transistor 112 comprise, in a per se known manner, respectively, a respective gate conductive portion 14c', 112c' extending into the dielectric stack 203 at the first face 4a of the substrate 4 and a respective gate dielectric 14c", 112c".

[0079] In another embodiment (not shown), the first N-well 12 comprises a plurality of P-MOS transistors and a plurality of P-wells, which in turn at least partially comprise respective N-MOS transistors. In another embodiment, the second N-well 26 also similarly comprises a plurality of P-MOS transistors and one or more P-wells, which in turn at least partially comprise one or more respective N-MOS transistors.

[0080] The dielectric stack 203 comprises a metal pre-dielectric layer 207 (reference Figures 4B-4C illustrated and described in greater detail) and a multilayer intermetal dielectric layer 209(1)-209(M) (reference Figures 4B-4C illustrated and described in greater detail). The thickness of the dielectric stack 203 along the z axis is for example comprised between 1 μm and 10 μm, in particular equal to 5 μm.

[0081] The dielectric stack 203 also accommodates one or more metal interconnections 20. The metal interconnections 20 comprise one or more metal layers 22(1)-22(N) (hereinafter referred to as metal layer 22) and a plurality of metal vias 21(1)-21(L) electrically connecting the metal layers 22(1)-22(N) to each other and to the substrate 4. Figures 4B-4C In more detail, the metal interconnections 20 comprise a first metal layer 22(1) and a second metal layer 22(2) (hereinafter referred to as metal layers 22(1) and 22(2), respectively). The metal layers 22(1) and 22(2) are electrically connected to each other by a plurality of metal vias 21(1)-21(L) (hereinafter referred to as metal vias 21).

[0082] The metal connections 23 electrically couple, in particular by the first metal layer 22(1) and the respective metal vias, the gate terminal 24c of the second P-MOS transistor 24 with the drain terminals 10d, 14d of the first P-MOS transistor 10 and the N-MOS transistor 14.

[0083] The dielectric stack 203 also comprises a reference Figure 2A and Figure 2B The metal connections 101, 103, 105, 107, 109, 111 and 113 of the protection circuit 50 and the capacitor 108 (the latter is hereinafter referred to as capacitor 108) described above are formed by the metal interconnections 20. Figure 4C and Figures 6A-6B In more detail, the first metal connection 101 connects the second ohmic contact region 12c to a first terminal of the capacitor 108, the second metal connection 103 connects a second terminal of the capacitor 108 to the gate node 110, the third metal connection 105 connects the source terminal 112a to the first ohmic contact region 4c, and thus to the substrate 4 (which forms the ground terminal GND). The fourth metal connection 107 connects the drain terminal 112b to the second ohmic contact region 12c, the fifth metal connection 109 connects the gate node 110 to the gate terminal 112c, thereby electrically coupling the second terminal of the capacitor 108 with the gate terminal 112c. Further, the sixth metal connection 111 connects the body terminal 112d to the first ohmic contact region 4c. When the seventh metal connection 113 is present (i.e., as mentioned, at the end of the manufacturing of the integrated circuit 100), the gate node 110 is connected to the source terminal 112a.

[0084] The metal connections 101, 103, 105, 107, 109, 111 can be formed at the same metal layer (e.g., the first metal layer 22(1)). With reference to Figure 2A The capacitor 108 described above can also be formed in the same metal layer as the metal connections 101, 103, 105, 107, 109, 111. However, other embodiments are possible, as shown below with reference to Figure 4C , Figure 5B and Figures 6A-6B For example, at least some of the metal connections 101, 103, 105, 107, 109, 111 can be formed in respective metal layers 22(1)-22(N) different from each other.

[0085] By utilizing the first metal layer 22 (1) to form metal connections 101, 103, 105, 107, 109, 111 and capacitor 108, the operability of the HV-NMOS transistor 112 during the fabrication steps following the patterning step of the first metal layer 22 (1), at least until the deposition of the final metal layer 22 (N), is ensured (and thus protected from plasma-induced damage). In one embodiment where the capacitor 108 is at least partially formed at the first metal layer 22 (1), the solid body 2 also includes a conductive region 108a ( Figure 4A , Figure 4C , Figures 5A-5B and Figure 6A As shown in the diagram, the conductive region 108a extends into the metal front dielectric layer 207. The conductive region 108a is configured to at least partially form the first plate of the capacitor 108.

[0086] In one embodiment, reference Figure 2B The described metal connection 113 is formed on the last metal layer 22 (N) (see Figure 5B )middle.

[0087] Figure 4A A reference illustratively illustrates, in a top view on the xy plane, a representation of one embodiment, and limited to some relevant elements for understanding that embodiment. Figure 2A The protection circuit 50 is described. Figures 4B-4C The reference is schematically illustrated in the transverse cross-sectional view on the xz plane. Figure 2A The corresponding part of the described protection circuit 50, wherein Figures 4B-4C The transverse cross-sectional views are respectively along Figure 4A The lines II and II-II are cut off. Figures 4A-4C In the middle, the protection circuit 50 and Figures 2A-2B and Figure 3 The common components of the protection circuit 50 are indicated by the same reference numerals and will not be described further where appropriate.

[0088] like Figures 4B-4C As shown, the front metal dielectric layer 207 and the inter-metal dielectric layers 209(1)-209(M) form a dielectric stack 203 as a whole. In one embodiment, the front metal dielectric layer 207 and the inter-metal dielectric layers 209(1)-209(M) are respective insulating or dielectric materials, such as, for example, silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), etc.

[0089] Figures 4B-4COne or more metal layers 22(1)-22(N-1) shown extend parallel to the xy plane within the dielectric layer 203, are a certain distance from the first surface 4a of the substrate 4, and are a certain distance from each other along the z-axis. Among the metal layers 22(1)-22(N), the first metal layer 22(1) is closest to the first surface 4a of the substrate 4, while the metal layers 22(N) ( Figures 4B-4C (Not shown in the image) is the last metal layer, that is, among the metal layers 22(1)-22(N), it is furthest from the first surface 4a of the substrate 4; the metal layers 22(2)-22(N-1) extend between the first metal layer 22(1) and the last metal layer 22(N).

[0090] Specifically, the first metal layer 22 (1) has a first side facing a first surface 4a of the substrate 4, and a second side facing the second metal layer 22 (2) along the z-axis opposite to the first side. A front metal dielectric layer 207 extends at least partially between the substrate 4 and the first metal layer 22 (1), and has a first surface 207a in direct physical contact with the first metal layer 22 (1), and a second surface 207b in direct physical contact with the first surface 4a of the substrate 4 and the first surface 5a of the insulating layer 5 along the z-axis opposite to the first surface. Each intermetallic dielectric layer 209 (1)-209 (M) extends at least partially between and in direct physical contact with the metal layers 22 (1)-22 (N-1). Depending on the manufacturing process of the integrated circuit 100, the number M of intermetallic dielectric layers 209 (1)-209 (M) can be assumed to be less than, equal to, or greater than the number N of the metal layers 22 (1)-22 (N).

[0091] The metal layers 22(1)-22(N) are, for example, copper (Cu) or aluminum (Al), with a thickness between 0.1 µm and 10 µm. The metal vias 21(1)-21(L) are, for example, made of copper (Cu) or tungsten (W).

[0092] refer to Figures 4A-4B The first portion 236 of the first metal layer 22 (1) extends in a principal dimension parallel to the x-axis between its first end placed at the second ohmic contact region 12c and its second end placed at the drain terminal 112b. The first portion 236 is electrically coupled to the second ohmic contact region 12c (node ​​104) through a metal via 21 (1) and electrically coupled to the drain terminal 112b through a corresponding metal via 21 (2), thereby forming at least partially the fourth metal connection 107.

[0093] The second portion 238 of the first metal layer 22(1) extends in the xy-plane at a distance from the first portion 236 with a main dimension parallel to the x-axis, has a first end at the source terminal 112a and a second end at the first ohmic contact region 4c, and is coupled to the source terminal 112a and the first ohmic contact region 4c, respectively, through the metal via 21(3) and the further metal via 21(4), thereby at least partially forming the third metal connection 105. The second portion 238 of the first metal layer 22(1) is also electrically coupled to the body terminal 112d at least through the metal via 21(5) at a region between its first end and its second end, thereby forming (with the metal via 21(4)) the metal connection 111.

[0094] Figure 4C An embodiment of the first branch 50a of the protection circuit 50 is illustrated in a non-limiting way.

[0095] With reference to Figure 4A and Figure 4C The third portion 240 of the first metal layer 22(1) extends in the xy-plane at a distance from the first portion 236 and the second portion 238, and has a first end at the second ohmic contact region 12c (node 104) and a second end at the gate terminal 112c.

[0096] The third portion 240 is also divided into three sub-portions 240a, 240b and 240c. The first sub-portion 240a extends between a first end at the second ohmic contact region 12c and a second end at a peripheral portion of the first plate 108a, and is coupled to the second ohmic contact region 12c through the respective metal via 21(6) and to the first plate 108a through the further respective metal via 21(7). The second sub-portion 240b extends in a plan view on the xy-plane at a distance from the first sub-portion 240a at the first plate 108a. The second sub-portion 240b has a first end facing and at a distance from the first sub-portion 240a and a second end in electrical contact with the third sub-portion 240c. In particular, the second sub-portion 240b at least partially forms the second plate 108b of the capacitor 108. The third sub-portion 240c has a first end in electrical contact with the second sub-portion 240b and a second end at the gate terminal 112c, and is electrically coupled to the gate terminal 112c of the HV-NMOS transistor 112 through the metal via 21(8), thereby forming the fifth electrical connection 109.

[0097] In a view on the xy plane, a portion 108c of the second metal layer 22 (2) extends over the first intermetallic dielectric layer 209 (1) at the first plate 108a and the second plate 108b, and is coupled to the first sub-part 240a at one end via a metal via 21 (7)'. In one embodiment, in a view on the xy side, the first plate 108a, the second plate 108b and the third plate 108c have a polygonal shape, substantially square or rectangular, and the first plate, the second plate and the third plate have first dimensions Lxa, Lxb, Lxc along the x-axis between 1 µm and 100 µm; and corresponding second dimensions Lya, Lyb, Lyc along the y-axis between 1 µm and 100 µm.

[0098] The conductive region 108a is made of, for example, a metallic material or doped polycrystalline silicon (Poly-Si), exhibiting N-type conductivity, and the dopant concentration is between 1 x 10⁻⁶. 19 at / cm 3 With 2x10 21 at / cm 3 Between, specifically equal to 1x10 21 at / cm 3 The conductive region 108a may be patterned, for example, during a manufacturing process step configured to form the conductive portions 210c', 214c', 224c', 112c'.

[0099] Therefore, according to one embodiment, the first plate 108a, the second plate 108b, and the third plate 108c are formed and implemented. Figure 2A and Figure 2B The capacitor is 108 and the capacitor is 250.

[0100] The capacitance C of capacitor 250 depends on the extension of the first plate 108a, the second plate 108b, and the third plate 108c in the xy plane, the thickness of the front metal dielectric layer 207, the thickness of the first intermetallic dielectric layer 209(1), and the corresponding dielectric constants of the front metal dielectric layer 207 and the first intermetallic dielectric layer 209(1). Capacitor 250 has a high specific capacitance, which is, for example, between 0.01 µF / cm² and 0.1 µF / cm², and particularly, for example, equal to 0.02 µF / cm².

[0101] Capacitor 250 simultaneously provides a reduced first parasitic capacitance between substrate 4 and gate node 110 and a reduced second parasitic capacitance between gate node 110 and metal layers 22(3)-22(N) above the second metal layer 22(2). Specifically, the first parasitic capacitance is reduced because the first plate 108a is at least partially located between substrate 4 and the first metal layer 22(1). The reduction in the first parasitic capacitance facilitates capacitive coupling between gate node 110 and node 104 via capacitor 250, thereby aiding in the conduction of HV-NMOS transistor 112 when necessary. The reduction in the second parasitic capacitance is a result of the presence of a third plate 108c, which is at least partially located between the first metal layer 22(1) and metal layers 22(3)-22(N). The reduction of the second parasitic capacitance is beneficial to the shielding of the gate node 110, which in turn is beneficial to the shielding of the gate terminal 112c relative to the upper metal layer 22(3)-22(N), thereby helping to turn off the HV-NMOS transistor 112 once the manufacturing process of the integrated circuit 100 is completed.

[0102] The additional metal via 21(8)' extends over the dielectric stack 203 and is aligned with the metal via 21(8) along the z-axis, contacting metal layers 22(1)-22(N-1), thereby forming an integral electrical connection configured to contact the final metal layer 22(N). In particular, since the third sub-part 240c of the first metal layer 22(1) and the metal vias 21(8), 21(8)' are electrically connected to each other, they collectively represent the gate node 110.

[0103] Refer again Figure 4C The second portion 238 of the first metal layer 22 (1) is also electrically coupled to the source terminal 112a, the body terminal 112d, and the first ohmic contact region 4c, respectively, through at least metal vias 21 (9), 21 (10), and 21 (11). Metal vias 21 (9)' extend over the dielectric stack 203 and are aligned with metal vias 21 (9) along the z-axis. Metal vias 21 (9)' contact multiple metal layers 22 (1)-22 (N-1), thereby forming an electrical connection configured to contact the last metal layer 22 (N).

[0104] Figure 5A The top view on the xy plane, and limited to some elements that help to understand the embodiment, are schematically illustrated. Figure 2B The protection circuit 50 is used in the manufacturing process. Figure 5B Along Figure 5A The transverse cross-section on the xz plane intercepted by line III-III is schematically illustrated in the diagram. Figure 2B The protection circuit 50 is used in the manufacturing process.

[0105] In Figures 5A-5B , the elements of the protection circuit 50 common to the protection circuits 50 of Figures 2A-2B , Figure 3 and Figures 4A-4C are indicated with the same reference numerals and are not further described.

[0106] With reference to Figures 5A-5B , a portion 242 of the last metal layer 22 (N) extends between the gate terminal 112c and the source terminal 112a and is electrically coupled to the gate terminal 112c through a successive metal via 21 (8)' and to the source terminal 112a through a successive metal via 21 (9)', thereby forming a metal connection 113.

[0107] Figure 6A and Figure 6B schematically illustrate respective embodiments of a capacitor 300 and a capacitor 400 for forming Figure 2A and Figure 2B capacitors 108, according to alternative embodiments of those for Figure 4C and Figure 5B .

[0108] Figure 6A The capacitor 300 is schematically illustrated in a lateral cross-sectional view on the xz plane.

[0109] The capacitor 300 comprises a first conductive plate 302 and a second conductive plate 304. In one embodiment, the second plate 304 is for example a portion of the second metal layer 22 (2). In another embodiment (not illustrated), the second conductive plate 304 is a portion of one of the metal layers 22 (3) - 22 (N-1).

[0110] The first plate 302 extends in contact with a surface 5a of the insulating layer 5.

[0111] A portion of the dielectric stack 203 having a thickness t ox along the z axis extends between the first plate 302 and the second plate 304.

[0112] The capacitance C' of the capacitor 300 depends at least on the extension of the first plate 302 and of the second plate 304 on the xy plane, on the thickness t ox and on the dielectric constant of the portion of the dielectric stack 203 extending between the first plate 302 and the second plate 304, in a manner known per se. The specific capacitance of the capacitor 300 is for example comprised between 0.05 µF / cm² and 0.1 µF / cm², in particular for example equal to 0.01 µF / cm².

[0113] Figure 6BA capacitor 400 according to another embodiment is illustrated in a top view on the xy plane.

[0114] Capacitor 400 is a planar metal-oxide-semiconductor (MOM) capacitor and includes a first portion of a first metal layer 22 (1) forming a first electrode 402 and a second portion of the first metal layer 22 (1) forming a second electrode 404. The first electrode 402 and the second electrode 404 are at least partially patterned in a comb shape and are mutually interdigitated. In one embodiment, the first electrode 402 of capacitor 400 is coupled to node 104 of protection circuit 50 via a first metal connection 101, and the second electrode 404 of capacitor 400 is coupled to gate node 110 of protection circuit 50 via a second metal connection 103, and vice versa.

[0115] The capacitance C'' of capacitor 400 depends, in a manner known per se, at least along the x-axis, on the distance d between the first electrode 402 and the second electrode 404. x And depends on the distance d along the y-axis between the first electrode 402 and the second electrode 404. y .exist Figure 6B In the embodiment shown, the distance d x equal to distance d y The distance d between the first electrode 402 and the second electrode 404 x and d y It is patterned during the manufacturing process, for example by a photolithography step, followed by a mask etching step on the first metal layer 22 (1). Therefore, by appropriately adjusting this distance d x and d y The size of the capacitor 400 is such that it can be configured to withstand a voltage drop V across its terminals. D Expected proportion V C For example, by using distance d x and d y With their sizes adjusted to be equal and within the range of 0.2 µm to 1.0 µm, capacitor 400 can withstand voltage drops ranging from 20 V to 100 V. C ''.

[0116] Capacitors 300 and 400 can withstand a voltage V greater than that of capacitor 250. C The corresponding voltage. The voltage V that capacitor 250 can withstand. C In practice, it is limited by the breakdown voltage threshold of the front metal dielectric layer 207 and / or the breakdown voltage threshold of the first intermetallic dielectric layer 209(1), and such voltage depends on the thickness of the respective layers 207, 209(1).

[0117] In embodiments of the integrated circuit 100 in which the metal pre-dielectric 207 and the intermetal dielectric layer 209(1) have a limited thickness, for example in the range 100 nm to 1000 nm, the capacitor 300 allows to sustain a voltage drop greater than V C This is because the thickness t ox of the portion of the dielectric stack 203 interposed between the first plate 302 and the second plate 304 is greater than the thickness of each layer 207, 209(1). However, when the capacitor 300 is used to implement the capacitor 108 in the protection circuit 50, the HV-NMOS transistor 112 is not activatable in all the process steps preceding the manufacturing of the second plate 304. Therefore, in this case, the capacitor 400 can be used so that the HV-NMOS transistor 112 is activatable starting from the step immediately following the patterning step of the metal layer 22(1) and in which the voltage drop that can be sustained by the capacitor 250 is not sufficiently high.

[0118] As previously mentioned, the proportion of the voltage drop V GS between the gate terminal 112c and the source terminal 112a of the HV-NMOS transistor 112 corresponds to the voltage drop V D depends on the capacitive divider resulting from the series of the capacitor 250, 300, 400 and the gate capacitance of the HV-NMOS transistor 112. By suitably adjusting the size of the capacitances C, C', C" of the respective capacitor 250, 300, 400, it is possible to configure the proportion of the voltage drop acting between the gate terminal 112c and the source terminal 112a of the HV-NMOS transistor 112 during the manufacturing process steps performed by means of a plasma-assisted process.

[0119] Figure 7 A portion of an integrated circuit 700 comprising a protection circuit 51 connected to a first circuit block 52 through the node 104 is schematically illustrated according to another embodiment. In particular, Figure 7 The integrated circuit 700 is illustrated in a lateral cross-sectional view on the xz plane in a three-axial system in which the x, y, z axes are mutually orthogonal and some elements are illustrated in an electrical circuit representation. In Figure 7 In the integrated circuit 700, the elements common to the integrated circuit 100 of Figure 3 are indicated with the same reference numerals and are not further described.

[0120] The protection circuit 51 comprises a gate-source coupling capacitor 702 having a capacitance C GSThe gate-source coupling capacitor also has a first end coupled to the gate node 110 through a metal connection 704 and a second end coupled to the source terminal 112a through a further metal connection 706. In one embodiment, the gate-source coupling capacitor 702 is of the same type as the capacitor 108 (i.e. can be implemented according to the embodiments of the capacitors 250, 300 and 400 described). In one embodiment where the gate-source coupling capacitor 702 is similar to the capacitor 250 or the capacitor 400, the metal connections 704 and 706 extend at least partially into the first metal layer 22(1).

[0121] In one embodiment, the protection circuit 51 further comprises a further metal interconnection 708 which acts as an antenna electrically coupled to the gate node 110 during plasma processing.

[0122] In the protection circuit 51, during plasma assisted processing, the voltage drop V GS is given by the sum of a first contribution and a second contribution. The first contribution is given by the voltage drop produced by the voltage divider, in which the capacitor 108 is placed in series with the parallel connection between the gate capacitance of the HV-NMOS transistor 112 and the capacitor 702. The second contribution is given by the voltage drop supplied by the plasma through the antenna 708.

[0123] By suitably adjusting the capacitance C GS of the gate-source coupling capacitor 702 based on the operating voltage of the first N-well 12 and the capacitance of the capacitor 108, it is possible to prevent the HV-NMOS transistor 112 from being turned on during the life cycle of the integrated circuit 700 without the need to apply an external bias voltage through a voltage generator dedicated to this purpose. At the same time, in the protection circuit 51, since the gate terminal 112c is not short-circuited to the source terminal 112a through the metal connection 113 shown in Figure 3 , the HV-NMOS transistor 112 is activatable during the process steps of the last metal layer 22(N).

[0124] Reference is made to Figures 8A-8F , now the manufacturing steps of the part of the protection circuit 50 shown in Figure 5B , are limited to the part of the capacitor 250 and the formation of the metal connections 101, 103, 105, 107, 109, 111 and 113. Figures 8A-8F is a lateral cross-sectional view on the xz plane.

[0125] Reference is made to Figure 8AAfter forming the substrate 4 and the doped region, gate dielectric 112c'', conductive portion 112c' and first plate 108a contained in the substrate 4 in a manner known per se, a deposition step of the metal front dielectric layer 207 is performed (e.g. by PECVD), followed by a planarization step (e.g. by chemical mechanical polishing (CMP)).

[0126] refer to Figure 8B One or more mask etching steps (e.g., by photolithography steps known per se and subsequent RIE or deep-RIE steps) are performed on the metal front dielectric layer 207 until the first surface 204a of the structural layer 204 and the corresponding surfaces of the conductive portion 112c' and the first plate 108a are reached, thereby obtaining the trench 80. Then, one or more metal material deposition steps (e.g., sputtering steps followed by electroplating steps) are performed until the trench 80 is completely filled, followed by a mask etching step on the metal material to selectively remove it from the first surface 207a of the metal front dielectric layer 207. Thus, the corresponding first portions of the metal vias 21(6)-21(11) are obtained. It should be noted that in this step, the corresponding first portions of other metal vias 21(1)-21(5) associated with the metal interconnect 20 are also obtained.

[0127] refer to Figure 8C A metal material deposition step (e.g., sputtering) is performed to form a first metal layer 22 (1), followed by a patterning step (e.g., photolithography and etching or stripping) to form a second plate 108b with metal connections 101, 103, 105, 109, 111 and capacitor 108. It should be noted that during these steps, for example... Figure 4B The metal connection 107 shown is also formed. After these steps, the capacitor 250 is able to operate, and the HV-NMOS transistor 112 is as referenced. Figure 2A The ground can be activated to protect integrated circuit 100. Similarly, in embodiments where capacitor 400 is used instead of capacitor 250 and / or where source-gate coupling capacitor 702 is present, HV-NMOS transistor 112 can be activated after these steps.

[0128] refer to Figure 8D , Execution and Reference Figures 8A-8CThe described process steps are similar to those described, thus forming and patterning, respectively, in a manner known per se: a first intermetallic dielectric layer 209 (1), corresponding metal vias 21 (1)'-21 (L)', and a second metal layer 22 (2). It should be noted that after this step, a third plate 108c is formed to provide capacitive coupling between the gate terminal 112c and node 104, thereby improving the HV-NMOS transistor 112's response to voltage drop V. D Response to changes. It should be noted that in these steps, the HV-NMOS transistor 112 is as referenced. Figure 2A The ground can be activated to protect integrated circuit 100.

[0129] refer to Figure 8E Recursive execution and reference Figure 8A Similar to the process steps described in Figure-8C, intermetallic dielectric layers 209(2)-209(M), corresponding metal vias 21(1)'-21(L)' and metal layers 222(3)-22(N-1) are formed and patterned in a manner known per se until a reference is obtained. Figure 4C The structure is described. It should be noted that in these steps, the HV-NMOS transistor 112 is as described in the reference. Figure 2A The ground can be activated to protect integrated circuit 100.

[0130] refer to Figure 8F , Execution and Reference Figure 8C The described process steps are similar to those used to form the final metal layer 22(N) portion 242, thereby forming the seventh metal connection 113. It should be noted that during and after these steps, the HV-NMOS transistor 112 is no longer activatable, as described in the reference. Figure 2B As mentioned above.

[0131] Optionally, a passivation or insulating material (e.g., SiN) deposition step is also performed over the dielectric stack 203 and the final metal layer 22(N) to provide protection and electrical insulation. Electrical contact regions are formed through the passivation layer for biasing the integrated circuit 100 in a manner known per se.

[0132] Finally, it is clear that modifications and variations may be made to the content described and illustrated herein without departing from the scope of the invention as defined in the appended claims.

[0133] Based on the foregoing disclosure, the advantages provided by this invention are clear.

[0134] Specifically, it is noteworthy that protection circuit 50 or 51 ensures protection against damage caused by plasma due to charging of doped regions during the fabrication process of integrated circuit 100 or 700, without the need for an external bias voltage applied via a voltage generator specifically designed for this purpose. Such an external bias voltage is relevant for reference... Figures 8C-8E The described process steps keep the HV-NMOS transistor 112 active, or as described in the reference. Figure 8F The steps described below are not necessary for deactivating the transistor, especially during the lifecycle of integrated circuit 100 or 700. In this way, protection against plasma-induced damage is achieved by reducing circuit area footprint, using a single transistor, one (protection circuit 50) or two (protection circuit 51) capacitors and corresponding interconnections.

[0135] Furthermore, the capacitive coupling between the gate terminal 112c and the node 104 to be discharged allows for reference... Figures 8C-8E During the described process steps, the HV-NMOS transistor 112 experiences a voltage drop V that is directly dependent on the potential of node 104. GS Control is performed. The sizes of the HV-NMOS transistor 112, capacitor 108 (in one of the described embodiments), and capacitor 702 (if present) are appropriately adjusted according to the architecture of the integrated circuit 100 or 700 to be protected to ensure the proper turn-on and turn-off of the HV-NMOS transistor 112.

[0136] It should also be noted that the protection circuits 50 or 51 connected to the node 104 to be discharged, rather than the node to be protected, simultaneously ensure protection for all circuit elements connected to said node 104 that may suffer damage due to charging caused by plasma.

[0137] Finally, it should be noted that although this document describes only one embodiment of the first circuit block 6 and the second circuit block 8, the protection circuit 50 or 51 is applicable to situations where the gate terminal of a MOS device located within the first circuit block is driven by the second circuit block, and one of the first and second circuit blocks is connected to multiple metal interconnects that act as antennas relative to the other of the first and second circuit blocks, both of which are insulated from the substrate by corresponding deep N-wells. In other words, the protection circuit 50 or 51 is suitable for applications where, during plasma processing, positive charge accumulates within the circuit block due to the so-called "antenna effect," and it is necessary to dissipate these charges.

Claims

1. An electronic device comprising: The circuit module includes: a PN junction electrically coupled between a reference terminal and an electrical node; and multiple metal interconnects electrically coupled to the electrical node and configured to be positively charged due to the antenna effect during plasma processing; and The protection module includes: a first transistor having an N-channel, the first transistor having a first conductive terminal, a second conductive terminal, and a control terminal; and a capacitor circuit; The second conductive terminal of the first transistor is electrically coupled to the electrical node, the first conductive terminal of the first transistor is electrically coupled to the reference terminal, and the control terminal of the first transistor is capacitively coupled to the electrical node through the capacitor circuit.

2. The electronic device according to claim 1, wherein the capacitor circuit includes a first capacitor, and the first capacitor includes a first conductive plate, a second conductive plate, and a third conductive plate; The first conductive plate extends between the surface of the substrate and the lower connecting line, the second conductive plate extends coplanarly with the lower connecting line, and the third conductive plate extends above the lower connecting line and directly faces the second conductive plate through a corresponding portion of the dielectric layer. The first and third conductive plates are electrically connected to the electrical node, and the second conductive plate is electrically connected to the control terminal of the first transistor.

3. The electronic device of claim 1, wherein the capacitor circuit comprises a first capacitor of the metal-oxide-metal (MOM) type, the first capacitor having interdigitated electrodes that are coplanar with the lower connecting line and electrically connected to the electrical node and to the control terminal of the first transistor, respectively.

4. The electronic device according to claim 1, wherein the capacitor circuit includes a first capacitor, and the first capacitor includes a first conductive plate and a second conductive plate; in, The first conductive plate extends between the surface of the substrate and the lower interconnect, and the second conductive plate extends above the lower interconnect and directly faces the first conductive plate through a corresponding portion of a dielectric layer with a thickness greater than 100 nanometers. The first conductive plate is electrically connected to the electrical node, and the second conductive plate is electrically connected to the control terminal of the first transistor.

5. The electronic device of claim 1, wherein the capacitor circuit comprises a parallel connection between a capacitor and the intrinsic capacitance of a first transistor, the intrinsic capacitance being located between the control terminal and the second conductive terminal.

6. The electronic device of claim 1, wherein the first transistor has a body terminal electrically connected to a first conductive terminal and a reference terminal.

7. The electronic device of claim 1, wherein the control terminal of the first transistor is electrically coupled to the first conductive terminal of the first transistor.

8. The electronic device of claim 7, wherein the control terminal of the first transistor is directly electrically connected to the first conductive terminal of the first transistor.

9. The electronic device of claim 7, wherein the control terminal of the first transistor is electrically coupled to the first conductive terminal of the first transistor via a second capacitor.

10. The electronic device of claim 1, wherein the threshold voltage of the first transistor is between 0.5 and 3V, and the specific capacitance of the capacitor circuit has a value between 0.01 fF / μm. 2 With 4.0 fF / μm 2 The values ​​between.

11. The electronic device according to claim 1, further comprising: A solid substrate having a surface and a dielectric layer extending on the surface of the solid substrate; The metal interconnect is formed in the dielectric layer and includes: a lower interconnect, an upper interconnect located above the lower interconnect, and at least one intermediate interconnect between the lower interconnect and the upper interconnect; The lower connecting line is the metal connecting line that is closest to the surface of the solid body, and the upper connecting line is the metal connecting line that is farthest from the surface of the solid body. The control terminal of the first transistor is electrically coupled to the first conductive terminal of the first transistor via an electrical connection that extends at least partially coplanar with or at least partially above the upper connection line.

12. The electronic device of claim 11, wherein the solid-state body is a semiconductor material having P-type conductivity and forms the reference terminal, the electronic device further comprising: A first doped region in a solid-state host, the first doped region facing the surface, being N-type and having a first doping value; as well as A second doped region embedded in a solid-state host, the second doped region being N-type and having a second doping value greater than the first doping value, wherein the second doped region extends between the solid-state host and a portion of the first doped region, and in direct electrical contact with the first doped region and the solid-state host; The PN junction is formed at the interface between the first and second doped regions and the solid-state host.

13. The electronic device of claim 12, wherein the first doped region houses at least one second transistor, and the metal interconnect is coupled to a conductive terminal of the second transistor.

14. A method of manufacturing an electronic device, comprising the following steps: The circuit module is formed by forming a PN junction electrically coupled between the reference terminal and the electrical node; And multiple metal interconnects formed by one or more plasma-assisted processes and electrically coupled to electrical nodes and configured to be positively charged due to the antenna effect during the one or more plasma-assisted processes; as well as The protection module is formed by: forming a first transistor with an N-channel, the first transistor having a first conductive terminal, a second conductive terminal, and a control terminal; and forming a capacitor circuit. The second conductive terminal of the first transistor is electrically coupled to the electrical node, the first conductive terminal of the first transistor is electrically coupled to the reference terminal, and the capacitor circuit is formed between the control terminal of the first transistor and the electrical node to electrically couple the control terminal to the electrical node.

15. The method of claim 14, further comprising the step of electrically coupling a control terminal of the first transistor to a first conductive terminal of the first transistor.

16. The method according to claim 15: The step of forming the plurality of metal connecting wires ends with the formation of the upper metal wire; and The step of electrically coupling the control terminal of the first transistor to the first conductive terminal includes forming an electrical connection simultaneously with forming the upper metal wire.

17. The method of claim 14, further comprising directly connecting the control terminal to a first conductive terminal of the first transistor.

18. The method of claim 14, further comprising electrically coupling the control terminal to a first conductive terminal of the first transistor via a second capacitor.

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