High density 3d electro-optic direct bond interconnect

Abstract

The present disclosure describes a system for providing high density three dimensional electro-optic direct bond interconnects. The system includes an electro-optical interposer substrate and a waveguide operatively coupled to the substrate. The waveguide includes an electrical redistribution path electrically coupling the at least one application specific integrated circuit to the photonic integrated circuit and an optical redistribution path optically coupling the circuit. This configuration enables micron-sized high density routing with both internal and external optical communication channels, allowing scalable integration of multiple electrical and optical devices.

Description

[0001] Cross-references to related applications This application claims priority and benefit to U.S. Provisional Patent Application No. 63 / 697,617, filed September 23, 2024, entitled "High-Density 3D Electro-Optical and Optical Direct Bond Interconnect," which is incorporated herein by reference in its entirety. Background Technology

[0002] By comparing conventional optical connections with some aspects of the present method and system illustrated in the remainder of this disclosure with reference to the accompanying drawings, the limitations and disadvantages of conventional optical connections will become apparent to those skilled in the art. Summary of the Invention

[0003] The system and method provide a high-density 3D electro-optic direct bonding interconnect, which is substantially as illustrated and / or described in conjunction with at least one figure, as more fully set forth in the claims. Attached Figure Description

[0004] Figure 1 Examples of single-sided electro-optic direct bonding interconnects according to various exemplary implementations of this disclosure are shown.

[0005] Figure 2 Examples of double-sided electro-optic direct bonding interconnects according to various exemplary implementations of this disclosure are shown. Detailed Implementation

[0006] The accompanying drawings illustrate a general construction method. To avoid unnecessarily obscuring this disclosure, descriptions and details of well-known features and techniques may be omitted. Furthermore, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding the examples discussed in this disclosure. The same reference numerals in different drawings denote the same elements.

[0007] The term "and / or" refers to any one or more items in a list connected by "and / or". For example, "x and / or y" refers to any element in the three-element set {(x), (y), (x, y)}. In other words, "x and / or y" means "one or both of x and y". As another example, "x, y and / or z" refers to any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y and / or z" means "one or more of x, y, and z".

[0008] The terms "comprises", "comprising", "includes", and / or "including" are "open-ended” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0009] The terms "first", "second", and the like can be used herein to describe various elements, and the elements should not be limited by such terms. Such terms are used only to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0010] Unless otherwise specified, the term "coupled" can be used herein to describe two elements that are in direct contact with each other or two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, then element A can be directly in contact with element B, or indirectly connected to element B through an intervening element C. Similarly, the term "above" or "on" can be used herein to describe two elements that are in direct contact with each other or two elements that are indirectly connected through one or more other elements.

[0011] Further, any numerical range recited herein is intended to include all sub-ranges of the same minimum and maximum values. For example, a range of "1 to 10" is intended to include all sub-ranges between (and including) the recited minimum value of 1 and the recited maximum value of 10, that is, all sub-ranges having a minimum value of equal to or greater than 1 and a maximum value of equal to or less than 10, and all sub-ranges having a minimum value of equal to or greater than 1 and a maximum value of equal to or less than 10, as well as all sub-ranges having a minimum value of equal to or greater than 1 and a maximum value of equal to or less than 10. For example, the range "1 to 10" includes sub-ranges such as 1 to 6.3, or 5.5 to 10, or 2.7 to 6.1.

[0012] Figure 1 An example of a single-sided electro-optical-direct bonding interconnect (EO-DBI) 100 is shown in accordance with various example implementations of the present disclosure.

[0013] The single-sided EO-DBI 100 includes a waveguide 101 on an electro-optical interposer substrate 103. The waveguide 101 includes a cladding of low refractive index optical material. The electro-optical interposer substrate 103 can include silicon, glass, silicon carbide, and / or other substrate materials. The waveguide 101 can be operatively coupled to one or more photonic integrated circuits (PICs) 107, 109.

[0014] The ASIC 105 can be interconnected with the PICs 107, 109 through electrical redistribution (ER) paths 112 and optical redistribution (OR) paths 115. The material used for the ER paths is electrically conductive. The material used for the OR paths is optically transparent for the wavelengths of interest and preferably has low optical loss. The single-sided EO-DBI 100 enables high-density electrical-optical routing on a 3D integrated interposer platform. Micron-scale line width and pitch can be achieved through dimensions defined by photolithography and microelectronic processes. High-density direct bonding of electrical ports 111 and optical ports 113 can be achieved at the interface of the PICs 107, 109, ASIC 105, and waveguide 101.

[0015] The ER paths 112 can be on or within the waveguide 101. The ER paths 112 can operatively couple the ASIC 105 and the PICs 107, 109 through the electrical ports 111 made of electrically conductive material.

[0016] The OR paths 115 include a relatively high-index optical material within the waveguide 101. The relatively high-index optical material can be a polysilicon material, an amorphous silicon material, silicon nitride, or other material having a high index of refraction compared to the low-index cladding layer material. The ASIC 105 and the PICs 107, 109 can be operatively coupled through the OR paths 115 and the optical ports 113 made of the high-index optical material that enables direct bonding.

[0017] The OR paths 115A show an external communication channel to the PIC 1 107 via, for example, a lens 119 and an optical fiber 117 above the waveguide 101. The OR paths 115C show an external communication channel to the PIC 1 107 via, for example, a lens 119 and an optical fiber 117 adjacent to the waveguide 101. The OR paths 115D, 115E show an internal communication channel between the PIC 1 107 and the PIC 2 109. The OR paths 115F show an internal communication channel from the PIC 2 109 to the PIC 2 109. The OR paths 115G show an external communication channel to the PIC 2 109 via, for example, a lens 119 and an optical fiber 117 adjacent to the waveguide 101. The ER paths 112 can also include external electrical connections 121.

[0018] Figure 2 An example double-sided EO-DBI 200 is shown in accordance with various example implementations of the present disclosure.

[0019] In addition to the elements in the single-sided EO-DBI 100, the double-sided EO-DBI 200 includes a waveguide 201 below the electro-optical interposer substrate 103. The thickness of the interposer can be, for example, tens of microns to a millimeter depending on mechanical dimensions. The thickness of the interposer will typically be thinner for high-speed optical communications.

[0020] The waveguide 201 is operatively coupled to at least one ASIC 205 and one or more PICs 207, 209.

[0021] The OR path 215A illustrates an external communication channel to the PIC 3 207 through the substrate 103 via, for example, the lens 119 and the optical fiber 117 adjacent to the waveguide 101. The OR path 215B illustrates a channel through the substrate 103 that distributes optical communications between the PIC 2 109 and the PIC 4 209.

[0022] A system according to various embodiments of the present disclosure includes an electro-optical interposer substrate and a waveguide. The waveguide is disposed on the electro-optical interposer substrate and includes an electrical redistribution (ER) path configured to operatively couple an application specific integrated circuit (ASIC) to a photonic integrated circuit (PIC) and an optical redistribution (OR) path configured to optically couple the ASIC to the PIC.

[0023] In various embodiments of the system, the waveguide includes a cladding layer of a low refractive index optical material.

[0024] In various embodiments of the system, the OR path contains a high refractive index material including one or more of polysilicon, amorphous silicon, and silicon nitride.

[0025] In various embodiments of the system, the ER path is placed, positioned, deposited, or otherwise disposed within the waveguide, and / or the ER path contains a conductive material forming an electrical port.

[0026] In various embodiments of the system, the OR path is configured to provide external optical communications via a lens and an optical fiber, or the OR path is configured to provide internal optical communications between a first PIC and a second PIC.

[0027] In various embodiments of the system, the waveguide is operatively coupled to at least one ASIC and a plurality of PICs.

[0028] In various embodiments of the system, the electro-optical interposer substrate contains one or both of silicon and glass.

[0029] In various embodiments of the system, the ER path and the OR path are configured for micron-scale line widths and line spacing defined by a lithographic process.

[0030] One other system in accordance with various embodiments of the present disclosure includes an electro-optical interposer substrate, a first waveguide disposed on a first surface of the electro-optical interposer substrate, and a second waveguide disposed on a second surface of the electro-optical interposer substrate opposite the first surface. The first waveguide and the second waveguide each include electrical redistribution (ER) paths and optical redistribution (OR) paths for interconnecting at least one ASIC with a plurality of PICs.

[0031] In various embodiments of the other system, the second waveguide is configured for optical communication through the substrate to a PIC on the first surface, or the second waveguide is configured for optical communication through the substrate between a first PIC and a second PIC disposed on opposite sides of the substrate.

[0032] In various embodiments of the other system, the ER paths of the first waveguide and the ER paths of the second waveguide provide electrical coupling between a plurality of ASICs disposed on opposite sides of the substrate.

[0033] In various embodiments of the other system, the OR paths of the first waveguide and the OR paths of the second waveguide include optical ports containing high refractive index material for direct bonding.

[0034] In various embodiments of the other system, the first waveguide includes external optical communication paths via lenses and optical fibers, and / or the second waveguide includes internal optical communication paths between a plurality of PICs disposed on opposite sides of the substrate.

[0035] In various embodiments of the other system, the first waveguide and the second waveguide each include a cladding layer having a low refractive index optical material.

[0036] In various embodiments of the other system, the electro-optical interposer substrate contains one or both of silicon and glass.

[0037] In various embodiments of the other system, high-density direct bonding of electrical ports and optical ports is achieved at a plurality of interfaces of the at least one ASIC and the plurality of PICs.

[0038] In various embodiments, the interface between the electro-optical interposer substrate waveguides and the ASICs and / or PICs can include an air gap or a dielectric material. The choice of interface material can be utilized to optimize optical confinement, mechanical stability, and coupling efficiency between electro-optical elements.

[0039] In various embodiments, the rigid attachment (die attach) between a chip (e.g., an ASIC or a PIC) and the substrate can be accomplished using direct bonding or state-of-the-art microsolder bump bonding techniques. Direct bonding can be advantageous for minimizing thermal resistance and enabling high-density port alignment, while microsolder bumps can provide mechanical compliance and reworkability.

[0040] In various embodiments, optical coupling tolerances can be ensured by design, for example by a gradual coupling structure such as a tapered waveguide formed between the interposer and the photonic device. Additional optical coupling implementations can include the use of micro-optics such as microlenses, gratings, or waveguide tapers that facilitate efficient coupling of light between on-chip photonic structures and off-chip photonic structures.

[0041] In some embodiments, microfabricated lenses can be employed to provide free-space coupling between the optical port and the optical fiber. These lenses can be defined by lithography and integrated with the interposer to maintain precise alignment with the optical redistribution path.

[0042] In various embodiments, gradual coupling can be achieved by positioning a tapered waveguide of a first chip in close proximity to a tapered waveguide of a second chip, such that the overlapping gradual fields enable efficient optical power transfer. This structure can be fabricated directly on the interposer substrate or across bonded chips.

[0043] In various embodiments, the PIC can be placed inside a recess formed within the waveguide substrate or formed on the surface of the waveguide substrate. Recessed placement can improve optical alignment tolerances, thermal management, and reduce parasitic effects, while surface placement can simplify fabrication and allow post-processing integration.

[0044] The figures described herein are cross-sectional illustrations, and the waveguides and redistribution paths (both ER and OR) can be laid out two-dimensionally across the substrate plane. While the figures show one-dimensional routing for clarity, in practice, the routing can be implemented in multiple directions across the interposer surface to enable high-density interconnect layouts.

[0045] While the present method and / or system has been described with reference to certain implementations, it is understood that various changes can be made and equivalents can be substituted for elements thereof without departing from the scope of the present method and / or system. In addition, many modifications can be made to adapt a particular situation or material to the teachings of the present disclosure without departing from the scope thereof. Therefore, it is intended that the present method and / or system not be limited to the readily disclosed implementations but be accorded the full scope of the appended claims.

Claims

1. A system comprising: Electro-optic interposer substrate; as well as A waveguide, disposed on the electro-optical interposer substrate, includes: Electrical redistribution (ER) paths are configured to operatively connect application-specific integrated circuits (ASICs) to photonic integrated circuits (PICs), and An optical redistribution (OR) path is configured to be optically coupled to the PIC.

2. The system according to claim 1, wherein, The waveguide includes a cladding layer with a low refractive index optical material.

3. The system according to claim 1, wherein, The OR path includes a high refractive index material, which includes one or more of polycrystalline silicon, amorphous silicon, and silicon nitride.

4. The system according to claim 1, wherein, The ER path is located within the waveguide.

5. The system according to claim 1, wherein, The ER path contains conductive material that forms electrical ports.

6. The system according to claim 1, wherein, The OR path is configured to provide external optical communication via lenses and optical fibers.

7. The system according to claim 1, wherein, The OR path is configured to provide internal optical communication between the first PIC and the second PIC.

8. The system according to claim 1, wherein, The waveguide is operationally connected to at least one ASIC and multiple PICs.

9. The system according to claim 1, wherein, The electro-optic interposer substrate comprises one or both of silicon and glass.

10. The system according to claim 1, wherein, The ER path and the OR path are configured for micrometer-level linewidth and line spacing defined by photolithography.

11. A system comprising: Electro-optic interposer substrate; A first waveguide is disposed on the first surface of the electro-optic interposer substrate; as well as A second waveguide is disposed on a second surface of the electro-optical interposer substrate opposite to the first surface, wherein the first waveguide and the second waveguide each include an electrical redistribution (ER) path and an optical redistribution (OR) path for interconnecting at least one ASIC with a plurality of PICs.

12. The system according to claim 11, wherein, The second waveguide is configured for optical communication with a PIC on the first surface via the substrate.

13. The system according to claim 11, wherein, The second waveguide is configured for optical communication between a first PIC and a second PIC disposed on opposite sides of the substrate via the substrate.

14. The system according to claim 11, wherein, The ER path of the first waveguide and the ER path of the second waveguide provide electrical connections between a plurality of ASICs disposed on opposite sides of the substrate.

15. The system according to claim 11, wherein, The OR path of the first waveguide and the OR path of the second waveguide include optical ports, the optical ports containing high refractive index material for direct bonding.

16. The system according to claim 11, wherein, The first waveguide includes an external optical communication path via a lens and an optical fiber.

17. The system according to claim 11, wherein, The second waveguide includes an internal optical communication path disposed between a plurality of PICs on opposite sides of the substrate.

18. The system according to claim 11, wherein, The first waveguide and the second waveguide each include a cladding layer with a low refractive index optical material.

19. The system according to claim 11, wherein, The electro-optic interposer substrate comprises one or both of silicon and glass.

20. The system according to claim 11, wherein, The system enables high-density direct bonding of electrical and optical ports at multiple interfaces of the at least one ASIC and the plurality of PICs.

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