Design scheme for realizing rapid access to low-speed bus device by using ASIC / FPGA with PCIE / parallel interface

Abstract

According to the core thought, ASIC / FPGA logic is used for achieving fast access of the low-speed bus. In the invention, the access of a central processing unit (CPU) to a low-speed bus device is logically divided into three steps: a, the CPU firstly uses a PCIE / parallel bus to configure ASIC / FPGA logic in a memory area writing manner; b, the ASIC / FPGA logic accesses a plurality of low-speed bus devices connected with the ASIC / FPGA logic for one time or multiple times according to the configuration requirements, access results are put into a storage area, and interruption is generated when necessary; and c, the CPU quickly obtains an access result through the read storage area by using the PCIE / parallel bus, or quickly processes the access result through interruption. And after a is executed once, b can be executed for multiple times according to the configuration of a, so that the CPU can quickly access a large number of low-speed bus devices only by executing the step c. Due to the fact that the access speed of the PCIE / parallel bus is far higher than that of the low-speed bus, the scheme greatly improves the access efficiency of CPU software to the low-speed bus device.

Description

Technical Field

[0001] This application relates to the field of chip design, such as an ASIC design with PCIe and / or parallel interfaces for connecting a central processing unit (CPU) and an external low-speed bus device, enabling the CPU to quickly access the external low-speed bus device.

[0002] This application relates to the field of FPGA design, for example to a logic design for an FPGA with PCIe and / or parallel interfaces for connecting a CPU and external low-speed bus devices, enabling the CPU to quickly access the external low-speed bus devices.

[0003] This application relates to the field of system design, such as using a combination of hardware and software methods to classify and process access to external low-speed buses and provide hardware assistance to accelerate software execution. Background Technology

[0004] In current embedded designs, a large number of microsensors, micromemories, microcontrollers, micromotors, SFPs, and other devices are frequently used. These devices require access via low-speed buses such as IIC, SPI, CAN, UART, and MDIO. High-speed CPUs use these low-speed buses to access and control these devices, but the slow transmission speed of these buses significantly slows down the CPU's execution efficiency when software programs frequently access these devices. Even increasing the CPU's clock speed does not solve this problem. Current technologies lack a good solution to this issue. With the development of robotics, a large number of sensors and controllers will be used, requiring the CPU to access external sensors and controllers in real time. The bottleneck of access efficiency from these low-speed bus devices will become increasingly apparent and urgently needs to be addressed. Summary of the Invention

[0005] To address the above problems, this invention provides a hardware and software combined approach to improve the CPU's access speed to external low-speed bus devices, reduce access time, and improve software efficiency.

[0006] To provide a basic understanding of the concept of this invention, a brief summary is given below. This summary is not a general commentary, nor is it intended to identify key components or define the scope of protection of this invention, but rather serves as an introduction to the detailed description that follows.

[0007] The core idea of ​​this invention is to use ASIC / FPGA logic to achieve fast CPU access to low-speed bus devices. In this invention, CPU access to low-speed bus devices logically consists of three steps: a. The CPU uses the PCIe / parallel bus to configure the configuration area of ​​the ASIC / FPGA logic's memory area; b. The ASIC / FPGA logic accesses its connected low-speed bus devices one or more times according to the configuration requirements of the configuration area, and places the access results in the memory area, and / or generates an interrupt; c. The CPU then uses the PCIe / parallel bus to quickly read the access results from the result area of ​​the ASIC / FPGA logic's memory area. The core of this invention is that after the CPU executes step a once, the ASIC / FPGA logic can execute step b multiple times according to the configuration of step a, thus allowing the CPU to quickly access a large number of low-speed bus devices through step c. This invention addresses the issues of reading registers, writing registers, and interrupts for low-speed bus devices as follows: For register reading, ASIC / FPGA logic pre-fetches or polls the register contents of external low-speed bus devices into the ASIC / FPGA's memory area. When needed, the CPU can directly read the ASIC / FPGA's memory area using the PCIe / parallel bus. For register writing, a large number of register write commands can be written to the ASIC / FPGA's memory area at once via the PCIe / parallel bus. The ASIC / FPGA logic processes each command in the memory area and writes it to each low-speed bus device. Timed or periodic register writing functionality can also be provided as needed. For interrupts, the ASIC / FPGA logic periodically reads the status registers of the low-speed bus devices according to configured interrupt requirements. When the conditions are met, an interrupt is triggered, eliminating the need for the CPU to continuously poll the low-speed bus's status register. This significantly enhances the CPU's ability to handle urgent tasks related to low-speed bus devices while reducing processing time. Considering that in low-speed bus device applications, the timeliness requirements for register values ​​are generally not very high, mostly in the millisecond or even second range, although the CPU does not obtain the results instantly, it does not affect usability. For accesses requiring high timeliness, interrupts can be used to obtain results faster. In this way, without affecting performance, the CPU's access time to external chips is greatly reduced.

[0008] By employing this invention, the CPU can achieve rapid access to a large number of low-speed bus devices, reduce software latency and frequent thread switching, accelerate the response speed to changes in the status of external chips, and solve the problem of low efficiency in low-speed bus access during embedded software program execution.

[0009] In this invention, "low speed" in the context of low-speed bus refers to a low speed in the general sense relative to PCIe / parallel bus. Low-speed bus can be one or more of the following: IIC, SPI, CAN, UART, or MDIO.

[0010] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0011] The accompanying drawings are illustrative and do not constitute a limitation on the invention. Figure 1 This is a common connection method for low-speed bus devices in embedded systems. Figure 2 This is a block diagram illustrating the design implementation of a PCIE / parallel bus-based high-speed access low-speed bus device provided by the present invention. Figure 3 This is a block diagram of the ASIC / FPGA logic design system in the solution provided by the present invention; Detailed Implementation

[0012] To provide a more detailed understanding of the features and technical content of this invention, the implementation of the invention will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the implementation of the invention. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the invention. However, the invention can still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0013] The term "serial number" in this invention is used to distinguish similar objects and is not necessarily used to describe a specific order; it should be understood that such data can be interchanged where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. In this invention, unless otherwise stated, the term "a plurality of" means two or more. The character " / " indicates that the preceding and following objects are in an "OR" relationship; for example, A / B means: A, B, or A and B.

[0014] The solution provided by the present invention will be described below with reference to the accompanying drawings.

[0015] Figure 1This is a common connection method between low-speed bus devices and the CPU in current embedded systems. The CPU directly accesses its built-in low-speed bus controllers such as IIC / SPI / CAN / MDIO to control peripheral low-speed bus devices or obtain their information. During access, the current thread is usually in a suspended state or in a loop, waiting for the return result. When there are many peripheral low-speed chips and frequent polling is required, this method not only severely blocks the current thread, causing delayed responses to other requests, but also leads to frequent thread switching, resulting in significant system overhead. Even choosing a CPU with a higher clock speed cannot alleviate the problem. Access to these low-speed bus devices keeps the system busy, thus delaying program response time and even causing problems with the operation of normal tasks. In addition, since most of these external low-speed devices do not have interrupts, the only way to know the state changes is through polling, which leads to untimely responses and increases the CPU load.

[0016] As mentioned above, the frequent access and control of various devices on the low-speed bus by the high-speed CPU significantly delays the execution efficiency of the CPU software program, and even increasing the CPU's clock speed does not help. To solve these problems, we propose a design scheme that designs ASIC / FPGA logic to access external low-speed bus devices, and uses PCIe / parallel bus to access the ASIC / FPGA to achieve fast access of the CPU to external low-speed bus devices. Figure 2 This is a system block diagram of a solution for fast access to low-speed bus devices based on PCIe / parallel bus provided by this invention.

[0017] To enable rapid interaction between the CPU and numerous low-speed bus devices, ASIC / FPGA logic implements the core functions, acting as the medium connecting the CPU and these devices. The CPU configures the ASIC / FPGA logic, specifying the access methods for the external low-speed bus devices (including chip-related information such as bus type, bus number, speed, bus address, and chip select number) and each access request (read / write register, interrupt reporting). The ASIC or FPGA logic, according to the CPU's configuration, fulfills each access request and stores the access results, initiating an interrupt if the interrupt condition is met. Finally, the CPU quickly reads the access results via the PCIe / parallel interface.

[0018] Figure 3This is a block diagram illustrating the implementation of the ASIC / FPGA logic design provided by this invention. In the diagram, the "PCIE / Parallel Interface" is the interface through which the CPU accesses the ASIC or FPGA. The "Dual-Port Memory Space" is a shared memory area located inside the ASIC / FPGA, accessible by both the PCIE / Parallel Interface and the "Control Logic" within the ASIC / FPGA. The "Access Configuration Space" is where the CPU configures the execution of the ASIC / FPGA logic, specifying how external low-speed bus devices access each other, which registers to access, and the access method. The "Access Result Space" stores the results of the ASIC / FPGA logic's access to external low-speed bus devices for the CPU to retrieve. The "Access Configuration Space" and "Access Result Space" are logically separate parts, not necessarily located in different address spaces; they can be integrated or separate. The "Control Logic" reads the configuration data from the "Access Configuration Space," accesses the devices on each low-speed bus according to the configuration data requirements, and stores the results in the "Access Result Space." If the interrupt condition is met, an interrupt is initiated. The "control logic" section is the processing unit inside the ASIC / FPGA logic. It is used to access low-speed bus chips according to the "access configuration space" settings. It can be ordinary logic or designed as MCU (microprocessor) firmware.

[0019] In this invention, the CPU uses the PCIe / parallel bus to configure the ASIC / FPGA, which includes three categories: configuration of each low-speed bus controller on the ASIC / FPGA logic, "bus configuration" of external low-speed bus devices, and "register access configuration" of external chips. The low-speed bus controller configuration refers to the configuration of the low-speed bus controller on the ASIC / FPGA, including pin configuration, attribute configuration, FIFO configuration, etc., used for the bus. The "bus configuration" of the low-speed bus device can include the following: bus type, bus number, bus frequency, device address or chip select number on the bus, external bus multiplexer configuration, etc., which can be added or removed as needed. This configuration is used to configure the access method of the external low-speed bus device, and each external low-speed bus device requires a "bus configuration". The "register access configuration" configures the access method of each register segment on the low-speed bus device, including access type, address width / command width, register address / command word, data length, cycle and cycle count, data, etc. The access types are defined to meet different needs and include, but are not limited to, the following: single read access, single write access, polling read-ahead access, multi-cycle write access, polling interrupt setting, GPIO setting and reading, bus reset, etc., used to configure the method and result processing of each access. These configurations are all recorded in the "Access Configuration Space".

[0020] In this invention, the "control logic" monitors changes in the "access configuration space" and initiates access commands to external low-speed bus devices according to the access requirements therein. Then, it writes the access progress (not started / accessing / error / no response / success, etc.), result (read result), and time (tick time of the last operation) into the "access result space." If the "access configuration" requires an interrupt and the access result meets the interrupt conditions, the "control logic" initiates an interrupt and writes the interrupt status into the "access result space." In this invention, the "access type" is a crucial component, serving as a vital basis for the "control logic" to process access requests. The following provides a detailed explanation of some access methods.

[0021] 1. Single Read Access: Used for a single register read. When the CPU initiates a single register read command by writing to the "Access Configuration Space," the ASIC / FPGA logic detects the change in the "Access Configuration Space" and, after the low-speed bus connected to the chip becomes idle, initiates the current read access on the low-speed bus. After completion, the result is written to the "Access Result Space" for the CPU to quickly read back. When the CPU reads back the result from the "Access Result Space," it needs to determine whether the operation is complete. A single read access can read a single register, multiple registers consecutively, or a single register (FIFO) consecutively. This type of single read access can batch-execute writing to the "Access Configuration Space" and then batch-reading the "Access Result Space," saving significant waiting time. If the result is read immediately after writing to the "Access Result Space," it needs to wait for the status to change to "Completed," which does not save time. However, the CPU-side driver software can wait based on the read access length and low-speed bus speed, freeing up CPU resources.

[0022] 2. Single Write Access: Used for immediate writing. When the CPU initiates a single write access by writing to the "Access Configuration Space," the ASIC / FPGA logic design detects the change in the "Access Configuration Space" and, once the low-speed bus where the chip resides is idle, directly initiates the write access. After the write operation is completed, the result is written to the access result space. A single write access can write to a single register, write to multiple registers consecutively, or write to a single register consecutively (FIFO). A single write access can directly write content or can include a masked write (first read the register value result, then perform a mask operation on result and the write value value: valueR = (result & ~mask) | (value & mask), and finally write valueR to the register). The result of a single write access is guaranteed by the ASIC / FPGA. If an access error occurs, "failure" can be written to the status of the "Access Result Space," or an interrupt can be initiated to notify the CPU. The CPU does not need to wait for the execution result.

[0023] 3. Polling Read-Ahead Access: Used for registers that require periodic readings. This access is for frequently accessed and changing registers, such as status registers, temperature registers, counter registers, speed registers, current / voltage registers, angle registers, etc. After the CPU initiates a polling read access by writing to the "Access Configuration Space," the ASIC / FPGA logic will access the corresponding chip registers on the low-speed bus during the set polling cycle and store the results in the "Access Result Space." When storing the access result area, the following processing methods can be used according to the configuration requirements of writing to the "Access Configuration Space": a. Final Raw Value: Write the last register value to the access result area; b. Latch or 0 Latch: For some registers, certain bits are automatically cleared or set to 1 after reading. We need to keep the current value in the access result space and clear it after the CPU reads it; c. Accumulated Count: For counters that are cleared after reading, this method is used. The value read each time is added to the previous value and placed in the result area; d. Accumulated Count Width Extension: Same as c, but the data width of the result area is extended to accommodate the accumulated count toggling.

[0024] 4. Multi-cycle write access: Used for multiple write accesses to one (or more) registers at fixed intervals. Each multi-cycle write access can be to write a single register, to write multiple registers consecutively, or to write a single register consecutively (FIFO). The purpose is to periodically trigger an action, causing the chip to perform a certain task continuously, such as: a. writing a fixed value to one or more registers every x milliseconds (to trigger a fixed action); b. writing different values ​​to one or more registers every x milliseconds (to trigger a different action).

[0025] 5. Polling Interrupt Setting: Used to generate interrupts and interrupt codes as needed. This includes, but is not limited to, the following: a. Insertion / Removal Interrupt: Depending on the bus type, the detection of chip insertion / removal varies; an interrupt is triggered when insertion / removal is detected. b. Read / Write Failure Interrupt: An interrupt is triggered when one or more register read / write commands fail. c. Register Status Interrupt: Polling to read a register value; an interrupt is triggered when certain bits are 1 / 0; used for interrupts of peripheral low-speed bus devices themselves. d. Generating interrupts based on the GPIO pins of the ASIC / FPGA connected to the interrupt lines of low-speed devices. When the corresponding situation occurs, the ASIC / FPGA logic saves the interrupt status in the "access result space" and initiates a CPU interrupt through the interrupt pin.

[0026] 6. GPIO setting and reading: ASIC / FPGA logic can provide some GPIOs to assist external low-speed bus devices, such as detecting device presence signals, device output signals, output control signals, output reset signals, etc. to external low-speed bus devices.

[0027] 7. Bus controller reset function: reset a low-speed bus controller on the ASIC / FPGA logic.

[0028] 8. For certain low-speed buses, the following functions can be implemented: a. IIC scan function: Scan the IIC bus as required to find out which devices are currently on the bus and write the scan results to the access result space; b. IIC discovery function: Access a chip at a specified address on the IIC bus as required and check for a response; c. IIC bus device access abort: Stop the peripheral chip's occupation of the bus by keeping SDA high and sending 9 clock signals on SCL, and end the previous unfinished access cycle by sending a termination signal; d. End bus access: When the status of a peripheral low-speed bus device is abnormal and the bus is suspended, a bus end command is needed to end its status. Different low-speed buses have different methods for ending the bus.

[0029] Users can categorize their accesses using the methods described above and call different driver interfaces to achieve the desired results.

[0030] Figure 3 The "control logic" module can be implemented using an MCU with firmware or purely logically. Its function is to monitor the configuration of the "access configuration space," access external low-speed bus devices according to the configuration requirements, and then store the access results in the "access result space." The MCU with firmware approach allows for functional upgrades through firmware updates, adapting to more flexible needs.

[0031] In this invention, due to the change in hardware connection method, the CPU driver software also needs to be changed accordingly. For example, two access lists need to be established: one is a list of information about low-speed bus devices connected to the ASIC / FPGA logic, and the other is a list of information about the registers to be accessed and the access methods. These two lists can be statically generated or dynamically added to or updated based on API calls. Through these two access lists, the driver software can directly access the PCIe / parallel interface to obtain the memory space within the ASIC / FPGA logic, to set "access requirements," and to obtain "access results." The two access lists are logically two parts, but they can also be combined or split into more functional lists through structural adjustments.

[0032] In this invention, the CPU can access the ASIC / FPGA logic in two ways: one is to periodically read the ASIC / FPGA logic's "access result space" into local memory, and then directly access local memory each time a drive reads; the other is to directly operate the PCIe / parallel bus to read the required ASIC / FPGA "access result space" each time a drive reads or writes. This depends on the requirements for software execution efficiency and system response time, and requires comprehensive consideration by the user.

[0033] All aspects of this invention not described in detail are well-known to those skilled in the art. For those skilled in the art, this invention is not limited to the above details, and can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention. Therefore, this specification should be considered exemplary and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description; thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention.

Claims

1. An ASIC design scheme or FPGA logic design scheme with a PCIe / parallel interface to enable a central processing unit to quickly access low-speed bus devices. Its features are as follows: The CPU connects to the ASIC / FPGA via a PCIe / parallel interface, and the ASIC / FPGA connects to external low-speed bus devices. The CPU first configures the ASIC / FPGA logic, and the ASIC / FPGA logic accesses the external low-speed bus devices according to the configuration requirements and caches the results in the ASIC / FPGA. When the CPU needs to access the low-speed bus devices, it directly reads the cached data in the ASIC / FPGA.

2. A method for categorizing and processing access to low-speed bus devices. This can be categorized into single-cycle read access, single-cycle write access, polling read-ahead access, multi-cycle write access, polling interrupt setting, GPIO setting and read / write, and bus / bus controller / device reset, allowing ASICs / FPGAs to perform special processing for each.

3. A software method, characterized in that, Create an access list and initialize it according to the initial configuration. Then, for each access, first check the access list. If it is in the access list, directly read the cached result from the access list and return it. For accesses that are not in the access list, add them to the access list and then read the cached result after a delay.

4. A system method, characterized in that, The central processing unit first reads the cached data in the external ASIC / FPGA logic into the local cache on a periodic basis, and then directly reads the local cache data when needed, reducing fragmented PCIe read access.

5. The PCIe interface according to claim 1 is applicable to all PCIe bus versions and bus counts.

6. The parallel interface according to claim 1 is applicable to all parallel data interfaces.

7. The low-speed bus according to claim 1 includes buses with transmission rates lower than PCIe, such as IIC, SPI, CAN, MDIO, and UART.

8. The ASIC design scheme or FPGA logic design scheme according to claim 1, characterized in that, It includes PCIe interface modules or parallel interface modules, storage modules, control logic modules, low-speed bus controller modules, and may also include GPIO modules.

9. The ASIC design or FPGA logic design according to claim 1, characterized in that, The ASIC / FPGA logic can be configured and monitored according to requirements, including GPIO, device connectivity, and device interrupt registers, and can initiate interrupts in specified states.

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