Chip, method for controlling memory fault repair, electronic equipment and medium

Abstract

A chip, a method of controlling memory failure repair, an electronic device, a non-transitory computer-readable storage medium, and a computer program product are provided. The chip comprises a power supply management unit, a repair management unit and a repair execution unit, wherein the power supply management unit is configured to provide a repair starting signal for a first power supply domain in a plurality of power supply domains through a power-on condition of the first power supply domain; the repair management unit is configured to determine first information at least according to a repair starting signal for the first power domain, and the first information comprises information indicating that a memory of the first power domain needs to be subjected to memory fault repair at present; sending a starting signal and first information to a repair execution unit; and the repair execution unit is configured to perform memory fault repair on the memory in the first power domain according to the starting signal and the first information.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of chips, and more specifically to chips, methods for controlling memory fault repair, electronic devices, and non-transitory computer-readable storage media. Background Technology

[0002] Memory occupies a large area in a System-on-Chips (SoC) and is often densely packed, making it more prone to failure. Therefore, the quality of the memory has a significant impact on chip yield. To avoid losses due to low yield, redundant or spare rows and columns are typically added to the memory cells. When a memory fails, it can be repaired by remapping the faulty cell to a redundant cell using specific mapping logic. This process is called memory repair. Summary of the Invention

[0003] This summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0004] According to one aspect of this disclosure, at least one embodiment provides a chip including a power management unit, a repair management unit, and a repair execution unit, wherein the power management unit is configured to provide a repair initiation signal for a first power domain based on the power-on status of a first power domain among a plurality of power domains; the repair management unit is configured to: determine first information based at least on the repair initiation signal for the first power domain, the first information including information indicating that the memory of the first power domain currently needs memory fault repair; send the initiation signal and the first information to the repair execution unit; and the repair execution unit is configured to perform memory fault repair on the memory in the first power domain based on the initiation signal and the first information.

[0005] According to another aspect of this disclosure, at least one embodiment provides a method for controlling memory fault repair, comprising: providing a repair initiation signal for a first power domain via a power management unit based on the power-on status of a first power domain among a plurality of power domains; determining first information via the repair management unit, at least based on the repair initiation signal for the first power domain, the first information including information indicating that the memory in the first power domain currently requires memory fault repair; sending the initiation signal and the first information to a repair execution unit via the repair management unit; and performing memory fault repair on the memory in the first power domain via the repair execution unit based on the initiation signal and the first information.

[0006] According to another aspect of this disclosure, at least one embodiment provides an electronic device including: a chip according to at least one embodiment of this disclosure.

[0007] According to another aspect of this disclosure, at least one embodiment provides a non-transitory computer-readable storage medium having computer instructions stored thereon, wherein, when executed by a processor, the computer instructions cause the processor to perform a method according to at least one embodiment of this disclosure.

[0008] According to another aspect of this disclosure, at least one embodiment provides an electronic device, including: a storage device storing computer instructions; and at least one processing device configured to execute the computer instructions in the storage device to perform a method according to at least one embodiment of this disclosure. Attached Figure Description

[0009] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0010] Figure 1 A block diagram of a chip according to at least one embodiment of the present disclosure is shown.

[0011] Figure 2 A flowchart illustrating the signals received and emitted by a repair management unit in a chip according to at least one embodiment of the present disclosure is shown.

[0012] Figure 3 A schematic diagram is shown illustrating the signal interaction between a chip on a chip and a subsystem on a chip and their power domains when powered on, according to at least one embodiment of the present disclosure.

[0013] Figure 4 A flowchart of a method for controlling memory fault repair according to at least one embodiment of the present disclosure is shown.

[0014] Figure 5 A block diagram of an exemplary electronic device according to at least one embodiment of the present disclosure is shown.

[0015] Figure 6 A schematic diagram of the structure of an electronic device suitable for implementing embodiments of the present disclosure is shown. Detailed Implementation

[0016] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0017] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0018] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0019] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0020] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0021] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0022] The method provided in this disclosure is generally executed by a computer device with a certain computing power.

[0023] Memory Built-in Self Repair (MBISR) is a hardware circuit that automatically completes the memory repair process. Memory repair typically requires the following two steps.

[0024] First, during testing with Automatic Test Equipment (ATE), the Memory Built-In Self-Test (MBIST) control unit detects faults within the memory. Specifically, the MBIST control unit generates test patterns using a built-in Finite State Machine (FSM) and applies these patterns to the memory. It then collects and analyzes the memory's response data to detect any faults. Common memory fault types include stuck-at faults, transition faults, and coupling faults. Next, the MBIST control unit stores redundant or spare row and column information for the memory requiring repair in a dedicated electrically programmable read-only memory (EPROM Fuse, eFuse) on the chip.

[0025] Then, when the chip is powered on, the MBISR control unit automatically loads the redundant or spare row and column information recorded in the eFuse, so that the mapping to the faulty memory is remapped to the redundant or spare rows and columns, thereby completing the fault repair of the memory.

[0026] Chips are typically integrated into the device side (or terminal side) of terminal products such as smartphones, tablets, wearable devices, smart home devices, and IoT devices. For low power consumption, chips often employ a non-standard multi-power domain (PD) design. Generally, a power domain refers to a region within a chip containing a set of related circuits and logic that can be independently powered. Each power domain can have its own power supply and control strategy, independently controlling its power supply and clock signals to achieve finer power management. On one hand, a chip's power domain can also contain multiple sub-power domains. For example, the central processing unit (CPU) subsystem, graphics processing unit (GPU) subsystem, memory subsystem, input / output subsystem, clock and reset subsystem, etc., may each have their own power domain and voltage. Due to constraints such as power-on sequence design, these need to be separated and designed according to a multi-power domain scheme. On the other hand, for cases where different parts of the CPU (e.g., core, cache, bus interface, etc.) are separated into different power domains, it is also necessary to design the chip using a combination of multiple power domains. However, memory in the power domain that is in a power-down (or power-off) domain cannot be accessed or tested normally, and therefore cannot be repaired. Therefore, this part of the memory needs to be connected in series with a Built-in Self-Repair (BISR) chain. A BISR chain refers to connecting multiple BISR registers or modules in series. When a memory region fails, repair information can be quickly transmitted to the corresponding repair module through the BISR chain, achieving rapid repair. Therefore, the memory fault repair process can only begin after the power domain is powered on. However, since the power-on and power-off processes of the sub-power domain are controlled by the Power Management Unit (PMU) or software, and the memory fault repair process is completed by the control logic inserted by Design for Test (DFT), the control logic of the PMU or software and the DFT cannot be fully aware of each other in the chip flow.

[0027] To complete the memory fault repair process in the power-on and power-off processes of each power domain of a low-power chip, the control logic of the PMU and the control logic of the DFT need to work closely together.

[0028] At least one embodiment provided in this disclosure can complete the memory fault repair process in the power-on and power-off process of each power domain by designing various signals that interact between the repair management unit, the power management unit, and the repair execution unit.

[0029] Figure 1 A block diagram of a chip 100 according to at least one embodiment of the present disclosure is shown.

[0030] like Figure 1 As shown, chip 100 may include a power management unit 110, a repair management unit 120, and a repair execution unit 130.

[0031] Here, the chip can be a system-on-a-chip (SOC), a multi-chip module (MCM), or other integrated circuits.

[0032] The unit can be implemented using hardware and / or a combination of hardware and software. Hardware implementations can be achieved using at least one of the following: Application-Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field-Programmable Gate Array (FPGA), processor, controller, microcontroller, microprocessor, or electronic unit designed to perform the functions and / or steps described herein. Software implementations include software, firmware, middleware, microcode, hardware description languages, or others, and should be broadly interpreted to mean instructions, instruction sets, code, code segments, program code, program, subroutine, software module, application, software application, software package, routine, subroutine, object, executable file, execution thread, processing and / or function, and other examples. Note that the name of the unit does not, in some cases, constitute a limitation on the unit itself.

[0033] The power management unit 110 can be configured to provide a repair startup signal for a first power domain based on the power-on status of a first power domain among a plurality of power domains 140 (power domains 1, 2...N). Here, N is a positive integer. Note that "first power domain" here refers to any one of the plurality of power domains, not a specific power domain. That is, providing a repair startup signal for a first power domain based on the power-on status of a first power domain among the plurality of power domains 140 (power domains 1, 2...N) can mean providing a repair startup signal for one or more power domains based on the power-on status of one or more power domains among the plurality of power domains 140 (power domains 1, 2...N). Other expressions such as "first," "second," etc., in this document refer to any one of them, not a specific one.

[0034] After each power domain is powered on, the power management unit 110 can determine the power-on status of each power domain and provide a repair start signal for the first power domain. The repair start signal can have multiple repair start bits, each corresponding to a power domain, and different repair start bits can indicate the power-on status of different power domains within the multiple power domains. For example, repair start bit 1 can correspond to the power-on / off status of power domain 1, with a first predetermined bit, such as 1, representing power-on and a second predetermined bit, such as 0, representing power-off. Repair start bit 2 can correspond to the power-on / off status of power domain 2, with 1 representing power-on and 0 representing power-off. Similarly, repair start bit N can correspond to the power-on / off status of power domain N, with 1 representing power-on and 0 representing power-off.

[0035] The repair management unit 120 can be configured to determine first information based at least on a repair initiation signal for a first power domain, the first information including information indicating that the memory of the first power domain currently requires memory fault repair.

[0036] The first information can also have multiple information bits, each corresponding to a power domain. Different information bits can indicate whether memory fault repair is currently required in different power domains. In response to a power domain not being powered on (e.g., the repair start bit corresponding to that power domain in the repair start signal indicates power-off), or the power domain being powered on (e.g., the repair start bit corresponding to that power domain in the repair start signal indicates power-on), but memory fault repair has already been performed on that power domain, the bit in the first information corresponding to that power domain can be a second predetermined bit, such as 0, indicating that memory fault repair is not currently required for that power domain. Conversely, in response to a power domain being powered on (e.g., the repair start bit corresponding to that power domain in the repair start signal indicates power-on), but the memory's built-in self-test result indicates a memory fault in that power domain, and memory fault repair has not yet been performed on that power domain, the bit in the first information corresponding to that power domain can be a first predetermined bit, such as 1, indicating that memory fault repair is currently required for that power domain.

[0037] The repair management unit 120 can be configured to send a start signal and first information to the repair execution unit 130.

[0038] Here, the first information indicates whether memory fault repair of the power domain memory is required, and the start signal can serve as a trigger signal to control when the repair execution unit 130 begins memory fault repair. The start signal can be issued periodically or based on other control signals.

[0039] The start signal can also be indicated by 0 and 1, where 1 represents start and 0 represents no start. When the start signal changes from 0 to 1, the repair execution unit 130 begins memory fault repair of the memory in the power domain that needs memory repair. Before the start signal changes from 1 to 0, it is best to ensure that the values ​​of each bit of the first information have stabilized and will not change. This ensures that memory fault repair can be performed on the memory in the power domain indicated by the stabilized first information during the time period when the start signal is 1. When the memory fault repair is completed, the start signal can be set to 0. Then, the start signal can be set to 1 again after bisr_resetn_duration clock cycles by software configuration, such as bisr_resetn_duration (start signal interval) in the bisr_resetn_duration register. In some embodiments, the start signal can also have multiple start bits, and different start bits indicate whether to start memory fault repair in different power domains of multiple power domains. This allows for individual control of the start of memory fault repair in each power domain, and allows for customization of the start order, parallel start, or non-parallel start of memory fault repair in each power domain.

[0040] In some embodiments, the power management unit 110, the repair management unit 120, and the repair execution unit 130 can be in a power domain that is always powered on during operation. This allows the repair management unit 120 to have global control over the memory fault repair process of the memory in each power domain that is in a power-on or power-off state.

[0041] Next, the repair execution unit 130 can be configured to perform memory fault repair on the memory in the first power domain based on the start signal and the first information.

[0042] In this way, by communicating with the power management unit 110 about the power-on and power-off status of the power domain, and understanding the memory fault repair needs of the memory in the power domain, the repair management unit 120 can uniformly control the repair execution unit 130 to start or not start the memory fault repair of the memory in the power domain. This can effectively coordinate information from all parties to efficiently and smoothly complete the memory fault repair process of each power domain in the power-on and power-off process.

[0043] Figure 2 A flowchart illustrating the signals received and emitted by the repair management unit 120 in a chip according to at least one embodiment of the present disclosure is shown.

[0044] Power management unit 110 can be configured to provide a repair startup signal for a first power domain (e.g., based on the power-on status of a first power domain among multiple power domains (power domain numbers can be 1, 2...N)). Figure 2 (as shown in bisr_start). Where N is a positive integer.

[0045] like Figure 2 As shown, in some embodiments, the repair management unit 120 may also be configured to: receive a first power domain (in the form of a power domain) from the power management unit 110. Figure 2 The repair start signal bisr_start_d1 of the previous clock cycle and the repair start signal bisr_start of the current clock cycle are indicated by the power domain number shown.

[0046] For example, a D flip-flop or equivalent register can be used to delay the previously received repair start signal by one clock cycle to obtain the repair start signal bisr_start_d1 of the previous clock cycle. Then, the repair start signal bisr_start_d1 of the previous clock cycle and the repair start signal bisr_start of the current clock cycle can be compared.

[0047] In some embodiments, the repair management unit 120 may further be configured to: determine first information in response to the inconsistency between the repair start signal bisr_start_d1 of the previous clock cycle and the repair start signal bisr_start of the current clock cycle in the first power domain, and the rising edge between the repair start signal bisr_start_d1 of the previous clock cycle and the repair start signal bisr_start of the current clock cycle. Since the inconsistency between the repair start signal bisr_start_d1 of the previous clock cycle and the repair start signal bisr_start of the current clock cycle in the first power domain, and the rising edge between the repair start signal bisr_start_d1 of the previous clock cycle and the repair start signal bisr_start of the current clock cycle, it can be determined that the repair start signal bisr_start of the current clock cycle is the repair start signal bisr_start_trigger for the newly powered-on first power domain. Therefore, the first information can indicate that the memory in the newly powered-on first power domain currently needs to undergo memory fault repair.

[0048] Here, if the signals bisr_start and bisr_start_d1 are inconsistent, and bisr_start is a rising edge, this combination of conditions indicates that a new power domain has just been powered on, meaning that the power domain has issued a request for memory fault repair startup. This is because the two signals will only be inconsistent when bisr_start changes from 0 to 1, and this change is registered in bisr_start_d1, and bisr_start will then exhibit a rising edge.

[0049] Once a new request to initiate memory fault repair (BISR) is detected (e.g., a BISR initiation request), a register named `bisr_start_trigger` can be updated using the `bisr_start_trigger` signal. This register records the first information `PwrDomGrpEn` (indicating Power Domain Group Enable), which records which power domains have issued BISR initiation requests, meaning which power domains currently require memory fault repair. Specifically, the bit corresponding to the power domain that has changed can be set to 1. In this way, the repair management unit 120 can know which power domains currently need to initiate the BISR process. It is worth noting that each bit of the first information `PwrDomGrpEn` in the `bisr_start_trigger` register corresponds to a specific power domain. When the corresponding power domain issues a BISR initiation request, the corresponding bit is set to 1. This design also allows the repair management unit 120 to process BISR initiation requests from multiple power domains simultaneously to initiate memory fault repair for memories in multiple power domains at the same time, or to process these requests sequentially according to priority.

[0050] Repair management unit 120 can be configured to send a start signal to repair execution unit 130 (e.g., Figure 2 The bisr_resetn shown) and the first information (such as Figure 2 The PwrDomGrpEn shown indicates whether to start the repair execution unit to repair memory faults in the power domain that is identified as requiring memory repair.

[0051] In some embodiments, the repair management unit 120 may be configured to latch a repair start signal for the second power domain in response to the repair management unit receiving a repair start signal for the second power domain during a memory fault repair process in which the repair management unit 120 is handshaking with the repair execution unit 130 to perform a memory fault repair in the first power domain.

[0052] like Figure 2As shown, the lock signal bisr_reset_lock in the bisr_reset_lock register can indicate whether the repair management unit 120 is sending or receiving signals from the repair execution unit 130 to perform memory fault repair, i.e., whether there is an ongoing memory fault repair handshake. 0 represents no ongoing handshake, and 1 represents an ongoing handshake. In response to determining that there is currently no ongoing memory fault repair for the memory in the first power domain, the repair management unit 120 determines first information based on the repair start signal for the first power domain. For example, when bisr_start_trigger is not 0 and bisr_reset_lock is equal to 0, the repair management unit 120 can set the first information PwrDomGrpEn in the bisr_start_trigger register to the current value of bisr_start_trigger and set the start signal bisr_resetn to 0. That is, in the absence of an ongoing handshake, the first information PwrDomGrpEn can be modified according to the repair start signal bisr_start_trigger of the newly powered-on power domain, so that the first information indicates that the memory in the newly powered-on power domain currently needs memory fault repair. However, when there is an ongoing handshake, the lock signal bisr_reset_lock in the bisr_reset_lock register being 1 can latch (rather than discard) the repair start signal bisr_start_trigger of the newly powered-on power domain, instead of sending the repair start signal bisr_start_trigger to the bisr_start_trigger register to modify the first information PwrDomGrpEn.

[0053] In some embodiments, after memory fault repair of the memory in the first power domain is completed (i.e., after the ongoing handshake is completed), the first information is modified in response to the repair start signal bisr_start_trigger of the second power domain to include information indicating that the memory in the second power domain currently needs memory fault repair.

[0054] That is, after the handshake in progress ends, the lock signal bisr_reset_lock can become 0, thereby allowing the repair start signal bisr_start_trigger to be sent to the bisr_start_trigger register to modify the first information PwrDomGrpEn, so that the first information indicates that the memory in the newly powered power domain currently needs to be repaired for memory faults.

[0055] In summary, based on the description of the lock signal, in some embodiments, the repair management unit 120 may also be configured to: in response to determining that there is currently an ongoing memory fault repair for the memory in the first power domain, set the lock signal bisr_reset_lock (registered as...) Figure 2 The register bisr_reset_lock (as shown) indicates the repair of memory lock in the first power domain and indicates that the repair execution unit is not started to repair memory faults in the second power domain.

[0056] like Figure 2 As shown, the repair startup signal bisr_start_trigger and the completion signal (such as...) can be obtained through the bisr_start_trigger register. Figure 2 The bisr_done (described later) is used to determine whether there is an ongoing memory fault repair for the memory in the first power domain. For example, if the repair start signal bisr_start_trigger corresponding to a power domain is 1 (indicating that the repair has been started) and the completion signal bisr_done corresponding to a power domain is 0 (indicating that the repair has not been completed), then there is an ongoing memory fault repair for the memory in that power domain.

[0057] In this way, the repair start signal of the newly powered power domain can be initiated during the handshake between the repair management unit and the repair execution unit, and after the handshake is completed, the latched repair start signal will be responded to to perform memory fault repair in the newly powered power domain.

[0058] The chip disclosed herein also includes a software configuration interface (not shown in the figures), which further supports first software takeover instructions (e.g., sent via the software configuration interface) Figure 2 As shown, bisr_sw_byp) and, for example, a first software control signal from a software register (e.g.) Figure 2 As shown, PwrDomGrpEn_sw) is used to bypass the repair start signal bisr_start_trigger to determine whether the memory in the first power domain currently needs or does not need to be repaired for memory faults, or directly as the first information PwrDomGrpEn.

[0059] In other words, in one embodiment, the repair management unit 120 is further configured to: respond to receiving a first software takeover instruction sent from the software configuration interface (e.g., Figure 2 As shown, bisr_sw_byp), and signals that specify whether to repair or not repair memory faults in the first power domain among multiple power domains (e.g., Figure 2As shown, PwrDomGrpEn_sw), ignores the repair startup signal of the first power domain (such as... Figure 2 The `bisr_start_trigger` is shown, and the first software control signal (`PwrDomGrpEn_sw`) determines whether the memory in the first power domain currently needs or does not need memory fault repair. Therefore, the repair initiation signal `bisr_start_trigger` is ignored, and software is used to determine whether the memory in the first power domain currently needs or does not need memory fault repair. This provides a sufficiently flexible software configuration interface, allowing software to directly bypass the hardware logic to perform the memory fault repair process. It can normally complete the handshake between various units and the memory fault repair process even if there are hardware circuit design errors or operational errors.

[0060] This disclosure also supports second software takeover commands sent via a software configuration interface (e.g., ...). Figure 2 As shown, bisr_sw_byp) and, for example, a second software control signal from a software register (e.g., Figure 2 As shown, `bisr_resetn_sw` bypasses the boot signal `bisr_resetn` to initiate memory fault repair, instead of controlling the boot process through a preset period `bisr_resetn_duration`. The boot signal `bisr_resetn` can be registered as... Figure 2 The register shown is bisr_resetn.

[0061] In some embodiments, the repair management unit 120 may also be configured to: respond to receiving a second software takeover instruction (e.g., sent from a software configuration interface) Figure 2 As shown, bisr_sw_byp), and a second software control signal specifying whether to start or not (e.g., Figure 2 As shown, bisr_resetn_sw), ignores startup signals (e.g. Figure 2 As shown, bisr_resetn), and the repair execution unit is started or not started according to the software control signal (bisr_resetn_sw) to repair memory faults of the determined memory that needs memory repair. In this way, by providing a sufficiently flexible software configuration interface, it is convenient for software to directly bypass the hardware logic to operate, and can normally complete the handshake between units and the memory fault repair process in the event of hardware circuit design errors or operational errors.

[0062] Note that the aforementioned first software takeover instruction can be the same as the second software takeover instruction; that is, one software takeover instruction can indicate both the takeover first information and the takeover start signal. Alternatively, the aforementioned first software takeover instruction can be a different software takeover instruction from the second software takeover instruction, indicating either the takeover first information or the takeover start signal, respectively.

[0063] Based on the software configuration interface described above, in the event of errors in circuit hardware design or operation, various signals can be set through the software configuration interface to ensure normal handshake and subsequent operations between various units. The specific process may include:

[0064] (1) Determine which power domain or subsystem's memory fault repair needs to be performed based on the power-on process.

[0065] (2) Configure the bisr_sw_byp signal in the software takeover instruction (bisr_sw_byp) register to 1 (here, it indicates both the takeover first information PwrDomGrpEn and the takeover start signal bisr_resetn).

[0066] (3) Configure the bisr_resetn_sw signal in the first software control signal (bisr_resetn_sw) register to 1, indicating that the first software control signal is used to determine whether to start memory fault repair.

[0067] (4) Configure the bit of the power domain or subsystem power domain corresponding to the second software control signal (PwrDomGrpEn_sw) to 1, indicating that the second software control signal is used to determine which power domain(s) memory needs to be repaired for memory faults.

[0068] (5) Configure the bisr_resetn_sw register to 0, and then configure the bisr_resetn_sw register to 1 so as to generate a rising edge to trigger the memory in the power domain that needs memory fault repair to perform memory fault repair.

[0069] (6) Read the bisr_done_raw register (the bisr_done_raw register stores whether the memory fault repair of the corresponding power domain or subsystem power domain is completed. If completed, it is 1; if not completed, it is 0). Check whether the corresponding bit of the power domain or subsystem power domain is 1. If it is equal to 1, proceed to the next step.

[0070] (7) Set the bit of the pd_bisr_done_sw signal corresponding to the power domain or subsystem power domain registered in the pd_bisr_done_sw register (a software-controlled register used to indicate whether the memory fault repair of the corresponding power domain or subsystem power domain is complete; 1 if complete, 0 if not) to 1.

[0071] (8) After the power-on process is completed, set the bit of the power domain or subsystem corresponding to pd_bisr_done_sw to 0. This indicates that the memory fault repair process controlled by the software has ended and the next round of power-on and memory fault repair can begin.

[0072] The above-described software-controlled memory fault repair process demonstrates that by using the software takeover instruction (bisr_sw_byp), the first software control signal (bisr_resetn_sw), and the second software control signal (PwrDomGrpEn_sw), the software can easily bypass the hardware logic to perform the memory fault repair process. This allows the software to complete the handshake between various units and the memory fault repair process normally even if there are errors in the hardware circuit design or operation.

[0073] Next, the repair execution unit 130 can complete the memory fault repair of the memory in the power domain that is determined to require memory repair.

[0074] During the memory fault repair completion process, the repair management unit 120 can also be configured to: in response to the repair execution unit completing memory fault repair for the memory in the first power domain out of multiple power domains, record a completion signal indicating that the memory in the first power domain has completed memory fault repair (e.g., ...). Figure 2 The bisr_done signal indicates that a memory fault repair in a certain power domain has been completed. It can be registered in the pd_bisr_done register and sent to the power management unit or subsystem power management unit, equivalent to a response to a repair start signal issued by the power management unit or subsystem power management unit.

[0075] The repair management unit 120 can also be configured to: in response to recording all completion signals of the repair execution unit completing memory fault repair for all memories in all power domains of multiple power domains, modify the first information to indicate that all memories in all power domains of multiple power domains do not currently need to undergo memory fault repair, and modify the locking signal to indicate that the repair is not locked for all memories in all power domains of multiple power domains.

[0076] For example, if all bisr_done values ​​are recorded for all power domains, a bisr_all_done signal can be generated to indicate that all power domains have completed. Figure 2 (Not shown in the image), indicating that the current round of memory fault repair is complete, the bisr_all_done signal will modify the first information PwrDomGrpEn (e.g., clear it) to indicate that all memories in all power domains across multiple power domains do not currently require memory fault repair (in order to proceed with the next round of modification of the first information), and modify the lock signal bisr_reset_lock (e.g., clear it) to indicate that repair of all memories in all power domains across multiple power domains is not locked, meaning that the next round of memory fault repair process can begin. For example... Figure 2 As shown, the lock signal bisr_reset_lock can be stored in the register bisr_reset_lock.

[0077] In this way, by recording the completion signal, it is possible to conveniently control whether to start the next round of memory fault repair process.

[0078] In some embodiments, the repair management unit 120 is further configured to: in response to the fact that all memories in all power domains of multiple power domains have not completed memory fault repair after the timeout period has expired, modify the first information to indicate that all memories in all power domains of multiple power domains do not currently need to be repaired for memory faults, and modify the locking signal to indicate that the repair of all memories in all power domains of multiple power domains is not locked.

[0079] For example, if the bist_all_done signal is not generated or received within the timeout period, it may indicate that an error or loop has occurred during the memory fault repair process, and it cannot be completed indefinitely. In order to avoid waiting indefinitely for all memory repairs to be completed, the first information PwrDomGrpEn and the lock signal bisr_reset_lock can be forcibly cleared in this case, thereby resolving the system crash problem in this situation.

[0080] In some embodiments, the repair management unit may also be configured to: record the memory fault repair failure of the memory in the first power domain in response to a memory fault repair failure in the memory of a memory in a first power domain among a plurality of power domains.

[0081] For example, in response to a memory fault repair failure in the first power domain of a plurality of power domains (e.g., via... Figure 2 Whether the memory fault repair shown is determined by the signal bisr_pass (e.g., bisr_pass = 1 indicates success, 1 = failure) can be determined as follows: Figure 2 The pd_bisr_fail register shown records this power domain (which can be accessed via...). Figure 2 The first information, PwrDomGrpEn, indicates which power domain (e.g., which power domain number) experienced the memory fault repair failure. The bisr_fail signal indicates a failure in a specific power domain. The system control recovery module can read these bisr_fail signals to analyze the cause of the failure and resolve the memory fault repair failure. The system control recovery module can be an on-chip module specifically designed for system monitoring, fault detection, self-repair, and recovery control. External personnel can also use the system control recovery module to read these bisr_fail signals to analyze the cause of the failure and resolve the problem. This provides a path to resolve memory fault repair failures throughout the entire memory fault repair process, making the entire process controllable.

[0082] Note that once a power domain bisr_fail signal is recorded in the pd_bisr_fail register, it is typically not removed (e.g., cleared) during subsequent memory fault repair in that power domain until the bisr_fail_clr register is configured by software to clear the bisr_fail signal. In other words, the bisr_fail signal will only be cleared when an external user resolves the memory fault repair failure and manually clears it using software. This ensures that the memory fault repair failure is actually resolved before further repairs can proceed in that power domain, preventing the failure from being ignored or maliciously tampered with.

[0083] Note that the terms "first power domain," "second power domain," "third power domain," "first power domain," etc., mentioned above are merely to represent any power domain and do not imply that they must be the same power domain or different power domains. This is not a restriction imposed in this paper. Furthermore, the signals mentioned in this paper can all be stored in corresponding registers in the circuit; descriptions of each register are omitted here.

[0084] In summary, by communicating with the power management unit about the power-on and power-off status of the power domains and understanding the memory fault repair needs of the memories within those power domains, the repair management unit can centrally control the initiation or non-initiation of memory fault repair for the memories within the power domains. This effectively coordinates information from all parties, enabling efficient and smooth completion of the memory fault repair process for each power domain during the power-on and power-off flow. Furthermore, the repair management unit can simultaneously process BISR start requests from multiple power domains to initiate memory fault repair for memories in multiple power domains concurrently, or process these requests sequentially according to priority. Furthermore, the repair management unit can initiate the repair start signal for newly powered-on power domains during the handshake between the repair management unit and the repair execution unit, and only after the handshake is complete will it respond to the latched repair start signal to perform memory fault repair for the memories in the newly powered-on power domains. Furthermore, a sufficiently flexible software configuration interface allows software to directly bypass hardware logic for operation. Furthermore, recording completion signals allows for convenient control over whether to initiate the next round of the memory fault repair process. Furthermore, it provides a path to resolve memory fault repair failures throughout the entire memory fault repair process, making the entire memory fault repair process controllable.

[0085] The defects and problems existing in the above-mentioned prior art solutions are also the result of the inventor's careful research after practical and creative labor. The discovery process of the above problems and the solutions proposed by at least one embodiment disclosed below for the above problems are all creative contributions of the inventor during the invention process.

[0086] Figure 3 A schematic diagram is shown illustrating the signal interaction of a chip and its on-chip subsystems and power domains according to at least one embodiment of the present disclosure when they are powered on.

[0087] As previously described, the power management unit, repair management unit, and repair execution unit in the chip can operate in a continuously powered power domain to ensure control over memory fault repair in each power domain during power-up and power-down cycles. However, the power-on process of these units and the related memory fault management also need to be defined. The following section will combine... Figure 3 This describes the power-on process of each unit in a uniformly powered power domain, as well as the power-on process of the power domain in a subsystem.

[0088] 1. The power-on process of a continuously powered power domain

[0089] During the power-on process of a continuously powered power domain, which includes a power management unit, a repair management unit, and a repair execution unit, the power management unit 310, repair management unit 320, and repair execution unit 330 also need to be powered on one by one. The power management unit 310 may not yet be powered on, therefore it cannot detect the power-on of other power domains and cannot send a repair start signal. In this case, the hardware power-on reset sequence control unit (por_seq_ctrl) 340 can send a repair start signal (such as...). Figure 3 The signal (aon_mbist_start) is sent to the repair management unit 320 (func_bisr_ctrl). The repair management unit 320 detects the input unit start signal (e.g., aon_mbist_start). Figure 3 After the rising edge of the indicated aon_mbist_start, a handshake with the repair execution unit (BISR Controller of DFT) 330 will automatically begin to initiate the process of controlling memory fault repair according to at least one embodiment of this disclosure (assuming that information indicating that the memory in the first power domain currently needs memory fault repair already exists). After the repair execution unit (BISR Controller of DFT) 330 completes the memory fault repair of the memory in the corresponding power domain, it will return a completion signal (bisr_done, where each bit can correspond to a power domain) and send it to the power-on reset sequence control unit (por_seq_ctrl) 340 through the repair management unit 320. After receiving the completion signal bisr_done, the power-on reset sequence control unit (por_seq_ctrl) 340 will continue to perform subsequent steps, such as controlling the power-on sequence of each module, power-on fault detection or recovery, etc. After the power management unit 310 is powered on, it will detect the power-on in each power domain and send a repair startup signal.

[0090] 2. Power-on process of the chip's subsystem

[0091] If the chip also has subsystems, the power management unit 310 will be powered on when the chip's subsystem is powered on, but the subsystem power management unit 350 of the chip's subsystem may not be powered on at this time. Therefore, the power management unit 310 will send a repair start signal (mbist_start) to the repair management unit 320. Here, the chip's subsystem refers to the part of the chip that is divided into different functional areas or modules, such as the central processing unit subsystem, graphics processing unit subsystem, memory subsystem, input / output subsystem, clock and reset subsystem, etc. After detecting the rising edge of the input repair start signal (mbist_start), the repair management unit 320 will automatically start handshaking with the repair execution unit 330. After the repair execution unit 330 completes the memory fault repair of the corresponding power domain, it will return a completion signal bisr_done and send it to the repair management unit 320 and the power management unit 310. The repair management unit 320 will mark the current handshake power domain as completed, while the power management unit 310 will continue to complete subsequent power-on control, such as power access, voltage detection, power-on sequence control, status monitoring, fault detection, etc.

[0092] 3. Power-on process of the internal power domain of the subsystem

[0093] After the chip's subsystem powers on, the subsystem's power management unit 350 also powers on. Therefore, when powering on a power domain within the subsystem, the subsystem's power management unit 350 detects and sends a subsystem power domain start signal (ss_mbist_start) to the repair management unit 320. Upon detecting the rising edge of the input subsystem power domain start signal (ss_mbist_start), the repair management unit 320 automatically begins handshaking with the repair execution unit 330. After completing the memory fault repair for the corresponding power domain, the repair execution unit 330 returns a completion signal (bisr_done) to both the repair management unit 320 and the subsystem's power management unit 350. The repair management unit 320 marks the current handshake as complete, while the subsystem's power management unit 350 continues with subsequent power-on control.

[0094] Both the power management unit 310 and the power management unit 350 of the subsystem can be regarded as power management units in this disclosure.

[0095] The above power-on process is based on the actual power-on situation and the sequence of power-on, ensuring that even if the power management unit itself has not yet been powered on and cannot issue the corresponding power domain repair start signal during the power-on process, other alternative modules can issue the corresponding power domain repair start signal.

[0096] Figure 4A flowchart of a method for controlling memory fault repair according to at least one embodiment of the present disclosure is shown.

[0097] like Figure 4 The method for controlling memory fault repair includes the following steps 410, 420 and 430.

[0098] In step 410, a repair start signal for the first power domain can be provided by the power management unit based on the power-on status of the first power domain among multiple power domains.

[0099] In step 420, the repair management unit can determine first information, at least based on the repair start signal for the first power domain. The first information includes information indicating that the memory of the first power domain currently needs memory fault repair.

[0100] In step 430, the repair management unit can send a start signal and first information to the repair execution unit.

[0101] In step 440, the memory fault repair in the first power domain can be performed by the repair execution unit based on the start signal and the first information.

[0102] In some embodiments, in step 420, determining the first information by the repair management unit, at least based on the repair start signal for the first power domain, may include: receiving the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle for the first power domain from the power management unit; determining the first information in response to the inconsistency between the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle for the first power domain, and the repair start signal of the previous clock cycle being a rising edge from the repair start signal of the previous clock cycle to the repair start signal of the current clock cycle.

[0103] In some embodiments, the method may further include: latching the repair start signal of the second power domain in response to the repair management unit receiving a repair start signal of the second power domain during a handshake between the repair management unit and the repair execution unit to perform memory fault repair of the memory in the first power domain; and modifying the first information to include information indicating that the memory in the second power domain currently needs memory fault repair after the memory fault repair of the memory in the first power domain has ended in response to the repair start signal of the second power domain.

[0104] In some embodiments, step 420 may include: in response to determining that there is currently no ongoing memory fault repair for the memory in the first power domain, determining first information based on a repair initiation signal for the first power domain.

[0105] In some embodiments, the method may further include: in response to determining that there is currently an ongoing memory fault repair for memory in a first power domain, setting a lock signal to indicate a lock repair for memory in the first power domain, and indicating that a repair execution unit is not started to perform memory fault repair for memory in a second power domain.

[0106] In some embodiments, the method may further include: in response to receiving a first software takeover instruction sent from a software configuration interface and a software control signal specifying whether to repair or not repair a memory fault in a memory in a first power domain among a plurality of power domains, ignoring a repair initiation signal of the first power domain, and determining, based on the software control signal, whether the memory in the first power domain currently needs or does not need to be repaired for a memory fault.

[0107] In some embodiments, the method may further include: in response to receiving a second software takeover instruction sent from a software configuration interface and a second software control signal specifying whether to start or not start, ignoring the start signal, and starting or not starting the repair execution unit according to the software control signal to perform memory fault repair on the determined memory that needs memory repair.

[0108] In some embodiments, the method may further include: in response to the repair execution unit completing memory fault repair for memory in a first power domain among a plurality of power domains, recording a completion signal indicating that the memory in the first power domain has completed memory fault repair; and / or in response to recording all completion signals that the repair execution unit has completed memory fault repair for all memory in all power domains among a plurality of power domains, modifying first information to indicate that all memory in all power domains among a plurality of power domains does not currently require memory fault repair, and modifying a locking signal to indicate that all memory in all power domains among a plurality of power domains is not locked for repair.

[0109] In some embodiments, the method may further include: in response to the fact that all memories in all power domains of multiple power domains have not completed memory fault repair after a timeout period, modifying first information to indicate that all memories in all power domains of multiple power domains do not currently need to undergo memory fault repair, and modifying a locking signal to indicate that repair is not locked for all memories in all power domains of multiple power domains.

[0110] In some embodiments, the method may further include: recording a memory fault repair failure of the memory in the first power domain in response to a memory fault repair failure of the memory in the first power domain.

[0111] In some embodiments, the repair start signal may have multiple repair start bits, and different repair start bits may indicate the power-on status of different power domains in multiple power domains. The first information has multiple information bits, and different information bits may indicate whether the memory in different power domains in multiple power domains currently needs to perform memory fault repair. The start signal may have multiple start bits, and different start bits may indicate whether to start the memory in different power domains in multiple power domains to perform memory fault repair.

[0112] In some embodiments, the power management unit, the repair management unit, and the repair execution unit can be located in a power domain that is always powered on during operation.

[0113] In summary, by communicating with the power management unit about the power-on and power-off status of the power domains and understanding the memory fault repair needs of the memories within those power domains, the repair management unit can centrally control the initiation or non-initiation of memory fault repair for the memories within the power domains. This effectively coordinates information from all parties, enabling efficient and smooth completion of the memory fault repair process for each power domain during the power-on and power-off flow. Furthermore, the repair management unit can simultaneously process BISR start requests from multiple power domains to initiate memory fault repair for memories in multiple power domains concurrently, or process these requests sequentially according to priority. Furthermore, the repair management unit can initiate the repair start signal for newly powered-on power domains during the handshake between the repair management unit and the repair execution unit, and only after the handshake is complete will it respond to the latched repair start signal to perform memory fault repair for the memories in the newly powered-on power domains. Furthermore, a sufficiently flexible software configuration interface allows software to directly bypass hardware logic for operation. Furthermore, recording completion signals allows for convenient control over whether to initiate the next round of the memory fault repair process. Furthermore, it provides a path to resolve memory fault repair failures throughout the entire memory fault repair process, making the entire memory fault repair process controllable.

[0114] Figure 5 A block diagram of an exemplary electronic device 500 according to at least one embodiment of the present disclosure is shown.

[0115] The electronic device 500 may include a chip 510 according to at least one embodiment of the present disclosure. Of course, the electronic device 500 may also include devices such as memory in a plurality of power domains 520.

[0116] The memory can be various embedded memories on the chip, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Flash memory, Embedded Read-Only Memory (ROM / Programmable Read-Only Memory, PROM), and other special types of memory (such as Through-Silicon Via (TSV)).

[0117] In addition, the electronic device 500 or its internal units may include (but are not limited to) a processor core, a graphics processing unit, a digital signal processor, registers, a communication interface, peripheral circuits, and a controller, etc. (not shown in the figure).

[0118] In one embodiment, the unit within the electronic device 500 may also include a processor or other computing device for executing at least one computer instruction to perform the steps of the various functions and / or methods in the embodiments described herein. Further details are omitted here.

[0119] The following is for reference. Figure 6 This diagram illustrates a structural schematic of an electronic device 600 suitable for implementing embodiments of the present disclosure. The terminal devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0120] like Figure 6 As shown, electronic device 600 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 610, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 620 or a program loaded from storage device 660 into random access memory (RAM) 630. RAM 630 also stores various programs and data required for the operation of electronic device 600. Processing device 610, ROM 620, and RAM 630 are interconnected via bus 640. Input / output (I / O) interface 650 is also connected to bus 640.

[0121] Typically, the following devices can be connected to I / O interface 650: input devices 660 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 670 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 660 including, for example, magnetic tapes, hard disks, etc.; and communication devices 690. Communication device 690 allows electronic device 600 to communicate wirelessly or wiredly with other devices to exchange data. Although... Figure 6 An electronic device 600 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0122] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 690, or installed from a storage device 660, or installed from a ROM 620. When the computer program is executed by the processing device 610, it performs the functions defined in the methods of embodiments of this disclosure.

[0123] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0124] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0125] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0126] The aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: acquire at least two Internet Protocol (IP) addresses; send a node evaluation request to a node evaluation device, including at least two IP addresses, wherein the node evaluation device selects an IP address from the at least two IP addresses and returns it; and receive the IP address returned by the node evaluation device; wherein the acquired IP address indicates an edge node in the content delivery network.

[0127] Alternatively, the aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: receive a node evaluation request including at least two Internet Protocol (IP) addresses; select an IP address from the at least two IP addresses; and return the selected IP address; wherein the received IP address indicates an edge node in the content delivery network.

[0128] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0129] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0130] The units described in the embodiments of this disclosure can be implemented in software or in hardware. The name of a unit does not necessarily limit the unit itself; for example, the first acquisition unit can also be described as "a unit that acquires at least two Internet Protocol addresses".

[0131] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0132] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0133] One or more embodiments of this disclosure provide at least the following examples:

[0134] Example 1. A chip, comprising a power management unit, a repair management unit, and a repair execution unit, wherein...

[0135] The power management unit is configured to provide a repair startup signal for a first power domain based on the power-on status of a first power domain among multiple power domains;

[0136] The repair management unit is configured as follows:

[0137] At least based on the repair initiation signal for the first power domain, first information is determined, the first information including information indicating that the memory of the first power domain currently needs memory fault repair;

[0138] Send a start signal and first information to the repair execution unit;

[0139] The repair execution unit is configured to perform memory fault repair on the memory in the first power domain based on the start signal and the first information.

[0140] Example 2. According to the chip in Example 1, the repair management unit is configured to determine first information at least based on a repair start signal for a first power domain by the following steps:

[0141] Receive the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle from the power management unit;

[0142] The first information is determined in response to the inconsistency between the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle in the first power domain, and the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle are rising edges.

[0143] Example 3. Based on the chip in Example 2, the repair management unit is further configured as follows:

[0144] In response to the repair management unit receiving a repair start signal for the second power domain during the period when the repair management unit is handshaking with the repair execution unit to perform memory fault repair for the memory in the first power domain, the repair management unit latches the repair start signal for the second power domain.

[0145] After memory fault repair in the first power domain is completed, the first information is modified in response to a repair initiation signal for the second power domain to include information indicating that memory fault repair is currently required in the second power domain.

[0146] Example 4. Based on the chip in Example 1, the repair management unit is further configured as follows:

[0147] In response to determining that there is currently no ongoing memory fault repair for the memory in the first power domain, first information is determined based on the repair initiation signal for the first power domain.

[0148] Example 5. Based on the chip in Example 1, wherein the chip further includes a software configuration interface, and the repair management unit is further configured as follows:

[0149] In response to receiving a first software takeover command sent from the software configuration interface, and a software control signal specifying whether to repair or not repair memory faults in the memory of the first power domain among multiple power domains, the repair initiation signal of the first power domain is ignored, and the memory in the first power domain is determined to be currently required or not required to undergo memory fault repair based on the software control signal.

[0150] Example 6. Based on the chip in Example 1, wherein the chip further includes a software configuration interface, and the repair management unit is further configured as follows:

[0151] In response to receiving a second software takeover command sent from the software configuration interface and a second software control signal specifying whether to start or not start, the start signal is ignored, and the repair execution unit is started or not started according to the software control signal to perform memory fault repair on the determined memory that needs memory repair.

[0152] Example 7. Based on the chip in Example 1, the repair management unit is further configured as follows:

[0153] In response to the repair execution unit completing memory fault repair for the memory in the first power domain out of multiple power domains, a completion signal indicating that the memory in the first power domain has completed memory fault repair is recorded.

[0154] In response to recording all completion signals that the repair execution unit has completed memory fault repair for all memories in all power domains across multiple power domains, the first information is modified to indicate that memory fault repair is not currently required for all memories in all power domains across multiple power domains, and the locking signal is modified to indicate that repair is not locked for all memories in all power domains across multiple power domains.

[0155] Example 8. Based on the chip in Example 1, the repair management unit is further configured as follows:

[0156] If, after the timeout period, all memories in all power domains of multiple power domains have still not completed memory fault repair, the first information is modified to indicate that all memories in all power domains of multiple power domains do not currently need to undergo memory fault repair, and the locking signal is modified to indicate that repair is not locked for all memories in all power domains of multiple power domains.

[0157] Example 9. Based on the chip in Example 1, the repair management unit is further configured as follows:

[0158] In response to a memory fault repair failure in the memory of the first power domain among multiple power domains, the memory fault repair failure in the memory of the first power domain is recorded.

[0159] Example 10. According to the chip of Example 1, wherein the repair start signal has multiple repair start bits, and different repair start bits indicate the power-on status of different power domains in multiple power domains, the first information has multiple information bits, and different information bits indicate whether the memory in different power domains in multiple power domains currently needs to perform memory fault repair, and wherein the start signal has multiple start bits, and different start bits indicate whether to start the memory in different power domains in multiple power domains to perform memory fault repair.

[0160] Example 11. According to the chip in Example 1, the power management unit, the repair management unit, and the repair execution unit are in a power domain that is always powered on during operation.

[0161] Example 12. A method for controlling memory fault repair, comprising:

[0162] The power management unit provides a repair startup signal for the first power domain based on the power-on status of the first power domain among multiple power domains.

[0163] By means of the repair management unit, at least based on the repair start signal for the first power domain, the first information is determined, the first information including information indicating that the memory of the first power domain currently needs to be repaired for memory faults.

[0164] The repair management unit sends a start signal and first information to the repair execution unit.

[0165] The repair execution unit performs memory fault repair on the memory in the first power domain based on the startup signal and the first information.

[0166] Example 13. According to the method of Example 12, wherein the first information is determined by the repair management unit based at least on a repair start signal for the first power domain, including:

[0167] Receive the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle from the power management unit;

[0168] The first information is determined in response to the inconsistency between the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle in the first power domain, and the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle are rising edges.

[0169] Example 14. Based on the method of Example 13, it also includes:

[0170] In response to the repair management unit receiving a repair start signal for the second power domain during the period when the repair management unit is handshaking with the repair execution unit to perform memory fault repair for the memory in the first power domain, the repair management unit latches the repair start signal for the second power domain.

[0171] After memory fault repair in the first power domain is completed, the first information is modified in response to a repair initiation signal for the second power domain to include information indicating that memory fault repair is currently required in the second power domain.

[0172] Example 15. According to the method of Example 12, by means of the repair management unit, first information is determined at least based on the repair start signal for the first power domain, including:

[0173] In response to determining that there is currently no ongoing memory fault repair for the memory in the first power domain, first information is determined based on the repair initiation signal for the first power domain.

[0174] Example 16. Based on the method of Example 12, it also includes:

[0175] In response to receiving a first software takeover command sent from the software configuration interface, and a software control signal specifying whether to repair or not repair memory faults in the memory of the first power domain among multiple power domains, the repair initiation signal of the first power domain is ignored, and the memory in the first power domain is determined to be currently required or not required to undergo memory fault repair based on the software control signal.

[0176] Example 17. Based on the method of Example 12, it also includes:

[0177] In response to receiving a second software takeover command sent from the software configuration interface and a second software control signal specifying whether to start or not start, the start signal is ignored, and the repair execution unit is started or not started according to the software control signal to perform memory fault repair on the determined memory that needs memory repair.

[0178] Example 18. Based on the method of Example 12, it also includes:

[0179] In response to the repair execution unit completing memory fault repair for the memory in the first power domain out of multiple power domains, a completion signal indicating that the memory in the first power domain has completed memory fault repair is recorded.

[0180] In response to recording all completion signals that the repair execution unit has completed memory fault repair for all memories in all power domains across multiple power domains, the first information is modified to indicate that memory fault repair is not currently required for all memories in all power domains across multiple power domains, and the locking signal is modified to indicate that repair is not locked for all memories in all power domains across multiple power domains.

[0181] Example 19. Following the method of Example 12, it also includes:

[0182] If, after the timeout period, all memories in all power domains of multiple power domains have still not completed memory fault repair, the first information is modified to indicate that all memories in all power domains of multiple power domains do not currently need to undergo memory fault repair, and the locking signal is modified to indicate that repair is not locked for all memories in all power domains of multiple power domains.

[0183] Example 20. Based on the method of Example 12, it also includes:

[0184] In response to a memory fault repair failure in the memory of the first power domain among multiple power domains, the memory fault repair failure in the memory of the first power domain is recorded.

[0185] Example 21. According to the method of Example 12, wherein the repair start signal has multiple repair start bits, and different repair start bits indicate the power-on status of different power domains in multiple power domains, the first information has multiple information bits, and different information bits indicate whether the memory in different power domains in multiple power domains currently needs to perform memory fault repair, and wherein the start signal has multiple start bits, and different start bits indicate whether to start the memory in different power domains in multiple power domains to perform memory fault repair.

[0186] Example 22. According to the method of Example 12, the power management unit, the repair management unit, and the repair execution unit are in a power domain that is always powered on during operation.

[0187] Example 23. An electronic device comprising:

[0188] The chip is based on any of the examples 1-11.

[0189] Example 24. A non-transitory computer-readable storage medium having computer instructions stored thereon,

[0190] When executed by a processor, the computer instructions cause the processor to perform a method according to any one of Examples 12-22.

[0191] Example 25. A computer program product comprising computer instructions,

[0192] When executed by a processor, the computer instructions cause the processor to perform a method according to any one of Examples 12-22.

[0193] Example 26. An electronic device comprising:

[0194] Storage device, which stores computer instructions;

[0195] At least one processing device is configured to execute computer instructions in a storage device to perform a method according to any one of Examples 12-22.

[0196] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0197] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0198] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A chip comprising a power management unit, a repair management unit, and a repair execution unit, wherein... The power management unit is configured to provide a repair startup signal for the first power domain based on the power-on status of the first power domain among a plurality of power domains. The repair management unit is configured as follows: At least based on the repair initiation signal for the first power domain, first information is determined, the first information including information indicating that the memory of the first power domain currently needs memory fault repair; Send a start signal and the first information to the repair execution unit; The repair execution unit is configured to perform memory fault repair on the memory in the first power domain based on the start signal and the first information.

2. The chip of claim 1, wherein the repair management unit is configured to determine first information by means of at least a repair start signal for the first power domain: The power management unit receives the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle for the first power domain. The first information is determined in response to the inconsistency between the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle in the first power domain, and the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle being a rising edge.

3. The chip according to claim 2, wherein, The repair management unit is also configured to: In response to the repair management unit receiving a repair start signal for the second power domain while the repair management unit is handshaking with the repair execution unit to perform memory fault repair for the memory in the first power domain, the repair management unit latches the repair start signal for the second power domain. After memory fault repair in the memory of the first power domain is completed, the first information is modified in response to a repair start signal for the second power domain to include information indicating that memory in the second power domain currently requires memory fault repair.

4. The chip according to claim 1, wherein, The repair management unit is also configured to: In response to determining that there is currently no ongoing memory fault repair for the memory in the first power domain, the first information is determined based on the repair initiation signal for the first power domain.

5. The chip according to claim 1, wherein, The chip also includes a software configuration interface, and the repair management unit is further configured to: In response to receiving a first software takeover instruction sent from the software configuration interface, and a software control signal specifying whether to repair or not repair a memory fault in the memory of the first power domain among the plurality of power domains, the repair initiation signal of the first power domain is ignored, and the memory in the first power domain is determined to be currently required or not required to undergo memory fault repair based on the software control signal.

6. The chip according to claim 1, wherein, The chip also includes a software configuration interface, and the repair management unit is further configured to: In response to receiving a second software takeover instruction sent from the software configuration interface and a second software control signal specifying whether to start or not start, the start signal is ignored, and the repair execution unit is started or not started according to the software control signal to perform memory fault repair on the determined memory that needs memory repair.

7. The chip according to claim 1, wherein, The repair management unit is also configured to: In response to the repair execution unit completing memory fault repair for the memory in the first power domain among the plurality of power domains, a completion signal indicating that the memory in the first power domain has completed memory fault repair is recorded. and / or In response to recording all completion signals of the repair execution unit completing memory fault repair for all memories in all power domains of the plurality of power domains, the first information is modified to indicate that all memories in all power domains of the plurality of power domains do not currently need to undergo memory fault repair, and the locking signal is modified to indicate that repair is not locked for all memories in all power domains of the plurality of power domains.

8. The chip according to claim 1, wherein, The repair management unit is also configured to: In response to the fact that all memories in all power domains of the plurality of power domains have not completed memory fault repair after the timeout period has expired, the first information is modified to indicate that all memories in all power domains of the plurality of power domains do not currently need to be repaired for memory faults, and the locking signal is modified to indicate that repair is not locked for all memories in all power domains of the plurality of power domains.

9. The chip according to claim 1, wherein, The repair management unit is also configured to: In response to a memory fault repair failure in the memory of the first power domain among the plurality of power domains, a memory fault repair failure in the memory of the first power domain is recorded.

10. The chip according to claim 1, wherein, The repair start signal has multiple repair start bits, and different repair start bits indicate the power-on status of different power domains in the multiple power domains. The first information has multiple information bits, and different information bits indicate whether the memory in different power domains in the multiple power domains currently needs to perform memory fault repair. The start signal has multiple start bits, and different start bits indicate whether to start the memory in different power domains in the multiple power domains to perform memory fault repair.

11. The chip according to claim 1, wherein, The power management unit, the repair management unit, and the repair execution unit are all in a power domain that is always powered on during operation.

12. A method for controlling memory fault repair, comprising: The power management unit provides a repair start signal for the first power domain based on the power-on status of the first power domain among multiple power domains. The repair management unit determines first information based at least on the repair initiation signal for the first power domain, the first information including information indicating that the memory of the first power domain currently needs memory fault repair. The repair management unit sends a start signal and the first information to the repair execution unit. The repair execution unit performs memory fault repair on the memory in the first power domain based on the start signal and the first information.

13. The method of claim 12, wherein determining the first information by the repair management unit, at least based on a repair initiation signal for the first power domain, includes: The power management unit receives the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle for the first power domain. The first information is determined in response to the inconsistency between the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle in the first power domain, and the repair start signal of the previous clock cycle and the repair start signal of the current clock cycle being a rising edge.

14. The method of claim 13, further comprising: In response to the repair management unit receiving a repair start signal for the second power domain while the repair management unit is handshaking with the repair execution unit to perform memory fault repair for the memory in the first power domain, the repair management unit latches the repair start signal for the second power domain. After memory fault repair in the memory of the first power domain is completed, the first information is modified in response to a repair start signal for the second power domain to include information indicating that memory in the second power domain currently requires memory fault repair.

15. The method of claim 12, wherein determining the first information by the repair management unit, at least based on a repair initiation signal for the first power domain, comprises: In response to determining that there is currently no ongoing memory fault repair for the memory in the first power domain, the first information is determined based on the repair initiation signal for the first power domain.

16. The method of claim 12, further comprising: In response to receiving a first software takeover instruction sent from the software configuration interface, and a software control signal specifying whether to repair or not repair a memory fault in the memory of the first power domain among the plurality of power domains, the repair initiation signal of the first power domain is ignored, and the memory in the first power domain is determined to be currently required or not required to undergo memory fault repair based on the software control signal.

17. The method of claim 12, further comprising: In response to receiving a second software takeover instruction sent from the software configuration interface and a second software control signal specifying whether to start or not start, the start signal is ignored, and the repair execution unit is started or not started according to the software control signal to perform memory fault repair on the determined memory that needs memory repair.

18. An electronic device comprising: The chip according to any one of claims 1-11.

19. A non-transitory computer-readable storage medium having computer instructions stored thereon, in, When executed by a processor, the computer instructions cause the processor to perform the method according to any one of claims 12-17.

20. An electronic device, comprising: Storage device, which stores computer instructions; At least one processing device is configured to execute the computer instructions in the storage device to perform the method according to any one of claims 12-17.

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