Nonvolatile memory data read operation test system

Abstract

According to the nonvolatile memory data read operation test system provided by the embodiment of the invention, after the test data is burnt to the memory, the system can automatically execute the read and comparison operation of the test data, the expected value is determined based on the comparison result, and the system can adaptively adjust the clock period range of the initial stable read data, so that the data read efficiency is improved. Therefore, the critical clock period of successful data reading can be accurately captured, so that the access time of the memory can be efficiently calculated. The method significantly improves the test coverage, has high implementation flexibility, can be conveniently applied to various test platforms or carriers, and realizes accurate measurement of the reading speed of the target memory.

Description

Technical Field

[0001] The embodiments of this application belong to the field of read operation testing technology, and in particular relate to a non-volatile memory data read operation testing system. Background Technology

[0002] Non-volatile memory (NVM) is a core component of integrated circuits, and measuring its read speed is not only a crucial step in performance verification but also an important basis for reliability analysis, system optimization, standard certification, and new technology development. Accurate read speed measurement methods can help engineers optimize designs, improve yield, reduce power consumption, and ensure stable chip operation in complex application environments. However, these methods are complex, and memory cells are susceptible to process deviations, noise, and aging, leading to read / write errors. Traditional testing methods rely on external testing equipment, such as applying test vectors via ATE (Automatic Test Equipment), which is time-consuming, costly, and unable to monitor internal data in real time. When comparing read speeds with expected values, fixed test patterns struggle to cover real-world scenarios, resulting in inaccurate read speed measurements.

[0003] While the Chinese patent with publication number CN 111696617 A provides a memory testing scheme, its static testing method based on preset fixed comparison data has significant shortcomings: First, this method cannot adapt to the testing needs of dynamic data scenarios, and its testing mode is singular and lacks flexibility; second, its address path requires strict timing balance, which is difficult to ensure timing consistency in actual chip manufacturing due to environmental factors such as process deviations and temperature changes, resulting in deviations in read speed measurement results. This makes it difficult to meet the requirements of modern memory for high-precision performance testing, especially in high-frequency, high-precision application scenarios where the reliability of test results will be severely compromised; in addition, relying on manual clock adjustment not only increases the inaccuracy of measurement but also introduces additional time costs. Summary of the Invention

[0004] To address or mitigate the problems in the prior art, this application provides a non-volatile memory data read operation test system, including a main control unit, a mode generation unit, a write operation generation unit, a data programming unit, a clock generation unit, a read operation generation unit, a data acquisition and comparison unit, and a signal multiplexing unit. The main control unit is connected to the pattern generation unit, clock generation unit, read operation generation unit and data acquisition and comparison unit respectively; The mode generation unit is connected to the write operation generation unit, and the clock generation unit is connected to the read operation generation unit and the data acquisition and comparison unit. Both the output of the write operation generation unit and the output of the read operation generation unit are connected to the signal multiplexing generation unit. The output terminal of the signal multiplexing unit is connected to the data acquisition and comparison unit; The signal multiplexing unit is also connected to the non-volatile memory; The mode generation unit is used to generate test data according to the configured data parameters, and as part of the automatic test, it generates data values ​​and stores them in the main control unit; and stores them in the status register as expected values. The write operation generation module is used to write the data generated by the pattern generation unit into the non-volatile memory; The signal multiplexing unit is used to select the non-volatile memory port signals; The clock generation unit receives parameters from the main control unit and generates a clock signal; The read operation generation unit is used to generate a number of read request signals and address signals equal to the address range, using the clock signal output by the clock generation unit as a synchronization clock.

[0005] The data acquisition and comparison unit is used to acquire readback data by using the clock signal output by the clock generation unit as a reference clock and delaying the sampling clock by two cycles from the clock that generates the rising edge of the read request signal. The desired data acquisition and comparison unit retrieves the desired value from the main control unit and synchronously compares it with the readback data in sequence.

[0006] In a preferred embodiment of this application, the read operation generation unit uses the rising edge of the clock to alternately generate a read request signal and an address signal.

[0007] In a preferred embodiment of this application, the main control unit includes a register unit, which includes a configuration register and a status register. The status register is used to store the expected value; The configuration register is used to configure data parameters.

[0008] Compared with existing technologies, this application provides a non-volatile memory data read operation testing system. After the test data is burned into the memory, the system can automatically perform test data read and comparison operations. Based on the comparison results to determine the expected value, the system can adaptively adjust the clock cycle range for initially stabilizing data reads to accurately capture the critical clock cycle for successful data reads. Therefore, the memory access time can be efficiently calculated. This method significantly improves test coverage and has high implementation flexibility, allowing for convenient application to various test platforms or carriers to achieve accurate measurement of the target memory read speed. Attached Figure Description

[0009] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a diagram of an automatic measurement system for data read speed of non-volatile memory provided in an embodiment of this application; Figure 2 This is a timing diagram for the first read request implementation in step S4; Figure 3 This is a timing diagram for the second read request implementation in step S4. Detailed Implementation

[0010] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0011] This application provides a method for testing data read operations of non-volatile memory to solve the problems of low efficiency, poor flexibility and high cost of existing measurement techniques.

[0012] This application provides a measurement system for testing memory read speed, without limiting the carrier, and can be ASIC, FPGA, IP, etc. that can generate the process described in this invention. This application can provide a flexible and configurable test architecture, such as supporting the rapid development of dedicated FPGA test equipment or ASIC test chips, or it can be integrated into the target IC as a configurable IP core, significantly improving the practicality and deployment efficiency of the test solution.

[0013] The operation of each part of the NVM data read speed automatic measurement system is as follows: The system mainly consists of eight parts: communication interface (100); main control unit (200); mode generation unit (300); write operation generation unit (400); clock generation unit (500); read operation generation unit (600); data acquisition and comparison unit (700); and signal multiplexing unit (800). The user configures the test register through communication interface 100. The user interface can be a common general-purpose interface such as I2C, UART, or SPI. The configuration includes: clock source CLKs, clock frequency range fmin, fmax; clock frequency step value fstep; test data format data_typte; and test address range [Addr_min, Addr_max]. To achieve diverse test data, the pattern generation unit 300 needs to generate various types of data. The pattern generation unit 300 receives the test data format data_typte from the register unit. This parameter has three values: 0: using built-in byte complementary data; 1: using user-configured data; 2: using truly random data (generated by the truly random number generation module integrated in the pattern generation unit 300). The pattern generation unit 300 is responsible for generating test data De1, De2, ..., Den according to the configured data parameter data_type. Simultaneously, as part of the automatic testing, the generated data values ​​are stored in a status register as expected values.

[0014] The write operation generation module 400 is responsible for writing the data generated by the pattern generation unit 300 into the NVM.

[0015] Because this system may be integrated into an ASIC or target IC as IP, and the NVM's port signals—WRITE (write request), DIN (data input), READ (read request), ADDR (address), and DOUT (data output)—are all common, the signal multiplexing unit 800 only selects these signals when the system is operating, in order not to affect the original logic. The core component of the signal multiplexing unit 800 is a set of multiplexers.

[0016] Clock generation unit 200 receives the following register unit parameters: 1) Clock source CLKs; 2) Clock frequency range fmin, fmax; 3) Clock frequency step value fstep. It then generates a clock: fmin + fstep * n, where n is a positive integer starting from 0, representing the nth round of testing.

[0017] The read operation generation unit 600 uses the clock output from the clock generation unit 500 as its synchronization clock. It generates the same number of read request (READ) and address (ADDR) signal groups as the address range. To address timing stability issues and the need for timing compensation, the read operation generation unit uses the rising edge of the clock to alternately generate the read request signal (READ) and the address signal (ADDR), such as... Figure 2 As shown.

[0018] Similarly, the data acquisition and comparison unit 700 uses the clock output from the clock generation unit as the reference clock, and the sampling clock and the clock that generates the rising edge of the read request signal READ are delayed by two cycles, such as... Figure 2 The SAMPLE_CLK shown represents the collected data as D0, D1, ..., Dn.

[0019] The data acquisition and comparison unit 700 retrieves the expected values ​​De1, De2, ..., Den from the status register in the main control unit and synchronously compares them sequentially with the readback data D0, D1, ..., Dn. A complete match is used as the condition for passing the comparison.

[0020] If round 0 fails, the status register will indicate that the set frequency range is unreasonable and the value of fmin is too large, and the value of fmin should be reduced to restart the test. If round 0 passes, the control unit will adjust the output clock of the clock generation unit and automatically start the next round of testing. This continues until round n fails. The data acquisition and comparison unit writes the frequency fmin + fstep * (n-1) back to the status register and sets the test completion flag to indicate that the entire test is complete.

[0021] By reading back the frequency through the communication interface and converting it into the corresponding clock period T, and combining it with T3-T4-T1 reported by the EDA tool, TAA can be quickly calculated.

[0022] This application is not limited to configuring the data required for testing through registers, but can also generate it randomly through internal logic. This application realizes automatic measurement of NVM data reading speed.

[0023] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0024] The implementation plan for the NVM read speed automatic measurement system is based on Figure 1 The communication interface is specified as an I2C interface, and the clock generation unit 500 is shown in detail, including clock generation logic, temperature compensation logic, and clock calibration logic. The specific logic implementation is as follows. 1) Configuration parameters: clock source CLKs; clock frequency range fmin, fmax; clock frequency step value fstep=5%; configure test data format data_typte=0; configure test address range [Addr_min, Addr_max]. Therefore, the data written to NVM has a word-complementary format, such as 0x00FFAA55, 0XAA5500FF, 0X55FFAA00, etc.

[0025] 2) The data burned is automatically written back to the status register of the register unit as the expected value De0, De1, ..., Den.

[0026] 3) The clock generation unit has a built-in temperature compensation and calibration unit, which stably outputs a clock CLK with a frequency of fmin + 5%n.

[0027] 4) The read operation generation unit uses CLK as the clock source, alternately generating the read request signal READ and the address signal, traversing the space [Addr_min, Addr_max], such as... Figure 3 As shown, this form solves the timing stability defects and the need for timing compensation.

[0028] 5) After the read request signal READ arrives at the NVM port for a time TAA, the NVM returns data to DOUT. The data changes sequentially to D0, D1, D2, ..., D_max.

[0029] 6) Because a read request is generated every two clock cycles, the data acquisition and comparison unit also samples the DOUT port every two clock cycles to obtain data D0, D1, D2, ..., D_max.

[0030] 7) The data acquisition and comparison unit retrieves the expected values ​​De1, De2, ..., Den from the register unit and simultaneously checks whether De0=D0, De1=D1, ..., Den=D_max; to determine whether to automatically execute clock adjustment and the next round of testing, until the comparison fails, and the test result is written back. This "single instruction trigger - direct result reading" automated test system completely eliminates external clock dependence and manual calibration, improving measurement efficiency.

[0031] 8) After the test is completed, read back the results through the I2C interface and calculate the TAA.

[0032] The NVM read speed automatic measurement system implemented in this application achieves the following core effects through an integrated architecture and a dynamically programmable mechanism: 1. Break through the limitations of fixed comparison data: Achieve rich automated test data generation through user-programmable data registers and multi-mode generation units.

[0033] 2. Achieve order-of-magnitude optimization in stability: Based on edge alignment technology of the same clock source, the impact of process and temperature drift is reduced.

[0034] 3. Significantly improved measurement efficiency and automation: The construction of a fully autonomous test line completely eliminates external clock dependence and manual calibration, and the operation complexity will be "single instruction trigger - direct result reading".

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A test system for data read operations of non-volatile memory, characterized in that, It includes a main control unit, a mode generation unit, a write operation generation unit, a data programming unit, a clock generation unit, a read operation generation unit, a data acquisition and comparison unit, and a signal multiplexing unit; The main control unit is connected to the pattern generation unit, clock generation unit, read operation generation unit and data acquisition and comparison unit respectively; The mode generation unit is connected to the write operation generation unit, and the clock generation unit is connected to the read operation generation unit and the data acquisition and comparison unit. Both the output of the write operation generation unit and the output of the read operation generation unit are connected to the signal multiplexing generation unit. The output terminal of the signal multiplexing unit is connected to the data acquisition and comparison unit; The signal multiplexing unit is also connected to the non-volatile memory; The mode generation unit is used to generate test data according to the configured data parameters, and as part of the automatic test, the generated data values ​​are stored in the main control unit. The desired value is sent to the status register. The write operation generation module is used to write the data generated by the pattern generation unit into the non-volatile memory; The signal multiplexing unit is used to select the non-volatile memory port signals; The clock generation unit receives parameters from the main control unit and generates a clock signal; The read operation generation unit is used to generate a number of read request signals and address signals equal to the address range, using the clock signal output by the clock generation unit as a synchronization clock. The data acquisition and comparison unit is used to acquire readback data by using the clock signal output by the clock generation unit as a reference clock and delaying the sampling clock by two cycles from the clock that generates the rising edge of the read request signal. The desired data acquisition and comparison unit retrieves the desired value from the main control unit and synchronously compares it with the readback data in sequence.

2. The non-volatile memory data read operation test system as described in claim 1, characterized in that, The read operation generation unit uses the rising edge of the clock to alternately generate read request signals and address signals.

3. The non-volatile memory data read operation test system as described in claim 1, characterized in that, The main control unit includes a register unit, which includes a configuration register and a status register; The status register is used to store the expected value; The configuration register is used to configure data parameters.

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