Ring communication method and system based on double five-wire system SPI (Serial Peripheral Interface) and storage medium

Abstract

The invention provides a ring communication method and system based on a double five-wire system SPI (Serial Peripheral Interface) and a storage medium, in the method, GPIO (General Purpose Input / Output) is pulled up through a Slave end (namely slave equipment) to serve as a signal for secure transmission, one-way data flow is concerned, communication logic is simplified, research and development difficulty is reduced, robustness is improved, research and development cost is reduced, and performance, data integrity and timeliness are considered.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a ring communication method, system and storage medium based on dual five-wire SPI. Background Technology

[0002] SPI is a high-speed, full-duplex, synchronous communication bus protocol commonly used for data transmission between microcontrollers and various peripherals, and can also serve as an inter-chip communication link. A standard SPI consists of four signal lines (SCLK, MOSI, MISO, SS / CS) and has a strict master / slave structure. Only the master device can generate the clock signal and control data transmission; the slave device cannot initiate transmission. Because SPI lacks a handshake signal, when the master initiates a transmission, the slave may still be preparing data, resulting in incomplete data after transmission. Furthermore, the SPI slave side needs to handle the DMA / FIFO buffer promptly; otherwise, data errors will occur.

[0003] In summary, the standard SPI bus suffers from incomplete data preparation during master-slave communication. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a ring communication method, system and storage medium based on dual five-wire SPI, so as to alleviate the technical problem of incomplete data preparation in master-slave communication of the standard SPI bus.

[0005] In a first aspect, the present invention provides a ring communication method based on dual five-wire SPI for realizing full-duplex data communication between a first chip and a second chip, the method comprising: In the communication direction from the first chip to the second chip, the following one-way communication control process is executed: The second chip, acting as a slave device, sets the first GPIO notification signal line to an active level after completing data reception or initialization. When the first chip, acting as the master device, detects that the first GPIO notification signal line is at an active level and has data to be sent to the second chip, it initiates SPI transmission to the second chip via the first SPI bus. After receiving and processing the data, the second chip sets the first GPIO notification signal line to an active level again. In the communication direction from the second chip to the first chip, the following one-way communication control process is executed in parallel and independently: The first chip, acting as a slave device, sets the second GPIO notification signal line to an active level after completing data reception or initialization. The second chip, acting as the master device, detects that the second GPIO notification signal line is at an active level and, when it has data to be sent to the first chip, initiates an SPI transmission to the first chip via the second SPI bus. After receiving and processing the data, the first chip sets the second GPIO notification signal line to an active level again; The two unidirectional communication control processes mentioned above are independent of each other and are executed in parallel, together forming a ring full-duplex communication.

[0006] Furthermore, in any communication direction, the necessary condition for initiating an SPI transmission is that the master device in that direction simultaneously meets the following two conditions: The GPIO notification signal line controlled by the peer slave device is detected to be at an active level; It has application data to be sent. If any condition is missing, the master device will not initiate an SPI transmission.

[0007] Furthermore, the active level GPIO notification signal line is actively executed by the slave device. As long as the slave device is in a data-receiving state, it maintains its GPIO notification signal line at an active level, thereby keeping the communication link always online and ready.

[0008] Furthermore, during the SPI transmission process, the application data flow is strictly unidirectional. Specifically, on the first SPI bus, data flows only from the first chip to the second chip; on the second SPI bus, data flows only from the second chip to the first chip.

[0009] Furthermore, the method also includes: When the master device has data to be sent and the slave device has data with low real-time requirements to be sent, while the master device initiates SPI transmission to send its data, the slave device utilizes the full-duplex characteristic of SPI to send the data with low real-time requirements to the master device through the MISO signal line within the same SPI transmission cycle.

[0010] Furthermore, the method also includes: The two unidirectional communication control processes mentioned above have independent SPI controllers and GPIO resources.

[0011] Furthermore, during system startup, an initialization process is executed: The first chip and the second chip respectively set the GPIO notification signal line controlled when they act as slave devices to an active level, thereby enabling the two unidirectional communication links to enter the ready state simultaneously.

[0012] Secondly, the present invention also provides a ring communication system based on dual five-wire SPI for realizing full-duplex data communication between a first chip and a second chip, the system comprising: The first unidirectional communication link includes: The first SPI bus connects the SPI master controller interface of the first chip and the SPI slave interface of the second chip. The first GPIO notification signal line is connected to the GPIO interrupt input interface of the first chip and the GPIO output controller of the second chip. The second unidirectional communication link includes: The second SPI bus connects the SPI master controller interface of the second chip and the SPI slave interface of the first chip. The second GPIO notification signal line is connected to the GPIO interrupt input interface of the second chip and the GPIO output controller of the first chip. Wherein, the first chip is configured to: when acting as the master device of the first unidirectional communication link, perform the operation corresponding to the first chip side in any of the methods of the first aspect; when acting as the slave device of the second unidirectional communication link, perform the operation corresponding to the first chip side in any of the methods of the first aspect; The second chip is configured to: when acting as the master device of the second unidirectional communication link, perform the operation corresponding to the second chip side in any of the methods of the first aspect; and when acting as the slave device of the first unidirectional communication link, perform the operation corresponding to the second chip side in any of the methods of the first aspect.

[0013] Furthermore, the first chip is a microcontroller (MCU), and the second chip is a system-on-a-chip (SoC).

[0014] Thirdly, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the method described in the first aspect.

[0015] This invention provides a ring communication method based on dual five-wire SPI for achieving full-duplex data communication between a first chip and a second chip. The method includes: executing the following one-way communication control flow in the communication direction from the first chip to the second chip: The second chip, acting as a slave device, sets the first GPIO notification signal line to an active level after completing data reception or initialization; the first chip, acting as a master device, detects that the first GPIO notification signal line is active and, when it has data to be sent to the second chip, initiates an SPI transmission to the second chip via the first SPI bus; after receiving and processing the data, the second chip sets the first GPIO notification signal line back to active level. The second GPIO notification signal line is set to an active level. In the communication direction from the second chip to the first chip, the following unidirectional communication control processes are executed in parallel and independently: The first chip, acting as a slave device, sets the second GPIO notification signal line to an active level after completing data reception or initialization; the second chip, acting as a master device, detects that the second GPIO notification signal line is active and, when it has data to send to the first chip, initiates an SPI transmission to the first chip via the second SPI bus; after receiving and processing the data, the first chip sets the second GPIO notification signal line to an active level again. These two unidirectional communication control processes are independent of each other and executed in parallel, together forming a ring full-duplex communication. As described above, the ring communication method based on dual five-wire SPI of this invention uses the Slave end (i.e., the slave device) to pull the GPIO high as a signal for secure transmission, focusing on unidirectional data flow, simplifying communication logic, reducing development difficulty, improving robustness, reducing development costs, and balancing performance, data integrity, and timeliness. This alleviates the technical problem of incomplete data preparation in master-slave communication using the standard SPI bus. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a ring communication method based on dual five-wire SPI provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a five-wire SPI communication link provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a ring-shaped dual five-wire SPI provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] In master-slave communication using the standard SPI bus, data preparation is incomplete.

[0020] Based on this, in the ring communication method based on dual five-wire SPI of the present invention, the GPIO is pulled high by the Slave end (i.e., the slave device) as a signal for safe transmission, focusing on unidirectional data flow, simplifying communication logic, reducing R&D difficulty, improving robustness, reducing R&D costs, and taking into account performance, data integrity and timeliness.

[0021] To facilitate understanding of this embodiment, a ring communication method based on dual five-wire SPI disclosed in this embodiment of the invention will first be described in detail.

[0022] Example 1: According to an embodiment of the present invention, an embodiment of a ring communication method based on dual five-wire SPI is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0023] Figure 1 This is a flowchart of a ring communication method based on dual five-wire SPI according to an embodiment of the present invention, as follows: Figure 1 As shown, a method for achieving full-duplex data communication between a first chip and a second chip includes the following steps: Step S102, in the communication direction from the first chip to the second chip, execute the following one-way communication control flow: The second chip, acting as a slave device, sets the first GPIO notification signal line to an active level after completing data reception or initialization. The first chip, acting as the master device, detects that the first GPIO notification signal line is at an active level and, when it has data to be sent to the second chip, initiates an SPI transmission to the second chip via the first SPI bus. After receiving and processing the data, the second chip sets the first GPIO notification signal line to an active level again. Step S104: In the communication direction from the second chip to the first chip, the following one-way communication control process is executed in parallel and independently: The first chip, acting as a slave device, sets the second GPIO notification signal line to an active level after completing data reception or initialization. The second chip, acting as the master device, detects that the second GPIO notification signal line is at an active level and, when it has data to be sent to the first chip, initiates an SPI transmission to the first chip via the second SPI bus. After receiving and processing the data, the first chip sets the second GPIO notification signal line to an active level again. The two unidirectional communication control processes mentioned above are independent of each other and are executed in parallel, together forming a ring full-duplex communication.

[0024] In this embodiment of the invention, a one-to-one communication scenario between two chips is the best practice. This invention constructs a ring communication mechanism using two sets of mutually master-slave five-wire SPI communication links, thereby achieving efficient and secure communication.

[0025] This invention describes the five-wired SPI (SPI) communication link. For example... Figure 2 The diagram illustrates the connection method for a five-wire SPI communication link. A standard four-wire SPI plus a GPIO pin constitutes a five-wire SPI. The Master side configures the GPIO interrupt (indicated by the small black dot to the left of GPIO_ready in the diagram). Unidirectional communication means that after the Slave pulls GPIO_ready high (i.e., the GPIO notification signal line is active), the Master controls data transmission when it has data; the Slave, after receiving data, immediately pulls GPIO_ready high to wait for the next transmission. Because the data flow is unidirectional, the Master does not need to process data sent from the Slave, and the Slave does not need to prepare data, thus significantly improving link communication efficiency.

[0026] The key characteristic of unidirectional streaming is that the Master controls data transmission according to its own needs after GPIO_ready.

[0027] This invention provides a ring communication method based on dual five-wire SPI for achieving full-duplex data communication between a first chip and a second chip. The method includes: executing the following one-way communication control flow in the communication direction from the first chip to the second chip: The second chip, acting as a slave device, sets the first GPIO notification signal line to an active level after completing data reception or initialization; the first chip, acting as a master device, detects that the first GPIO notification signal line is active and, when it has data to be sent to the second chip, initiates an SPI transmission to the second chip via the first SPI bus; after receiving and processing the data, the second chip sets the first GPIO notification signal line back to active level. The second GPIO notification signal line is set to an active level. In the communication direction from the second chip to the first chip, the following unidirectional communication control processes are executed in parallel and independently: The first chip, acting as a slave device, sets the second GPIO notification signal line to an active level after completing data reception or initialization; the second chip, acting as a master device, detects that the second GPIO notification signal line is active and, when it has data to send to the first chip, initiates an SPI transmission to the first chip via the second SPI bus; after receiving and processing the data, the first chip sets the second GPIO notification signal line to an active level again. These two unidirectional communication control processes are independent of each other and executed in parallel, together forming a ring full-duplex communication. As described above, the ring communication method based on dual five-wire SPI of this invention uses the Slave end (i.e., the slave device) to pull the GPIO high as a signal for secure transmission, focusing on unidirectional data flow, simplifying communication logic, reducing development difficulty, improving robustness, reducing development costs, and balancing performance, data integrity, and timeliness. This alleviates the technical problem of incomplete data preparation in master-slave communication using the standard SPI bus.

[0028] The above provides a brief overview of the ring communication method based on dual five-wire SPI of the present invention. The specific details involved are described in detail below.

[0029] In an optional embodiment of the present invention, in any communication direction, the necessary condition for initiating SPI transmission is that the master device in that direction simultaneously satisfies the following two conditions: The GPIO notification signal line controlled by the peer slave device is detected to be at an active level; It has application data to be sent. If any condition is missing, the master device will not initiate an SPI transmission.

[0030] In an optional embodiment of the present invention, the active level GPIO notification signal line is actively executed by the slave device. As long as the slave device is in a data-receiving state, it maintains its GPIO notification signal line at an active level, thereby keeping the communication link always online and ready.

[0031] In an optional embodiment of the present invention, during SPI transmission, the application data flow is strictly unidirectional, wherein on the first SPI bus, data flows only from the first chip to the second chip; and on the second SPI bus, data flows only from the second chip to the first chip.

[0032] In an optional embodiment of the present invention, the method further includes: When the master device has data to be sent and the slave device has data with low real-time requirements to be sent, while the master device initiates SPI transmission to send its data, the slave device utilizes the full-duplex feature of SPI to send the data with low real-time requirements to the master device through the MISO signal line within the same SPI transmission cycle.

[0033] In an optional embodiment of the present invention, the method further includes: The two unidirectional communication control processes mentioned above have independent SPI controllers and GPIO resources.

[0034] In an optional embodiment of the present invention, an initialization process is executed when the system starts up: The first and second chips respectively set the GPIO notification signal lines controlled when they act as slave devices to an active level, thereby enabling the two unidirectional communication links to enter the ready state simultaneously.

[0035] Specifically, such as Figure 3 As shown, the configuration method of a ring dual five-wire SPI is illustrated using an MCU and a SoC as examples. The two SPI paths are mutually master and slave. The master is configured to receive the ready signal from the slave via GPIO interrupt. The data flow is from the master to the slave. The master only controls data transmission when it needs to transmit data.

[0036] The advantages of a dual five-wire SPI loop are its extremely simple logic while ensuring performance, bandwidth, and data integrity. The disadvantage is that it requires slightly higher hardware specifications, necessitating two SPI controllers. However, most embedded chips have multiple SPI controllers, so the cost increase is negligible.

[0037] For communication scenarios that require high bandwidth, the full-duplex feature of SPI can be utilized to carry data that does not require high real-time performance in the Slave-to-Master direction while transmitting data unidirectionally from Master to Slave. It should be noted that the Slave should prepare the data before pulling GPIO_ready high.

[0038] This invention proposes a ring communication mechanism using dual five-wire SPI unidirectional transmission to improve communication efficiency, reduce development difficulty, enhance code robustness, and ensure data integrity. Combined with the SPI protocol stack design, it enables the retransmission of lost critical data. The aforementioned dual five-wire SPI unidirectional transmission ring link fully utilizes the redundant SPI controller in the chip, using the Slave pin to pull high GPIO as a secure transmission signal, focusing on unidirectional data flow, simplifying communication logic, reducing development difficulty, improving robustness, lowering development costs, and balancing performance, data integrity, and timeliness.

[0039] This invention proposes a communication mechanism for a dual five-wire SPI unidirectional transmission ring link, improving and perfecting the standard SPI communication logic. Because it is a dual-GPIO link, both chips have the ability to actively send data. This invention proposes using the added GPIO through the five-wire system to notify the Master that the Slave is ready for transmission, almost guaranteeing that the Slave is online in real time, which is key to achieving efficient collaborative communication. This invention also proposes a solution to increase bandwidth, namely, utilizing the duplex characteristic of SPI to carry data with low real-time requirements in a reverse unidirectional flow.

[0040] The core objective of this invention is to construct a high-bandwidth, high-reliability, and logically simple inter-chip communication link. Its design philosophy is to abandon complex bidirectional collaborative handshaking and instead adopt a structured ring channel based on unidirectional data flow.

[0041] Core architecture: From unidirectional links to ring networks.

[0042] Basic unit: Five-wire SPI unidirectional link.

[0043] Composition: Standard SPI four-wire (SCLK, MOSI, MISO, CS) + 1 GPIO line (GPIO_ready).

[0044] Data flow: Strictly unidirectional, flowing from the Master to the Slave.

[0045] GPIO function: After the slave finishes receiving and processing data, it immediately pulls GPIO_ready high to indicate that it is ready to receive the next frame of data. After the master detects this signal, it will only initiate the next SPI transmission when it has data to send.

[0046] Key feature: The Slave only receives, does not send, application data (via the MOSI line); the Master only sends, does not receive, application data (via the MISO line). This simplifies the data flow logic.

[0047] Core innovation: Ring-shaped bidirectional communication architecture.

[0048] Composition: Two independent, opposite-direction five-wire SPI unidirectional links are established between two communication chips (such as MCU and SoC).

[0049] Link 1: Chip A acts as the Master, and chip B acts as the Slave. The data flow is A→B.

[0050] Link 2: Chip B acts as the Master, and chip A acts as the Slave. The data flow is B→A.

[0051] Work mode: Each link operates independently using the aforementioned unidirectional transmission mechanism.

[0052] Chip A can actively send data to chip B through link 1, and chip B can also actively send data to chip A through link 2.

[0053] The two links operate in parallel without interfering with each other, achieving true, independent full-duplex communication.

[0054] Workflow: Centered on data transmission.

[0055] Taking "chip A sending data to chip B" as an example (link 1: A is the master, B is the slave): Preparation and notification: After completing the last data reception, chip B (Slave) immediately pulls GPIO_ready high to notify chip A "I am ready".

[0056] Master device decision: Chip A (Master) detected that GPIO_ready is high.

[0057] If chip A has data to send to chip B, it initiates an SPI transmission and sends the data out.

[0058] If chip A has no data to send, it does nothing and waits for the next GPIO_ready signal (which may come from new data arriving).

[0059] Receive from device: Chip B receives data, processes it, and then pulls GPIO_ready high again to wait for the next transmission.

[0060] Reverse link: Link 2 (B→A) operates independently in exactly the same way.

[0061] Advanced features: Bandwidth enhancement techniques.

[0062] Optimization technique: Utilize the full-duplex feature of SPI to carry low-frequency data on the reverse channel.

[0063] Principle: During transmission on link 1 (A→B), although B is the slave and does not actively send application data, SPI is a full-duplex protocol, with both the MOSI and MISO lines operating simultaneously. Therefore, when A sends high-speed data to B, it can "incidentally" transmit back low-frequency data that B needs to send to A, which does not have high real-time requirements, via the MISO line.

[0064] Effect: It fully utilizes the bandwidth of the physical link without increasing additional transmission overhead, thus achieving "piggyback" transmission.

[0065] Key Invention Points: Invention Point 1: A ring full-duplex communication architecture based on a dual five-wire SPI unidirectional link.

[0066] Technical problem to be solved: The standard SPI bidirectional communication logic is complex, and the master and slave devices are mutually constrained, making it difficult to achieve efficient and independent full-duplex transmission.

[0067] Technical approach: By using two physically independent, opposite-direction "five-wire SPI unidirectional links", the complex bidirectional coordination problem is decoupled into two simple, independent unidirectional flow control problems.

[0068] Technical effect: It realizes extremely simplified logic, true full-duplex, high-bandwidth inter-chip communication, and both parties can independently and proactively send data to each other.

[0069] Invention Point 2: A "device readiness notification" mechanism for unidirectional data flow.

[0070] Technical problem to be solved: Ensure data integrity in one-way transmission, while avoiding blind transmission by the master device.

[0071] Technical approach: Add a GPIO_ready signal to the slave device in a unidirectional link. The slave device immediately pulls this signal high after each reception to declare readiness; the master device only initiates transmission when it detects the readiness signal and has data of its own.

[0072] Technical benefits: It ensures that the slave device is always in a ready state to receive data, fundamentally avoiding data loss or incompleteness; at the same time, the master device has complete sending scheduling rights and clear logic.

[0073] Invention Point 3: Utilizing the full-duplex physical characteristics of SPI to achieve reverse data piggybacking.

[0074] The technical problem to be solved: How to further increase effective bandwidth without increasing the number of additional transmissions.

[0075] Technical means: During the same SPI transmission cycle in which the master device sends high-speed data (master data stream) to the slave device, low-frequency, non-urgent data from the slave device to the master device is "piggybacked" using the reverse MISO line.

[0076] Technical benefits: It maximizes the use of the physical bandwidth of the SPI bus, realizes near-zero overhead reverse data transmission, and improves overall communication efficiency.

[0077] Example 2: A ring communication system based on dual five-wire SPI is used to achieve full-duplex data communication between a first chip and a second chip. The system includes: The first unidirectional communication link includes: The first SPI bus connects the SPI master controller interface of the first chip and the SPI slave interface of the second chip. The first GPIO notification signal line is connected to the GPIO interrupt input interface of the first chip and the GPIO output controller of the second chip. The second unidirectional communication link includes: The second SPI bus connects the SPI master controller interface of the second chip and the SPI slave interface of the first chip. The second GPIO notification signal line connects the GPIO interrupt input interface of the second chip to the GPIO output controller of the first chip. The first chip is configured to: when acting as the master device of the first unidirectional communication link, execute the operation corresponding to the first chip side in any of the methods in Embodiment 1; when acting as the slave device of the second unidirectional communication link, execute the operation corresponding to the first chip side in any of the methods in Embodiment 1. The second chip is configured to: when acting as the master device of the second unidirectional communication link, perform the operation corresponding to the second chip side in any of the methods in Embodiment 1; when acting as the slave device of the first unidirectional communication link, perform the operation corresponding to the second chip side in any of the methods in Embodiment 1.

[0078] Optionally, the first chip is a microcontroller (MCU) and the second chip is a system-on-a-chip (SoC).

[0079] The system provided in this embodiment of the invention has the same implementation principle and technical effects as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the system embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0080] Corresponding to the above-described ring communication method based on dual five-wire SPI, this application embodiment also provides a computer-readable storage medium storing machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions cause the processor to perform the steps of the above-described ring communication method based on dual five-wire SPI.

[0081] The ring communication system based on dual five-wire SPI provided in this application embodiment can be specific hardware on a device or software or firmware installed on the device. The system provided in this application embodiment has the same implementation principle and technical effects as the foregoing method embodiments. For the sake of brevity, any parts not mentioned in the device embodiment section can be referred to the corresponding content in the foregoing method embodiments. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can all be referred to the corresponding processes in the above method embodiments, and will not be repeated here.

[0082] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0083] For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0084] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0085] In addition, the functional units in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0086] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the ring communication method based on dual five-wire SPI described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0087] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0088] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A ring communication method based on dual five-wire SPI, characterized in that, The method for enabling full-duplex data communication between a first chip and a second chip includes: In the communication direction from the first chip to the second chip, the following one-way communication control process is executed: The second chip, acting as a slave device, sets the first GPIO notification signal line to an active level after completing data reception or initialization. When the first chip, acting as the master device, detects that the first GPIO notification signal line is at an active level and has data to be sent to the second chip, it initiates SPI transmission to the second chip via the first SPI bus. After receiving and processing the data, the second chip sets the first GPIO notification signal line to an active level again. In the communication direction from the second chip to the first chip, the following one-way communication control process is executed in parallel and independently: The first chip, acting as a slave device, sets the second GPIO notification signal line to an active level after completing data reception or initialization. The second chip, acting as the master device, detects that the second GPIO notification signal line is at an active level and, when it has data to be sent to the first chip, initiates an SPI transmission to the first chip via the second SPI bus. After receiving and processing the data, the first chip sets the second GPIO notification signal line to an active level again; The two unidirectional communication control processes mentioned above are independent of each other and are executed in parallel, together forming a ring full-duplex communication.

2. The method according to claim 1, characterized in that, In any communication direction, the necessary condition for initiating an SPI transmission is that the master device in that direction simultaneously meets the following two conditions: The GPIO notification signal line controlled by the peer slave device is detected to be at an active level; It has application data to be sent. If any condition is missing, the master device will not initiate an SPI transmission.

3. The method according to claim 1, characterized in that, The active GPIO notification signal line is actively executed by the slave device. As long as the slave device is in a data-receiving state, it maintains its GPIO notification signal line at an active level, thereby keeping the communication link always online and ready.

4. The method according to claim 1, characterized in that, During the SPI transmission process, the application data flow is strictly unidirectional. Specifically, on the first SPI bus, data flows only from the first chip to the second chip; on the second SPI bus, data flows only from the second chip to the first chip.

5. The method according to claim 1, characterized in that, The method further includes: When the master device has data to be sent and the slave device has data with low real-time requirements to be sent, while the master device initiates SPI transmission to send its data, the slave device utilizes the full-duplex characteristic of SPI to send the data with low real-time requirements to the master device through the MISO signal line within the same SPI transmission cycle.

6. The method according to claim 1, characterized in that, The two unidirectional communication control processes mentioned above have independent SPI controllers and GPIO resources.

7. The method according to claim 1, characterized in that, The initialization process is executed during system startup: The first chip and the second chip respectively set the GPIO notification signal line controlled when they act as slave devices to an active level, thereby enabling the two unidirectional communication links to enter the ready state simultaneously.

8. A ring communication system based on dual five-wire SPI, characterized in that, The system is used to enable full-duplex data communication between a first chip and a second chip. The first unidirectional communication link includes: The first SPI bus connects the SPI master controller interface of the first chip and the SPI slave interface of the second chip. The first GPIO notification signal line is connected to the GPIO interrupt input interface of the first chip and the GPIO output controller of the second chip. The second unidirectional communication link includes: The second SPI bus connects the SPI master controller interface of the second chip and the SPI slave interface of the first chip. The second GPIO notification signal line is connected to the GPIO interrupt input interface of the second chip and the GPIO output controller of the first chip. The first chip is configured to: when acting as the master device of the first unidirectional communication link, perform the operation corresponding to the first chip side in the method of any one of claims 1 to 7; and when acting as the slave device of the second unidirectional communication link, perform the operation corresponding to the first chip side in the method of any one of claims 1 to 7. The second chip is configured to: when acting as the master device of the second unidirectional communication link, perform the operation corresponding to the second chip side in the method of any one of claims 1 to 7; and when acting as the slave device of the first unidirectional communication link, perform the operation corresponding to the second chip side in the method of any one of claims 1 to 7.

9. The system according to claim 8, characterized in that, The first chip is a microcontroller (MCU), and the second chip is a system-on-a-chip (SoC).

10. A computer-readable storage medium storing a computer program thereon, characterized in that, The computer program is executed by the processor to perform the method of any one of claims 1 to 7.

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