Method of manufacturing semiconductor device and method of manufacturing electronic device

Abstract

The invention relates to a method of manufacturing a semiconductor device and a method of manufacturing an electronic device. The method of manufacturing a semiconductor device includes: forming a laminate; forming a channel hole in the laminated body; forming a preliminary channel layer in the channel hole; forming a cover layer on the preliminary channel layer, the cover layer having a first thickness in a first portion of the cover layer and having a second thickness greater than the first thickness in a second portion of the cover layer; forming a metal seed crystal in the covering layer; diffusing the metal seed crystal into the preliminary channel layer through the covering layer; and forming a channel layer by crystallizing the preliminary channel layer using the metal seed crystal.

Description

Technical Field

[0001] This disclosure relates to an electronic device, including but not limited to methods for manufacturing semiconductor devices and methods for manufacturing electronic devices. Background Technology

[0002] The integration density of semiconductor devices is determined by the area occupied by a single memory cell. As the integration density of semiconductor devices where memory cells are formed in a single layer on a substrate reaches its limit, three-dimensional semiconductor devices where memory cells are stacked on a substrate are under development. Various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0003] In one embodiment, a method of manufacturing a semiconductor device may include: forming a laminate; forming a channel via in the laminate; forming a preliminary channel layer in the channel via; forming a capping layer on the preliminary channel layer, the capping layer having a first thickness in a first portion of the capping layer and a second thickness greater than the first thickness in a second portion of the capping layer; forming a metal seed crystal in the capping layer; diffusing the metal seed crystal through the capping layer into the preliminary channel layer; and forming a channel layer by crystallizing the preliminary channel layer using the metal seed crystal.

[0004] In one embodiment, a method of manufacturing a semiconductor device may include: forming a laminate; forming an opening in the laminate; forming an amorphous silicon layer in the opening; forming a capping layer on the amorphous silicon layer, the capping layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; doping the capping layer with a metal, having a first doping concentration difference between the first portion and the second portion; doping the amorphous silicon layer by diffusing the metal through the capping layer, having a second doping concentration difference between a third portion and a fourth portion, wherein the second doping concentration difference is less than the first doping concentration difference; and forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer using the metal as a seed crystal.

[0005] In one embodiment, a method of manufacturing a semiconductor device may include: forming a preliminary channel layer in a hole in a laminate; forming a capping layer on the preliminary channel layer, wherein the capping layer has a varying thickness; forming a metal seed crystal in the capping layer; diffusing the metal seed crystal through the capping layer into the preliminary channel layer; and forming a channel layer by crystallizing the preliminary channel layer using the metal seed crystal. Attached Figure Description

[0006] Figure 1This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0007] Figures 2A to 2D This is a diagram illustrating a semiconductor device formed using a method for manufacturing a semiconductor device according to one embodiment.

[0008] Figures 3A to 3H This is a view showing a semiconductor device formed using a method for manufacturing a semiconductor device according to one embodiment.

[0009] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0010] Figure 5 This is a configuration diagram of a semiconductor device according to one embodiment.

[0011] Figure 6 This is a configuration diagram of a semiconductor device according to one embodiment. Detailed Implementation

[0012] In all the accompanying figures, the cross shading indicates corresponding or similar areas between the figures, rather than indicating the material associated with those areas.

[0013] Terms such as “vertical,” “above,” “below,” “above,” “upper,” “inner,” “upper part,” “topmost,” “lower part,” “lowest part,” “higher,” “column,” “row,” “height,” and other terms that suggest relative spatial relationships or orientations are used only for purposes of ease of description or reference to the accompanying drawings and are not intended to limit in any other way.

[0014] When one component is marked "connected" to another component, these components can be directly connected or connected via an intermediate component between them. When two components are marked "directly connected," one component is directly connected to the other without any intermediate component between them.

[0015] This disclosure relates to a method for manufacturing a semiconductor device having a stable structure and improved properties.

[0016] By stacking memory cells in three dimensions, the integration density of semiconductor devices can be improved. This allows for the production of semiconductor devices with stable structures and improved reliability.

[0017] Embodiments of this disclosure will be described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0018] Figure 1 This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0019] Reference Figure 1 The semiconductor device includes a gate structure GST and a channel structure CH. The gate structure GST may include conductive layers 11 alternately stacked with insulating layers 12. The conductive layers 11 may be gate lines, such as drain select lines, source select lines, and word lines. For example, at least one lowermost conductive layer 11 may be a source select line, at least one uppermost conductive layer 11 may be a drain select line, and other conductive layers 11 may be word lines. The conductive layers 11 may include conductive materials such as polysilicon, tungsten, or molybdenum. The insulating layer 12 insulates the stacked conductive layers 11 from each other and may include insulating materials such as oxides, nitrides, or air gaps.

[0020] The channel structure CH extends through the gate structure GST. For example, the channel structure CH extends through the gate structure GST in a vertical direction relative to the figures. The channel structure CH includes a channel layer 14 and a channel pad 15, and at least one of a memory layer 13 and an insulating core 16.

[0021] The channel layer 14 may include a semiconductor material such as silicon or germanium and may have a polycrystalline structure. For example, the channel layer 14 may be a polycrystalline silicon layer and may include grains with uniform size. The grain size at the upper end of the channel layer 14 may be substantially the same as the grain size at the lower end of the channel layer 4.

[0022] Insulating core 16 and channel pad 15 are located inside channel layer 14, with channel pad 15 located on insulating core 16. Channel pad 15 is located inside channel layer 14 and contacts the inner wall of channel layer 14. Memory layer 13 surrounds the outer wall of channel layer 14. Memory layer 13 includes at least one of tunneling layer, data storage layer, and barrier layer. Data storage layer may include floating gate, polysilicon, charge trapping material, nitride, variable resistance material, etc.

[0023] In one embodiment, a source-select transistor, a drain-select transistor, or a memory cell is located in the region where the channel structure CH intersects with the conductive layer 11. For example, at least one source-select transistor, multiple memory cells, and at least one drain-select transistor are stacked vertically along the channel structure CH. As a result, the integration density of the semiconductor device can be increased or improved. When the channel layer 14 includes grains with uniform size, the memory cells have uniform characteristics, regardless of the stack height. The channel layer 14 can have a larger grain size, and the cell current can be increased. Therefore, the operating characteristics of the semiconductor device can be improved.

[0024] Figures 2A to 2DThis is a diagram illustrating a semiconductor device formed using a method for manufacturing a semiconductor device according to one embodiment.

[0025] Reference Figure 2A An opening OP can be formed in the laminate ST. The opening OP can extend vertically through the laminate ST. Multiple openings OP can be formed, and, for example, parallel to... Figure 2A In the bottom XY plane, multiple openings OP can have similar shapes, such as circular, elliptical, or polygonal shapes.

[0026] An amorphous layer 21 is formed in the opening OP. For example, the amorphous layer 21 may be an amorphous silicon layer. The amorphous layer 21 is formed along the outer surface of the stack ST and extends to the upper surface of the stack ST.

[0027] A capping layer 22 is formed on the amorphous layer 21. The capping layer 22 is a layer that facilitates the adjustment of the diffusion rate of the dopant and has a thickness that varies according to, for example, vertical height or position. The capping layer 22 includes a lower portion or first part P1 having a first thickness T1 and an upper portion or second part P2 having a second thickness T2. The second thickness T2 is greater than the first thickness T1. The first part P1 is located at a lower height than the second part P2. The first part P1 is located near the lower end of the opening OP, and the second part P2 is located near the upper end of the opening OP. For example, the first thickness T1 could be... to And the second thickness T2 can be to

[0028] The capping layer 22 can be formed using a deposition method. For example, the capping layer 22 can be formed by depositing a capping material using a method with poor step coverage. The capping layer 22 can be formed using deposition methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Due to the step coverage characteristics of the deposition method, the capping material can be deposited at varying thicknesses. The capping material can be deposited thicker at the upper or second portion P2 than at the lower or first portion P1. Therefore, the capping layer 22 can have a drooping structure. The capping layer 22 can include oxides. For example, the capping layer 22 can include silicon oxide. The capping layer 22 can be formed by deposition rather than oxidation methods, and the amorphous layer 21 can be prevented from being lost during the process of forming the capping layer 22.

[0029] Reference Figure 2BThe capping layer 22 is doped with a seed material M. The seed material M serves as a nucleus for crystallizing the amorphous layer 21 and may include a metal such as nickel (Ni). For example, the capping layer 22 is doped with a precursor comprising a metal via a CVD method. As the precursor is supplied, oxygen atoms bond with metal atoms on the surface of the capping layer 22, and any remaining components of the precursor may volatilize. Through this process, the metal is adsorbed onto the surface of the capping layer 22. Due to the bonding of oxygen atoms to metal atoms in the capping layer 22, the adsorption rate of the metal increases compared to directly doping the amorphous layer 21 with metal.

[0030] The doping concentration of the seed material M varies depending on the region of the capping layer 22. The doping concentration in the region near the upper end of the opening OP may be higher than that in the region near the lower end of the opening OP. For example, the doping concentration of the second portion P2 may be higher than that of the first portion P1, and the first portion P1 may have a different doping concentration than the second portion P2. Compared to directly doping the amorphous layer 21 with the seed material M without a capping layer, doping the amorphous layer 21 with the seed material M through the O-Ni bonds of the capping layer 22 increases the doping concentration of both the first portion P1 and the second portion P2.

[0031] Reference Figure 2C Metal seed crystals are formed by annealing the capping layer 22, and the metal seed crystals diffuse through the capping layer 22 into the amorphous layer 21. Through this process, the amorphous layer 21 is doped with metal seed crystals at a uniform concentration. The metal seed crystals may include metal silicides MA and / or metal silicide clusters MB.

[0032] Metal seed crystals are formed by annealing the capping layer 22. For example, the capping layer 22 can be annealed at a temperature of 400°C to 500°C. The seed material M may undergo a phase transformation during annealing. The seed material M reacts with the silicon (Si) of the capping layer 22 to form a metal silicide MA. For example, nickel (Ni) reacts with silicon (Si) to form nickel silicide (NiSi2). The metal silicide MA can aggregate to form a metal silicide cluster MB. The capping layer 22 includes at least one of the seed material M, the metal silicide MA, and the metal silicide cluster MB.

[0033] By annealing the capping layer 22, metal seeds diffuse into the amorphous layer 21. Seed material M that has not undergone a phase transition can diffuse into the amorphous layer 21, and at least one of the seed material M, metal silicide MA, and metal silicide cluster MB can diffuse into the amorphous layer 21. The diffused seed material M can undergo a phase transition to become metal silicide MA, and the diffused metal silicide MA can aggregate to form metal silicide cluster MB. Through this process, the amorphous layer 21 is doped with metal seeds. Some of the seed material M, metal silicide MA, and / or metal silicide cluster MB can remain inside the capping layer 22.

[0034] Metal seed crystals diffuse through capping layer 22. The diffusion rate of the metal seed crystals varies with height when capping layer 22 has different thicknesses at different levels or heights. In the second portion P2, which has a relatively large thickness T2, the path traversed by the metal seed crystals is longer; therefore, compared to the first portion P1, a lower proportion of metal seed crystals ultimately reach the amorphous layer 21 in the second portion P2, and the diffusion rate is relatively low. In the first portion P1, which has a relatively small thickness T1, the path traversed by the metal seed crystals is shorter; therefore, compared to the second portion P2, a higher proportion of metal seed crystals ultimately reach the amorphous layer 21 in the first portion P1, and the diffusion rate is relatively high.

[0035] The amorphous layer 21 includes a third portion P3 near a first portion P1 of the capping layer 22 and a fourth portion P4 near a second portion P2 of the capping layer 22. The third portion P3 is doped through the first portion P1, and the fourth portion P4 is doped through the second portion P2. The doping concentrations of the third portion P3 and the fourth portion P4 are determined based on the difference in diffusion rates between the first portion P1 and the second portion P2.

[0036] By allowing the metal seed crystal to diffuse through the first portion P1 and the second portion P2, which have different thicknesses, the doping concentration difference between the third portion P3 and the fourth portion P4 can be reduced. The capping layer 22, directly doped with the seed material M, can have a larger doping concentration difference at different heights, while the amorphous layer 21, indirectly doped with the metal seed crystal through the capping layer 22, has a smaller doping concentration difference at different heights. The first doping concentration difference between the first portion P1 and the second portion P2 is different from the second doping concentration difference between the third portion P3 and the fourth portion P4. Because the diffusion rate of the second portion P2 is less than the diffusion rate of the first portion P1, the second doping concentration difference is less than the first doping concentration difference. For example, the doping concentration of the second portion P2 is higher than the doping concentration of the first portion P1, and the third portion P3 can have essentially the same doping concentration as the fourth portion P4.

[0037] Reference Figure 2DThe amorphous layer 21 is annealed and crystallized to form a polycrystalline layer 21A. For example, a polycrystalline silicon layer can be formed by annealing the amorphous silicon layer at a temperature of 600°C to 800°C. During the crystallization process, metal silicides MA and / or metal silicide clusters MB are used as crystal nuclei, and the amorphous layer 21 can be crystallized by a metal-induced crystallization (MIC) method.

[0038] According to the MIC method, nickel atoms generate crystalline silicon while moving to the amorphous layer. Nickel atoms have the lowest free energy at the interface between nickel silicide and amorphous silicon, and silicon atoms have the lowest free energy at the interface between nickel silicide and crystalline silicon. Therefore, nickel atoms move towards the amorphous silicon, and silicon atoms move towards the crystalline silicon. The nickel and silicon atoms move in opposite directions, and the metal seed crystal moves and crystallizes. By using a metal seed crystal to crystallize the amorphous layer 21 as described above, grains can be grown to a larger size compared to the example without a metal seed crystal.

[0039] The amorphous layer 21 is crystallized by using a metal seed crystal doped at a uniform concentration. The polycrystalline layer 21A includes grains with larger sizes near the upper end of the opening OP and near the lower end of the opening OP. When the amorphous layer is directly doped with metal without using the capping layer 22, the doping concentration difference may be greater depending on the height. Due to the difference in the doping environment, the doping concentration near the lower end of the opening OP is lower than the doping concentration near the upper end of the opening OP. As a result, the grain size of the polycrystalline layer 21A is non-uniform. The grain size near the lower end of the opening is smaller than the grain size near the upper end of the opening. According to one embodiment of the present disclosure, a metal seed crystal doped at a uniform concentration is used as a nucleus, so the grains grow to a uniform size in the polycrystalline layer 21A.

[0040] although Figure 2D It is not shown in the figure, but the cover layer 22 can be removed and the remaining part of the opening OP can be filled.

[0041] According to one embodiment of the manufacturing method, a capping layer 22 is formed before the amorphous layer 21 crystallizes. The thickness of the capping layer 22 at each height can be determined based on the doping concentration of the metal seed and the diffusion rate of the metal seed. When the thickness of the capping layer 22 is... When the thickness of the capping layer 22 is greater than or equal to the required value, the doping concentration of the metal seed crystals can be increased. When the thickness is greater than or equal to the amorphous layer 21, the metal seed crystal may not be able to reach it. Therefore, the first thickness T1 can be... to The second thickness T2 can be to When the first thickness T1 is to And the second thickness T2 is to In this case, the amorphous layer 21 can be doped with metal seed crystals at a uniform concentration. Therefore, the polycrystalline layer 21A can be formed with a uniform grain size that does not vary based on height. The polycrystalline layer 21A can be used as a layer such as a channel layer, electrode layer, or contact layer.

[0042] Figures 3A to 3H This is a diagram illustrating a semiconductor device formed using a method for manufacturing a semiconductor device according to one embodiment.

[0043] Reference Figure 3A A stack ST is formed comprising a first material layer 31 alternately stacked with a second material layer 32. The first material layer 31 comprises a material having high etch selectivity relative to the etch selectivity of the second material layer 32. The first material layer 31 can be used to form gate lines. The first material layer 31 may comprise a sacrificial material such as a nitride or a conductive material such as polysilicon. The second material layer 32 insulates the stacked gate lines from each other. The second material layer 32 may comprise an insulating material such as an oxide, nitride, or air gap.

[0044] A hole is formed in the laminate ST. For example, a channel hole H is formed in the laminate ST. The channel hole H extends vertically through the laminate ST. Multiple channel holes H are formed, and are, for example, parallel to... Figure 3A In the bottom XY plane, multiple channel holes H can have similar shapes, such as circular, elliptical or polygonal shapes.

[0045] Memory layer 33 may be formed in the via H and on the stack ST. Memory layer 33 is formed along the outer surface of the stack ST and extends to the upper surface of the stack ST. Memory layer 33 includes at least one of a barrier layer, a data storage layer, and a tunneling layer. For example, a barrier layer is formed on the stack ST, a data storage layer is formed on the barrier layer, and a tunneling layer is formed on the data storage layer.

[0046] A preliminary channel layer 34 may be formed on the memory layer 33 or in the channel via H. The preliminary channel layer 34, when formed on the memory layer 33, may also be formed on the inner surface of the channel via H and the upper surface of the stack ST. The preliminary channel layer 34 is used to form a channel layer by utilizing a crystallization process and may include an amorphous silicon layer.

[0047] A capping layer 35 is formed on the preliminary channel layer 34. The capping layer 35 includes a first portion P1 near the lower end of the channel hole H and a second portion P2 near the upper end of the channel hole H. The thickness of the first portion P1 of the capping layer 35 differs from the thickness of the second portion P2. The first portion P1 has a first thickness T1, and the second portion P2 has a second thickness T2 greater than the first thickness T1. T1 can be the average thickness, maximum thickness, or minimum thickness of the first portion P1. T2 can be the average thickness, maximum thickness, or minimum thickness of the second portion P2. The capping layer 35 can be formed using a deposition method with poor step coverage and can have a drooping structure. The capping layer 35 can include oxides. For example, the capping layer 22 can include silicon oxide.

[0048] Reference Figure 3B The capping layer 35 is doped with a seed material M. The seed material M serves as a nucleus for crystallizing the initial channel layer 34 and may include a metal such as nickel (Ni). The doping concentration of the seed material M in the first portion P1 of the capping layer 35 differs from that in the second portion P2. The doping concentration in the second portion P2 is higher than that in the first portion P1.

[0049] Reference Figure 3C Metal seed crystals are formed by annealing the capping layer 35, and the metal seed crystals diffuse into the preliminary channel layer 34 through the capping layer 35. The metal seed crystals include metal silicides MA and / or metal silicide clusters MB. Seed material M can diffuse into the preliminary channel layer 34, and seed material M can react with the preliminary channel layer 34 to form metal seed crystals.

[0050] Metal seed diffusion occurs through capping layer 35. The initial channel layer 34 includes a third portion P3 near a first portion P1 and a fourth portion P4 near a second portion P2. The third portion P3 is doped through the first portion P1, and the fourth portion P4 is doped through the second portion P2. A first doping concentration difference between the first portion P1 and the second portion P2 differs from a second doping concentration difference between the third portion P3 and the fourth portion P4, which is smaller than the first doping concentration difference. The third portion P3 and the fourth portion P4 may have substantially the same doping concentration.

[0051] Reference Figure 3D The preliminary channel layer 34 is annealed and crystallized to form channel layer 34A. During the crystallization process, metal silicides MA and / or metal silicide clusters MB can be used as crystal nuclei, and the preliminary channel layer 34 can be crystallized by the metal-induced crystallization (MIC) method.

[0052] Because the initial channel layer 34 is crystallized using metal seed crystals with uniform doping concentration, the channel layer 34A includes grains with larger sizes near the upper end and lower end of the channel hole H. The channel layer 34A is formed with grains of uniform size grown near the upper and lower ends of the channel layer 34A.

[0053] Reference Figure 3E The capping layer 35 is removed. For example, hydrogen fluoride (HF) can be used to remove the capping layer 35. The capping layer 35, including the metal seed crystals, is selectively removed.

[0054] A buffer layer 36 may be formed on the channel layer 34A. A detachment layer 37 may be formed on the buffer layer 36 or the channel layer 34A. The buffer layer 36 protects the channel layer 34A during the detachment process and comprises a material having high etch selectivity relative to the etch selectivity of the detachment layer 37. The buffer layer 36 comprises a material resistant to chemicals used in removing the detachment layer 37. For example, the detachment layer 37 may comprise nitrides, polysilicon, etc., and the buffer layer 36 may comprise SiCN, SiCO, etc.

[0055] By annealing the absorber layer 37, metal seeds in the channel layer 34A diffuse into the absorber layer 37. An absorber layer 37 comprising amorphous silicon is formed, and the amorphous silicon crystallizes into polycrystalline silicon through the annealing process.

[0056] Reference Figure 3F The absorbent layer 37 is removed. For example, the absorbent layer 37 can be selectively etched by a wet etching method using phosphoric acid. During the removal of the absorbent layer 37, the buffer layer 36 is exposed and protects the channel layer 34A.

[0057] The removal process can be repeated. A removal layer can be formed on the channel layer 34A. The metal seed crystals in the channel layer 34A can be diffused into the removal layer by performing an annealing process, and the removal layer can be removed. By repeating the removal process, the metal seed crystals in the channel layer 34A can be removed, and the concentration of the remaining metal seed crystals in the channel layer 34A can be reduced.

[0058] The buffer layer 36 is removed. For example, the buffer layer 36 can be oxidized using an oxidation process, and the oxidized buffer layer 36 can be removed using hydrogen fluoride (HF).

[0059] Reference Figure 3G An insulating core 38 is formed in the remainder of the channel hole H. For example, an insulating layer can be formed to fill the channel hole H, and the insulating core 38 can be formed by etching back the insulating layer. For example, a dry cleaning process can be used to etch the insulating layer.

[0060] During the etching of the insulating layer, the channel layer 34A is exposed, and the upper end of the channel layer 34A may be damaged. When the channel layer 34A includes metal seed crystals, the metal seed crystals react with the channel layer 34A during the high-temperature removal process. As the size or number of metal silicide clusters increases, agglomeration of the channel layer 34A can occur. During the etching process of the insulating layer, the area where agglomeration occurs may be damaged, and the channel layer 34A and the surrounding layer may also be damaged. According to one embodiment of this disclosure, the metal seed crystal doping concentration at the upper end of the initial channel layer 34 is reduced, and the concentration of the remaining metal seed crystals on the upper end of the channel layer 34A is also reduced. Therefore, agglomeration caused during the removal process can be reduced, and damage to the channel layer 34A can be reduced.

[0061] Reference Figure 3H A channel pad 39 is formed. For example, a conductive layer is formed on the insulating core 38, and the channel pad 39 is formed by planarizing the conductive layer until the surface of the laminate ST is exposed. The channel pad 39 may comprise polysilicon.

[0062] When the first material layer 31 is a sacrificial layer, it is replaced with a third material layer. The third material layer is used to form the gate line and may include a metal such as tungsten or molybdenum. This process forms a gate structure comprising a third material layer alternately stacked with the second material layer 32. When the first material layer 31 is a conductive layer, the process of replacing the first material layer with a third material layer is not required. The first material layer 31 can be used as a gate line, and the stack ST can be used as the gate structure.

[0063] According to one embodiment of the manufacturing method of this disclosure, a metal seed crystal is used as a nucleus to form the channel layer 34A, thus the channel layer 34A has a large grain size. The initial channel layer 34 is doped with metal seed crystals at a uniform concentration according to the thickness difference within the capping layer 35, and the channel layer 34A can be formed with a uniform grain size without size differences at different heights. Therefore, the unit current can be improved. The metal seed crystals in the channel layer 34A are removed by a removal process, and damage to the channel layer 34A due to the metal seed crystals can be reduced.

[0064] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0065] Reference Figure 4The semiconductor device includes a first semiconductor structure S1, a second semiconductor structure S2, and a junction structure BS located between the first semiconductor structure S1 and the second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 can be formed during separate processes and are electrically connected to each other through the junction structure BS. For example, the first semiconductor structure S1 includes peripheral circuitry, and the second semiconductor structure S2 includes a memory cell array.

[0066] The first semiconductor structure S1 includes a substrate 100, a transistor TR, a first interconnect structure IC1, and a first interlayer insulating layer IL1. The active region includes a device isolation layer 104 in the substrate 100, and the transistor TR is located within the active region. The transistor TR includes a gate insulating layer 101, a gate electrode 102, and a junction 103. The transistor TR is included in a peripheral circuit PC.

[0067] The first interconnect structure IC1 is located in the first interlayer insulating layer IL1 and includes vias 105, wiring 106, etc. The first interconnect structure IC1 is electrically connected to the peripheral circuit PC and is also electrically connected to the transistor TR.

[0068] The second semiconductor structure S2 includes a source structure 200, a gate structure GST, an insulating layer 203, a second interconnect structure IC2, and a second interlayer insulating layer IL2. The source structure 200 can be located above or below the gate structure GST. The source structure 200 can include a conductive material such as polysilicon or metal.

[0069] The gate structure GST includes conductive layers 201 alternately stacked with insulating layers 202. Conductive layers 201 can be gate lines, such as source select lines, drain select lines, and word lines. A channel structure CH extends through the gate structure GST and connects to the source structure 200. The channel structure CH includes a channel layer 204, channel pads 209, a memory layer 205, and an insulating core 206. (Referencing a reference...) Figures 2A to 2D and Figures 3A to 3H The described manufacturing method forms the channel structure CH.

[0070] The second interconnect structure IC2 is located in the second interlayer insulating layer IL2 and includes vias 207, wiring 208, etc. The second interconnect structure IC2 is electrically connected to the channel structure CH, the gate structure GST, etc.

[0071] The bonding structure BS includes a first bonding layer BL1, a second bonding layer BL2, a first bonding pad BP1, and a second bonding pad BP2. The first bonding layer BL1 is in contact with the second bonding layer BL2, and the first bonding pad BP1 is in contact with the second bonding pad BP2. The first bonding layer BL1 and the second bonding layer BL2 may each include SiCN, tetraethyl orthosilicate (TEOS), etc. The first bonding pad BP1 is electrically connected to the first interconnect structure IC1, and the second bonding pad BP2 is electrically connected to the second interconnect structure IC2. The memory cell array CA is electrically connected to the peripheral circuit PC through the first bonding pad BP1 and the second bonding pad BP2.

[0072] The structure and manufacturing method according to the described embodiments can be applied to semiconductor devices with various structures. Figure 5 and Figure 6 An example configuration of a semiconductor device to which the implementation method is applicable is shown.

[0073] Figure 5 This is a configuration diagram of a semiconductor device according to one embodiment of the present disclosure.

[0074] Reference Figure 5 A semiconductor device includes a substrate (SUB), peripheral circuitry (PC), and a memory cell array (CA). The peripheral circuitry (PC) and the memory cell array (CA) can be formed on the same substrate.

[0075] The substrate SUB can be made of or comprise a semiconductor material. In one embodiment, the semiconductor material may include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors as described in the periodic table. Group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors may include gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), indium gallium arsenide phosphide (GaInAsP), aluminum arsenide (AlAs), aluminum gallium phosphide (AlGa), indium phosphide (InP), indium antimonide (InSb), or indium gallium arsenide (InGaAs). Group II-VI compound semiconductors may include zinc sulfide (ZnS), zinc oxide (ZnO), or cadmium sulfide (CdS).

[0076] The substrate SUB includes a dielectric layer. The substrate SUB can be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB can include organic materials. In one embodiment, the substrate SUB can include graphene.

[0077] The substrate SUB can be a bulk wafer or an epitaxial layer grown using the Selective Epitaxial Growth (SEG) method. The substrate SUB can be a layer formed using the Metal-Induced Lateral Crystallization (MILC) method and may partially comprise a metal. The substrate SUB can be monocrystalline, polycrystalline, or amorphous. The substrate SUB can include Group II, III, IV, V, or VI impurities. In one embodiment, the substrate SUB can include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0078] The peripheral circuitry PC is disposed between the substrate SUB and the memory cell array CA. The peripheral circuitry PC includes row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. In one embodiment, the peripheral circuitry PC includes NMOS transistors, PMOS transistors, resistors, capacitors, etc. The peripheral circuitry PC may include interconnect structures. The interconnect structures include paths for transmitting operating voltages and may include contact plugs, lines, etc.

[0079] A memory cell array (CA) includes memory cells. In one embodiment, the memory cell array (CA) includes memory strings connected between source lines and bit lines, and each memory string may include stacked memory cells. In another embodiment, the memory cell array (CA) includes memory cells connected between word lines and bit lines. The memory cell array (CA) includes interconnect structures.

[0080] Figure 6 This is a configuration diagram of a semiconductor device according to one embodiment of the present disclosure.

[0081] Reference Figure 6 The semiconductor device includes a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. The peripheral circuitry PC and memory cell array CA can be formed on separate substrates and bonded together. The semiconductor device optionally includes a support base SP-B.

[0082] The substrate SUB is a support used during the process of forming the peripheral circuit PC. The support base SP-B is a support used during the process of forming the memory cell array CA. In one embodiment, after fabricating a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC, the first wafer and the second wafer are electrically connected by a bonding structure BS. After bonding, at least a portion of the support base SP-B of the first wafer is removed. The support base SP-B may be completely removed or may be partially retained on the memory cell array CA.

[0083] The support substrate SP-B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The support substrate SP-B can be a bulk wafer, an epitaxial layer grown using the selective epitaxial growth (SEG) method, or a layer formed using the metal-induced lateral crystallization (MILC) method. The support substrate SP-B can be monocrystalline, polycrystalline, or amorphous. The support substrate SP-B can include group II, III, IV, V, or VI impurities.

[0084] The bonding structure BS connects the memory cell array CA and the peripheral circuit PC. In one embodiment, the memory cell array CA and the peripheral circuit PC are bonded using a wafer-on-wafer bonding method, a chip-on-wafer bonding method, a chip-on-chip bonding method, etc. The bonding structure BS includes bonding pads, bonding layers, bonding interfaces, etc. The bonding pads may include metals such as copper and aluminum, and / or alloys. The bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array CA and the peripheral circuit PC are electrically connected through the bonding structure BS.

[0085] Interconnect structures included in the memory cell array (CA) and / or peripheral circuitry (PC) can be directly connected without the need for bonding pads. In one embodiment, bonding layers included in the memory cell array (CA) and bonding layers included in the peripheral circuitry (PC) can be bonded to form a bonding interface, and interconnect structures included in the memory cell array (CA) and interconnect structures included in the peripheral circuitry (PC) can be directly connected. Contact plugs, lines, etc., formed on different wafers can be electrically connected without separate bonding pads.

[0086] Other configurations can be similarly referenced. Figure 5 The configuration described.

[0087] Semiconductor devices may have a reference therein Figure 5 and Figure 6 The described implementation method combines various elements into a structure, or may have a partially modified structure. (Refer to...) Figure 5 and Figure 6 In the described implementation, the positions of the memory cell array CA and the peripheral circuit PC can be changed. At least one memory cell array CA and / or at least one peripheral circuit PC can be incorporated into the reference. Figure 5 and Figure 6 The described implementation. In one implementation, a portion of the peripheral circuitry PC is disposed in the memory cell array CA.

[0088] The concept has been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions are possible without departing from the scope and concept of this disclosure. The embodiments disclosed in this specification should be considered from an illustrative rather than a restrictive perspective. Therefore, the scope of this disclosure is not limited to the foregoing description. All variations within the meaning and equivalent scope of the claims are included within its scope.

[0089] Cross-references to related applications

[0090] This application claims priority to Korean Patent Application No. 10-2024-0128947, filed on September 24, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a layered structure; Channels are formed in the laminate; A preliminary channel layer is formed in the channel holes; A cover layer is formed on the initial channel layer, the cover layer having a first thickness in a first portion of the cover layer and a second thickness in a second portion of the cover layer that is thicker than the first thickness; Metal seed crystals are formed in the capping layer; The metal seed crystals diffuse through the capping layer into the preliminary channel layer; as well as The channel layer is formed by crystallizing the initial channel layer using the metal seed crystal.

2. The method according to claim 1, wherein, The covering layer has a hanging structure.

3. The method according to claim 1, wherein, The step of forming the metal seed crystals in the capping layer includes the following steps: The surface of the capping layer is doped with a precursor including a metal; Adsorbing the metal onto the surface of the cover layer; and Metal silicides are formed by annealing the capping layer.

4. The method according to claim 3, wherein, The step of forming the metal seed crystals in the capping layer further includes the step of forming metal silicide clusters by agglomerating the metal silicides.

5. The method according to claim 1, wherein, The metal seed crystals include at least one of metal silicides and metal silicide clusters.

6. The method according to claim 1, wherein, When the metal seed is diffused, the diffusion rate of the metal seed at the second portion is less than the diffusion rate of the metal seed at the first portion.

7. The method of claim 1, further comprising the step of removing the covering layer.

8. The method according to claim 1, further comprising the following step: An adsorption layer is formed on the channel layer; The metal seed crystals diffuse into the absorption layer; as well as Remove the absorbent layer.

9. The method according to claim 1, further comprising the following steps: A buffer layer is formed on the channel layer; An absorption layer is formed on the buffer layer; The metal seed crystals diffuse into the absorption layer; as well as Remove the absorbent layer.

10. The method according to claim 1, further comprising the following step: An insulating core is formed within the channel layer; and A channel pad is formed on the insulating core.

11. The method according to claim 10, wherein, The steps for forming the insulating core include the following: An insulating layer is formed to fill the space within the channel layer; and The insulating core is formed by etching the insulating layer to expose the channel layer using a dry cleaning process.

12. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a layered structure; An opening is formed in the laminate; An amorphous silicon layer is formed in the opening; A capping layer is formed on the amorphous silicon layer, the capping layer comprising a first portion having a first thickness and a second portion having a second thickness that is thicker than the first thickness; The capping layer is doped with a metal, and a first doping concentration difference exists between the first portion and the second portion; The amorphous silicon layer is doped by diffusing the metal through the capping layer, and a second doping concentration difference exists between the third and fourth portions of the amorphous silicon layer, wherein the second doping concentration difference is smaller than the first doping concentration difference. as well as A polycrystalline silicon layer is formed by using the metal as a seed crystal to crystallize the amorphous silicon layer.

13. The method according to claim 12, wherein, The third portion is doped through the first portion, and the fourth portion is doped through the second portion.

14. The method according to claim 12, wherein, When the amorphous silicon layer is doped, the metal diffusion rate of the second portion is less than that of the first portion.

15. The method according to claim 12, wherein, The metal doping concentration of the second part is higher than that of the first part; and The metal doping concentration in the third part is basically the same as that in the fourth part.

16. The method according to claim 12, further comprising the step of: At least one of a metal silicide and a metal silicide cluster is formed by annealing the capping layer doped with the metal.

17. The method of claim 16, wherein, in forming the polycrystalline silicon layer, one of the metal silicide and the metal silicide cluster is used as a metal seed crystal.

18. The method of claim 12, further comprising the step of removing the covering layer.

19. The method of claim 12, further comprising the step of: An absorption layer is formed on the polycrystalline silicon layer; The metal diffuses from the polycrystalline silicon layer to the absorption layer; as well as Remove the absorbent layer.

20. A method of manufacturing an electronic device, the method comprising the following steps: A preliminary channel layer is formed in the pores of the laminate; A capping layer is formed on the initial channel layer, wherein the capping layer has a varying thickness; Metal seed crystals are formed in the capping layer; The metal seed crystals diffuse through the capping layer into the initial channel layer; and The channel layer is formed by crystallizing the initial channel layer using the metal seed crystal.

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