High electron mobility transistor and manufacturing method
By using a P-type gallium nitride layer and an N-type gallium nitride layer to form a PN junction in a high electron mobility transistor, and setting a charge release layer at the edge of the P-type gallium nitride layer, the problems of Schottky junction degradation and the inability to quickly release trapped charges are solved, thereby improving the reliability and stability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-16
- Publication Date
- 2026-03-24
AI Technical Summary
In existing high electron mobility transistors (HEMTs), the Schottky junction of the gate structure is prone to degradation, leading to reliability issues, and the trapped charge cannot be released quickly, affecting device stability.
A PN junction is formed by P-type gallium nitride (GaN) layer and N-type GaN layer to replace the Schottky junction. A charge release layer is set at the edge of the P-type GaN layer. An ohmic contact structure is used to realize a path for rapid release of trapped charges. A charge release layer is also set in the P-type GaN layer to form a rapid release path.
This improves the reliability of the gate structure, reduces the impact of trapped charge on the threshold voltage, and enhances the stability of the transistor.
Smart Images
Figure CN121728796A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and in particular to a high electron mobility transistor and a method for fabricating it. Background Technology
[0002] High electron mobility transistors (HEMTs) have attracted widespread attention due to their excellent performance in high-frequency, high-power applications. In enhancement-mode GaN-based HEMT devices, the gate typically includes a P-type gallium nitride (P-GaN) layer to achieve the normally off state of the channel.
[0003] In existing technologies, HEMT gates are typically made of metals such as TiN or Ni, directly connected to the P-GaN layer to form a Schottky junction. Simultaneously, a PN junction is formed between the P-GaN layer and the underlying layer (such as an AlGaN barrier layer), making the gate structure equivalent to two diodes connected in reverse series. When a high positive voltage is applied to the gate, the P-GaN region is completely depleted, and the diode corresponding to the PN junction is in a forward-biased state, experiencing a constant voltage drop. With further increases in gate voltage, since the diode's voltage drop remains constant, most of the increased voltage is applied to the Schottky junction. A high electric field exists at the Schottky interface, and under long-term high gate voltage stress, the Schottky junction degrades, leading to gate reliability issues.
[0004] In addition, the gate is equivalent to two diodes connected in reverse series. When a gate stress voltage or a drain stress voltage is applied, a large number of trapped charges will exist in the P-GaN layer of the gate. The trapped charges will attract or deplete the electrons in the conductive channel. Due to the influence of the reverse series diode structure, the trapped charges cannot be released quickly, which leads to the problem of threshold voltage drift and thus affects the stability of the transistor device.
[0005] Therefore, how to avoid the impact of Schottky junction degradation on gate reliability and reduce the impact of trap charge on device stability are urgent problems to be solved. Summary of the Invention
[0006] This application provides a high electron mobility transistor and a method for fabricating it, in order to solve the defects in the prior art transistors where the formation of a Schottky junction in the gate structure affects gate reliability and the equivalent of two reverse series diodes causes the trapped charge to not be released quickly.
[0007] This application provides a high electron mobility transistor, comprising: Substrate structure, used to form conductive channels; A source and a drain, wherein the source and the drain are disposed on the substrate structure; A p-type gallium nitride layer is disposed on the substrate structure. The p-type gallium nitride layer includes an edge portion and an intermediate portion located between the source and the drain. The p-type gallium nitride layer is used to consume the charge carriers of the conductive channel so that the conductive channel is normally closed. An N-type gallium nitride layer is disposed on the P-type gallium nitride layer. The N-type gallium nitride layer has a first opening located at the edge portion, and the first opening is used to expose the edge portion. A charge release layer is disposed on the P-type gallium nitride layer and located within the first opening; In this configuration, a PN junction is formed between the P-type gallium nitride layer and the N-type gallium nitride layer, and the gate leakage current of the charge release layer is greater than the gate leakage current of the N-type gallium nitride layer.
[0008] According to a high electron mobility transistor provided in this application, the P-type gallium nitride layer is provided with an etched recess, the etched recess is located at the edge portion and the projection of the first opening covers the etched recess, and the charge release layer fills the etched recess.
[0009] According to a high electron mobility transistor provided in this application, the cross-section of the over-etched recess is inverted trapezoidal.
[0010] According to the high electron mobility transistor provided in this application, the thickness of the P-type gallium nitride layer is in the range of 50 nanometers to 100 nanometers, and / or the thickness of the N-type gallium nitride layer is in the range of 10 nanometers to 40 nanometers, and / or the depth of the over-etched recess is within 5 nanometers.
[0011] According to the high electron mobility transistor provided in this application, a gate metal layer is further disposed on the N-type gallium nitride layer, an ohmic contact is formed between the gate metal layer and the N-type gallium nitride layer, and the gate metal layer is provided with a second opening corresponding to the first opening, the second opening being used to expose the edge portion.
[0012] According to a high electron mobility transistor provided in this application, the charge release layer is an ohmic contact layer, and an ohmic contact is formed between the ohmic contact layer and the P-type gallium nitride layer.
[0013] According to the high electron mobility transistor provided in this application, there are two sources, one of which is located on one side of the drain and the other source is located on the other side of the drain. The P-type gallium nitride layer includes two intermediate portions. The intermediate portions are disposed between the drain and the two sources. The two intermediate portions are connected to the edge portion. The N-type gallium nitride layer is disposed on the two intermediate portions.
[0014] According to a high electron mobility transistor provided in this application, the P-type gallium nitride layer includes two edge portions, one of which is connected to one side of the two middle portions and the other edge portion is connected to the other side of the two middle portions.
[0015] This application also provides a high electron mobility transistor, wherein the substrate structure includes a substrate layer, a gallium nitride buffer layer and an aluminum gallium nitride layer stacked sequentially from bottom to top, and a two-dimensional electron gas is formed between the gallium nitride buffer layer and the aluminum gallium nitride layer as the conductive channel.
[0016] This application also provides a method for fabricating a high electron mobility transistor, including: Construct the base structure; Define a P-type gallium nitride layer pattern on the substrate structure to fabricate the P-type gallium nitride layer; Define an N-type gallium nitride layer pattern on the P-type gallium nitride layer to fabricate the N-type gallium nitride layer; Define a gate metal layer pattern on the N-type gallium nitride layer and fabricate the gate metal layer; Through the first etching process, a second opening is formed on the gate metal layer, a first opening is formed on the N-type gallium nitride layer, and an over-etched recess is formed at the edge of the P-type gallium nitride layer. A first passivation layer is fabricated to cover the substrate structure, the P-type gallium nitride layer, and the N-type gallium nitride layer; A second etching process is used to form source and drain openings that expose the substrate structure, with the middle portion of the P-type gallium nitride layer located between the source and drain openings; A source electrode is formed at the source opening and a drain electrode is formed at the drain opening by a first metal deposition process. A second passivation layer is fabricated to cover the first passivation layer, the source electrode, and the drain electrode; Through the third etching process, a source via exposing the source electrode, a drain via exposing the drain electrode, an edge via exposing the edge portion of the P-type gallium nitride layer, and a gate via exposing the gate metal layer are formed. A second metal deposition process is used to form a source lead-out layer in the source via, a drain lead-out layer in the drain via, a charge release layer in the edge via, and a gate lead-out layer in the gate via.
[0017] This application provides a high electron mobility transistor and its fabrication method, which has at least the following advantages: The middle portion of the P-type gallium nitride layer is located between the source and drain, and the substrate structure forms a conductive channel. The P-type gallium nitride layer keeps the conductive channel between the source and drain normally closed, thus achieving the function of an enhancement-mode device. An N-type gallium nitride layer is disposed on the P-type gallium nitride layer, and the N-type gallium nitride layer has a first opening at the edge of the P-type gallium nitride layer to expose the underlying P-type gallium nitride layer, allowing the charge release layer to be directly connected to the P-type gallium nitride layer. With this structure, an N-type gallium nitride layer is disposed on the P-type gallium nitride layer, forming a PN junction between the two to replace the Schottky junction. This fundamentally avoids the problem of reduced gate reliability caused by Schottky junction degradation, which is beneficial to improving the reliability of the gate structure. At the same time, the N-type gallium nitride layer has a first opening at the corresponding position on the edge, allowing the charge release layer to be directly connected to the P-type gallium nitride layer. Since the gate leakage current of the charge release layer is greater than that of the N-type gallium nitride layer, the charge release layer can provide a faster path for releasing trapped charges compared to the N-type gallium nitride layer. This allows the trapped charges in the P-type gallium nitride layer to be released quickly through the charge release layer, reducing the impact of trapped charges on the threshold voltage and improving the overall stability of the transistor. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a top view schematic diagram of one embodiment of a high electron mobility transistor provided by the present invention.
[0020] Figure 2 This invention provides a high electron mobility transistor. Figure 1 A schematic diagram of the cross-section at point A in the embodiment.
[0021] Figure 3 This invention provides a high electron mobility transistor. Figure 1 A schematic diagram of the cross-section at point B in the embodiment.
[0022] Figure 4 This invention provides a method for fabricating a high electron mobility transistor and... Figure 1 The process diagrams corresponding to the embodiments (the left side is the process diagram of section A, and the right side is the process diagram of section B).
[0023] Figure label: 100: Substrate structure; 110: Substrate layer; 120: Gallium nitride buffer layer; 130: AlGaN layer; 200: Source; 300: Drain; 400: P-type gallium nitride layer; 410: Edge portion; 420: Middle portion; 430: Over-etched recess; 500: N-type gallium nitride layer; 510: First opening; 600: Charge release layer; 700: Gate metal layer; 710: Second opening; 800: Edge lead-out layer; 900: Passivation layer; 910: Source lead-out layer; 920: Drain lead-out layer; 930: Gate lead-out layer. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0025] The following is combined Figures 1 to 4 This application describes a high electron mobility transistor, comprising: Substrate structure 100 is used to form conductive channels; A source electrode 200 and a drain electrode 300 are disposed on the substrate structure 100. A p-type gallium nitride layer 400 is disposed on the substrate structure 100. The p-type gallium nitride layer 400 includes an edge portion 410 and a middle portion 420 located between the source electrode 200 and the drain electrode 300. The p-type gallium nitride layer 400 is used to consume the charge carriers of the conductive channel so that the conductive channel is normally closed. An N-type gallium nitride layer 500 is disposed on the P-type gallium nitride layer 400. The N-type gallium nitride layer 500 is provided with a first opening 510, which is located on the edge portion 410 and is used to expose the edge portion 410. A charge release layer 600 is disposed on the P-type gallium nitride layer 400 and located within the first opening 510; A PN junction is formed between the P-type gallium nitride layer 400 and the N-type gallium nitride layer 500, and the gate leakage current of the charge release layer 600 is greater than the gate leakage current of the N-type gallium nitride layer 500.
[0026] The middle portion 420 of the P-type gallium nitride layer 400 is located between the source 200 and the drain 300. The substrate structure 100 forms a conductive channel. The P-type gallium nitride layer 400 keeps the conductive channel between the source 200 and the drain 300 normally closed, realizing the function of an enhancement-mode device. An N-type gallium nitride layer 500 is disposed on the P-type gallium nitride layer 400, and the N-type gallium nitride layer 500 has a first opening 510 at the edge portion 410 of the P-type gallium nitride layer 400 to expose the underlying P-type gallium nitride layer 400, so that the charge release layer 600 can be directly connected to the P-type gallium nitride layer 400.
[0027] With this structure, an N-type gallium nitride layer 500 is disposed on the P-type gallium nitride layer 400, forming a PN junction between the two to replace the Schottky junction. This fundamentally avoids the problem of reduced gate reliability caused by Schottky junction degradation, which is beneficial to improving the reliability of the gate structure. At the same time, the N-type gallium nitride layer 500 has a first opening 510 at the position corresponding to the edge portion 410, allowing the charge release layer 600 to be directly connected to the P-type gallium nitride layer 400. Since the gate leakage current of the charge release layer 600 is greater than that of the N-type gallium nitride layer 500, the charge release layer 600 can provide a faster path for releasing trapped charges compared to the N-type gallium nitride layer 500. This allows the trapped charges in the P-type gallium nitride layer 400 to be released quickly through the charge release layer 600, reducing the impact of trapped charges on the threshold voltage and improving the overall stability of the transistor.
[0028] It is important to emphasize that the P-type gallium nitride layer 400, in addition to the middle portion 420 between the source 200 and the drain 300, also includes an edge portion 410 not located between the source 200 and the drain 300. The edge portion 410 is used to connect with the charge release layer 600. That is, the charge release layer 600 is not located between the source 200 and the drain 300, which helps to reduce the impact of the charge release layer 600 on gate performance. While ensuring the gate structure's control over the conductive path between the source 200 and the drain 300, the connection between the charge release layer 600 and the P-type gallium nitride layer 400 at the edge portion 410 provides a path for rapid release of trapped charges, improving the threshold voltage drift problem.
[0029] In some embodiments of this application, an ohmic contact or an incomplete ohmic contact may be formed between the charge release layer 600 and the P-type gallium nitride layer 400, so that the gate leakage current of the charge release layer 600 is greater than the gate leakage current of the N-type gallium nitride layer 500, thereby achieving the effect of providing a faster path for releasing trapped charges.
[0030] In some embodiments of this application, the charge release layer 600 may be a single-layer structure, such as being formed of a material like titanium (Ti). In some embodiments, the charge release layer 600 may also be a multilayer structure, such as being formed of a multilayer of titanium (Ti), titanium nitride (TiN), and tungsten (W). In some embodiments, the charge release layer 600 may also function as a lead-out layer, i.e., fulfilling the function of a metal lead-out layer; in some embodiments, it may also be formed of a through-hole metal.
[0031] It is understandable that P-type gallium nitride layer 400 refers to a P-type doped gallium nitride layer, and N-type gallium nitride layer 500 refers to an N-type doped gallium nitride layer.
[0032] refer to Figure 2 and Figure 4 In some embodiments of a high electron mobility transistor in this application, the P-type gallium nitride layer 400 is provided with an etched recess 430, the etched recess 430 is located on the edge portion 410 and the projection of the first opening portion 510 covers the etched recess 430, and the charge release layer 600 fills the etched recess 430.
[0033] An etched recess 430 is provided at the edge 410 of the P-type gallium nitride layer 400, and the charge release layer 600 fills the etched recess 430. This structure increases the contact area and depth between the charge release layer 600 and the P-type gallium nitride layer 400, reducing the resistance between them and allowing for more efficient extraction and release of trapped charges, further optimizing charge release efficiency and stability. Simultaneously, the structure of the etched recess 430 ensures that etching necessarily penetrates the N-type gallium nitride layer 500, making the formation of the first opening 510 more stable and reliable, guaranteeing the connection between the charge release layer 600 and the P-type gallium nitride layer 400, thus ensuring the formation of a rapid release path for the trapped charges.
[0034] refer to Figure 2 and Figure 4 In some embodiments of a high electron mobility transistor of this application, the cross-section of the over-etched recess 430 is inverted trapezoidal.
[0035] By making the cross-section of the over-etched recess 430 an inverted trapezoid, with the opening width of the inverted trapezoid being greater than the bottom width, it facilitates the smooth filling of the charge release layer 600 material during filling, avoiding the formation of voids on the sidewalls of the over-etched recess 430. This helps ensure the continuity of the ohmic contact between the charge release layer 600 and the P-type gallium nitride layer 400. Simultaneously, the inverted trapezoidal cross-section of the over-etched recess 430 prevents the formation of sharp angles, thus avoiding excessive charge concentration and stress concentration, which helps improve the reliability of the gate.
[0036] It should be noted that the cross-sectional shape of the over-etched recess 430 is not limited to an inverted trapezoid. In some embodiments of this application, the cross-section of the over-etched recess 430 may also be in the form of an arc or other shapes.
[0037] In some embodiments of a high electron mobility transistor of this application, the thickness of the P-type gallium nitride layer 400 is in the range of 50 nanometers to 100 nanometers, and / or the thickness of the N-type gallium nitride layer 500 is in the range of 10 nanometers to 40 nanometers, and / or the depth of the over-etched recess 430 is within 5 nanometers.
[0038] The thickness of the P-type gallium nitride layer 400 is in the range of 50nm to 100nm, which is beneficial for providing sufficient thickness to consume the charge carriers in the conductive channel and ensure the reliability of the depletion channel. The thickness of the N-type gallium nitride layer 500 is in the range of 10nm to 40nm, which ensures the formation of an effective PN junction while avoiding excessive resistance due to excessive thickness. The depth of the etched recess 430 is within 5nm, which ensures that the etching penetrates the N-type gallium nitride layer 500 to form the first opening 510 and to allow effective contact between the charge release layer 600 and the P-type gallium nitride layer 400, while avoiding excessive etching depth that would affect the performance of the P-type gallium nitride layer 400 and ensuring the overall reliability of the gate structure.
[0039] Understandably, the specific values of the thickness of the P-type gallium nitride layer 400, the thickness of the N-type gallium nitride layer 500, and the depth of the over-etched recess 430 can be adjusted according to the actual application, such as material quality, specific device design voltage, and process capability.
[0040] refer to Figures 1 to 4 In some embodiments of a high electron mobility transistor of this application, a gate metal layer 700 is further provided on the N-type gallium nitride layer 500, an ohmic contact is formed between the gate metal layer 700 and the N-type gallium nitride layer 500, and the gate metal layer 700 is provided with a second opening 710 corresponding to the first opening 510, the second opening 710 being used to expose the edge portion 410.
[0041] By providing a gate metal layer 700 on the N-type gallium nitride layer 500, operations such as lead-out and connection are facilitated. An ohmic contact is formed between the gate metal layer 700 and the N-type gallium nitride layer 500, and the gate metal layer 700 has a second opening 710 that cooperates with the first opening 510 to expose the edge portion 410 of the P-type gallium nitride layer 400. With this structure, the gate metal layer 700, based on a low-contact-resistance ohmic contact, provides the basis for electrical connection and signal input for the gate structure. The second opening 710 and the first opening 510 of the N-type gallium nitride layer 500 together determine the location and size of the region where the P-type gallium nitride layer 400 releases trapped charges at the edge portion 410.
[0042] It is important to emphasize that, due to the different energy level structures of the N-type gallium nitride (GaN) layer 500 and the P-type GaN layer 400, the N-type GaN layer 500 readily forms an ohmic contact with the metal, while the P-type GaN layer 400 readily forms a Schottky contact with the metal. By incorporating the N-type GaN layer 500, a PN junction is formed between the N-type GaN layer 500 and the P-type GaN layer 400, avoiding the formation of a Schottky junction. This fundamentally prevents the degradation of the Schottky junction and the resulting decrease in reliability. Furthermore, the ohmic contact formed between the N-type GaN layer 500 and the gate metal layer 700, compared to a Schottky contact, reduces contact resistance and helps reduce losses. It should be further noted that while the P-type GaN layer 400 readily forms a Schottky contact with the metal, this does not mean it can only form a Schottky contact; under suitable material and process conditions, an ohmic contact can also be formed.
[0043] In some embodiments of this application, the gate metal layer 700 may be a titanium nitride (TiN) layer, a titanium (Ti) layer, or other implementations.
[0044] In some embodiments of a high electron mobility transistor of this application, the charge release layer 600 is an ohmic contact layer, and an ohmic contact is formed between the ohmic contact layer and the p-type gallium nitride layer 400.
[0045] The charge release layer 600 is an ohmic contact layer that forms an ohmic contact with the P-type gallium nitride layer 400. An ohmic contact means that the current-voltage relationship is linear and there is no rectification effect. That is, the equivalent structure of the ohmic contact will not form a diode, so that whether the charge accumulated in the P-type gallium nitride layer 400 is positive or negative, it can be quickly released through the ohmic contact layer, thus providing a direct and efficient charge release channel.
[0046] It is understandable that the P-type gallium nitride layer 400, the N-type gallium nitride layer 500, and the ohmic contact layer form a hybrid gate structure. By applying a voltage to the N-type gallium nitride layer 500, the on / off state of the conductive channel between the source 200 and the drain 300 can be controlled. The trapped charge in the P-type gallium nitride layer 400 can be quickly released through the ohmic contact layer, avoiding accumulation that could lead to threshold voltage drift.
[0047] refer to Figure 1 and Figure 3 In some embodiments of a high electron mobility transistor of this application, there are two sources 200, one of which is located on one side of the drain 300 and the other source 200 is located on the other side of the drain 300. The P-type gallium nitride layer 400 includes two intermediate portions 420. The intermediate portion 420 is disposed between the drain 300 and the two sources 200. Both intermediate portions 420 are connected to the edge portion 410. The N-type gallium nitride layer 500 is disposed on both intermediate portions 420.
[0048] By providing source electrodes 200 on both sides of the drain 300, and a middle portion 420 of a P-type gallium nitride layer 400 between each of the two source electrodes 200 and the drain 300, with an N-type gallium nitride layer 500 on each middle portion 420, a conductive channel can be formed on both sides of the drain 300 by applying a voltage to the N-type gallium nitride layer 500, thus forming a dual-channel structure. This is beneficial for increasing the maximum current and maximum power consumption, thereby improving the transistor's performance. Furthermore, both middle portions 420 are connected to the edge portion 410, sharing a path for trap charge release, resulting in a compact and efficient structure.
[0049] In some embodiments of this application, multiple drains 300 and sources 200 may be provided, with the drains 300 and sources 200 arranged alternately, and a middle portion 420 of a P-type gallium nitride layer 400 is provided between each group of drains 300 and sources 200, which can further increase the maximum current and maximum power consumption.
[0050] refer to Figure 1 In some embodiments of a high electron mobility transistor of this application, the P-type gallium nitride layer 400 includes two edge portions 410, one of which is connected to one side of the two intermediate portions 420 and the other edge portion 410 is connected to the other side of the two intermediate portions 420.
[0051] The P-type gallium nitride layer 400 includes two edge portions 410, which are located at both ends of two intermediate portions 420. That is, the two ends of the intermediate portions 420 are respectively provided with edge portions 410, and the two ends of the intermediate portions 420 are respectively connected to the edge portions 410. This allows the trapped charges in the intermediate portions 420 to move towards the nearest edge portion 410 for release, which helps to shorten the moving distance of the P-type gallium nitride layer 400 to release the trapped charges, improve the efficiency of trapped charge release, further reduce the influence of trapped charges, and more effectively suppress dynamic threshold voltage drift.
[0052] refer to Figure 2 In some embodiments of a high electron mobility transistor of this application, the portion of the N-type gallium nitride layer 500 located on the edge portion 410 surrounds the charge release layer 600.
[0053] The N-type gallium nitride layer 500 simultaneously covers the middle portion 420 and the edge portion 410 of the P-type gallium nitride layer 400. The portion of the N-type gallium nitride layer 500 located on the edge portion 410 surrounds the charge release layer 600. By modulating the electric field using the N-type gallium nitride layer 500, the electric field peak at the edge is uniformly dispersed, avoiding local electric field concentration that could lead to breakdown. This further reduces the impact of the charge release layer 600 on the gate leakage current performance, thereby improving the reliability and safety of the gate.
[0054] refer to Figure 2 In some embodiments of a high electron mobility transistor of this application, the portion of the N-type gallium nitride layer 500 located on the edge portion 410 is connected to the charge release layer 600.
[0055] The portion of the N-type gallium nitride layer 500 located on the edge portion 410 surrounds the charge release layer 600 and is in side contact with each other, so that the N-type gallium nitride layer 500 and the charge release layer 600 have the same potential, which helps to make the electric field of the overall gate more uniform.
[0056] In some embodiments of this application, in addition to the N-type gallium nitride layer 500 being directly connected to the charge release layer 600, the N-type gallium nitride layer 500 and the charge release layer 600 can also be interconnected when led out, so that the N-type gallium nitride layer 500 and the charge release layer 600 are at the same potential.
[0057] refer to Figure 1 and Figure 2 In some embodiments of a high electron mobility transistor of this application, an edge lead-out layer 800 is further included, which is disposed on the charge release layer 600, and the resistivity of the edge lead-out layer 800 is less than the resistivity of the charge release layer 600.
[0058] When the charge release layer 600 is an ohmic contact layer, the range of materials that can be selected for the ohmic contact layer is limited in order to form an ohmic contact between the ohmic contact layer and the P-type gallium nitride layer 400. For example, materials such as nickel and titanium can be selected to form the ohmic contact layer. However, materials such as nickel and titanium have high resistivity. By setting an edge lead-out layer 800 on the charge release layer 600, i.e. the ohmic contact layer, the resistivity of the edge lead-out layer 800 is less than that of the ohmic contact layer, thereby reducing the overall resistance value, which is beneficial to reducing heat generation and power consumption.
[0059] In some embodiments of this application, only an ohmic contact layer may be provided, that is, the ohmic contact layer is directly led out for connection.
[0060] refer to Figures 1 to 4 In some embodiments of a high electron mobility transistor according to this application, a passivation layer 900, a source lead-out layer 910, a drain lead-out layer 920, and a gate lead-out layer 930 are further included. The passivation layer 900 covers the substrate structure 100, the P-type gallium nitride layer 400, the N-type gallium nitride layer 500, the source 200, and the drain 300. The passivation layer 900 is provided with a source via corresponding to the source 200, a drain via corresponding to the drain 300, a gate via corresponding to the intermediate portion 420, and a gate via corresponding to the intermediate portion 420. The edge portion 410 has an edge via, the source lead-out layer 910 is disposed in the source via and is connected to the source 200, the drain lead-out layer 920 is disposed in the drain via and is connected to the drain 300, the gate lead-out layer 930 is disposed in the gate via and is connected to the N-type gallium nitride layer 500, and the edge lead-out layer 800 is disposed in the edge via and is connected to the charge release layer 600.
[0061] By providing a passivation layer 900, which includes source vias, drain vias, gate vias, and edge vias corresponding to the source 200, drain 300, N-type gallium nitride layer 500, and charge release layer 600, respectively, a source lead-out layer 910 is provided in the source via to lead out the source 200, a drain lead-out layer 920 is provided in the drain via to lead out the drain 300, a gate lead-out layer 930 is provided in the gate via to lead out the N-type gallium nitride layer 500, and an edge lead-out layer 800 is provided in the edge via to lead out the charge release layer 600, the passivation layer 900 covers and protects the substrate structure 100, the P-type gallium nitride layer 400, the N-type nitride layer, the source 200, and the drain 300. This prevents oxidation and corrosion of the structure covered by the passivation layer 900, improving the reliability and safety of the structure.
[0062] refer to Figures 1 to 4In some embodiments of a high electron mobility transistor in this application, the substrate structure 100 includes a substrate layer 110, a gallium nitride buffer layer 120, and an aluminum gallium nitride layer 130 stacked sequentially from bottom to top, and a two-dimensional electron gas is formed between the gallium nitride buffer layer 120 and the aluminum gallium nitride layer 130 as the conductive channel.
[0063] A gallium nitride (GaN) buffer layer 120 is epitaxially grown on the substrate layer 110, and an aluminum gallium nitride (AlGaN) layer 130 is epitaxially grown on the gallium nitride buffer layer 120. The gallium nitride buffer layer 120 and the aluminum gallium nitride layer 130 form a heterojunction, and a two-dimensional electron gas (2DEG) is formed at the interface between the two as a conductive channel.
[0064] The middle portion 420 of the P-type gallium nitride layer 400 is located between the source 200 and the drain 300. The substrate structure 100 forms a conductive channel. The P-type gallium nitride layer 400 keeps the conductive channel between the source 200 and the drain 300 normally closed, realizing the function of enhancement-mode HEMT. An N-type gallium nitride layer 500 is disposed on the P-type gallium nitride layer 400, and the N-type gallium nitride layer 500 has a first opening 510 at the edge portion 410 of the P-type gallium nitride layer 400 to expose the underlying P-type gallium nitride layer 400, so that the charge release layer 600 can be directly connected to the P-type gallium nitride layer 400.
[0065] Therefore, in a high electron mobility transistor (HEMT), an N-type gallium nitride (GaN) layer 500 is disposed on a P-type GaN layer 400, forming a PN junction to replace the Schottky junction. This fundamentally avoids the problem of reduced gate reliability caused by Schottky junction degradation, thus improving the reliability of the gate structure. Simultaneously, the N-type GaN layer 500 has a first opening 510 at the position corresponding to the edge 410, allowing the charge release layer 600 to be directly connected to the P-type GaN layer 400. Since the gate leakage current of the charge release layer 600 is greater than that of the N-type GaN layer 500, the charge release layer 600 provides a faster path for releasing trapped charges compared to the N-type GaN layer 500. This allows the trapped charges in the P-type GaN layer 400 to be quickly released through the charge release layer 600, reducing the impact of trapped charges on the threshold voltage and improving the overall stability of the HEMT.
[0066] In some embodiments of a high electron mobility transistor of this application, the gate metal layer 700 is a titanium nitride (TiN) layer, the charge release layer 600 is an ohmic contact layer, and the ohmic contact layer is a titanium (Ti) layer.
[0067] The following describes a method for fabricating a high electron mobility transistor provided in this application. The method described below can be referred to in correspondence with the method described above.
[0068] refer to Figure 4 This application also provides a method for fabricating a high electron mobility transistor, comprising: Create a 100mm base structure; A P-type gallium nitride layer 400 pattern is defined on the substrate structure 100, and the P-type gallium nitride layer 400 is fabricated. Define an N-type gallium nitride layer 500 pattern on the P-type gallium nitride layer 400, and fabricate the N-type gallium nitride layer 500; Define a gate metal layer 700 pattern on the N-type gallium nitride layer 500, and fabricate the gate metal layer 700. Through the first etching process, a second opening 710 is formed on the gate metal layer 700, a first opening 510 is formed on the N-type gallium nitride layer 500, and an over-etched recess 430 is formed on the edge portion 410 of the P-type gallium nitride layer 400. A first passivation layer is fabricated to cover the substrate structure 100, the P-type gallium nitride layer 400, and the N-type gallium nitride layer 500; The second etching process forms a source 200 opening and a drain 300 opening that expose the substrate structure 100, with the middle portion 420 of the P-type gallium nitride layer 400 located between the source 200 opening and the drain 300 opening. A source electrode 200 is formed by opening the source electrode 200 through a first metal deposition process, and a drain electrode 300 is formed by opening the drain electrode 300. A second passivation layer is fabricated to cover the first passivation layer, the source electrode 200, and the drain electrode 300; Through the third etching process, a source via exposing the source 200, a drain via exposing the drain 300, an edge via exposing the edge portion 410 of the P-type gallium nitride layer 400, and a gate via exposing the gate metal layer 700 are formed. A second metal deposition process is used to form a source lead-out layer 910 in the source via, a drain lead-out layer 920 in the drain via, a charge release layer 600 in the edge via, and a gate lead-out layer 930 in the gate via.
[0069] After fabricating the substrate structure 100, the P-type gallium nitride layer 400, the N-type gallium nitride layer 500, and the gate metal layer 700, a first etching process is performed to form a second opening 710 at the corresponding position of the edge portion 410 in the gate metal layer 700 and a first opening 510 at the corresponding position of the edge portion 410 in the N-type gallium nitride layer 500. This allows the subsequent charge release layer 600 to directly contact the P-type gallium nitride layer 400, providing a path for rapid release of trapped charges. After fabricating the first passivation layer, a second etching process is performed to form the source 200 opening and the drain 300 opening, exposing the substrate structure 100. The source 200 and drain 300 are fabricated by metal deposition, ensuring that both the source 200 and drain 300 are in direct contact with the substrate structure 100, forming an ohmic contact. A second passivation layer is then fabricated to cover the first passivation layer, the source 200, and the drain 300 for protection. Through the third etching process, a source via exposing the source 200, a drain via exposing the drain 300, an edge via exposing the edge portion 410 of the P-type gallium nitride layer 400, and a gate via exposing the gate metal layer 700 are formed. Through metal deposition, a source lead-out layer 910 is formed in the source via, a drain lead-out layer 920 is formed in the drain via, a gate lead-out layer 930 is formed in the gate via, and a charge release layer 600 is formed in the edge via.
[0070] It is understood that the first passivation layer and the second passivation layer formed the aforementioned passivation layer 900. In some embodiments of this application, the first passivation layer and the second passivation layer may be formed using the same material, such as silicon oxide, silicon nitride, etc. In some embodiments of this application, the first passivation layer and the second passivation layer may also be formed using different materials, such as using silicon oxide for the first passivation layer and silicon nitride for the second passivation layer.
[0071] It should be noted that the second metal deposition process can be the deposition of multiple layers of through-hole metal, such as sequentially stacking titanium (Ti), titanium nitride (TiN), and tungsten (W). In the edge via, the titanium layer serves as the charge release layer 600, and the titanium nitride and tungsten layers serve as the edge lead-out layers 800. The source lead-out layer 910, drain lead-out layer 920, and gate lead-out layer 930 all consist of titanium, titanium nitride, and tungsten. Thus, by forming source vias, drain vias, edge vias, and gate vias through the via process, the charge release layer 600 and edge lead-out layer 800 can be fabricated during the metal deposition process, which simplifies the processing steps and improves processing efficiency.
[0072] Fabricating the substrate structure 100 may include: epitaxially growing a gallium nitride buffer layer 120 on the substrate; and epitaxially growing an aluminum gallium nitride layer 130 on the gallium nitride buffer layer 120.
[0073] Understandably, after the second metal deposition process, bonding, encapsulation, and other processing steps may also be included.
[0074] It should be noted that source vias, drain vias, edge vias, and gate vias only expose a portion of their corresponding areas to achieve the purpose of lead-out layer connection, and do not need to completely expose the entire area of the underlying layer.
[0075] The transistor fabricated using the high electron mobility transistor fabrication method provided in this application has a P-type gallium nitride layer 400 with a middle portion 420 located between the source 200 and the drain 300. The substrate structure 100 forms a conductive channel. The P-type gallium nitride layer 400 keeps the conductive channel between the source 200 and the drain 300 normally closed, thus realizing the function of an enhancement-mode device. An N-type gallium nitride layer 500 is disposed on the P-type gallium nitride layer 400, and the N-type gallium nitride layer 500 has a first opening 510 at the edge portion 410 of the P-type gallium nitride layer 400 to expose the underlying P-type gallium nitride layer 400, allowing the charge release layer 600 to be directly connected to the P-type gallium nitride layer 400.
[0076] With this structure, an N-type gallium nitride layer 500 is disposed on the P-type gallium nitride layer 400, forming a PN junction between the two to replace the Schottky junction. This fundamentally avoids the problem of reduced gate reliability caused by Schottky junction degradation, which is beneficial to improving the reliability of the gate structure. At the same time, the N-type gallium nitride layer 500 has a first opening 510 at the position corresponding to the edge portion 410, allowing the charge release layer 600 to be directly connected to the P-type gallium nitride layer 400. Since the gate leakage current of the charge release layer 600 is greater than that of the N-type gallium nitride layer 500, the charge release layer 600 can provide a faster path for releasing trapped charges compared to the N-type gallium nitride layer 500. This allows the trapped charges in the P-type gallium nitride layer 400 to be released quickly through the charge release layer 600, reducing the impact of trapped charges on the threshold voltage and improving the overall stability of the transistor.
[0077] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0078] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A high electron mobility transistor, characterized in that, include: A substrate structure (100) is used to form conductive channels; A source (200) and a drain (300) are disposed on the substrate structure (100); A p-type gallium nitride layer (400) is disposed on the substrate structure (100). The p-type gallium nitride layer (400) includes an edge portion (410) and an intermediate portion (420) located between the source (200) and the drain (300). The p-type gallium nitride layer (400) is used to consume the charge carriers of the conductive channel so that the conductive channel is normally closed. An N-type gallium nitride layer (500) is disposed on the P-type gallium nitride layer (400). The N-type gallium nitride layer (500) is provided with a first opening (510). The first opening (510) is located on the edge portion (410) and is used to expose the edge portion (410). A charge release layer (600) is disposed on the P-type gallium nitride layer (400) and located within the first opening (510); A PN junction is formed between the P-type gallium nitride layer (400) and the N-type gallium nitride layer (500), and the gate leakage current of the charge release layer (600) is greater than the gate leakage current of the N-type gallium nitride layer (500).
2. The high electron mobility transistor according to claim 1, characterized in that, The P-type gallium nitride layer (400) has an etched recess (430) located at the edge portion (410) and the projection of the first opening portion (510) covers the etched recess (430), and the charge release layer (600) fills the etched recess (430).
3. The high electron mobility transistor according to claim 2, characterized in that, The cross-section of the over-etched recess (430) is an inverted trapezoid.
4. The high electron mobility transistor according to claim 2, characterized in that, The thickness of the P-type gallium nitride layer (400) is in the range of 50 nanometers to 100 nanometers, and / or the thickness of the N-type gallium nitride layer (500) is in the range of 10 nanometers to 40 nanometers, and / or the depth of the over-etched recess (430) is within 5 nanometers.
5. The high electron mobility transistor according to claim 1, characterized in that, It also includes a gate metal layer (700) disposed on the N-type gallium nitride layer (500), wherein an ohmic contact is formed between the gate metal layer (700) and the N-type gallium nitride layer (500), and the gate metal layer (700) is provided with a second opening (710) corresponding to the first opening (510), wherein the second opening (710) is used to expose the edge portion (410).
6. The high electron mobility transistor according to claim 1, characterized in that, The charge release layer (600) is an ohmic contact layer, and an ohmic contact is formed between the ohmic contact layer and the p-type gallium nitride layer (400).
7. The high electron mobility transistor according to any one of claims 1 to 6, characterized in that, There are two sources (200), one of which is located on one side of the drain (300) and the other source (200) is located on the other side of the drain (300). The P-type gallium nitride layer (400) includes two intermediate portions (420). The intermediate portion (420) is disposed between the drain (300) and the two sources (200). The two intermediate portions (420) are connected to the edge portion (410). The N-type gallium nitride layer (500) is disposed on the two intermediate portions (420).
8. The high electron mobility transistor according to claim 7, characterized in that, The p-type gallium nitride layer (400) includes two edge portions (410), one of which is connected to one side of the two middle portions (420) and the other edge portion (410) is connected to the other side of the two middle portions (420).
9. The high electron mobility transistor according to claim 1 is characterized in that, The substrate structure (100) includes a substrate layer (110), a gallium nitride buffer layer (120), and an aluminum gallium nitride layer (130) stacked sequentially from bottom to top. A two-dimensional electron gas is formed between the gallium nitride buffer layer (120) and the aluminum gallium nitride layer (130) as the conductive channel.
10. A method for fabricating a high electron mobility transistor, characterized in that, include: Construct the base structure; Define a P-type gallium nitride layer pattern on the substrate structure to fabricate the P-type gallium nitride layer; Define an N-type gallium nitride layer pattern on the P-type gallium nitride layer to fabricate the N-type gallium nitride layer; Define a gate metal layer pattern on the N-type gallium nitride layer and fabricate the gate metal layer; Through the first etching process, a second opening (710) is formed on the gate metal layer, a first opening is formed on the N-type gallium nitride layer, and an over-etched recess is formed at the edge of the P-type gallium nitride layer. A first passivation layer is fabricated to cover the substrate structure, the P-type gallium nitride layer, and the N-type gallium nitride layer; A second etching process is used to form source and drain openings that expose the substrate structure, with the middle portion of the P-type gallium nitride layer located between the source and drain openings; A source electrode is formed at the source opening and a drain electrode is formed at the drain opening by a first metal deposition process. A second passivation layer is fabricated to cover the first passivation layer, the source electrode, and the drain electrode; Through the third etching process, a source via exposing the source electrode, a drain via exposing the drain electrode, an edge via exposing the edge portion of the P-type gallium nitride layer, and a gate via exposing the gate metal layer are formed. A second metal deposition process is used to form a source lead-out layer in the source via, a drain lead-out layer in the drain via, a charge release layer in the edge via, and a gate lead-out layer in the gate via.