Semiconductor device

Abstract

The invention provides a semiconductor device. Comprising a substrate with a first conductive type, an epitaxial layer which is arranged on the substrate and has the first conductive type, a groove structure which extends into the epitaxial layer from the top surface of the epitaxial layer, and a well with a second conductive type, a first heavily doped portion having a first conductivity type and a second heavily doped portion having a second conductivity type are formed in the well. The trench structure includes a conductive portion and an insulating layer covering a side wall and a bottom surface of the conductive portion. The well and the groove structure are separated in the first direction, the well extends in the second direction, and the first heavily doped parts and the second heavily doped parts extend in the first direction and are alternately arranged in the second direction. The semiconductor device also includes a gate structure formed on the top surface of the epitaxial layer and corresponding to the well, wherein the gate structure extends along the second direction.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to miniaturized semiconductor devices. Background Technology

[0002] The semiconductor industry continues to improve the integration density of various electronic components by continuously reducing the minimum component size, allowing more components to be integrated within a given area. For example, the trench gate metal-oxide-semiconductor field-effect transistor (MOSFET), widely used in power switch components, utilizes a vertical structure design to reduce cell pitch and increase functional density. It uses the back of the chip as the drain, while multiple transistor sources and gates are fabricated on the front of the chip. As a result, the drive current flows vertically instead of in a planar direction, which also enables the semiconductor device to achieve high reverse breakdown voltage and low on-resistance.

[0003] However, as the functional density requirements of semiconductor devices continue to increase, the complexity of the components integrated into these devices and their fabrication methods also increases. Therefore, while existing semiconductor devices are generally appropriate and sufficient to meet their intended purposes, they are not entirely satisfactory in all respects. Summary of the Invention

[0004] Some embodiments disclosed herein provide a semiconductor device including a substrate having a first conductivity type, an epitaxial layer on the substrate having the first conductivity type, a trench structure extending from the top surface of the epitaxial layer into the epitaxial layer, and a well having a second conductivity type. At least one first heavily doped portion and at least one second heavily doped portion are formed in the well and extend along a first direction, and are alternately arranged in a second direction. The first heavily doped portion has the first conductivity type, and the second heavily doped portion has the second conductivity type. The trench structure includes a conductive portion and an insulating layer covering the sidewalls and bottom surface of the conductive portion. The well is spaced apart from the trench structure in the first direction, and the well extends in a second direction, which is different from the first direction. The semiconductor device further includes a gate structure formed on the top surface of the aforementioned epitaxial layer and corresponding to the well, wherein the gate structure extends along the second direction. Attached Figure Description

[0005] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E-1 , Figure 1E-2 This is a schematic cross-sectional view of a semiconductor device during an intermediate manufacturing stage according to some embodiments of the present disclosure.

[0006] Figure 2 This is a top view of a semiconductor device at an intermediate manufacturing stage according to some embodiments of the present disclosure.

[0007] Figure 3 This is a top view of a semiconductor device at an intermediate manufacturing stage according to some embodiments of the present disclosure.

[0008] Figure 4A , Figure 4B These are a cross-sectional view and a top view of a semiconductor device at an intermediate manufacturing stage, respectively.

[0009] Figure 5A , Figure 5B These are, respectively, a cross-sectional schematic diagram and a top view of a semiconductor device at an intermediate manufacturing stage according to some embodiments of the present disclosure.

[0010] Symbol Explanation

[0011] 10, 40, 50: Semiconductor devices

[0012] 100, 400: Base

[0013] 102, 402: Epitaxial layer

[0014] 102a: Top surface

[0015] 103, 403: Trench structure

[0016] 103-1: First trench structure

[0017] 103-2: Second trench structure

[0018] 103-3: Third trench structure

[0019] 104: Insulation layer

[0020] 104-3: Insulating Liner

[0021] 105: Conductive part

[0022] 105-3: Conductive filler layer

[0023] 105-3L: Conductive lower part

[0024] 105-3U: Conductive upper part

[0025] 105s, S11, S12, S21, S22: Sidewall

[0026] 105b: Bottom surface

[0027] 106, 406: Trap

[0028] 107: Lightly doped portion

[0029] 108, 408: First doped region

[0030] 108-S1, 109-S1: First sidewall

[0031] 108-S2, 109-S2: Second sidewall

[0032] 109, 409: Second doped portion

[0033] 110, 410: Gate structure

[0034] 110-1: First gate structure

[0035] 110-2: Second gate structure

[0036] 111: Gate dielectric layer

[0037] 112: Gate electrode

[0038] 113, 413: Interlayer dielectric layer

[0039] 116, 116-S, 116-T1, 116-T2, 116-G1, 116-G2, 416: Contact elements

[0040] 117: Contact Barrier Layer

[0041] 118: Contact conductive layer

[0042] R D Drift Zone

[0043] Dp: Depth

[0044] C1-C1, C2-C2: Section lines

[0045] Wch: Channel width

[0046] d1, d4, d5: Distance

[0047] L1: First Length

[0048] L2: Second Length

[0049] D1: First Direction

[0050] D2: Second Direction

[0051] D3: Third direction Detailed Implementation

[0052] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided semiconductor device. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in different examples of embodiments of the invention. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments discussed.

[0053] Furthermore, spatially related terms such as "below," "under," "below," "above," "above," and other similar expressions may be used in the following description to simplify the statement of the relationship between an element or component and other elements or components as shown in the figure. These spatially related terms include not only the direction depicted in the figure but also the different orientations of the device during use or operation. The device may be positioned in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptions used herein may be interpreted accordingly.

[0054] The following describes some variations of the embodiments. In embodiments with different figures and descriptions, similar element symbols are used to identify similar elements. It is understood that additional steps may be provided before, during, or after the method, and some described steps may be replaced or omitted for other embodiments of the method.

[0055] This disclosure provides semiconductor devices and methods for forming them, which, in some embodiments, can be used to fabricate semiconductor devices suitable for miniaturization or micro-miniaturization. The embodiments are applicable to metal-oxide-semiconductor (MOS) devices, such as MOSFETs. In some of the following embodiments, MOS MOSFETs comprising a planar gate and a conductive trench structure are used as examples of semiconductor devices.

[0056] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E-1 This is a schematic cross-sectional view of a semiconductor device at various intermediate manufacturing stages according to some embodiments of this disclosure.

[0057] Reference Figure 1AAccording to some embodiments, a substrate 100 having a first conductivity type is provided. In some embodiments, the substrate 100 may be a block-shaped semiconductor substrate, such as a semiconductor wafer. For example, the substrate 100 is a silicon wafer. In some embodiments, the substrate 100 may be made of silicon or other semiconductor materials, or the substrate 100 may contain other elemental semiconductor materials, such as germanium. In some embodiments, the substrate 100 may include compound semiconductors, such as silicon carbide or gallium nitride. In some embodiments, the substrate 100 may include alloy semiconductors, such as silicon-germanium, silicon-germanium carbide, or other suitable substrates. In some embodiments, the substrate 100 may consist of a multilayer material, such as silicon / silicon-germanium or silicon / silicon carbide.

[0058] In this example, the substrate 100 is, for example, a silicon wafer doped with a first conductivity type. In an application of a metal-oxide-semiconductor field-effect transistor (MOSFET) with vertical conductive trenches, the substrate 100 with the first conductivity type can serve as the drain region of the semiconductor device. Furthermore, in this example, the first conductivity type is n-type, but this disclosure is not limited thereto. In some other examples, the first conductivity type can also be p-type.

[0059] In some embodiments, an epitaxial growth process is performed to form an epitaxial layer 102 on a substrate 100. The substrate 100 and the epitaxial layer 102 have the same conductivity type. In this example, the epitaxial layer 102 has a first conductivity type, such as n-type. In some embodiments, the doping concentration of the epitaxial layer 102 is less than the doping concentration of the substrate 100. In an application of a vertical trench gate metal-oxide-semiconductor field-effect transistor, the epitaxial layer 102 having the first conductivity type can serve as a drift region of the semiconductor device.

[0060] In some embodiments, the epitaxial growth process described above can be performed using metal-organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable processes, or combinations thereof.

[0061] Then, refer to Figure 1B According to some embodiments, a plurality of trench structures 103 are formed in the epitaxial layer 102. According to some embodiments disclosed herein, the positions of the trench structures 103 can be defined by a suitable photolithographic patterning process. Subsequently, a portion of the epitaxial layer 102 can be removed by an etching process to form grooves (not shown) in the epitaxial layer 102. In some embodiments, the positions of these grooves correspond to... Figure 1B The location of the trench structure 103 is shown. The depth of these grooves in the epitaxial layer 102, for example, the depth along the third direction D3, is equal to the depth Dp of the subsequently formed trench structure 103 in the epitaxial layer 102. The above etching process includes a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the foregoing processes. Furthermore, it is understood that the size, shape, and location of the grooves and the trench structure 103 formed therein are for illustrative purposes only and are not intended to limit the embodiments of the present invention.

[0062] Each trench structure 103 includes an insulating layer 104 and a conductive portion 105, wherein the insulating layer 104 covers the sidewalls 105s and the bottom surface 105b of the conductive portion 105. In some embodiments, such as Figure 1B As shown, the trench structures 103 are spaced apart from each other in the first direction D1, and each trench structure 103 extends in the epitaxial layer 102 along the second direction D2. In this example, two trench structures 103 are shown in the figure for clarity.

[0063] The interaction between the trench structure 103 and other subsequently formed components, as proposed in the embodiments, can improve the electrical performance of the formed semiconductor device. For example, if the trench structure 103 is subsequently electrically connected to the gate, the on-resistance can be significantly reduced; or if the trench structure 103 is subsequently electrically connected to the source, it can effectively reduce the on-resistance while also having good dynamic characteristics, such as shortening the switching time between on and off and significantly reducing switching energy loss.

[0064] The trench structure 103 proposed in the embodiment can be electrically coupled to the source or the gate, so the insulating layer 104 and the conductive part 105 can be appropriately selected according to the coupling situation in actual application.

[0065] In some embodiments where the trench structure 103 is electrically coupled to the source, the insulating layer 104 may be silicon oxide, germanium oxide, other suitable semiconductor oxide materials, or combinations thereof. In some examples, an oxidation process can be used to isotropically form the insulating material on the sidewalls and bottom surfaces of the trench and on the top surface 102a of the epitaxial layer 102. In some embodiments, the oxidation process may be thermal oxidation, radical oxidation, or other suitable processes. In some embodiments, a thermal process may also be selectively applied to the insulating material to increase its density. In some embodiments, the aforementioned thermal process may be a rapid thermal annealing (RTA) process.

[0066] In some embodiments where the trench structure 103 is electrically coupled to the gate, i.e., the trench structure 103 serves as a trench gate structure, the insulating layer 104 may be silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, alumina-hafnium alloy, silicon-hafnium dioxide, silicon-oxygen-hafnium, tantalum-hafnium oxide, titanium-hafnium oxide, zirconium-hafnium oxide, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, an insulating material may be formed on the sidewalls and bottom surfaces of the trench and on the top surface 102a of the epitaxial layer 102 by a deposition process, such as an isotropic deposition process, and may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, other suitable deposition processes, or combinations thereof.

[0067] Subsequently, according to some embodiments, a conductive material (not shown) can be deposited on top of the insulating material using a deposition process, with the conductive material filling the space in the groove excluding the insulating material. A thermal process, such as an annealing process, can be selectively applied to the conductive material. In some embodiments, the conductive material can be a single-layer or multi-layer structure, formed of amorphous silicon, polycrystalline silicon, or a combination of the aforementioned materials. In some examples, the deposition process can be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the aforementioned processes.

[0068] Next, some of the insulating material and some of the conductive material are removed to form a structure like... Figure 1BThe trench structure 103 is shown. For example, an excess portion of conductive material and excess portion of insulating material located above the top surface 102a of the epitaxial layer 102 can be removed by a planarization process, exposing the top surface 102a of the epitaxial layer 102. The planarization process described above is, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the foregoing processes.

[0069] After the above removal steps, the remaining portion of the insulating material becomes the insulating layer 104, and the remaining portion of the conductive material becomes the conductive portion 105. The conductive portion 105 is separated from the epitaxial layer 102 by the insulating layer 104. In some examples, after the planarization process, the conductive portion 105 is located on the insulating layer 104, and the top surface of the conductive portion 105 and the top surface of the insulating layer 104 are substantially coplanar with the top surface 102a of the epitaxial layer 102.

[0070] In some embodiments, the conductive portion 105 may selectively include a dopant of a first conductivity type, such as an n-type dopant. In some embodiments, the dopant of the conductive portion 105 may be phosphorus or other suitable dopant. In some embodiments where the trench structure 103 is subsequently electrically connected to a gate, the conductive portion 105 of the trench structure 103, in addition to reducing on-resistance, may further enhance the effect of reducing the surface field (RESURF) by having a conductive portion 105 of the first conductivity type.

[0071] After forming the trench structure 103, refer to Figure 1C According to some embodiments, a well 106 is formed in the epitaxial layer 102, and this well 106 has a different conductivity type than the epitaxial layer 102, such as a second conductivity type. In this example, the well 106 is p-type, also referred to as a p-body region. In some embodiments, the well 106 is spaced apart from the trench structure 103 in a first direction D1, and the well 106 extends in a second direction D2. In some embodiments, the doping concentration of the well 106 is approximately 1E16 atoms / cm². 3 Up to approximately 1E18 atoms / cm 3 Between the ranges. According to some embodiments, the surface of well 106 can serve as a channel region of a semiconductor device.

[0072] Furthermore, in some embodiments where the semiconductor device is a vertically-diffused metal-oxide-semiconductor (VDMOS) element, the epitaxial portion outside and below the well 106 is a drift region R of the semiconductor device. D Therefore, the drift region R DHaving a first conductivity type (e.g., n-type), and in contact with the sidewalls and bottom surface of the well 106, such as Figure 1C As shown.

[0073] According to some embodiments, doping can be performed on the top surface 102a of the epitaxial layer 102 through deposition, photolithography patterning, etching, and implantation processes to form a doping layer in the epitaxial layer 102. Figure 1C The well 106 is shown. Therefore, the well 106 is doped downwards from the top surface 102a of the epitaxial layer 102 to a specific depth in the epitaxial layer 102. Furthermore, the depth of the well 106 in the epitaxial layer 102 (e.g., along the third direction D3) is less than the depth of the trench structure 103 in the epitaxial layer 102 (along the third direction D3). That is, the bottom surface of the trench structure 103 (i.e., the bottom surface of the insulating layer 104) is closer to the substrate 100 than the bottom surface of the well 106.

[0074] In one example, an oxide hardmask material layer (not shown) may be deposited over the top surface 102a of the epitaxial layer 102. Then, a patterned photoresist corresponding to the location of the well 106 may be formed on this oxide hardmask material layer. The oxide hardmask material layer may be etched according to this patterned photoresist to form an oxide hardmask. The patterned photoresist may be removed. The epitaxial layer 102 may be doped according to the formed oxide hardmask to form the well 106 in the epitaxial layer 102. After that, the oxide hardmask may be removed.

[0075] It should be noted that, although Figure 1C The cross-sectional view cannot be shown, but each well 106 is a doped region extending in the first direction D1, the second direction D2, and the third direction D3. Furthermore, in the process of some embodiments, when viewed from above the epitaxial layer 102, the mask defining the well 106 and the mask defining the trench structure 103 (e.g., extending in the first direction D1 and the second direction D2, both not shown) do not overlap in the first direction D1, so that the subsequently fabricated well 106 can be spaced appropriately from the trench structure 103 in the first direction D1.

[0076] Subsequently, according to some embodiments, a first heavily doped portion 108 and a second heavily doped portion 109 with different conductivity types are formed in the well 106, and the first heavily doped portion 108 and the second heavily doped portion 109 are alternately arranged along the second direction D2. Furthermore, a planar gate is formed on the epitaxial layer 102.

[0077] Please refer to the following at the same time Figure 1D and Figure 2 . Figure 2 This is a top view of a semiconductor device at an intermediate manufacturing stage according to some embodiments of the present disclosure. Figure 1D For example, it is along Figure 2 A schematic cross-sectional view of a semiconductor device taken by section line C1-C1.

[0078] like Figure 1D , Figure 2 As shown, according to some embodiments disclosed herein, a plurality of first heavily doped portions 108 and a plurality of second heavily doped portions 109 are formed in the well 106, and these first heavily doped portions 108 and second heavily doped portions 109 are alternately arranged along the second direction D2. Figure 2 In some embodiments where the semiconductor device is a vertically-diffused metal-oxide-semiconductor (VDMOS) element, a channel width Wch of the semiconductor device extends, for example, in a second direction D2. Therefore, in some embodiments, these first heavily doped portions 108 and second heavily doped portions 109 in the well are alternately arranged in the direction of the channel width.

[0079] According to some embodiments, the first heavily doped region 108 has a first conductivity type, such as n-type. The second heavily doped region 109 has a second conductivity type, such as p-type. In some embodiments where the semiconductor device is a VDMOS element, the first heavily doped region 108 may serve as source regions, and the second heavily doped region 109 may serve as base regions. Furthermore, according to some embodiments, the first heavily doped region 108 may or may not surround the second heavily doped region 109.

[0080] Note that, due to Figure 1D It is based on Figure 2 The cross-section C1-C1 is a cross-section taken through the first heavily doped section 108, therefore Figure 1D Only the first heavily doped portion 108 is shown in the well 106.

[0081] According to some embodiments, the top surface of the self-well 106 (i.e., the top surface 102a of the epitaxial layer 102) is doped with a dopant having a first conductivity type to form a first heavily doped portion 108. For example... Figure 2 As shown, the first heavily doped portion 108 extends in a first direction D1, which differs from the extension direction of the subsequently formed gate structure 110 (e.g., a second direction D2). In one example, the extension direction of the first heavily doped portion 108 is substantially perpendicular to the extension direction of the gate structure 110. Furthermore, the doping concentration of the first heavily doped portion 108 is greater than the doping concentration of the epitaxial layer 102. In some embodiments, the doping concentration of these first heavily doped portions 108 is, for example (but not limited to), about 1E18 atoms / cm². 3Up to approximately 1E21 atoms / cm 3 Between the ranges.

[0082] According to some embodiments, a first heavily doped portion 108 can be formed in the well 106 by doping the top surface 102a of the epitaxial layer 102 with a dopant of a first conductivity type through deposition, photolithography patterning, etching, and implantation processes. In one example, an oxide hard mask material layer (not shown) can be deposited over the top surface 102a of the epitaxial layer 102. Then, a patterned photoresist corresponding to the location of the first heavily doped portion 108 can be formed on this oxide hard mask material layer. The oxide hard mask material layer can be etched according to this patterned photoresist to form an oxide hard mask. The patterned photoresist can be removed. The epitaxial layer 102 can be doped according to the formed oxide hard mask to form the first heavily doped portion 108 in the well 106. Afterward, the oxide hard mask can be removed.

[0083] Furthermore, in some embodiments, the top surface of the self-well 106 (i.e., the top surface 102a of the epitaxial layer 102) is doped with a dopant having a second conductivity type to form a second heavily doped portion 109. For example... Figure 2 As shown, the second heavily doped portion 109 extends in a first direction D1, which differs from the extension direction of the subsequently formed gate structure 110 (e.g., a second direction D2). In one example, the extension direction of the second heavily doped portion 109 is substantially perpendicular to the extension direction of the gate structure 110. The doping concentration of the second heavily doped portion 109 is greater than the doping concentration of the well 106. Furthermore, in some embodiments, the doping concentration of these second heavily doped portions 109 is, for example (but not limited to), about 1E18 atoms / cm². 3 Up to approximately 1E21 atoms / cm 3 Between the ranges.

[0084] Alternatively, a second doped portion 109 can be formed in the well 106 by doping the top surface 102a of the epitaxial layer 102 with a dopant of a second conductivity type through deposition, photolithography patterning, etching, and implantation processes. The method for forming the second doped portion 109 can refer to the method for forming the first doped portion 108 described above, and will not be repeated here.

[0085] Furthermore, according to some embodiments disclosed herein, these second heavily doped portions 109 are alternately disposed with the first heavily doped portions 108 in the extension direction (e.g., the second direction D2) of the gate structure 110. In embodiments having at least two first heavily doped portions 108 and two second heavily doped portions 109, when viewed from above the epitaxial layer 102, the middle first heavily doped portion 108 is located between the two second heavily doped portions 109. Furthermore, in this example, as... Figure 2As shown, viewed from above the epitaxial layer 102, each of the second doped portions 109 is located between two first doped portions 108.

[0086] More specifically, according to some embodiments, the first heavily doped portion 108 is connected to the second heavily doped portion 109 in the second direction D2. For example... Figure 2 As shown, the first heavily doped portion 108 includes, for example, opposing first sidewalls 108-S1 and second sidewalls 108-S2. The second heavily doped portion 109 includes, for example, opposing first sidewalls 109-S1 and second sidewalls 109-S2. The first sidewall 108-S1 of the first heavily doped portion 108 abuts against the second sidewall 109-S2 of the second heavily doped portion 109, and the second sidewall 109-S2 is adjacent to and at least partially in contact with the first sidewall 108-S1.

[0087] Furthermore, according to some embodiments, such as Figure 2 As shown, the first heavily doped portion 108 has a first length L1 in the first direction D1, and the second heavily doped portion 109 has a second length L2 in the first direction D1, wherein the first length L1 is greater than the second length L2.

[0088] Furthermore, in some embodiments, such as Figure 2 As shown, the semiconductor device also includes a lightly doped portion 107 extending in the second direction D2, wherein the lightly doped portion 107 and the first heavily doped portion 108 have the same conductivity type, and the edges of the lightly doped portion 107 and the first heavily doped portion 108 are substantially flush. The lightly doped portion 107 has a first conductivity type, such as n-type. In some examples, before forming the first heavily doped portion 108 and the second heavily doped portion 109, a low concentration of dopant of the first conductivity type is first doped from the top surface 102a of the epitaxial layer 102 to form the lightly doped portion 107 in the well 106, and the depth of the lightly doped portion 107 in the well 106 is shallower than that of the subsequently formed first heavily doped portion 108 and the second heavily doped portion 109. In some embodiments, the doping concentration of the lightly doped portion 107 is, for example (but not limited to), about 1E14 atoms / cm². 3 Up to approximately 1E16 atoms / cm 3 Between the ranges.

[0089] Furthermore, according to some embodiments disclosed herein, the extension direction of the lightly doped portion 107, such as the second direction D2, is different from the extension direction of the first heavily doped portion 108 and the second heavily doped portion 109, such as the first direction. In some examples, such as Figure 2As shown, the sidewalls of the first heavily doped portion 108 (e.g., the first sidewalls 108-S1 and 108-S2) and the sidewalls of the second heavily doped portion 109 (e.g., the first sidewalls 109-S1 and 109-S2) are perpendicular to the extending direction of the lightly doped portion 107 (e.g., the second direction D2).

[0090] Furthermore, according to some embodiments disclosed herein, the lightly doped portion 107 extending in the second direction D2 is a side edge connecting the alternately arranged first heavily doped portions 108 and second heavily doped portions 109. In embodiments having at least two first heavily doped portions 108 and one second heavily doped portion 109, when viewed from above the epitaxial layer 102, the second heavily doped portion 109 is surrounded by two adjacent first heavily doped portions 108 and lightly doped portions 107.

[0091] Please refer to again Figure 1D , Figure 2 According to some embodiments, after forming the lightly doped portion 107, the first heavily doped portion 108, and the second heavily doped portion 109, a planar gate structure 110 is formed on the top surface 102a of the epitaxial layer 102, wherein the gate structure 110 corresponds to the underlying well 106 and extends along the second direction D2. Figure 2 More specifically, the gate structure 110 includes a first heavily doped portion 108 and a portion of the drift region R that are disposed across the corresponding well 106, a portion of the well 106, and a portion of the drift region R. D Above.

[0092] According to some embodiments, such as Figure 2 As shown, the extension direction (e.g., first direction D1) of the first heavily doped portion 108 and the second heavily doped portion 109 is different from the extension direction (e.g., second direction D2) of the gate structure 110.

[0093] In some embodiments, such as Figure 1D As shown, the gate structure 110 includes a gate dielectric layer 111 and a gate electrode 112 located above the gate dielectric layer 111. The gate dielectric layer 111 may be silicon oxide or other suitable dielectric material. The gate electrode 112 may include polysilicon or other suitable conductive material. A dielectric material layer (not shown) can be formed on the epitaxial layer 102 by a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD)) or a thermal oxidation process. Then, a conductive material (not shown) is deposited on the dielectric material layer, the deposition process being a physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable process. Next, the dielectric material layer and the conductive material can be patterned by photolithography and etching processes to form the gate dielectric layer 111 and the gate electrode 112 of the gate structure 110.

[0094] This example uses a semiconductor device with a symmetric configuration of components for illustration. Figure 1D , Figure 2 As shown, two gate structures correspond to well 106, including a first gate structure 110-1 corresponding to one side of well 106 and a second gate structure 110-2 corresponding to the other side of well 106. The first gate structure 110-1 and the second gate structure 110-2 have similar configurations and both extend along the second direction D2. The second gate structure 110-2 is spaced apart from the first gate structure 110-1 by a distance in the first direction D1, for example... Figure 2 The distance d1 is shown.

[0095] Furthermore, in this example, such as Figure 1D , Figure 2 As shown, the well 106 is located between two trench structures, for example, between a first trench structure 103-1 and a second trench structure 103-2. The first trench structure 103-1 and the second trench structure 103-2 are spaced apart in a first direction D1, while the first gate structure 110-1 and the second gate structure 110-2 are located between the first trench structure 103-1 and the second trench structure 103-2. The first trench structure 103-1 and the second trench structure 103-2 have similar configurations; for example, each trench structure includes an insulating layer 104 and a conductive portion 105, wherein the insulating layer 104 covers the sidewalls and 105s of the conductive portion 105. Figure 2 As shown, both the first trench structure 103-1 and the second trench structure 103-2 extend in the second direction D2.

[0096] Furthermore, according to some embodiments, the two opposite ends of each first heavily doped portion 108 extend below the adjacent sidewalls of the first gate structure 110-1 and the second gate structure 110-2, respectively, and partially overlap with the first gate structure 110-1 and the second gate structure 110-2.

[0097] More specifically, in this example, the first gate structure 110-1 has opposing sidewalls S11 and S12, and the second gate structure 110-2 has opposing sidewalls S21 and S22. The two opposing ends of each first heavily doped portion 108 extend below the sidewalls S11 and S22, respectively, and overlap with portions of the first gate structure 110-1 and portions of the second gate structure 110-2, respectively. In other words, in some embodiments, the projected areas of the two opposing ends of the first heavily doped portion 108 on the substrate 100 partially overlap with the projected areas of the first gate structure 110-1 and the second gate structure 110-2 on the substrate 100, respectively.

[0098] According to some embodiments, such as Figure 2 As shown, the first heavily doped portion 108 has a first length L1 in the first direction D1, and the second gate structure 110-2 is separated from the first gate structure 110-1 by a distance d1 in the first direction D1. In this example, the first length L1 is greater than the distance d1 between the second gate structure 110-2 and the first gate structure 110-1.

[0099] Furthermore, according to some embodiments, the two opposite ends of each second heavily doped portion 109 extend below the adjacent sidewalls of the first gate structure 110-1 and the second gate structure 110-2, respectively. The second heavily doped portion 109 may partially overlap with the first gate structure 110-1 and the second gate structure 110-2 or may not overlap.

[0100] More specifically, in this example, the two opposite ends of each of the second heavily doped portions 109 extend below the sidewall S11 of the first gate structure 110-1 and the sidewall S22 of the second gate structure 110-2, respectively. For example, the two opposite ends of the second heavily doped portions 109 extend below the sidewalls S11 and S22, respectively, and are substantially flush with the sidewalls S11 and S22. In other words, in some embodiments, the projected areas of the two opposite ends of the second heavily doped portions 109 on the substrate 100 are respectively adjacent to the projected areas of the first gate structure 110-1 and the second gate structure 110-2 on the substrate 100, and these projected areas do not substantially overlap.

[0101] According to some embodiments, such as Figure 2 As shown, the second heavily doped portion 109 has a second length L2 in the first direction D1, and the second gate structure 110-2 is spaced apart from the first gate structure 110-1 by a distance d1 in the first direction D1. In this example, the second length L2 is approximately equal to the distance d1 between the second gate structure 110-2 and the first gate structure 110-1.

[0102] Reference Figure 1E-1 , Figure 1E-2 According to some embodiments, after forming a planar gate structure 110 (e.g., a first gate structure 110-1 and a second gate structure 110-2) on the top surface 102a of the epitaxial layer 102, an interlayer dielectric (ILD) layer 113 is formed on the epitaxial layer 102, and a plurality of contacts 116 are formed in the interlayer dielectric layer 113.

[0103] Please refer to the following at the same time Figure 1E-1 , Figure 1E-2 and Figure 3 . Figure 3 This is a top view of a semiconductor device at an intermediate manufacturing stage according to some embodiments of the present disclosure. Figure 1E-1 For example, it is along Figure 3 A cross-sectional schematic diagram of a semiconductor device taken by section line C1-C1, wherein section line C1-C1 corresponds to the first heavily doped part 108. Figure 1E-2 For example, it is along Figure 3 A cross-sectional schematic diagram of a semiconductor device is shown, taken along section line C2-C2, where section line C2-C2 corresponds to the lightly doped portion 107 and the heavily doped portion 109. Note that... Figure 3 Only the contacts 116-S on the first doped portion 108 and the second doped portion 109 are shown, while other contacts on the gate structure 110 and the trench structure 103 are omitted to facilitate a clear top view of the semiconductor device.

[0104] According to some embodiments, such as Figure 1E-1 , Figure 1E-2 As shown, the interlayer dielectric layer 113 is formed on the top surface 102a of the epitaxial layer 102 and covers the gate structure 110 (including the first gate structure 110-1 and the second gate structure 110-2), the first heavily doped portion 108, the second heavily doped portion 109 and the trench structure 103 (including the first trench structure 103-1 and the second trench structure 103-2).

[0105] In some embodiments, the interlayer dielectric layer 113 may be silicon oxide, other suitable low-k dielectric materials, or combinations thereof. In some embodiments, the material of the interlayer dielectric layer 113 is different from the material of the insulating layer 104 of the trench structure 103. In some other embodiments, the material of the interlayer dielectric layer 113 is the same as the material of the insulating layer 104 of the trench structure 103. Furthermore, the interlayer dielectric layer 113 may be deposited over the epitaxial layer 102 by a deposition process. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or combinations thereof.

[0106] Subsequently, according to some embodiments, a portion of the interlayer dielectric layer 113 is removed to form a plurality of contact holes (not shown). More specifically, after the removal step, the formed contact holes expose a first gate structure 110-1, a second gate structure 110-2, a first trench structure 103-1, a second trench structure 103-2, a portion of a first heavily doped portion 108, and a portion of a second heavily doped portion 109.

[0107] Subsequently, according to some embodiments, a photolithographic patterning process and an etching process can be used to form contact holes in the interlayer dielectric layer 113. In one example, after depositing an interlayer dielectric material (not shown) over the epitaxial layer 102, a portion of the interlayer dielectric layer 113 is removed, for example, by one or more etching processes, to form contact holes. In some embodiments, the photolithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or combinations of the foregoing processes. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or combinations of the foregoing processes.

[0108] In some examples, viewed from above the epitaxial layer 102, the contact holes above the first heavily doped portion 108 and the second heavily doped portion 109 can be arranged generally along the second direction D2, for example... Figure 3 The location corresponding to contact 116-S is shown in the diagram. However, this disclosure is not limited to this. The contact holes may be arranged in one or more straight lines, or adjacent contact holes may be staggered.

[0109] Subsequently, according to some embodiments, contacts 116 are formed in these contact holes. For example... Figure 1E-1 , Figure 1E-2 As shown, a contact 116-S (also known as source contacts) is formed that is electrically connected to the first heavily doped portion 108 and the second heavily doped portion 109, a contact 116-T1 that is electrically connected to the first trench structure 103-1 and a contact 116-T2 (also known as trench contacts) that is electrically connected to the second trench structure 103-2, a contact 116-G1 that is electrically connected to the first gate structure 110-1 and a contact 116-G2 (also known as gate contacts) that is electrically connected to the second gate structure 110-2.

[0110] In some embodiments, each of the above-described contacts includes a contact barrier layer 117 and a contact conductive layer 118. The contact barrier layer 117 is formed on the sidewalls and bottom surface of the contact hole as a barrier liner, and the contact conductive layer 118 fills the remaining space in the contact hole. In this example, such as Figure 1E-1 , Figure 1E-2As shown, the top surface of the contact (including the top surface of the contact barrier layer 117 and the top surface of the contact conductive layer 118) is substantially coplanar with the top surface of the interlayer dielectric layer 113.

[0111] In some examples, a barrier material (not shown) can be formed on the interlayer dielectric layer 113 by a deposition process, and the barrier material is isotropically deposited in the contact hole; then a conductive material (not shown) is deposited on top of the barrier material layer, and the conductive material fills the remaining space in the contact hole. Next, the excess portions of the conductive material and barrier material above the interlayer dielectric layer 113 are removed, for example by etching or other suitable means, to form a contact barrier layer 117 and a contact conductive layer 118 in the contact hole.

[0112] In some embodiments, the material of the contact barrier layer 117 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), cobalt tungsten phosphide (CoWP), ruthenium (Ru), aluminum oxide (Al2O3), magnesium oxide (MgO), aluminum nitride (AlN), tantalum pentoxide (Ta2O5), silicon dioxide (SiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), magnesium fluoride (MgF2), calcium fluoride (CaF2), other suitable barrier materials, or combinations thereof. In some embodiments, the contact barrier layer 117 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable processes, or combinations thereof.

[0113] In some embodiments, the contact conductive layer 118 may be a single layer or multiple layers, and its conductive material may include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), other suitable metals, or combinations of the foregoing materials. Furthermore, in some embodiments, this conductive material may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, other suitable processes, or combinations of the foregoing processes.

[0114] Furthermore, in some other embodiments where the conductive portion 105 of the trench structure 103 in the epitaxial layer 102 and the gate electrode 112 of the gate structure 110 are polysilicon, a self-aligned silicide (also known as Salicide) process can be performed before forming the contact hole to form a silicide layer (not shown) on the first heavily doped portion 108, the second heavily doped portion 109, the conductive portion 105, and the gate electrode 112, respectively. After forming the contact hole, a conductive layer is filled into the contact hole to contact the underlying silicide layer. The silicide layer can reduce the contact resistance.

[0115] For example, a metal material can be deposited on the first heavily doped portion 108, the second heavily doped portion 109, the conductive portion 105, and the gate electrode 112 using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable processes, or combinations thereof. Then, a first annealing process is performed, for example, using a rapid heating process (RTP), with an annealing temperature in the range of 450°C to 650°C. In some examples, the metal material includes titanium, cobalt, nickel, or other suitable materials. In the lower-temperature first annealing process, the metal material reacts with the silicon in the first heavily doped portion 108, the second heavily doped portion 109, the conductive portion 105, and the gate electrode 112 to first form a high-resistivity metal silicide. Subsequently, a higher-temperature second annealing process is performed, with an annealing temperature greater than 750°C, to convert the high-resistivity metal silicide into a low-resistivity metal silicide, forming a metal silicide layer. Taking titanium as an example, after the first annealing treatment, a high-resistivity Ti2Si state is formed, and then the second annealing treatment transforms the high-resistivity Ti2Si state into a low-resistivity TiSi2 state. After forming the contact hole, a conductive layer is filled into the contact hole to contact the underlying metal silicide layer. Since this example forms a continuous metal silicide layer on the entire top surface of the first heavily doped portion 108 and the second heavily doped portion 109, the contact holes on the first heavily doped portion 108 and the second heavily doped portion 109 can be placed at any position, such as corresponding to the first heavily doped portion 108, the second heavily doped portion 109, or the position between the first heavily doped portion 108 and the second heavily doped portion 109. The subsequently formed contact 116-S can be well electrically connected to the first heavily doped portion 108 and the second heavily doped portion 109.

[0116] After the contact elements are formed, for example Figure 1E-1 , Figure 1E-2The contacts 116-S, 116-T1, 116-T2, 116-G1, and 116-G2 shown can be used for subsequent processes of other components. According to some embodiments, a metal layer (not shown) is formed over the interlayer dielectric layer 113 and the contacts. The metal layer covers the contacts and is in physical and electrical contact with them; therefore, the metal layer is electrically connected to the first heavily doped portion 108, the second heavily doped portion 109, and the well 106 through the contacts.

[0117] In some embodiments, the metal layer may comprise copper, silver, gold, aluminum, tungsten, other suitable metallic materials, or combinations thereof. In some embodiments, the material of the metal layer is the same as the material of the contact. In some other embodiments, the material of the metal layer is different from the material of the contact. According to some embodiments, the metal layer can be formed on the contact by a deposition process. In some embodiments, the deposition process may be physical vapor deposition, chemical vapor deposition, other suitable processes, or combinations thereof. After the metal layer is formed, the process of a semiconductor device 10 is completed. According to some embodiments, this metal layer may serve as the top metal of a semiconductor device 10 for electrical connection with the first heavily doped portion 108, which serves as the source region, and is therefore also referred to as the source metal layer.

[0118] in addition, Figure 4A , Figure 4B These are a cross-sectional view and a top view of a semiconductor device at an intermediate manufacturing stage, respectively. Note that... Figure 4B The interlayer dielectric layer on the epitaxial layer and multiple contacts on the gate structure, trench structure 103, and heavily doped portions serving as source / base are omitted to facilitate a clear top view of the semiconductor device. Furthermore, Figure 4A , Figure 4B Zhongyu Figure 1E-1 , Figure 1E-2 Identical or similar components are referred to by the same or similar reference numbers, and the content regarding the components in the above embodiments can be consulted.

[0119] Figure 4A , Figure 4BThe semiconductor device 40 shown includes an epitaxial layer 402 on a substrate 400, a trench structure 403 in the epitaxial layer 402, a first heavily doped portion 408 and a second heavily doped portion 409 in a well 406, a gate structure 410 and an interlayer dielectric layer 413 on the epitaxial layer 402, and contacts 416 in the interlayer dielectric layer 413 connecting the trench structure 403, the first heavily doped portion 408, the second heavily doped portion 409 and the gate structure 410, respectively. The first heavily doped portion 408 and the second heavily doped portion 409 are the source regions and the bulk regions of the semiconductor device 40, respectively.

[0120] Details regarding the configuration, materials, and fabrication methods of the various components in the semiconductor device 40, such as their relative positions, conductivity types, and dopant implantation, can be found above. Figures 1A to 1E-1 , Figure 1E-2 , Figure 2 The relevant explanations will not be repeated here.

[0121] according to Figure 4B The semiconductor device 40 shown, including the trench structure 403, the first heavily doped portion 408, the second heavily doped portion 409, and the gate structure 410, all extend, for example, in a second direction D2. In other words, the extending directions of the first heavily doped portion 408 and the second heavily doped portion 409 (e.g., the second direction D2) are substantially parallel to the extending direction of the gate structure 410. Furthermore, as... Figure 4B As shown, a strip-shaped second heavily doped region 409 (serving as a base region) is typically provided between two strip-shaped first heavily doped regions 408 (serving as source regions). This means that three strip-shaped heavily doped regions 408 and 409 need to be placed in the space between two adjacent gate structures 410 separated by a distance d4 in the first direction D1.

[0122] However, the width of each heavily doped portion of the first heavily doped portion 408 and the second heavily doped portion 409 in the first direction D1 is related to the capability of the photolithography etching process. In other words, the width of the first heavily doped portion 408 and the second heavily doped portion 409 is also limited by the capability of the photolithography etching process, thus preventing further reduction in the distance d4 between two adjacent gate structures 410 after reaching a certain distance. The embodiments disclosed herein mainly propose to arrange the first heavily doped portion 108 and the second heavily doped portion 109 alternately in the second direction D2, thereby shortening the distance d1 between two adjacent gate structures 110 in the first direction D1, thereby reducing the cell pitch of the semiconductor device fabricated on the wafer, and improving the yield of the fabricated semiconductor device.

[0123] Therefore, compared to Figure 4B Semiconductor device 40 and Figure 2 Semiconductor device 10, Figure 2 The distance d1 between two adjacent gate structures 110 in the first direction D1 is significantly smaller than that between the two adjacent gate structures 110 in the first direction D1. Figure 4B The distance d4 between two adjacent gate structures 410 in the first direction D1. For example, the distance d4 that would normally require three strip-shaped heavily doped portions 408 and 409 may, in some embodiments, only require the distance of one strip-shaped heavily doped portion; that is, the distance d1 is less than the distance d4, or the distance d1 is less than or equal to 1 / 3 of the distance d4.

[0124] Furthermore, this disclosure is not limited to the component configuration exemplified by the semiconductor device described above. According to some other embodiments, another trench structure may be added in the epitaxial layer, and this trench structure passes through the well 106.

[0125] Figure 5A , Figure 5B These are, respectively, a cross-sectional schematic diagram and a top view of a semiconductor device at an intermediate manufacturing stage according to some embodiments of this disclosure. Note that, Figure 5B The interlayer dielectric layer on the epitaxial layer and multiple contacts on the gate structure and trench structure are omitted to facilitate a clear top view of the semiconductor device 50.

[0126] Furthermore, Figure 5A , Figure 5B Zhongyu Figure 1E-1 , Figure 1E-2 Identical or similar components use the same or similar reference numerals, and details of the configuration, materials, and manufacturing methods of the various components in the semiconductor device 50, such as relative positions, conductivity types, and dopant implantation, can be found in the above description. Figures 1A to 1E-1 , Figure 1E-2 , Figure 2 The relevant descriptions of the components will not be repeated here.

[0127] According to some embodiments, Figure 5A , Figure 5B The semiconductor device 50 shown includes an epitaxial layer 102 on a substrate 100, a trench structure 103 in the epitaxial layer 102 (including a first trench structure 103-1, a second trench structure 103-2, and a second trench structure 103-3), a lightly doped portion 107, a first heavily doped portion 108 and a second heavily doped portion 109 alternately disposed in a well 106 along a second direction D2, a gate structure 110 on the epitaxial layer 102 (including a first gate structure 110-1 and a second gate structure 110-2), and an interlayer dielectric layer 113.

[0128] The semiconductor device 50 also includes contacts 116-T1, 116-T2, 116-S, 116-G1, and 116-G2, respectively, which connect the first trench structure 103-1, the second trench structure 103-2, the first heavily doped portion 108, the second heavily doped portion 109, the first gate structure 110-1, and the second gate structure 110-2 in the interlayer dielectric layer 113. The first heavily doped portion 108 and the second heavily doped portion 109 are the source regions and the bulk regions of the semiconductor device 50, respectively.

[0129] According to some embodiments, similar to the arrangement of the first trench structure 103-1 and the second trench structure 103-2, the third trench structure 103-3 extends from the top surface 102a of the epitaxial layer 102 in a third direction D3 and passes through the well 106. In this example, the third trench structure 103-3 extends along a second direction D2, in the same direction as the first trench structure 103-1 and the second trench structure 103-2. Furthermore, the third trench structure 103-3 is spaced apart from the first trench structure 103-1 and the second trench structure 103-2 by a distance d5 in the first direction D1.

[0130] Furthermore, in some embodiments, the third trench structure 103-3 may have a similar profile and contain the same material as the first trench structure 103-1 and the second trench structure 103-2. However, in some other embodiments, such as Figure 5A , Figure 5B As shown, the third trench structure 103-3 can also be a split-gate trench structure. This disclosure does not impose any restrictions on this.

[0131] According to some embodiments, such as Figure 5B As shown, the third trench structure 103-3 includes an insulating liner 104-3 and a conductive filler layer 105-3. The conductive filler layer 105-3 includes a conductive lower portion 105-3L and a conductive upper portion 105-3U, which are separated from each other by a portion of the insulating liner 104-3. Furthermore, in some embodiments, the insulating layers 104 of the first trench structure 103-1 and the second trench structure contain the same material as the insulating liner 104-3 of the third trench structure 103-3; the conductive portions 105 of the first trench structure 103-1 and the second trench structure contain the same material as the conductive lower portion 105-3L and the conductive upper portion 105-3U of the third trench structure 103-3.

[0132] In some embodiments, such as Figure 5BAs shown, if viewed from above the substrate 100, the extension directions (e.g., the first direction D1) of the first heavily doped portion 108 and the second heavily doped portion 109 are perpendicular to the extension direction (e.g., the second direction D2) of the second trench structure.

[0133] Furthermore, according to some embodiments, such as Figure 5B As shown, except that the first heavily doped portion 108 and the second heavily doped portion 109 are alternately arranged along the second direction D2 (e.g., along the extension direction of a channel width of the semiconductor device), the first heavily doped portion 108 and the second heavily doped portion 109 extend along the first direction D1 and pass through the third trench structure 103-3.

[0134] In summary, according to the semiconductor device and its formation method proposed in some embodiments of this disclosure, a first heavily doped portion and a second heavily doped portion can be alternately arranged on one side of a planar gate structure along the extension direction of the gate structure (i.e., the second direction D2 in the figure), wherein the first heavily doped portion and the second heavily doped portion have different conductivity types. In some embodiments where the semiconductor device is a VDMOS element, the first heavily doped portion and the second heavily doped portion can serve as the source region and base region of the VDMOS element, respectively. As mentioned above, the semiconductor device with alternating first and second heavily doped portions proposed in the embodiments can overcome the limitation on the width of the first and second heavily doped portions by the photolithography etching process, thereby reducing the distance between two adjacent gate structures 110 in a direction different from the extension direction of the gate structure (i.e., the first direction D1 in the figure). Therefore, by applying the semiconductor device and its formation method of some embodiments of this disclosure, the cell pitch of the semiconductor device fabricated on the wafer can be reduced, thereby increasing the total number of semiconductor devices on the wafer and improving the yield of the fabricated semiconductor device.

[0135] Furthermore, the semiconductor device formation method proposed in this disclosure embodiment can form alternating first and second doped regions through processes compatible with existing technologies. Therefore, it also offers advantages such as simplified processes, the ability to be performed using existing equipment, and minimal increase in manufacturing costs. Moreover, the embodiments of this invention are applicable to the fabrication of miniaturized or micro-sized semiconductor devices, thereby increasing the density of semiconductor devices fabricated on wafers and increasing the total number of semiconductor devices on a wafer. Therefore, the embodiments of this invention can reduce the production cost and energy consumption of manufacturing a single semiconductor device, thereby reducing carbon emissions per unit of semiconductor device production. Furthermore, since the semiconductor device and its formation method of this invention can improve device yield and reduce material and energy waste during manufacturing, the embodiments of this invention also provide green semiconductor technology.

[0136] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand, from the disclosure of some embodiments of this disclosure, current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first type of conductivity; An epitaxial layer is formed on the substrate, and the epitaxial layer has the first conductivity type; A trench structure extends from the top surface of the epitaxial layer into the epitaxial layer, the trench structure including a conductive portion and an insulating layer covering the sidewalls and bottom surface of the conductive portion; A well extends from the top surface of the epitaxial layer into the epitaxial layer, and the well has a second conductivity type, wherein the well is spaced apart from the trench structure in a first direction, and the well extends in a second direction, the second direction being different from the first direction; At least one first heavily doped portion and at least one second heavily doped portion are formed in the well and extend along the first direction, and are alternately arranged in the second direction, wherein the first heavily doped portion has the first conductivity type, and the second heavily doped portion has the second conductivity type; and A gate structure is formed on the top surface of the epitaxial layer and corresponds to the well, wherein the gate structure extends along the second direction.

2. The semiconductor device as claimed in claim 1, characterized in that, The first heavily doped region is the source region, and the second heavily doped region is the base region.

3. The semiconductor device as claimed in claim 1, characterized in that, The first heavily doped portion is connected to the second heavily doped portion in the second direction, and the first sidewall of the first heavily doped portion abuts against the second sidewall of the second heavily doped portion.

4. The semiconductor device as claimed in claim 3, characterized in that, Including: A lightly doped portion extends in the second direction, and the lightly doped portion has the first conductivity type. The first sidewall of the first heavily doped portion and the second sidewall of the second heavily doped portion are perpendicular to the extending direction of the lightly doped portion.

5. The semiconductor device as claimed in claim 1, characterized in that, One channel width of the semiconductor device extends in the second direction.

6. The semiconductor device as claimed in claim 1, characterized in that, It includes a plurality of first heavily doped portions and a plurality of second heavily doped portions alternately arranged along the second direction.

7. The semiconductor device as claimed in claim 6, characterized in that, Including: A lightly doped portion extends in the second direction, and the lightly doped portion has the first conductivity type. The lightly doped portion is connected to the first heavily doped portion and the second heavily doped portion, which are alternately arranged.

8. The semiconductor device as claimed in claim 7, characterized in that, One of the second heavily doped regions is surrounded by two adjacent first heavily doped regions and the lightly doped region.

9. The semiconductor device as claimed in claim 1, characterized in that, The first heavily doped portion has a first length in the first direction, and the second heavily doped portion has a second length in the first direction, wherein the first length is greater than the second length.

10. The semiconductor device as claimed in claim 1, characterized in that, The gate structure is one side of the first gate structure corresponding to the well, and the semiconductor device further includes: A second gate structure is formed on the top surface of the epitaxial layer, corresponding to the other side of the well. The second gate structure extends along the second direction, and the second gate structure is separated from the first gate structure by a first distance in the first direction.

11. The semiconductor device as claimed in claim 10, characterized in that, The two opposite ends of the first heavily doped portion extend below the adjacent sidewalls of the first gate structure and the second gate structure, respectively, and partially overlap with the first gate structure and the second gate structure.

12. The semiconductor device as claimed in claim 10, characterized in that, The two opposite ends of the second heavily doped portion extend below the adjacent sidewalls of the first gate structure and the second gate structure, respectively.

13. The semiconductor device as claimed in claim 10, characterized in that, The first heavily doped portion has a first length in the first direction, and the first length is greater than the first distance between the second gate structure and the first gate structure.

14. The semiconductor device as claimed in claim 10, characterized in that, The second heavily doped portion has a second length in the first direction, and the second length is equal to the first distance between the second gate structure and the first gate structure.

15. The semiconductor device as claimed in claim 10, characterized in that, The trench structure is a first trench structure, and the semiconductor device further includes: A second trench structure extends upward from the top surface of the epitaxial layer and through the well, wherein the second trench structure extends along the second direction with the first trench structure and is spaced apart by a second distance in the first direction.

16. The semiconductor device as claimed in claim 15, characterized in that, Viewed from above the substrate, the extension directions of the first heavily doped portion and the second heavily doped portion are respectively perpendicular to one extension direction of the second trench structure.

17. The semiconductor device as claimed in claim 15, characterized in that, The first heavily doped portion and the second heavily doped portion extend along the first direction and pass through the second trench structure.

18. The semiconductor device as claimed in claim 15, characterized in that, The second trench structure includes a conductive filling layer and an insulating liner covering the sidewalls and bottom surface of the conductive filling layer.

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