Shield gate trench power MOSFET and preparation method thereof

Abstract

The invention discloses a shield gate trench power MOSFET and a preparation method thereof, the shield gate trench power MOSFET comprises a first epitaxial layer, a plurality of trench structures, a first doped region, a second epitaxial layer, a second doped region, a dielectric layer, a metal layer and at least two third doped regions, the trench structures are arranged and distributed in the first epitaxial layer; the first doped region is located in the first epitaxial layer between the adjacent groove structures, and the two sides of the first doped region are in contact with the outer side surfaces of the groove structures; the second epitaxial layer is located in the first doped region, and the bottom surface of the second epitaxial layer is in contact with the upper surface of the first epitaxial layer; the second doped region is located on the upper surface of the first doped region, and the at least two third doped regions are arranged in the first epitaxial layer right below the second epitaxial layer from top to bottom and located in the middle positions of the adjacent groove structures. According to the invention, two additional third doped regions are introduced into the first epitaxial layer between two traditional groove structures, so that the electric field of the middle section can be further pulled up to improve the breakdown voltage of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor devices, and particularly relates to a shield gate trench power MOSFET and a preparation method thereof. BACKGROUND

[0002] The shielding gate MOSFET realizes the performance close to the physical limit of silicon-based materials in the medium and low voltage application field, and its structure is as shown in the figure. Figure 1 The structure fully utilizes the charge balance principle, and only needs to use a thinner and lower resistivity epitaxial layer to realize a higher withstand voltage capacity, thereby effectively reducing the on-resistance of the device.

[0003] However, unlike the super junction structure which realizes charge balance by simply arranging PN symmetrically to form an ideal electric field distribution, the shielding gate trench structure mainly realizes charge balance through the field plate mechanism, so the electric field intensity in the middle region of the structure is often low, as shown in the figure. Figure 1 The actual 1 curve electric field distribution is poorer than the ideal curve electric field distribution. At present, how to effectively improve the electric field intensity in the middle region has become one of the key problems widely concerned and researched in the technical field. SUMMARY

[0004] In order to solve the above problems, the present application provides a method for increasing the breakdown voltage of a shielding gate trench power MOSFET, which introduces two third doped regions in the first epitaxial layer between adjacent trenches, and adds a second epitaxial layer with a lower concentration than the first doped region above the third doped region, so as to increase the electric field intensity in the middle field region, thereby realizing a substantial increase in the breakdown voltage of the device.

[0005] The main technical scheme adopted in the present application is: A shielding gate trench power MOSFET, comprising: A first epitaxial layer having a first conductivity type; A plurality of trench structures arranged and distributed in the first epitaxial layer, and the upper surface of each trench structure is flush with the upper surface of the first epitaxial layer; A first doped region located in the first epitaxial layer between adjacent trench structures, and the two sides of the first doped region are in contact with the outer sides of the trench structures, and the first doped region has a second conductivity type; A second epitaxial layer located in the first doped region, and the bottom surface of the second epitaxial layer is in contact with the upper surface of the first epitaxial layer, and the second epitaxial layer has a second conductivity type; a second doped region on the upper surface of the first doped region and in contact with the lateral surface of the trench structure, the upper surface of the second doped region being flush with the upper surface of the trench structure, the second doped region having the first conductivity type; a dielectric layer on the upper surface of the second doped region and the upper surface of the trench structure; a metal layer on the upper surface of the dielectric layer and in contact with the upper surface of the second epitaxial layer through the dielectric layer and the second doped region; at least two third doped regions arranged from top to bottom in the first epitaxial layer directly below the second epitaxial layer and located at the middle of the adjacent trench structures, the third doped regions having the second conductivity type.

[0006] Preferably, the trench structure comprises a bottom oxide layer, a source polysilicon, a gate oxide layer and a gate polysilicon, the bottom oxide layer is in the first epitaxial layer to form a trench, the source polysilicon fills in the trench, and the upper surfaces of the bottom oxide layer and the source polysilicon are flush, the gate oxide layer covers the two lateral surfaces and the bottom surface of the gate polysilicon, and the upper surfaces of the gate oxide layer and the gate polysilicon are flush with the upper surface of the first epitaxial layer, the gate oxide layer is on the upper surfaces of the bottom oxide layer and the source polysilicon.

[0007] Preferably, the thickness of the first epitaxial layer is 5-12um, and the concentration is 1e16-5e16cm -3 .

[0008] Preferably, the concentration of the second epitaxial layer is 1e15-3e15cm -3 .

[0009] Preferably, the thickness of the bottom oxide layer is 0.3-0.7um.

[0010] Preferably, the thickness of the gate oxide layer is 0.05-0.1um.

[0011] Preferably, the doping concentration of the first doped region is 5e12-5e13cm -2 ; the doping concentration of the second doped region is 5e14-5e16cm -2 ; the doping concentration of the third doped region is 2e12-5e12cm -2 .

[0012] Preferably, the upper surface of the second epitaxial layer is lower than the upper surface of the first doped region.

[0013] A preparation method of a shielded gate trench power MOSFET, the specific steps are as follows: After the trench structure, the first doped region, the second doped region and the dielectric layer are sequentially completed on the first epitaxial layer, the dielectric layer and the first epitaxial layer are etched by a photoetching process respectively until the bottom of the first doped region, and the metal contact hole is completed; At least two third doped regions are formed in the first epitaxial layer at the bottom of the metal contact hole by at least two times of ion implantation with different energies subsequently; Then, a low-temperature process is adopted to fill the second epitaxial layer in the metal contact hole, so that the upper surface of the second epitaxial layer is lower than the bottom surface of the second doped region; Finally, a metal layer is deposited on the whole structure to complete the electrode contact and interconnection, and the final device is formed.

[0014] Preferably, the two third doped regions arranged above and below are formed by ion implantation with an energy of 200 keV and 450 keV respectively.

[0015] Beneficial effects: The present application provides a shield gate trench power MOSFET and a preparation method thereof, which has the following advantages: (1) The present application introduces two additional third doped regions in the first epitaxial layer between the traditional two-trench structure, which can further improve the electric field intensity in the middle region, thereby improving the breakdown voltage of the device.

[0016] (2) Unlike the process of the super-junction structure which is completed by multiple doping methods from the initial epitaxial growth stage, the present application completes the preparation of the third doped region by high-energy ion implantation after forming the metal contact hole, which avoids the long-time high-temperature process in the middle and prevents the third doped region from excessive thermal diffusion, thereby affecting the current path and ensuring low on-resistance. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 for the structure and electric field distribution of the existing power metal-oxide-semiconductor field-effect transistor; Figure 2 for the structure and electric field distribution of the power metal-oxide-semiconductor field-effect transistor of embodiment 1; Figure 3 for the structure schematic diagram of step 1 of embodiment 1; Figure 4 for the structure schematic diagram of step 2 of embodiment 1; Figure 5 for the structure schematic diagram of step 3 of embodiment 1; Figure 6 for the structure schematic diagram of step 4 of embodiment 1; In the figure: the first epitaxial layer 100, the bottom oxide layer 101, the source polysilicon 102, the gate oxide layer 103, the gate polysilicon 104, the first doped region 105, the second doped region 106, the dielectric layer 107, the third doped region 108, the second epitaxial layer 109, the metal layer 110, the metal contact hole 111. DETAILED DESCRIPTION

[0018] In order to make the person skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application are described clearly and completely below. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should be within the scope of protection of the present application. Embodiment 1

[0019] In this embodiment 1, taking the first conductivity type as N type and the second conductivity type as P type as an example, a shielding trench power MOSFET structure with increased breakdown voltage is disclosed, as shown in Figure 2 , which comprises: The first epitaxial layer 100 is an N-type epitaxial layer. A plurality of trench structures are arranged and distributed in the first epitaxial layer 100, and the upper surface of each trench structure is flush with the upper surface of the first epitaxial layer 100. The first doped region 105 is a P-type doped region, located in the first epitaxial layer 100 between adjacent trench structures, and the two sides of the first doped region 105 are in contact with the outer side of the trench structure. The second epitaxial layer 109 is a P-type epitaxial layer, located in the first doped region 105, and the bottom surface of the second epitaxial layer 109 is in contact with the first epitaxial layer 100, and the upper surface of the second epitaxial layer 109 is lower than the upper surface of the first doped region 105. The second doped region 106 is an N-type doped region, located on the upper surface of the first doped region 105, and the two sides of the second doped region 106 are in contact with the outer side of the trench structure, and the upper surface of the second doped region 106 is flush with the upper surface of the trench structure. The dielectric layer 107 is located on the upper surface of the second doped region 106 and the upper surface of the trench structure. The metal layer 110 is located on the upper surface of the dielectric layer 107, and sequentially passes through the dielectric layer 107 and the second doped region 106 to contact the upper surface of the second epitaxial layer 109. And two third doped regions 108 are P-type doped regions, arranged and arranged from top to bottom in the first epitaxial layer 100 directly below the second epitaxial layer 109, and located between adjacent trench structures.

[0020] In this embodiment 1, the trench structure includes a bottom oxide layer 101, a source polysilicon 102, a gate oxide layer 103, and a gate polysilicon 104. The bottom oxide layer 101 is located within the first epitaxial layer 100, forming a trench. The source polysilicon 102 fills the trench, and the upper surfaces of the bottom oxide layer 101 and the source polysilicon 102 are flush. The gate oxide layer 103 covers both sides and the bottom surface of the gate polysilicon 104, and the upper surfaces of the gate oxide layer 103 and the gate polysilicon 104 are flush with the upper surface of the first epitaxial layer 100. The gate oxide layer 103 is located on the upper surface of the bottom oxide layer 101 and the source polysilicon 102.

[0021] In Example 1, the thickness of the first epitaxial layer 100 is 5-12 μm, the thickness of the bottom oxide layer 101 is 0.3-0.7 μm, the thickness of the gate oxide layer 103 is 0.05-0.1 μm, the thickness of the dielectric layer 107 is 0.8-1.5 μm, and the thickness of the metal layer 110 is 4-5 μm.

[0022] In this embodiment 1, the concentration of the first epitaxial layer 100 is 1e16~5e16cm. -3 The concentration of the second epitaxial layer 109 is 1e15~3e15cm. -3 .

[0023] In this embodiment 1, the doping concentration of the first doped region 105 is 5e12~5e13 cm⁻¹. -2 The doping concentration of the second doped region 106 is 5e14~5e16cm. -2 The doping concentration of the third doped region 108 is 2e¹² to 5e¹² cm⁻¹. -2 .

[0024] In this embodiment 1, the metal layer 110 is preferably an aluminum metal layer.

[0025] The specific design principle of this embodiment 1 is as follows: the electric field intensity reaches a local peak at each PN junction, therefore, a high electric field region can be generated by introducing multiple PN junctions. Figure 1 The actual electric field distribution curve (actual curve 1) is used for adjustment. This design causes the electric field, which originally decreases longitudinally, to be raised again at the PN junction, thereby obtaining... Figure 2 The actual electric field distribution shown (actual curve 2) is closer to the ideal electric field distribution. Furthermore, the doping concentration of the second epitaxial layer is lower than the overall concentration of the first doped region (in this embodiment 1, the overall concentration of the first doped region is >7e15cm). -3 This can reduce the electric field strength at the interface, thereby increasing the electric field in the rest of the device and achieving an optimized distribution of the overall electric field.

[0026] The specific steps of the preparation method of the shielded gate trench power metal-oxide-semiconductor field-effect crystal described in Example 1 are as follows: Step 1: As Figure 3 As shown, after completing the trench structure, the first doped region 105, the second doped region 106 and the dielectric layer 107 on the first epitaxial layer 100 in sequence, the dielectric layer 107 and the first epitaxial layer 100 are etched by photolithography until the bottom of the first doped region 105, thus completing the metal contact hole 111.

[0027] Step 2: As Figure 4 As shown, two third doped regions 108 are directly formed within the first epitaxial layer 100 at the bottom of the metal contact hole 111 through two ion implantations (P-type ion doping). In this embodiment 1, the implantation energies are 200 keV (upper third doped region 108) and 450 keV (lower third doped region 108), respectively, and the center positions of the doping concentration peaks are approximately 0.5 µm apart longitudinally. In this embodiment 1, the order of the two ion implantations with different energies can be selected according to actual needs.

[0028] Step 3: As Figure 5 As shown, a low-temperature process is used to fill the metal contact hole 111 with a second epitaxial layer 109, so that the upper surface of the second epitaxial layer 109 is lower than the bottom surface of the second doped region 106. Step 4: As Figure 6 As shown, a metal layer 110 is deposited on the entire structure to complete electrode contacts and interconnections, forming the final device.

[0029] In this Example 1, the temperature range of the low-temperature process is 800–1000°C.

[0030] In this embodiment 1, the trench structure, the first doped region 105, the second doped region 106 and the dielectric layer 107 can be completed sequentially on the first epitaxial layer 100 using existing preparation methods. This is a conventional technique and therefore has not been described in detail.

[0031] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A shielded gate trench power MOSFET, characterized in that, include: The first epitaxial layer has a first conductivity type; Several trench structures are arranged and distributed within the first epitaxial layer, and the upper surface of each trench structure is flush with the upper surface of the first epitaxial layer. The first doped region is located in the first epitaxial layer between adjacent trench structures, and the two sides of the first doped region are in contact with the outer surface of the trench structure. The first doped region has a second conductivity type. The second epitaxial layer is located within the first doped region, and the bottom surface of the second epitaxial layer is in contact with the top surface of the first epitaxial layer. The second epitaxial layer has a second conductivity type. The second doped region is located on the upper surface of the first doped region, and the two sides of the second doped region are in contact with the outer surface of the trench structure. The upper surface of the second doped region is flush with the upper surface of the trench structure. The second doped region has a first conductivity type. The dielectric layer is located on the upper surface of the second doped region and the trench structure; A metal layer is located on the upper surface of the dielectric layer and passes through the dielectric layer and the second doped region in sequence to contact the upper surface of the second epitaxial layer; At least two third doped regions are arranged from top to bottom in the first epitaxial layer directly below the second epitaxial layer and located in the middle of adjacent trench structures. The third doped regions have a second conductivity type.

2. The shielded gate trench power MOSFET according to claim 1, characterized in that, The trench structure includes a bottom oxide layer, a source polysilicon, a gate oxide layer, and a gate polysilicon. The bottom oxide layer is located within the first epitaxial layer, forming a trench. The source polysilicon fills the trench, and the top surfaces of the bottom oxide layer and the source polysilicon are flush. The gate oxide layer covers both sides and the bottom surface of the gate polysilicon, and the top surfaces of the gate oxide layer and the gate polysilicon are flush with the top surface of the first epitaxial layer. The gate oxide layer is located on the top surface of the bottom oxide layer and the source polysilicon.

3. The shielded gate trench power MOSFET according to claim 1, characterized in that, The thickness of the first epitaxial layer is 5–12 μm, and the concentration is 1e16–5e16 cm⁻¹. -3 .

4. The shielded gate trench power MOSFET according to claim 1, characterized in that, The concentration of the second epitaxial layer is 1e15 to 3e15 cm⁻¹ -3 .

5. The shielded gate trench power MOSFET according to claim 2, characterized in that, The thickness of the bottom oxide layer is 0.3–0.7 μm.

6. The shielded gate trench power MOSFET according to claim 3, characterized in that, The thickness of the gate oxide layer is 0.05–0.1 μm.

7. The shielded gate trench power MOSFET according to claim 1, characterized in that, The doping concentration of the first doped region is 5e12~5e13cm. -2 The doping concentration of the second doped region is 5e14~5e16cm. -2 The doping concentration of the third doped region is 2e¹² to 5e¹² cm⁻¹. -2 .

8. The shielded gate trench power MOSFET according to claim 1, characterized in that, The upper surface of the second epitaxial layer is lower than the upper surface of the first doped region.

9. A method for fabricating a shielded gate trench power MOSFET, used to fabricate a shielded gate trench power MOSFET as described in any one of claims 1-8, characterized in that, The specific steps are as follows: After completing the trench structure, the first doped region, the second doped region and the dielectric layer on the first epitaxial layer in sequence, the dielectric layer and the first epitaxial layer are etched by photolithography until the bottom of the first doped region to complete the metal contact hole. Subsequently, at least two third doped regions were formed directly in the first epitaxial layer at the bottom of the metal contact hole through at least two ion implantations of different energies. Next, a low-temperature process is used to fill the metal contact hole with a second epitaxial layer, so that the upper surface of the second epitaxial layer is lower than the bottom surface of the second doped region; Finally, a metal layer is deposited over the entire structure to complete the electrode contacts and interconnections, forming the final device.

10. The method for fabricating a shielded gate trench power MOSFET according to claim 9, characterized in that, The two third doped regions, located at the top and bottom, were formed using ion implantation energies of 200 keV and 450 keV, respectively.

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