Image sensor, preparation method thereof and electronic equipment

Abstract

The invention provides an image sensor, a preparation method thereof and electronic equipment. The image sensor includes: a first substrate; each pixel circuit comprises a photodiode and a suspension diffusion region which are arranged on one side of the first substrate and electrically connected, the photodiode is used for generating photo-generated charges in response to incident light, and the suspension diffusion region is used for receiving the photo-generated charges; the plurality of capacitors are arranged on one side of the first substrate, and each capacitor comprises a first polar plate, a second polar plate and a dielectric layer located between the first polar plate and the second polar plate; the first polar plate is electrically connected with the suspension diffusion region, the first polar plate is in a cylinder shape with one end open, and the opening faces the side away from the first substrate; the dielectric layer covers the first polar plate in a conformal manner; the second pole plate is located on the side, away from the first substrate, of the dielectric layer and covers the dielectric layer in a shape follow-up mode. According to the invention, the imaging quality in a high dynamic range scene and the capacitance value and stability of the transverse overflow set capacitor are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular, relates to an image sensor, a preparation method thereof and an electronic device. BACKGROUND

[0002] In recent years, in order to improve the dynamic range of an image sensor (CIS), the industry has developed a lateral overflow integration capacitor (LOFIC) technology, which can achieve a high dynamic range (HDR) in a single exposure without multiple exposures.

[0003] However, the LOFIC capacitor in the related art is similar to an MOSCAP structure, and its capacitance is unstable and changes with voltage and frequency. SUMMARY

[0004] The present application provides an image sensor, a preparation method thereof and an electronic device to solve the technical problem of unstable capacitance in the related art.

[0005] In a first aspect, an embodiment of the present application provides an image sensor, comprising: a first substrate; a plurality of pixel circuits, each pixel circuit comprising a photodiode and a floating diffusion region disposed on one side of the first substrate and electrically connected, the photodiode being configured to generate photo-generated charges in response to incident light, and the floating diffusion region being configured to receive the photo-generated charges; a plurality of capacitors disposed on one side of the first substrate, each capacitor comprising a first plate, a second plate, and a dielectric layer between the first plate and the second plate; the first plate is electrically connected to the floating diffusion region, and the first plate has a shape of a cylinder with an open end, the open end facing away from the first substrate; the dielectric layer conformally covers the first plate; the second plate is located on a side of the dielectric layer away from the first substrate and conformally covers the dielectric layer.

[0006] In some optional embodiments of the present application, the first plate has an inner cavity; the dielectric layer comprises a first covering layer conformally covering the first plate and a second covering layer connected to the first covering layer and extending away from the first plate; the second plate fills the inner cavity and conformally covers the first covering layer and the second covering layer.

[0007] In some optional embodiments of the present application, the first plate comprises a bottom wall and a side wall, the side wall has a cross-sectional shape of a circular ring in a horizontal cross section, and the bottom wall and the side wall are connected to have a shape of a cylinder.

[0008] In some optional embodiments of the present application, the pixel circuit further comprises a transfer transistor and a selection transistor arranged on the side of the first substrate; The transfer transistor is electrically connected with the photodiode and the floating diffusion region respectively, and is configured to transfer the photo-generated charge generated by the photodiode to the floating diffusion region; The selection transistor is electrically connected with the floating diffusion region and the first plate respectively, and is configured to control the connection or disconnection between the floating diffusion region and the first plate.

[0009] In some optional embodiments of the present application, the image sensor further comprises a second substrate, and the pixel circuit further comprises a reset transistor and a source follower transistor; The second substrate is interlacedly bonded with the first substrate; The source or drain of the reset transistor is electrically connected with the first plate, and the gate of the source follower transistor is electrically connected with the floating diffusion region; The reset transistor and the source follower transistor are arranged on the first substrate and located on the side of the capacitor facing the first substrate.

[0010] In some optional embodiments of the present application, the image sensor further comprises: A lens arranged on the side of the photodiode away from the capacitor; Or, A filter and a lens arranged on the side of the photodiode away from the capacitor and sequentially arranged in the direction away from the photodiode, and the orthographic projection of the lens and the filter on the first substrate intersects.

[0011] In a second aspect, the embodiments of the present application provide a preparation method of an image sensor, comprising: Manufacturing a first plate electrically connected with a floating diffusion region of a pixel circuit on the side of a first substrate, and making the first plate into a barrel shape with one end open, and the opening facing away from the first substrate; the pixel circuit comprises a photodiode and a floating diffusion region arranged on the first substrate and electrically connected, the photodiode is configured to generate photo-generated charge in response to incident light, and the floating diffusion region is configured to receive the photo-generated charge; Manufacturing a dielectric layer, and making the dielectric layer conformal to the first plate; Manufacturing a second plate, and making the second plate conformal to the dielectric layer, and the first plate, the dielectric layer and the second plate form a capacitor corresponding to the pixel circuit.

[0012] In some optional embodiments of the present application, before manufacturing the first plate electrically connected with the floating diffusion region of the pixel circuit on the side of the first substrate, the method further comprises: The transfer transistor, the selection transistor, the reset transistor and the source follower transistor of the pixel circuit are fabricated on one side of the first substrate, the photodiode is electrically connected to the floating diffusion region through the transfer transistor, and the gate of the selection transistor and the source follower transistor are electrically connected to the floating diffusion region; The first isolation medium layer covering the first substrate is fabricated. The first interconnection structure penetrating the first isolation medium layer and electrically connected to the transfer transistor, the selection transistor, the floating diffusion region, the reset transistor and the source follower transistor is fabricated. The first electrode is fabricated at the end of each first interconnection structure away from the first substrate.

[0013] In some optional embodiments of the present application, the first plate electrically connected to the floating diffusion region of the pixel circuit is fabricated on one side of the first substrate, and the first plate is in the shape of a cylinder with one end open, and the opening is directed away from the first substrate, comprising: The first initial plate covering the plurality of first electrodes is fabricated. The first initial plate is patterned to form the first plate, the first plate is electrically connected to the first electrode located at the side of the selection transistor away from the first substrate, and the orthographic projection of the first plate on the first substrate intersects the orthographic projection of the selection transistor on the first substrate.

[0014] In some optional embodiments of the present application, the medium layer is fabricated, and the medium layer is conformally covering the first plate, comprising: The dielectric material is grown to form the initial medium layer, the initial medium layer covering the plurality of first electrodes and the first plate; The initial medium layer is patterned to remove the initial medium layer except for covering the first plate and the periphery of the first plate, and the remaining initial medium layer forms the medium layer, the orthographic projection of the medium layer on the first substrate covering the orthographic projection of the first electrode electrically connected to the selection transistor on the first substrate; And, the second plate is fabricated, and the second plate is conformally covering the medium layer, comprising: The second initial plate covering the plurality of first electrodes and the medium layer and filling the inner cavity of the first plate is fabricated. The second initial plate is patterned to remove the second initial plate located outside the orthographic projection of the medium layer on the first substrate, and the remaining second initial plate forms the second plate.

[0015] In some optional embodiments of the present application, after the second plate is fabricated and the second plate is conformally covering the medium layer, further comprising: A second isolation dielectric layer and an interconnect stack are fabricated, which sequentially cover a plurality of first electrodes and second plates; the interconnect stack includes a plurality of second electrodes; at least one first electrode is electrically connected to at least one second electrode through at least one second interconnect structure penetrating the second isolation dielectric layer.

[0016] In some optional embodiments of this application, after fabricating a second insulating dielectric layer and an interconnect stack that sequentially cover a plurality of first electrodes and second plates, the method further includes: Flip the first substrate having interconnected stacks; The interconnect stack on one side of the first substrate is bonded to the second substrate; The side of the first substrate furthest from the interconnect stack is thinned. At least one third via is formed by using through-silicon via (TSV) technology to expose the electrodes in the interconnect stack on the bottom. A third interconnect structure is formed within the third via, and a pad is fabricated on the side of the third interconnect structure away from the second substrate; A lens is fabricated on the side of the first substrate away from the interconnect stack, or a filter and a lens are fabricated sequentially, wherein the orthogonal projection of the lens onto the first substrate intersects at least with the orthogonal projection of the photodiode onto the first substrate.

[0017] Thirdly, embodiments of this application provide an electronic device, including: Such as the image sensor mentioned above; or, An image sensor is prepared using the image sensor preparation method described above.

[0018] The beneficial technical effects of the technical solutions provided in this application include: In this embodiment, a first substrate is used to support multiple pixel circuits and multiple capacitors. The photodiodes of the pixel circuits are electrically connected to a floating diffusion region. The photodiodes generate photocharge in response to incident light, and the floating diffusion region receives the photocharge generated by the photodiodes. The first plate of the capacitor is electrically connected to the floating diffusion region of the corresponding pixel circuit. The capacitor acts as a lateral overflow collection capacitor; when the photocharge exceeds the maximum capacity of the floating diffusion region, the excess photocharge flows into the capacitor, preventing overexposure and ensuring that bright images are clearly displayed in the image, thus improving imaging quality in high dynamic range scenes. Multiple capacitors correspond one-to-one with multiple pixel circuits, ensuring that each pixel circuit has a corresponding lateral overflow collection capacitor.

[0019] The first plate of each capacitor is a cylindrical shape with one open end, and the opening of the first plate faces away from the first substrate. The first plate has an inner wall and an outer wall, making each lateral overflow capacitor a double-layered cylindrical shape. The dielectric layer conformally covers the inner and outer walls of the first plate. The second plate is located on the side of the dielectric layer away from the first substrate and conformally covers the dielectric layer, which increases the corresponding area of ​​the first and second plates of each capacitor, greatly improving the capacitance value. The larger the capacitance value of the lateral overflow capacitor, the greater the amount of charge it can carry, and the greater the amount of charge allowed to overflow from the pixel circuit to the lateral overflow capacitor. This can reduce the impact of excessive brightness of the captured object or excessive photogenerated charge on the pixel circuit, reduce or even avoid the probability of pixel overexposure, and enhance the overall exposure stability of the image sensor. The larger the capacitance value of the lateral overflow capacitor, the greater the amount of charge it can carry, the greater the limit of charge carried by the pixel of the image sensor (well capacity), and the stronger the brightness of the captured object, thereby further increasing the dynamic range.

[0020] This application provides a novel LOFIC CIS structure with a cylindrical capacitor. It uses a cylindrical first plate, and sequentially covers a dielectric layer and a second plate to form a cylindrical capacitor. It creatively adopts a cylindrical DRAM capacitor structure to replace the MOSCAP capacitor in related technologies, thus solving the problem of capacitor instability in related technologies.

[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0022] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the pixel circuit structure of an image sensor provided in an embodiment of this application; Figure 2 A schematic flowchart illustrating a method for fabricating an image sensor according to an embodiment of this application; Figures 3 to 17 The diagram shows the structure of an image sensor fabrication method provided in this application at different stages. Figure 18 This is a schematic diagram of the structure of an image sensor provided in an embodiment of this application.

[0023] Figure label: 100 - Image sensor; 10 - First substrate; 20-pixel circuit; 21-Photodiode; 22-Floating diffusion region; 23-Transfer transistor; 24-Selection transistor; 25-Reset transistor; 26-Source follower transistor; 30-capacitor; 31 - First electrode plate; 311-Opening; 312-Inner cavity; 313-Bottom wall; 314-Side wall; 315-First initial electrode plate; 32 - Second electrode plate; 321 - Second initial electrode plate; 33-Dielectric layer; 331 - First cover layer; 332 - Second cover layer; 333 - Initial dielectric layer; 40 - Second substrate; 41 - Bonding layer; 51-Lens; 52-Filter; 61-First isolation dielectric layer; 62-Second isolation dielectric layer; 63-Fourth isolation dielectric layer; 71-First interconnect structure; 72-First electrode; 73-Second interconnect structure; 74-First via; 75-Third isolation dielectric layer; 76-Second via; 80 - Interconnect stack; 81 - Second electrode; 82 - Fourth interconnect structure; 83 - Third electrode; 84 - Fifth interconnect structure; 85 - Fourth electrode; 91-Third via; 92-Third interconnect structure; 93-Pad; 110 - Medium structure. Detailed Implementation

[0024] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0025] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in the specification of this application means the presence of the stated features, integers, steps, operations, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" can be implemented as "A," or as "B," or as "A and B."

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0027] The relevant technologies are explained below: First, let's introduce and explain several terms used in this application: Dynamic range (DR), simply put, describes the range of light intensity distribution in an image, from the darkest shadows to the brightest highlights. It's usually expressed in decibels (dB). A higher DR is better. For example, describing a scene as having a wide dynamic range means that the exposure values ​​between shadows and highlights in that scene differ greatly, resulting in high contrast and rich detail. Generally, the human eye can see a range of about 10^5, but typical monitors, such as cameras, can only represent 256 (2^8 orders of magnitude) different brightness levels.

[0028] Dynamic range can be viewed as the ratio of full-well capacity (FWC) to transient noise (TN). Full-well capacity refers to the maximum charge stored in a single pixel before saturation. Transient noise refers to the unexpected changes in brightness and color of the image caused by fluctuations in the numerical values ​​generated by individual pixels during the conversion of incident photons into electrons. The dynamic range calculation formula is as follows: =

[0029] According to the dynamic range calculation formula, the dynamic range can be optimized by increasing the full-well capacity or reducing transient noise.

[0030] In recent years, in order to improve the dynamic range of image sensors (CIS), the industry has developed lateral overflow integration capacitor (LOFIC) technology, which can achieve high dynamic range (HDR) in a single exposure without the need for multiple exposures.

[0031] LOFIC (Low-Intensity Focused Light) is a technique that improves the dynamic range of a sensor by altering the circuit structure of pixels. In ordinary sensors, photodiodes (PDs) and floating diffusion regions (FDs) are used to carry electrons generated by the photodiodes when illuminated. When the brightness of the captured object is too strong, a large amount of charge is concentrated in a single pixel, resulting in an overexposed image. In pixels with LOFIC, a charge storage (CS) capacitor is added. When the charge exceeds the maximum capacity that the pixel can hold (maximum well capacity), the excess charge flows into the CS, preventing overexposure and allowing bright scenes to be clearly displayed in the image.

[0032] However, in related technologies, LOCIC capacitors are all similar to MOSCAP structures, and their capacitance is unstable, with the capacitance value varying with changes in voltage and frequency.

[0033] The image sensor, its fabrication method, and electronic device provided in this application are intended to solve the aforementioned technical problems in related technologies.

[0034] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0035] This application provides an image sensor 100, the pixel circuit structure of which is shown in the schematic diagram below. Figure 1 As shown, compared with the traditional 4T (Transistor) CIS circuit, the CIS with LOFIC provided in this application embodiment adds a select transistor (SG) and a lateral overflow collection capacitor (LOFIC).

[0036] Optionally, such as Figure 1 As shown in the embodiments of this application, the pixel circuit structure of the image sensor 100 includes a photodiode (PD), a transfer gate (TX / TG), a floating diffusion region (FD), a storage gate (SG), a lateral overflow collection capacitor (LOFIC), a reset transistor (RST), a source follower transistor (SF), and a row select transistor (RS).

[0037] Optionally, such as Figure 1 As shown in the embodiment of this application, one end of the photodiode (PD) is grounded, and the other end is electrically connected to one of the source and drain of the transfer transistor (TX / TG). The gate of the transfer transistor (TX / TG) receives the transfer control signal, and the other of the source and drain of the transfer transistor (TX / TG) is electrically connected to the floating diffusion region (FD).

[0038] The floating diffusion region (FD) is electrically connected to one of the source and drain of the select transistor (SG). The gate of the select transistor (SG) receives the select control signal. The other of the source and drain of the select transistor (SG) is electrically connected to the lateral overflow collection capacitor (LOFIC). Similarly, one of the source and drain of the reset transistor (RST) is electrically connected to the lateral overflow collection capacitor (LOFIC). The gate of the reset transistor (RST) receives the reset control signal. The other of the source and drain of the reset transistor (RST) is electrically connected to the power supply voltage (e.g., VDD).

[0039] The floating diffusion region (FD) is electrically connected to the gate of the source follower transistor (SF), one of the source and drain of the source follower transistor (SF) is electrically connected to one of the source and drain of the row select transistor (RS), and the other of the source and drain of the source follower transistor (SF) is electrically connected to the power supply voltage (such as VDD).

[0040] The gate of the row select transistor (RS) is electrically connected to the row line (ROW), and the other of the source and drain of the RS is electrically connected to the column line (COL). The RS is used to control the signal output of the pixel circuits, allowing control over which pixel circuit's signal is output first and which pixel circuit's signal is output later.

[0041] Optionally, in the embodiments of this application, such as Figure 1 As shown, before illumination, the reset transistor (RST) and transfer transistor (TX / TG) are turned on to release the electrons in the photodiode (PD) region. During illumination, all transistors are turned off, and the photodiode (PD) generates photocharge in response to the incident light. During readout, the transfer transistor (TX / TG) is turned on to transfer the charge stored in the photodiode (PD) region to the floating diffuser (FD). After the transfer, the transfer transistor (TX / TG) is turned off and waits for the next illumination. When the photocharge exceeds the maximum capacity that the floating diffuser (FD) can hold, the select transistor (SG) is turned on, allowing the excess photocharge to flow into the lateral overflow collection capacitor (LOFIC). To obtain a high full-well capacity, the lateral overflow collection capacitor (LOFIC) can collect electrons that overflow from the photodiode during exposure until the signal is readout. The charge signal in the floating diffuser (FD) region is then used to adjust the source follower transistor (SF), converting the charge into voltage, and outputting current to the analog-to-digital converter circuit through the row select transistor (RS).

[0042] Optionally, in this embodiment, a high conversion gain mode (HCG) signal is used for low-light scenes, and only the FD readout voltage is used during reading. The induced charges of the photodiode and the levitated diffusion region are mixed, and the mixed signal is read out. For high-light scenes, a low conversion gain mode (LCG) signal is used, and both FD and LOFIC readout voltages are used during reading. By collecting low-flux signals with high conversion gain and collecting high-flux signals with low conversion gain, the dynamic range can be extended, thus achieving HDR.

[0043] Compared to pixels without capacitors, the dynamic range expansion of pixels after adding LOFIC is theoretically greater. C FD C is the capacitance value of the suspended diffusion region. CS The capacitance value is to increase the lateral overflow collection capacitance, but according to relevant studies, the actual improvement in dynamic range with LOFIC CIS is higher than this theoretical calculation result.

[0044] A schematic diagram of the structure of the image sensor 100 provided in this application embodiment is shown below. Figure 3 , Figure 16 and Figure 17 As shown, the image sensor 100 includes: a first substrate 10, a plurality of pixel circuits 20 and a plurality of capacitors 30.

[0045] The pixel circuit 20 includes a photodiode 21 and a floating diffusion region 22 disposed on one side of the first substrate 10 and electrically connected thereto. The photodiode 21 is used to generate photocharge in response to incident light, and the floating diffusion region 22 is used to receive the photocharge. A plurality of capacitors 30 are disposed on one side of the first substrate 10. Each capacitor 30 includes a first electrode 31, a second electrode 32, and a dielectric layer 33 located between the first electrode 31 and the second electrode 32.

[0046] The first electrode plate 31 is electrically connected to the levitation diffusion region 22. The first electrode plate 31 is cylindrical with one end open, and the opening 311 (as shown in the image) Figures 7 to 9 The first electrode 31 is oriented away from the first substrate 10; the dielectric layer 33 conformally covers the first electrode 31; the second electrode 32 is located on the side of the dielectric layer 33 away from the first substrate 10 and conformally covers the dielectric layer 33.

[0047] In this embodiment, the first substrate 10 is used to support multiple pixel circuits 20 and multiple capacitors 30. The photodiode 21 of the pixel circuit 20 is electrically connected to the floating diffusion region 22. The photodiode 21 generates photocharge in response to incident light, and the floating diffusion region 22 receives the photocharge generated by the photodiode 21. The first plate 31 of the capacitor 30 is electrically connected to the corresponding floating diffusion region 22 of the pixel circuit 20. The capacitor 30 acts as a lateral overflow collection capacitor (LOFIC). When the photocharge exceeds the maximum capacity that the floating diffusion region 22 can originally bear, the excess photocharge flows into the capacitor 30, preventing overexposure and ensuring that bright images are clearly displayed in the image, thus improving the imaging quality in high dynamic range scenes.

[0048] Multiple capacitors 30 correspond one-to-one with multiple pixel circuits 20, so that each pixel circuit 20 has a corresponding lateral overflow collection capacitor.

[0049] The first electrode 31 of each capacitor 30 is cylindrical with one end open, and the opening 311 of the first electrode 31 faces away from the first substrate 10. The first electrode 31 has an inner wall and an outer wall, so that each lateral overflow collection capacitor is a double-layered cylindrical shape. The dielectric layer 33 conformally covers the inner wall and outer wall of the first electrode 31. The second electrode 32 is located on the side of the dielectric layer 33 away from the first substrate 10 and conformally covers the dielectric layer 33, which increases the corresponding area of ​​the first electrode 31 and the second electrode 32 of each capacitor 30, greatly improving the capacitance value; the capacitance value of the lateral overflow collection capacitor. The larger the value of the lateral overflow capacitor, the greater the amount of charge it can carry. This allows for a greater amount of charge to overflow from the pixel circuit to the lateral overflow capacitor, reducing the impact of excessively bright objects or excessive photogenerated charges on the pixel circuit. This reduces or even eliminates the chance of pixel overexposure, thus enhancing the overall exposure stability of the image sensor. The larger the value of the lateral overflow capacitor, the greater the amount of charge it can carry. This increases the limit of charge that a pixel in the image sensor can carry (well capacity), allowing for the capture of brighter objects and further increasing the dynamic range.

[0050] This application provides a novel LOFIC CIS structure with a cylindrical capacitor. It uses a cylindrical first electrode 31, and sequentially covers a dielectric layer 33 and a second electrode 32 to form a cylindrical capacitor 30. It creatively adopts a cylindrical DRAM capacitor structure to replace the MOSCAP capacitor in related technologies, thus solving the problem of capacitor instability in related technologies.

[0051] In some optional embodiments of this application, the diameter and height of the first electrode plate 31 can be adjusted according to actual needs, and the dielectric layer 33 and the second electrode plate 32 sequentially cover the first electrode plate 31, thereby making the diameter and height of the capacitor 30 adjustable, which can greatly improve the capacitance value and stability of the lateral overflow collection capacitor.

[0052] In some optional embodiments of this application, such as Figure 12 As shown, the first electrode plate 31 is a vertical cylinder, and the dielectric layer 33 and the second electrode plate 32 successively cover the first electrode plate 31 in a conformal manner, thereby forming the capacitor 30 into a vertical cylindrical capacitor.

[0053] Optionally, in this embodiment, the first substrate 10 is a silicon substrate.

[0054] In some optional embodiments of this application, such as Figures 7 to 9 As shown, the first electrode plate 31 has an inner cavity 312; the dielectric layer 33 includes a first cover layer 331 that conformally covers the first electrode plate 31 and a second cover layer 332 that is connected to the first cover layer 331 and extends in a direction away from the first electrode plate 31; the second electrode plate 32 fills the inner cavity 312 and conformally covers the first cover layer 331 and the second cover layer 332.

[0055] In this embodiment, the wall surface of the first electrode plate 31 located within the inner cavity 312 is the inner wall surface, and the wall surface located outside the inner cavity 312 is the outer wall surface. The first cover layer 331 of the dielectric layer 33 covers the inner and outer wall surfaces of the first electrode plate 31, and the second cover layer 332 is connected to the first cover layer 331 and extends outward in a direction away from the first electrode plate 31. The second electrode plate 32 conformally covers the first cover layer 331 and the second cover layer 332, and the first cover layer 331 and the second cover layer 332 together electrically isolate the first electrode plate 31 and the second electrode plate 32.

[0056] In some optional embodiments of this application, such as Figure 7 As shown, the first electrode plate 31 includes a bottom wall 313 and a side wall 314. The side wall 314 has an annular cross-sectional shape in the horizontal section, and the bottom wall 313 and the side wall 314 are connected to form a cylinder. The bottom wall 313 and the side wall 314 form an inner cavity 312.

[0057] In some optional embodiments of this application, such as Figure 3 , Figure 16 and Figure 17As shown, the pixel circuit 20 also includes a transfer transistor 23 and a selection transistor 24 disposed on one side of the first substrate 10; the transfer transistor 23 is electrically connected to the photodiode 21 and the floating diffusion region 22 respectively, and is used to transfer the photogenerated charge generated by the photodiode 21 to the floating diffusion region 22; the selection transistor 24 is electrically connected to the floating diffusion region 22 and the first electrode 31 respectively, and is used to control the connection or disconnection between the floating diffusion region 22 and the first electrode 31.

[0058] In this embodiment, the photodiode 21 generates photogenerated charge in response to incident light, and the transfer transistor 23 is turned on, so that the photodiode 21 and the floating diffusion region 22 are turned on. The photogenerated charge generated by the photodiode 21 can be transferred to the floating diffusion region 22. When the photogenerated charge exceeds the maximum limit that the floating diffusion region 22 can originally bear, the selection transistor 24 can be turned on, so that the floating diffusion region 22 and the capacitor 30 are turned on. The excess photogenerated charge will flow into the capacitor 30, avoiding overexposure and ensuring image quality.

[0059] In some optional embodiments of this application, such as Figure 3 , Figure 16 and Figure 17 As shown, the image sensor 100 also includes a second substrate 40, and the pixel circuit 20 includes a reset transistor 25 and a source follower transistor 26; the second substrate 40 is bonded to the interconnect stack 80 of the first substrate 10; the source or drain of the reset transistor 25 is electrically connected to the first electrode plate 31, and the gate of the source follower transistor 26 is electrically connected to the floating diffusion region 22; the reset transistor 25 and the source follower transistor 26 are disposed on the first substrate 10 and are located on the side of the capacitor 30 facing the first substrate 10.

[0060] In this embodiment, the first substrate 10 and the second substrate 40 are bonded together using a hybrid bonding process, which reduces the complexity of the manufacturing process.

[0061] In this embodiment, the reset transistor 25 is used to reset the voltage signal in the pixel circuit 20, thereby resetting the floating diffusion region 22; the source follower transistor 26 is used to convert the charge signal in the floating diffusion region 22 into a voltage signal.

[0062] Optionally, such as Figure 16 and Figure 17As shown in this embodiment, the reset transistor 25 and the source follower transistor 26 are disposed on the first substrate 10 and located on the side of the capacitor 30 facing the first substrate 10. The first substrate 10 carries the reset transistor 25 and the source follower transistor 26. The transfer transistor 23, the select transistor 24, the reset transistor 25, and the source follower transistor 26 are all disposed on the first substrate 10. In this way, the transfer transistor 23, the select transistor 24, the reset transistor 25, and the source follower transistor 26 can be fabricated in a single process, thereby simplifying the process.

[0063] Of course, in another optional embodiment of this application, the reset transistor 25 and the source follower transistor 26 may be disposed on the second substrate 40 as needed. Optionally, in embodiments of this application, the row select transistor (RS) may be disposed on the first substrate 10 or on the second substrate 40.

[0064] In some optional embodiments of this application, such as Figure 17 and Figure 18 As shown, the image sensor 100 also includes a filter 52 and a lens 51. The filter 52 and the lens 51 are located on the side of the photodiode 21 away from the capacitor 30 and are arranged sequentially in a direction away from the photodiode 21. The orthogonal projections of the lens 51 and the filter 52 on the first substrate 10 intersect.

[0065] In this embodiment, a filter 52 is disposed between the lens 51 and the photodiode 21, which can absorb light of a specific wavelength. Optionally, the filter 52 includes, but is not limited to, an infrared cutoff filter.

[0066] In this embodiment, the photodiode 21 is disposed on the first substrate 10, and the second substrate 40 is bonded to the first substrate 10 and located on the side of the capacitor 30 away from the first substrate 10. The filter 52 and lens 51 are located on the side of the photodiode 21 away from the capacitor 30 and are arranged sequentially in a direction away from the photodiode 21. That is, the filter 52 and lens 51 are located on the side of the first substrate 10 away from the second substrate 40, and the image sensor 100 adopts back-illuminated (BSI) process compatibility, which greatly improves the light sensitivity.

[0067] Of course, in some alternative embodiments of this application, the image sensor 100 may include a lens 51, which may be disposed on the side of the photodiode 21 away from the capacitor 30, and no filter may be disposed between the lens 51 and the photodiode 21, depending on actual needs.

[0068] Based on the same inventive concept, this application provides a method for fabricating an image sensor, the flowchart of which is shown below. Figure 2As shown, the structural schematic diagrams of the image sensor fabrication method at different stages are as follows: Figures 3 to 17 As shown, the method for fabricating this image sensor includes: S101. A first electrode plate 31 electrically connected to the floating diffusion region 22 of the pixel circuit 20 is formed on one side of the first substrate 10, and the first electrode plate 31 is made into a cylindrical shape with one end open, the opening 311 facing away from the first substrate 10; the pixel circuit 20 includes a photodiode 21 disposed on the first substrate 10 and electrically connected to the floating diffusion region 22, the photodiode 21 is used to generate photogenerated charge in response to incident light, and the floating diffusion region 22 is used to receive photogenerated charge.

[0069] S102. Fabricate dielectric layer 33 and make dielectric layer 33 conformally cover the first electrode plate 31.

[0070] S103. Fabricate the second electrode plate 32 and make the second electrode plate 32 cover the dielectric layer 33 in a conformal manner. The first electrode plate 31, the dielectric layer 33 and the second electrode plate 32 form a capacitor 30 corresponding to the pixel circuit 20.

[0071] In this embodiment, a first electrode 31, a dielectric layer 33, and a second electrode 32 are sequentially fabricated on one side of the first substrate 10 to form a capacitor 30. The first electrode 31 is electrically connected to the floating diffusion region 22 of the pixel circuit 20. The photodiode 21 of the pixel circuit 20 generates photogenerated charge in response to incident light. The floating diffusion region 22 of the pixel circuit 20 receives the photogenerated charge generated by the photodiode 21. The capacitor 30 serves as the lateral overflow collection capacitor (LOFIC) corresponding to the pixel circuit 20. When the photogenerated charge exceeds the maximum limit that the floating diffusion region 22 can originally bear, the excess photogenerated charge will flow into the capacitor 30, avoiding overexposure and enabling the bright image to be clearly displayed in the image, thus improving the imaging quality in high dynamic range scenes.

[0072] In this embodiment, the first electrode plate 31 is a cylindrical shape with one open end, and the opening 311 of the first electrode plate 31 faces away from the first substrate 10. The first electrode plate 31 has an inner wall and an outer wall, so that each lateral overflow collection capacitor is a double-layered cylindrical shape. The dielectric layer 33 is then fabricated to cover the inner and outer walls of the first electrode plate 31. The second electrode plate 32 is then fabricated to cover the dielectric layer 33, so that the corresponding areas of the first electrode plate 31 and the second electrode plate 32 of the capacitor 30 are increased, which can greatly improve the capacitance value. The larger the capacitance value of the lateral overflow collection capacitor, the greater the lateral overflow collection capacitor. The larger the amount of charge that the overflow capacitor can hold, the larger the amount of charge allowed to overflow from the pixel circuit to the lateral overflow capacitor. This can reduce the impact of excessive brightness of the captured object or excessive photogenerated charge on the pixel circuit, reduce or even avoid the probability of pixel overexposure, and enhance the overall exposure stability of the image sensor. The larger the capacitance value of the lateral overflow capacitor, the larger the amount of charge that the lateral overflow capacitor can hold, the larger the limit of charge that the image sensor pixels can hold (well capacity), the stronger the brightness of the captured object, and thus further increase the dynamic range.

[0073] This application provides a manufacturing process for a novel LOFIC CIS structure with a cylindrical capacitor. A cylindrical first electrode 31, a dielectric layer 33 conformally covering the first electrode 31, and a second electrode 32 conformally covering the dielectric layer 33 are sequentially fabricated to form a cylindrical capacitor 30. This innovative use of a cylindrical DRAM capacitor structure replaces the MOSCAP capacitor in related technologies, solving the problem of capacitor instability in related technologies.

[0074] In optional embodiments of this application, such as Figures 3 to 5 As shown, before fabricating the first electrode 31, which is electrically connected to the floating diffusion region 22 of the pixel circuit 20, on one side of the first substrate 10, the following steps are also included: like Figure 3 As shown, a pixel circuit 20 consisting of a transfer transistor 23, a selection transistor 24, a reset transistor 25, and a source follower transistor 26 is fabricated on one side of the first substrate 10. The photodiode 21 is electrically connected to the floating diffusion region 22 through the transfer transistor 23. The gates of the selection transistor 24 and the source follower transistor 26 are both electrically connected to the floating diffusion region 22.

[0075] In this embodiment, the first substrate 10 is used to carry the transfer transistor 23, the selection transistor 24, the reset transistor 25, and the source follower transistor 26 of the pixel circuit 20.

[0076] Optionally, such as Figure 1As shown in the embodiment of this application, the pixel circuit 20 also includes a row selection transistor (RS), which can be fabricated in one process, thereby simplifying the process.

[0077] Optionally, in the embodiments of this application, devices such as photodiodes (PD) 21, floating diffusion regions (FD) 22, transfer transistors (TX / TG) 23, select transistors (SG) 24, reset transistors (RST) 25, source follower transistors (SF) 26, and row select transistors (RS) can be formed on the first substrate 10 (such as a wafer) according to a general CIS front-end manufacturing process.

[0078] Next, as Figure 4 As shown, a first isolation dielectric layer 61 is fabricated to cover the first substrate 10.

[0079] Optionally, a dielectric material is grown on the first substrate 10 to form an inter-layer dielectric (ILD) as the first isolation dielectric layer 61. Optionally, the material of the first isolation dielectric layer 61 includes, but is not limited to, silicon dioxide (SiO2).

[0080] Next, as Figure 4 As shown, a first interconnect structure 71 is fabricated that penetrates the first isolation dielectric layer 61 and is electrically connected to the transfer transistor 23, the selection transistor 24, the floating diffusion region 22, the reset transistor 25, and the source follower transistor 26.

[0081] Optionally, such as Figure 4 As shown in the embodiment of this application, a plurality of first vias 74 are fabricated that penetrate the first isolation dielectric layer 61 and correspond one-to-one with the transfer transistor 23, the selection transistor 24, the floating diffusion region 22, the reset transistor 25, and the source follower transistor 26. The bottom of the plurality of first vias 74 exposes the corresponding transfer transistor 23, the selection transistor 24, the floating diffusion region 22, the reset transistor 25, and the source follower transistor 26, respectively. Then, a first interconnect structure 71 is formed in each first via 74, such that the plurality of first interconnect structures 71 formed are electrically connected one-to-one with the transfer transistor 23, the selection transistor 24, the floating diffusion region 22, the reset transistor 25, and the source follower transistor 26, respectively.

[0082] Optionally, in this embodiment, the material of the first interconnect structure 71 includes, but is not limited to, tungsten (W).

[0083] It should be noted that, in the embodiments of this application, due to routing and layout design, such as Figures 4 to 11 , Figures 13 to 17As shown, the first interconnect structure 71, which is electrically connected to the selection transistor 24, is not shown.

[0084] Next, as Figure 5 As shown, a first electrode 72 is formed at the end of each first interconnect structure 71 away from the first substrate 10. The first electrode 72 is electrically connected to the first interconnect structure 71.

[0085] Optionally, such as Figure 5 As shown in the embodiment of this application, a conductive material is deposited on the side of the first interconnect structure 71 away from the first substrate 10 to form a first initial electrode. The first initial electrode covers the first isolation dielectric layer 61 and a plurality of first interconnect structures 71. Then, the first initial electrode is patterned, and the first initial electrode except for the portion corresponding to the first interconnect structure 71 is removed. The remaining first initial electrode corresponding to the first interconnect structure 71 that has not been removed forms a plurality of first electrodes 72.

[0086] Optionally, in the embodiments of this application, such as Figures 5 to 11 , Figures 13 to 17 As shown, the selection transistor 24 is electrically connected to the first electrode 72 located above the selection transistor 24 through a first interconnect structure 71 (not shown in the figure) that is electrically connected to it.

[0087] Optionally, in the embodiments of this application, the material of the first initial electrode includes, but is not limited to, metals, such as W, Cu, etc.

[0088] Optionally, the first initial electrode can be patterned using processes such as photolithography and etching.

[0089] In some optional embodiments of this application, such as Figure 5 As shown, after fabricating the first electrode 72, a dielectric material is deposited to form a third isolation dielectric layer 75, and a planarization process is performed so that the third isolation dielectric layer 75 covers the first isolation dielectric layer 61, and the surface of the third isolation dielectric layer 75 away from the first substrate 10 is flush with the surface of the first electrode 72 away from the first substrate 10.

[0090] Optionally, the material of the third insulating dielectric layer 75 includes, but is not limited to, oxides, such as SiO2.

[0091] In optional embodiments of this application, such as Figure 6 and Figure 7 As shown, a first electrode plate 31 electrically connected to the floating diffusion region 22 of the pixel circuit 20 is formed on one side of the first substrate 10, and the first electrode plate 31 is shaped like a cylinder with one end open, the opening 311 facing away from the first substrate 10, including: like Figure 6 As shown, a first initial electrode plate 315 covering multiple first electrodes 72 is fabricated.

[0092] Optionally, in this embodiment, the first initial electrode 315 covers the third insulating dielectric layer 75 and a plurality of first electrodes 72. The material of the first initial electrode 315 includes, but is not limited to, conductive materials, such as TiN.

[0093] Next, as Figure 7 As shown, the first initial electrode plate 315 is patterned to form the first electrode plate 31. The first electrode plate 31 is electrically connected to the first electrode 72 located on the side of the selection transistor 24 away from the first substrate 10. The orthographic projection of the first electrode plate 31 on the first substrate 10 intersects with the orthographic projection of the selection transistor 24 on the first substrate 10.

[0094] In this embodiment, the first electrode 31 is electrically connected to the selection transistor 24 via the first electrode 72 corresponding to the selection transistor 24. The first electrode 31 defines the location of the capacitor 30.

[0095] Optionally, in this embodiment of the application, the first initial electrode plate 315 is patterned by etching process to form a cylindrical first electrode plate 31, and the opening 311 of the first electrode plate 31 faces away from the first substrate 10.

[0096] In optional embodiments of this application, such as Figure 8 and Figure 9 As shown, the process of fabricating a dielectric layer 33 and conformally covering the first electrode plate 31 includes: like Figure 8 As shown, a dielectric material is grown to form an initial dielectric layer 333, which covers a plurality of first electrodes 72 and first electrode plates 31.

[0097] Optionally, such as Figure 8 As shown in the embodiment of this application, a high dielectric constant material is grown to form an initial dielectric layer 333, such that the initial dielectric layer 333 covers the third isolation dielectric layer 75, a plurality of first electrodes 72 and a first electrode plate 31.

[0098] Optionally, in the embodiments of this application, the high dielectric constant material includes dielectrics with a dielectric constant k greater than or equal to 3.9, such as ZAZ (ZrO-AlO-ZrO).

[0099] Next, as Figure 9 As shown, the initial dielectric layer 333 is patterned, and the initial dielectric layer 333 except for the portion covering the first electrode plate 31 and the portion located around the first electrode plate 31 is removed. The remaining initial dielectric layer 333 forms the dielectric layer 33. The orthographic projection of the dielectric layer 33 on the first substrate 10 covers the orthographic projection of the first electrode 72, which is electrically connected to the selection transistor 24, on the first substrate 10.

[0100] Optionally, in this embodiment, the initial dielectric layer 333 is patterned by an etching process. The remaining initial dielectric layer 333 that is not removed and covers the first electrode plate 31 forms the first capping layer 331 of the dielectric layer 33, and the remaining initial dielectric layer 333 that is not removed and is located around the first electrode plate 31 forms the second capping layer 332 of the dielectric layer 33.

[0101] In optional embodiments of this application, such as Figure 10 and Figure 11 As shown, the fabrication of the second electrode 32, and the conformal covering of the dielectric layer 33 by the second electrode 32, includes: like Figure 10 As shown, a second initial electrode plate 321 is fabricated, which covers multiple first electrodes 72 and dielectric layer 33, and fills the inner cavity 312 of the first electrode plate 31.

[0102] Optionally, such as Figure 10 As shown in the embodiment of this application, a conductive material is grown to form a second initial electrode plate 321, such that the second initial electrode plate 321 covers the third isolation dielectric layer 75, a plurality of first electrodes 72 and dielectric layer 33, and fills the inner cavity 312 of the first electrode plate 31.

[0103] Optionally, in the embodiments of this application, the material of the second initial electrode 321 includes, but is not limited to, TiN.

[0104] Next, as Figure 11 As shown, the second initial electrode 321 is patterned, and the second initial electrode 321 located outside the orthogonal projection of the dielectric layer 33 on the first substrate 10 is removed, and the remaining second initial electrode 321 forms the second electrode 32.

[0105] Optionally, in this embodiment, the second initial electrode 321 is patterned using an etching process to remove the second initial electrode 321 located outside the orthographic projection of the dielectric layer 33 onto the first substrate 10. The remaining second initial electrode 321 forms the second electrode 32. The orthographic projection of the second electrode 32 onto the first substrate 10 overlaps with the orthographic projection of the dielectric layer 33 onto the first substrate 10. Figure 12 As shown ( Figure 12 for Figure 11 (A partially enlarged view), the second electrode 32, the dielectric layer 33 and the first electrode 31 form a capacitor 30.

[0106] Optionally, in this embodiment of the application, the same or similar manufacturing process as that used for DRAM cylindrical capacitors in the field can be used to sequentially fabricate the first electrode 31, the dielectric layer 33, and the second electrode 32, thereby manufacturing the capacitor 30.

[0107] In optional embodiments of this application, such as Figures 13 to 15As shown, after fabricating the second electrode plate 32 and conformally covering the dielectric layer 33, the process further includes: fabricating a second isolation dielectric layer 62 and an interconnect stack 80 that sequentially cover a plurality of first electrodes 72 and the second electrode plate 32; the interconnect stack 80 includes a plurality of second electrodes 81; at least one first electrode 72 is electrically connected to at least one second electrode 81 through at least one second interconnect structure 73 penetrating the second isolation dielectric layer 62.

[0108] Optionally, in the embodiments of this application, such as Figure 13 As shown, a second insulating dielectric layer 62 is fabricated covering multiple first electrodes 72 and second electrode plates 32.

[0109] Optionally, such as Figure 13 As shown in the embodiment of this application, a dielectric material is filled in the non-capacitor region to form a second isolation dielectric layer 62, such that the second isolation dielectric layer 62 covers the third isolation dielectric layer 75, the plurality of first electrodes 72 and the capacitor 30, and is planarized so that the surface of the second isolation dielectric layer 62 away from the first substrate 10 is flat.

[0110] Optionally, the material of the second insulating dielectric layer 62 includes, but is not limited to, SiO2.

[0111] Optionally, in the embodiments of this application, such as Figure 14 As shown, a second interconnect structure 73 is fabricated that penetrates the second isolation dielectric layer 62 and is electrically connected to at least one first electrode 72 in a one-to-one correspondence.

[0112] Optionally, such as Figure 14 As shown in the embodiment of this application, a second via 76 is fabricated that penetrates the second isolation dielectric layer 62 and corresponds one-to-one with at least one first electrode 72. The orthographic projection of the second via 76 on the first substrate 10 overlaps with the orthographic projection of the corresponding first electrode 72 on the first substrate 10. Conductive material is filled in each second via 76 to form a second interconnect structure 73. The bottom of the second interconnect structure 73 is electrically connected to the corresponding first electrode 72.

[0113] Optionally, such as Figure 14 As shown in the embodiment of this application, a plurality of second vias 76 and a plurality of second interconnect structures 73 are fabricated; the bottom of one of the second vias 76 exposes a second electrode 32, and the bottom of a second interconnect structure 73 corresponding to the second via 76 is electrically connected to the second electrode 32; the bottoms of the remaining second vias 76 respectively expose corresponding first electrodes 72, and the second interconnect structures 73 formed in these second vias 76 are electrically connected to the corresponding first electrodes 72.

[0114] Optionally, in this embodiment, the second via 76 is formed by an etching process. The material of the second interconnect structure 73 includes, but is not limited to, Ti, TiN, W, etc.

[0115] Optionally, in the embodiments of this application, such as Figure 15 As shown, an interconnect stack 80 is fabricated, the interconnect stack 80 includes at least a second electrode 81, and at least one second interconnect structure 73 has a second electrode 81 formed at one end away from the first substrate 10.

[0116] In this embodiment of the application, among the plurality of second interconnect structures 73 fabricated, at least one second interconnect structure 73 has a second electrode 81 formed at one end away from the first substrate 10, and the second electrode 81 is electrically connected to the second interconnect structure 73 in a one-to-one correspondence.

[0117] Optionally, such as Figure 15 As shown in the embodiments of this application, the interconnect stack 80 further includes a fourth interconnect structure 82, a third electrode 83, a fifth interconnect structure 84, and a fourth electrode 85, which are sequentially formed along a direction gradually moving away from the first substrate 10. The materials of the fourth interconnect structure 82, the third electrode 83, the fifth interconnect structure 84, and the fourth electrode 85 are, but are not limited to, conductive materials, such as metals.

[0118] Optionally, in this embodiment, the second electrode 81, the third electrode 83, and the fourth electrode 85 may be manufactured using the same or similar processes as the first electrode 72, which will not be described in detail here. The fourth interconnect structure 82 and the fifth interconnect structure 84 may be manufactured using the same or similar processes as the first interconnect structure 71, which will not be described in detail here.

[0119] Optionally, such as Figure 15 As shown in the embodiment of this application, a fourth isolation dielectric layer 63 made of dielectric material is filled outside each electrode and each interconnect structure of the interconnect stack 80. The fourth isolation dielectric layer 63 is used to electrically isolate each electrode and each interconnect structure of the interconnect stack 80.

[0120] Optionally, in this embodiment, a mature copper back-end process can be used to form the electrodes and interconnect structures of the interconnect stack 80. The number of electrodes and interconnect structures in the interconnect stack 80 can be appropriately increased or decreased according to design requirements.

[0121] In optional embodiments of this application, such as Figure 16 and Figure 17 As shown, after fabricating the second isolation dielectric layer 62 and the interconnect stack 80 that sequentially cover multiple first electrodes 72 and second electrode plates 32, the process further includes: Flip the first substrate 10 having interconnect stack 80.

[0122] Next, as Figure 16 As shown, the interconnect stack 80 on one side of the first substrate 10 is bonded to the second substrate 40.

[0123] In this embodiment, the first substrate 10 is flipped so that the side of the first substrate 10 with the interconnect stack 80 faces the second substrate 40; then, the side of the first substrate 10 with the interconnect stack 80 is bonded to the second substrate 40. The second substrate 40 serves as a carrier wafer, carrying the first substrate 10, pixel circuit 20, capacitor 30, interconnect stack 80, and other electrodes and interconnect structures.

[0124] Optionally, such as Figure 16 As shown in the embodiment of this application, after the first substrate 10 with interconnect stack 80 is bonded to the second substrate 40, a bonding layer 41 is formed between the fourth isolation dielectric layer 63 and the second substrate 40.

[0125] Optionally, the material of the bonding layer 41 includes, but is not limited to, a dielectric material, such as liquid wax or liquid adhesive.

[0126] Optionally, a hybrid bonding process can be used to bond the first substrate 10, on which the interconnect stack 80 is formed, to the second substrate 40, thereby reducing the complexity of the manufacturing process. Other bonding processes may also be used in other exemplary embodiments, and this application does not limit them.

[0127] Next, as Figure 17 As shown, the side of the first substrate 10 away from the interconnect stack 80 is thinned. The side of the first substrate 10 opposite to the second substrate 40 is also thinned to an appropriate thickness, for example, in the range of 2µm-10µm.

[0128] Next, as Figure 17 As shown, at least one third via 91 is formed by through-silicon via (TSV) technology, exposing the bottom of the electrodes in the interconnect stack 80.

[0129] Next, as Figure 17 As shown, a third interconnect structure 92 is formed in the third via 91, and a pad 93 is fabricated on the side of the third interconnect structure 92 away from the second substrate 40.

[0130] Optionally, a standard TSV (Through Silicon Via) process can be performed on the first substrate 10 and the dielectric layers formed on the first substrate 10 to form a third via 91 that exposes the electrodes in the interconnect stack 80 at the bottom; then, conductive material is filled into the third via 91 to form a third interconnect structure 92 for connection to the circuit below; then, pads 93 are formed on the third interconnect structure 92. Optionally, the material of the pads 93 includes, but is not limited to, Al.

[0131] Next, as Figure 17As shown, a filter 52 and a lens 51 are sequentially fabricated on the side of the first substrate 10 away from the interconnect stack 80. The orthogonal projection of the lens 51 on the first substrate 10 intersects at least with the orthogonal projection of the photodiode 21 on the first substrate 10.

[0132] Optionally, such as Figure 17 As shown in the embodiment of this application, a color filter 52 and a lens 51 are formed on the top of the photodiode (PD) 21 (on the side away from the second substrate 40).

[0133] Of course, in some alternative embodiments of this application, the lens 51 may be fabricated on the side of the first substrate 10 away from the interconnect stack 80, depending on actual needs. That is, the lens 51 is formed only on top of the photodiode (PD) 21, and no color filter 52 is formed between the lens 51 and the photodiode (PD) 21.

[0134] It should be noted that in the embodiments of this application, each process flow diagram is only a schematic diagram. In reality, the layout will be different. The photodiode (PD) 21 array is closely arranged. The process flow diagram is only illustrated using the pixel circuit 20 of one photodiode (PD) 21 as an example.

[0135] Optionally, such as Figure 18 As shown in the embodiments of this application, the first isolation dielectric layer 61, the second isolation dielectric layer 62, the fourth isolation dielectric layer 63, the bonding layer 41, and the third isolation dielectric layer 75 are represented by dielectric structure 110.

[0136] It should be noted that the image sensor in this application embodiment can be fabricated using the image sensor fabrication method provided in this application embodiment. Therefore, the image sensor in this application embodiment also has the above-mentioned beneficial effects of the image sensor fabrication method provided in this application embodiment, which will not be repeated here.

[0137] Based on the same inventive concept, embodiments of this application provide an electronic device, which includes: the image sensor 100 as described above; or, an image sensor prepared using the image sensor preparation method described above.

[0138] It should be noted that since the electronic devices of the present application embodiments include the image sensors of the present application embodiments or the image sensors prepared using the preparation methods of the image sensors of the present application embodiments, the electronic devices of the present application embodiments also have the above-mentioned beneficial effects of the image sensors of the present application embodiments or the image sensors prepared using the preparation methods of the image sensors of the present application embodiments, which will not be repeated here.

[0139] In some optional embodiments of this application, the electronic device includes, but is not limited to, common devices with photographic functions such as digital cameras, mobile phones, tablets, and wearable devices. Of course, the image sensor provided in the embodiments of this application can also be applied to other types of electronic devices with photographic functions.

[0140] By applying the embodiments of this application, at least the following beneficial effects can be achieved: In this embodiment, a first substrate is used to support multiple pixel circuits and multiple capacitors. The photodiodes of the pixel circuits are electrically connected to a floating diffusion region. The photodiodes generate photocharge in response to incident light, and the floating diffusion region receives the photocharge generated by the photodiodes. The first plate of the capacitor is electrically connected to the floating diffusion region of the corresponding pixel circuit. The capacitor acts as a lateral overflow collection capacitor; when the photocharge exceeds the maximum capacity of the floating diffusion region, the excess photocharge flows into the capacitor, preventing overexposure and ensuring that bright images are clearly displayed in the image, thus improving imaging quality in high dynamic range scenes. Multiple capacitors correspond one-to-one with multiple pixel circuits, ensuring that each pixel circuit has a corresponding lateral overflow collection capacitor.

[0141] The first plate of each capacitor is a cylindrical shape with one open end, and the opening of the first plate faces away from the first substrate. The first plate has an inner wall and an outer wall, making each lateral overflow capacitor a double-layered cylindrical shape. The dielectric layer conformally covers the inner and outer walls of the first plate. The second plate is located on the side of the dielectric layer away from the first substrate and conformally covers the dielectric layer, which increases the corresponding area of ​​the first and second plates of each capacitor, greatly improving the capacitance value. The larger the capacitance value of the lateral overflow capacitor, the greater the amount of charge it can carry, and the greater the amount of charge allowed to overflow from the pixel circuit to the lateral overflow capacitor. This can reduce the impact of excessive brightness of the captured object or excessive photogenerated charge on the pixel circuit, reduce or even avoid the probability of pixel overexposure, and enhance the overall exposure stability of the image sensor. The larger the capacitance value of the lateral overflow capacitor, the greater the amount of charge it can carry, the greater the limit of charge carried by the pixel of the image sensor (well capacity), and the stronger the brightness of the captured object, thereby further increasing the dynamic range.

[0142] This application provides a novel LOFIC CIS structure with a cylindrical capacitor. It uses a cylindrical first plate, and sequentially covers a dielectric layer and a second plate to form a cylindrical capacitor. It creatively adopts a cylindrical DRAM capacitor structure to replace the MOSCAP capacitor in related technologies, thus solving the problem of capacitor instability in related technologies.

[0143] In this embodiment, the first substrate and the second substrate are bonded together using a hybrid bonding process, which reduces the complexity of the manufacturing process. The filter and lens are located on the side of the first substrate away from the second substrate, and the image sensor uses a back-illuminated process, which greatly improves the light sensitivity.

[0144] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0145] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0146] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0147] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0148] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0149] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. An image sensor, characterized in that, include: First substrate; Multiple pixel circuits, each pixel circuit including a photodiode disposed on one side of the first substrate and electrically connected to it, the photodiode being used to generate photogenerated charge in response to incident light, and the floating diffusion region being used to receive the photogenerated charge; Multiple capacitors are disposed on one side of the first substrate, each capacitor including a first electrode plate, a second electrode plate, and a dielectric layer located between the first electrode plate and the second electrode plate; The first electrode plate is electrically connected to the suspended diffusion region. The first electrode plate is cylindrical with one end open, and the opening faces away from the first substrate. The dielectric layer conformally covers the first electrode plate; The second electrode is located on the side of the dielectric layer away from the first substrate and conformally covers the dielectric layer.

2. The image sensor according to claim 1, characterized in that, The first electrode plate has an inner cavity; The dielectric layer includes a first cover layer that conformally covers the first electrode plate and a second cover layer that is connected to the first cover layer and extends in a direction away from the first electrode plate; The second electrode plate fills the inner cavity and conforms to the shape of the first and second covering layers.

3. The image sensor according to claim 1, characterized in that, The first electrode plate includes a bottom wall and a side wall. The side wall has an annular cross-sectional shape in a horizontal section, and the bottom wall and the side wall are connected in a cylindrical shape.

4. The image sensor according to claim 1, characterized in that, The pixel circuit also includes a transfer transistor and a selection transistor disposed on one side of the first substrate; The transfer transistor is electrically connected to the photodiode and the levitation diffusion region respectively, and is used to transfer the photogenerated charge generated by the photodiode to the levitation diffusion region; The selection transistor is electrically connected to the levitation diffusion region and the first electrode plate respectively, and is used to control the connection or disconnection between the levitation diffusion region and the first electrode plate.

5. The image sensor according to any one of claims 1 to 4, characterized in that, It also includes a second substrate, and the pixel circuit further includes a reset transistor and a source follower transistor; The second substrate is bonded to the first substrate via an interconnect stack; The source or drain of the reset transistor is electrically connected to the first plate, and the gate of the source follow transistor is electrically connected to the floating diffusion region. The reset transistor and the source follower transistor are disposed on the first substrate and located on the side of the capacitor facing the first substrate.

6. The image sensor according to claim 5, characterized in that, Also includes: A lens is disposed on the side of the photodiode away from the capacitor; or, A filter and a lens are located on the side of the photodiode away from the capacitor and are arranged sequentially in a direction away from the photodiode. The orthogonal projections of the lens and the filter on the first substrate intersect.

7. A method for fabricating an image sensor, characterized in that, include: A first electrode plate electrically connected to the floating diffusion region of the pixel circuit is formed on one side of the first substrate, and the first electrode plate is in the shape of a cylinder with one end open, the opening facing away from the first substrate; the pixel circuit includes a photodiode disposed on the first substrate and electrically connected to the floating diffusion region, the photodiode being used to generate photocharge in response to incident light, and the floating diffusion region being used to receive the photocharge. A dielectric layer is fabricated, and the dielectric layer is made to conformally cover the first electrode plate; A second electrode plate is fabricated and conformally covers the dielectric layer. The first electrode plate, the dielectric layer, and the second electrode plate form a capacitor corresponding to the pixel circuit.

8. The method for fabricating an image sensor according to claim 7, characterized in that, Before fabricating a first electrode plate electrically connected to the floating diffusion region of the pixel circuit on one side of the first substrate, the method further includes: A transfer transistor, a selection transistor, a reset transistor, and a source follower transistor for a pixel circuit are fabricated on one side of the first substrate. The photodiode is electrically connected to the floating diffusion region through the transfer transistor, and the gates of the selection transistor and the source follower transistor are both electrically connected to the floating diffusion region. Fabricate a first insulating dielectric layer covering the first substrate; A first interconnect structure is fabricated that extends through the first isolation dielectric layer and is electrically connected to the transfer transistor, the selection transistor, the floating diffusion region, the reset transistor, and the source follower transistor, respectively; A first electrode is fabricated at the end of each of the first interconnect structures that is furthest from the first substrate.

9. The method for fabricating an image sensor according to claim 8, characterized in that, A first electrode plate electrically connected to the floating diffusion region of the pixel circuit is fabricated on one side of the first substrate, and the first electrode plate is shaped like a cylinder with one end open, the opening facing away from the first substrate, including: Fabricate a first initial electrode plate covering multiple of the first electrodes; The first initial electrode plate is patterned to form the first electrode plate, and the first electrode plate is electrically connected to the first electrode located on the side of the selection transistor away from the first substrate; the orthographic projection of the first electrode plate on the first substrate intersects the orthographic projection of the selection transistor on the first substrate.

10. The method for fabricating an image sensor according to claim 8, characterized in that, Fabricating a dielectric layer and conformally covering the first electrode plate includes: A dielectric material is grown to form an initial dielectric layer, which covers a plurality of the first electrodes and the first plate; The initial dielectric layer is patterned, and the initial dielectric layer except for the portion covering the first electrode plate and the portion located around the first electrode plate is removed. The remaining initial dielectric layer forms the dielectric layer. The orthographic projection of the dielectric layer on the first substrate covers the orthographic projection of the first electrode electrically connected to the selection transistor on the first substrate. And, fabricating a second electrode plate, and conformally covering the dielectric layer with the second electrode plate, including: A second initial electrode plate is fabricated, which covers multiple first electrodes and the dielectric layer and fills the inner cavity of the first electrode plate; The second initial electrode is patterned, and the second initial electrode located outside the orthogonal projection of the dielectric layer on the first substrate is removed, and the remaining second initial electrode forms the second electrode.

11. The method for manufacturing an image sensor according to any one of claims 7 to 10, characterized in that, After fabricating the second electrode plate and conformally covering the dielectric layer, the process further includes: A second isolation dielectric layer and an interconnect stack are fabricated to sequentially cover a plurality of first electrodes and second electrode plates; the interconnect stack includes a plurality of second electrodes; at least one first electrode is electrically connected to at least one second electrode through at least one second interconnect structure penetrating the second isolation dielectric layer.

12. The method for fabricating an image sensor according to claim 11, characterized in that, After fabricating a second insulating dielectric layer and an interconnect stack that sequentially cover multiple first electrodes and second plates, the process further includes: Flip the first substrate having the interconnect stack; The interconnect stack on one side of the first substrate is bonded to the second substrate; The side of the first substrate furthest from the interconnect stack is thinned. At least one third via is formed using through-silicon via (TSV) technology, exposing the bottom of the electrodes in the interconnect stack. A third interconnect structure is formed within the third via, and a pad is fabricated on the side of the third interconnect structure away from the second substrate; A lens is fabricated on the side of the first substrate away from the interconnect stack, or a filter and a lens are fabricated sequentially, wherein the orthogonal projection of the lens on the first substrate intersects at least the orthogonal projection of the photodiode on the first substrate.

13. An electronic device, characterized in that, include: The image sensor as described in any one of claims 1 to 6; or, An image sensor prepared using the method for preparing an image sensor as described in any one of claims 7 to 12.

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