Chip packaging structure and preparation method thereof

Abstract

In order to solve the problem that heat interference exists between chips in existing chip stacking packaging, the invention provides a chip packaging structure and a preparation method thereof.The chip packaging structure comprises a PCB main board, a heat sink heat dissipation block, a packaging chip and a transverse heat conduction sheet, the packaging chip comprises a chip substrate, a first chip, a second chip and a packaging layer, and the transverse heat conduction sheet is arranged between the first chip and the second chip. The heat sink heat dissipation block is embedded in the PCB mainboard, the chip substrate is located on one side of the heat sink heat dissipation block and is electrically connected with the PCB mainboard, the packaging layer is located on the chip substrate, the first chip and the second chip are packaged in the packaging layer, and the first chip and the second chip are electrically connected with the packaging layer. The transverse heat-conducting fin comprises a first polymer graphitization film, a foaming heat insulation layer and a second polymer graphitization film, the transverse heat-conducting fin is provided with a built-in part and an external part, the built-in part is located between the first chip and the second chip, and the first polymer graphitization film of the external part is in heat conduction with the heat sink heat dissipation block.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, specifically relating to a chip packaging structure and its preparation method. Background Technology

[0002] With the rapid development of portable electronic devices, wearable terminals, and miniature sensors, the market is placing increasingly higher demands on the integration and functional density of these devices, while the need for miniaturization and lightweight design is becoming more urgent. As the core functional carrier of these small devices, the space occupied by the chip directly determines the overall size design of the device. In existing technologies, to achieve miniaturization, chip integration layouts are constantly being optimized, among which the vertical stacking of chips with different functions is a widely researched and applied technique.

[0003] Vertically stacked chip solutions, by stacking multiple chips that were originally arranged in a planar layout along a vertical direction, can effectively reduce the horizontal area occupied by chips inside a device, significantly improving the functional integration per unit space. This provides key support for the thinner and lighter design of small devices. For example, stacked chip structures have been gradually adopted in the processor modules of smartphones and the sensing modules of wearable devices, realizing the integration of multiple functions such as computing, storage, and sensing, while effectively controlling the overall size of the device.

[0004] However, while the aforementioned vertical chip stacking solution solves the space occupation problem, it also presents a severe heat dissipation challenge. Chips inevitably generate heat during operation, and the vertical stacking structure results in extremely small physical spacing between multiple chips, making it difficult for heat to dissipate quickly and easily leading to heat accumulation within the stacked structure. Crucially, chips with different functions (such as computing chips, memory chips, and sensing chips) have significantly different heat dissipation power; for example, high-performance computing chips typically generate far more heat than low-power sensing chips. Furthermore, the high-temperature tolerance of various chips also varies. Some precision sensing chips and low-power control chips are temperature-sensitive devices with narrow operating temperature ranges, making them extremely sensitive to fluctuations in ambient temperature.

[0005] In a vertically stacked structure, the large amount of heat generated by a chip with high heat output can be directly transferred to adjacent temperature-sensitive chips, causing severe thermal interference. This thermal interference can cause the operating temperature of the temperature-sensitive chips to exceed their tolerance range, leading to a series of problems: at best, it can cause a decrease in chip performance, such as reduced computational accuracy, slower response speed, and abnormally high power consumption; at worst, it can damage the internal circuitry of the chip, causing functional failure, and even affecting the reliability and lifespan of the entire device. Summary of the Invention

[0006] To address the problem of thermal interference between chips in existing chip stacking packages, this invention provides a chip packaging structure and its fabrication method.

[0007] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows: On one hand, the present invention provides a chip packaging structure, including a PCB motherboard, a heat sink, a packaged chip, and a lateral thermal conductive sheet. The packaged chip includes a chip substrate, a first chip, a second chip, and a packaging layer. The heat sink is embedded in the PCB motherboard. The chip substrate is located on one side of the heat sink and is electrically connected to the PCB motherboard. The first chip is located on the surface of the chip substrate facing away from the PCB motherboard and is electrically connected to the chip substrate. The second chip is stacked on the side of the first chip facing away from the chip substrate and is electrically connected to the first chip. The layer is located on the chip substrate, and the first chip and the second chip are encapsulated in the encapsulation layer. The lateral thermal conductive sheet includes a first polymer graphitized film, a foamed heat insulation layer and a second polymer graphitized film stacked in sequence. The lateral thermal conductive sheet has an internal portion and an external portion. The internal portion is located between the first chip and the second chip, and the first polymer graphitized film of the internal portion conducts heat with the first chip. The second polymer graphitized film of the internal portion conducts heat with the second chip. The external portion of the lateral thermal conductive sheet extends out of the encapsulation layer, and the first polymer graphitized film of the external portion conducts heat with the heat sink.

[0008] Optionally, the first polymer graphitized film and the second polymer graphitized film are selected from polyimide graphitized films, wherein the polyimide graphitized film has a plurality of sequentially parallel graphite sheets, the planar thermal conductivity of the polyimide graphitized film is 1200~1500 W / m·K, and the vertical thermal conductivity of the polyimide graphitized film is 5~10 W / m·K.

[0009] Optionally, the foamed insulation layer is obtained by foaming and curing a foamed resin coating, the foamed resin coating comprising the following components by weight: The ingredients are: 40-60 parts of organosilicon resin, 7-12 parts of azodicarbonamide, 4-6 parts of aminosilane curing agent, 1-3 parts of dispersant, 0.5-2 parts of silane coupling agent, and 10-30 parts of solvent.

[0010] Optionally, a first alumina layer is disposed between the first polymer graphitized film and the first chip, and a second alumina layer is disposed between the second polymer graphitized film and the second chip.

[0011] Optionally, the chip packaging structure further includes a heat sink and ceramic screws. The heat sink is disposed on the surface of the second polymer graphitized film of the external portion away from the foamed heat insulation layer. The ceramic screws pass through the heat sink and the lateral heat-conducting sheet in sequence and are connected to the heat sink block.

[0012] Optionally, the number of packaged chips is multiple, and the multiple packaged chips are disposed on the outer periphery of the heat sink block. The multiple packaged chips share a single transverse heat-conducting sheet. The packaged layer abuts against the outer wall of the heat sink block and the heat sink. The bottom of the heat sink block is provided with a porous metal layer, and the porous metal layer does not protrude from the surface of the PCB motherboard.

[0013] Optionally, the second chip is offset from the first chip. The first chip has a stepped surface not covered by the second chip. The first chip has a first pad at the stepped surface. The second chip has a second pad. The chip substrate has a third pad. The third pad and the first pad are electrically connected by a first metal line. The second pad and the first pad are electrically connected by a second metal line.

[0014] Optionally, the bottom surface of the chip substrate is provided with a plurality of solder balls, and the chip substrate is electrically connected to the PCB motherboard through the solder balls.

[0015] Furthermore, the present invention provides a method for fabricating the chip packaging structure as described above, comprising the following steps: S1. Apply foamed resin coating to the surface of the first polymer graphitized film, then cover the surface of the foamed resin coating with the second polymer graphitized film, and perform heating curing and foaming treatment to obtain a transverse heat-conducting sheet. S2. The first chip, the lateral heat-conducting sheet and the second chip are stacked in sequence and pre-fixed on the chip substrate. The chip substrate, the first chip and the second chip are wired. The first chip, the lateral heat-conducting sheet and the second chip on the chip substrate are packaged to form a package layer to obtain a packaged chip. A portion of the lateral heat-conducting sheet extends out of the package layer to form an external part. S3. The packaged chip is attached to the PCB motherboard with the heat sink embedded, so that the first polymer graphitized film of the external part comes into contact with the heat sink for heat conduction.

[0016] Optionally, the following operations are also included: S4. Place the heat sink on the surface of the external part away from the heat sink block, so that the heat sink contacts the second polymer graphitized film, and fix the heat sink and the heat sink block with ceramic screws, with the external part clamped between the heat sink and the heat sink block.

[0017] According to the chip packaging structure provided by the present invention, the lateral heat-conducting sheet adopts a sandwich structure of "first polymer graphitized film + foamed insulation layer + second polymer graphitized film". The first and second polymer graphitized films have excellent thermal anisotropy. Specifically, they have excellent thermal conductivity in the planar direction, which can quickly collect the heat generated by the first chip and the second chip respectively, and conduct the heat to the heat sink embedded in the PCB motherboard or directly dissipate heat to the outside through the external part of the packaging layer, realizing the directional heat dissipation. At the same time, the polymer graphitized film has extremely low thermal conductivity in the vertical direction (perpendicular to the direction of the polymer graphitized film). Compared with other thermal conductive materials, it can avoid the mutual conduction of heat between the first chip and the second chip in the longitudinal direction, suppressing the thermal interference between the first chip and the second chip. Furthermore, combined with the foamed insulation layer, it can block the vertical heat conduction path between the first chip and the second chip. The low thermal conductivity of the insulation material can be used to suppress the heat penetration from the high-temperature chip to the low-temperature sensitive chip, thereby alleviating the thermal interference problem from the root. While maintaining the advantage of small space occupation in vertically stacked chips, this chip packaging structure effectively solves the problem of thermal interference between chips with different heat dissipation characteristics, ensures the working stability of temperature-sensitive chips, and improves the reliability and service life of the entire packaging structure. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the chip packaging structure provided by the present invention; Figure 2 This is a schematic diagram of the structure of the transverse heat-conducting sheet provided by the present invention.

[0019] The reference numerals in the accompanying drawings are as follows: 1. PCB motherboard; 2. Heat sink; 21. Porous metal layer; 3. Packaged chip; 31. First chip; 311. First pad; 32. Second chip; 321. Second pad; 33. Package layer; 34. Chip substrate; 341. Third pad; 342. Solder ball; 35. First metal line; 36. Second metal line; 4. Lateral heat-conducting sheet; 41. Internal part; 42. External part; 43. First polymer graphitized film; 44. Foamed thermal insulation layer; 45. Second polymer graphitized film; 46. First alumina layer; 47. Second alumina layer; 5. Heat sink; 6. Ceramic screw. Detailed Implementation

[0020] To make the technical problems solved, the technical solutions, and the beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0021] like Figure 1 and Figure 2 As shown, an embodiment of the present invention provides a chip packaging structure, including a PCB motherboard 1, a heat sink 2, a packaged chip 3, and a lateral heat-conducting sheet 4. The packaged chip 3 includes a chip substrate 34, a first chip 31, a second chip 32, and a packaging layer 33. The heat sink 2 is embedded in the PCB motherboard 1. The chip substrate 34 is located on one side of the heat sink 2 and is electrically connected to the PCB motherboard 1. The first chip 31 is located on the surface of the chip substrate 34 facing away from the PCB motherboard 1 and is electrically connected to the chip substrate 34. The second chip 32 is stacked on the side of the first chip 31 facing away from the chip substrate 34 and is electrically connected to the first chip 31. The packaging layer 33 is located on the side of the first chip 31 facing away from the chip substrate 34. On the chip substrate 34, and with the first chip 31 and the second chip 32 encapsulated in the encapsulation layer 33, the lateral heat-conducting sheet 4 includes a first polymer graphitized film 43, a foamed heat insulation layer 44, and a second polymer graphitized film 45 stacked sequentially. The lateral heat-conducting sheet 4 has an internal portion 41 and an external portion 42. The internal portion 41 is located between the first chip 31 and the second chip 32, and the first polymer graphitized film 43 of the internal portion 41 conducts heat with the first chip 31, and the second polymer graphitized film 45 of the internal portion 41 conducts heat with the second chip 32. The external portion 42 of the lateral heat-conducting sheet 4 extends out of the encapsulation layer 33, and the first polymer graphitized film 43 of the external portion 42 conducts heat with the heat sink 2.

[0022] According to the chip packaging structure provided by the present invention, the lateral heat-conducting sheet 4 adopts a sandwich structure of "first polymer graphitized film 43 + foamed heat insulation layer 44 + second polymer graphitized film 45". The first polymer graphitized film 43 and the second polymer graphitized film 45 have excellent thermal anisotropy. Specifically, they have excellent thermal conductivity in the planar direction, which can quickly collect the heat generated by the first chip 31 and the second chip 32 respectively, and conduct the heat to the heat sink 2 embedded in the PCB motherboard 1 or directly dissipate heat to the outside through the external part 42 extending out of the packaging layer 33. This design achieves directional heat dissipation. Simultaneously, the polymer graphitized film exhibits extremely low thermal conductivity in the vertical direction (perpendicular to the polymer graphitized film direction). Compared to other thermally conductive materials, this prevents longitudinal heat conduction between the first chip 31 and the second chip 32, suppressing thermal interference between them. Furthermore, the foamed insulation layer 44 blocks the vertical heat conduction path between the first chip 31 and the second chip 32. The low thermal conductivity of the insulation material further inhibits heat penetration from the high-temperature chip to the low-temperature sensitive chip, mitigating thermal interference at its source. This chip packaging structure, while maintaining the advantage of a small space footprint for vertically stacked chips, effectively solves the thermal interference problem between chips with different heat dissipation characteristics, ensuring the operational stability of the temperature-sensitive chip and improving the reliability and lifespan of the entire packaging structure.

[0023] In some embodiments, the encapsulation layer 33 is an epoxy resin layer.

[0024] In some embodiments, the first polymer graphitized film 43 and the second polymer graphitized film 45 are selected from polyimide graphitized films, wherein the polyimide graphitized film has a plurality of sequentially parallel graphite sheets, the planar thermal conductivity of the polyimide graphitized film is 1200~1500 W / m·K, and the vertical thermal conductivity of the polyimide graphitized film is 5~10 W / m·K.

[0025] Polyimide graphitized film is selected as the thermally conductive substrate. This material has excellent mechanical strength and high temperature resistance, making it suitable for the complex operating environment of the chip. Its planar thermal conductivity is 1200~1500 W / m·K, maximizing lateral thermal conductivity and quickly transferring heat generated by the chip along the film plane to the heat sink 2 or the external environment, preventing localized heat accumulation. Its vertical thermal conductivity is only 5~10 W / m·K. This extremely low vertical thermal conductivity helps the foamed insulation layer 44 further block vertical heat transfer, reducing thermal crosstalk between the first chip 31 and the second chip 32. The extremely low vertical thermal conductivity of the polyimide graphitized film mainly stems from the strong sp2 bond coupling of carbon atoms in the graphite layer within the two-dimensional honeycomb layer, resulting in extremely high in-plane thermal conductivity. However, the weak van der Waals forces between the graphite layers significantly limit vertical thermal conductivity. This chip packaging structure utilizes this thermal anisotropy to achieve both thermal conductivity and the blocking of vertical thermal interference.

[0026] In some embodiments, the thickness of the first polymer graphitized film 43 and the second polymer graphitized film 45 is 20~50 μm.

[0027] In some embodiments, the surface of the polyimide graphitized film is subjected to plasma treatment with a power of 100-200W and a treatment time of 30-60s.

[0028] In some embodiments, the foamed insulation layer 44 is obtained by foaming and curing a foamed resin coating, the foamed resin coating comprising the following components by weight: The ingredients are: 40-60 parts of organosilicon resin, 7-12 parts of azodicarbonamide, 4-6 parts of aminosilane curing agent, 1-3 parts of dispersant, 0.5-2 parts of silane coupling agent, and 10-30 parts of solvent.

[0029] Using 40-60 parts of silicone resin as the matrix, which has excellent thermal insulation, aging resistance and adhesion, it can ensure a tight fit between the thermal insulation layer and the graphitized films on both sides, avoiding thermal insulation failure due to interlayer delamination; 7-12 parts of azodicarbonamide as a foaming agent can generate uniform bubbles during the curing process, forming a porous thermal insulation structure. The porous structure can significantly reduce the thermal conductivity of the thermal insulation layer and improve the thermal insulation effect; 4-6 parts of aminosilane curing agent ensures the full curing of silicone resin and improves the mechanical strength of the thermal insulation layer; 1-3 parts of dispersant and 0.5-2 parts of silane coupling agent can optimize the dispersion uniformity of each component, improve the overall structural stability and environmental resistance of the foamed thermal insulation layer 44, so that the foamed thermal insulation layer 44 has both excellent thermal insulation performance and good structural integrity and adhesion, and can play a stable thermal insulation role for a long time.

[0030] In some embodiments, the dispersant is selected from polycarboxylate dispersants.

[0031] In some embodiments, the solvent is selected from a mixture of xylene and ethanol, wherein the volume ratio of xylene to ethanol is 1:1 to 3:1.

[0032] In some embodiments, the thickness of the foamed insulation layer 44 is 50~200μm.

[0033] In some embodiments, a first alumina layer 46 is disposed between the first polymer graphitized film 43 and the first chip 31, and a second alumina layer 47 is disposed between the second polymer graphitized film 45 and the second chip 32.

[0034] The first alumina layer 46 and the second alumina layer 47 are provided to fill the microscopic gaps between the graphitization film and the chip surface, reduce contact thermal resistance, and transfer the heat generated by the chip to the graphitization film more efficiently, thereby improving the overall heat dissipation efficiency. On the other hand, they can prevent the graphitization film from directly contacting the metal electrodes on the chip surface, prevent electrical faults such as short circuits, and ensure the electrical safety of the packaging structure.

[0035] In some embodiments, the thickness of the first alumina layer 46 and the second alumina layer 47 is 10~30μm, and they are prepared by sputtering process.

[0036] The heat sink 2 is used for auxiliary heat dissipation of the first chip 31. Its heat conduction path is: first chip 31 - first polymer graphitized film 43 - heat sink 2. This is mainly because the first chip 31 is usually selected from chips such as control chips that have direct electrical connection with the chip substrate 34 and have electrical connection with other chips. Its heat generation is high. Therefore, the heat sink 2 is set to improve its heat dissipation efficiency.

[0037] If the second chip 32 is selected from low-heat chips, it can directly dissipate heat to the outside through the second polymer graphitization film 45 of the external part 42 without setting an additional heat dissipation auxiliary structure.

[0038] In some embodiments, if the second chip 32 is selected from a high-heat-generating chip, the chip packaging structure further includes a heat sink 5 and a ceramic screw 6. The heat sink 5 is disposed on the surface of the second polymer graphitized film 45 of the external portion 42 away from the surface of the foamed heat insulation layer 44. The ceramic screw 6 passes through the heat sink 5 and the transverse heat-conducting sheet 4 in sequence and is connected to the heat sink block 2.

[0039] The heat sink 5 is used for auxiliary heat dissipation of the second chip 32. Its heat conduction path is: second chip 32 - second polymer graphitized film 45 - heat sink 5. The heat conduction paths of the first chip 31 and the second chip 32 are isolated from each other and have opposite heat conduction directions, which can avoid mutual interference between them. The ceramic screw 6 can fix the heat sink 5 and the heat sink block 2 and clamp the transverse heat conduction plate 4 between the heat sink 5 and the heat sink block 2 to improve the heat conduction efficiency. At the same time, the ceramic screw 6 itself has poor thermal conductivity and will not form heat conduction between the heat sink 5 and the heat sink block 2.

[0040] In some embodiments, the heat sink 2 is a copper block, and the heat sink 5 is an aluminum alloy heat sink with multiple heat dissipation fins on its surface. The height of the heat dissipation fins is 5-10mm, and the spacing between adjacent fins is 2-5mm.

[0041] In some embodiments, there are multiple packaged chips 3, which are disposed on the outer periphery of the heat sink 2 and share a single transverse heat-conducting sheet 4. The packaged layer 33 abuts against the outer wall of the heat sink 2 and the heat sink 5. A porous metal layer 21 is provided at the bottom of the heat sink 2, and the porous metal layer 21 does not protrude from the surface of the PCB motherboard 1.

[0042] By having the encapsulation layer 33 abut against the outer wall of the heat sink 2 and the heat sink 5, the middle part of the transverse heat-conducting sheet 4 can be prevented from being exposed, thus avoiding the thermal conductivity effect from being affected by the breakage of the middle part of the transverse heat-conducting sheet 4 due to external interference.

[0043] A porous metal layer 21 is provided at the bottom of the heat sink 2. The porous metal layer 21 has a high specific surface area, which can increase the heat exchange area between the heat sink 2 and the external environment, thereby improving the heat dissipation effect on the first chip 31 without protruding from the PCB motherboard 1.

[0044] In some embodiments, the second chip 32 is offset from the first chip 31. The first chip 31 has a stepped surface not covered by the second chip 32. The first chip 31 has a first pad 311 at the stepped surface. The second chip 32 has a second pad 321. The chip substrate 34 has a third pad 341. The third pad 341 and the first pad 311 are electrically connected by a first metal line 35. The second pad 321 and the first pad 311 are electrically connected by a second metal line 36.

[0045] The second chip 32 is offset from the first chip 31 to form a stepped surface, which exposes the first pad 311 of the first chip 31, avoiding the stacked chips from blocking the first pad 311 and providing sufficient space for lead wire operations. The third pad 341 is connected to the first pad 311 by the first metal line 35, and the second pad 321 is connected to the first pad 311 by the second metal line 36, which achieves a stable electrical connection between the chip substrate 34 and the two stacked chips, ensuring the reliability of signal transmission.

[0046] In some embodiments, a plurality of solder balls 342 are provided on the bottom surface of the chip substrate 34, and the chip substrate 34 is electrically connected to the PCB motherboard 1 through the solder balls 342.

[0047] Another embodiment of the present invention provides a method for fabricating the chip packaging structure as described above, comprising the following steps: S1. Apply foamed resin coating to the surface of the first polymer graphitized film 43, then cover the surface of the foamed resin coating with the second polymer graphitized film 45, and perform heating curing and foaming treatment to obtain the transverse heat-conducting sheet 4. S2. The first chip 31, the lateral heat-conducting sheet 4 and the second chip 32 are stacked in sequence and pre-fixed on the chip substrate 34. The chip substrate 34, the first chip 31 and the second chip 32 are wired. The first chip 31, the lateral heat-conducting sheet 4 and the second chip 32 on the chip substrate 34 are packaged to form a packaging layer 33, and a packaged chip 3 is obtained. A portion of the lateral heat-conducting sheet 4 extends out of the packaging layer 33 to form an external part 42. S3. The packaged chip 3 is attached to the PCB motherboard 1 with the heat sink 2 embedded, so that the first polymer graphitized film 43 of the external part 42 contacts the heat sink 2 for heat conduction.

[0048] By constructing an integrated structure of "2 heat sinks + 4 layered horizontal heat-conducting sheets + stacked packaged chips", the heat dissipation problem of stacked chips is solved from two dimensions: heat conduction path optimization and thermal interference isolation. This ensures the working stability of temperature-sensitive chips and improves the reliability and service life of the entire package structure.

[0049] In some embodiments, the following operations are also included: S4. Place the heat sink 5 on the surface of the external part 42 away from the heat sink block 2, so that the heat sink 5 contacts the second polymer graphitized film 45, and fix the heat sink 5 and the heat sink block 2 with ceramic screws 6, with the external part 42 clamped between the heat sink 5 and the heat sink block 2.

[0050] By fixing the radiator 5 and the heat sink block 2 with ceramic screws 6, the external part 42 of the horizontal heat-conducting plate 4 can be firmly clamped between the two, ensuring the stability and continuity of the heat dissipation path, avoiding the increase of contact gap due to temperature changes or vibration, and thus ensuring the long-term stability of heat dissipation efficiency.

[0051] In some embodiments, in step S1, a first alumina layer 46 is sputtered to form on the surface of the first polymer graphitized film 43, and a second alumina layer 47 is sputtered to form on the surface of the second polymer graphitized film 45.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that, The system includes a PCB motherboard, a heat sink, a packaged chip, and a lateral thermal conductive sheet. The packaged chip includes a chip substrate, a first chip, a second chip, and a packaging layer. The heat sink is embedded in the PCB motherboard. The chip substrate is located on one side of the heat sink and is electrically connected to the PCB motherboard. The first chip is located on the surface of the chip substrate facing away from the PCB motherboard and is electrically connected to the chip substrate. The second chip is stacked on the side of the first chip facing away from the chip substrate and is electrically connected to the first chip. The packaging layer is located on the chip substrate. The first chip and the second chip are encapsulated in the encapsulation layer. The lateral heat-conducting sheet includes a first polymer graphitized film, a foamed heat insulation layer and a second polymer graphitized film stacked sequentially. The lateral heat-conducting sheet has an internal portion and an external portion. The internal portion is located between the first chip and the second chip, and the first polymer graphitized film of the internal portion conducts heat with the first chip. The second polymer graphitized film of the internal portion conducts heat with the second chip. The external portion of the lateral heat-conducting sheet extends out of the encapsulation layer, and the first polymer graphitized film of the external portion conducts heat with the heat sink.

2. The chip packaging structure according to claim 1, characterized in that, The first polymer graphitized film and the second polymer graphitized film are selected from polyimide graphitized films. The polyimide graphitized film has a plurality of graphite sheets stacked in parallel in sequence. The planar thermal conductivity of the polyimide graphitized film is 1200~1500 W / m·K, and the vertical thermal conductivity of the polyimide graphitized film is 5~10 W / m·K.

3. The chip packaging structure according to claim 1, characterized in that, The foamed insulation layer is obtained by foaming and curing a foamed resin coating, and the foamed resin coating comprises the following components by weight: The ingredients are: 40-60 parts of organosilicon resin, 7-12 parts of azodicarbonamide, 4-6 parts of aminosilane curing agent, 1-3 parts of dispersant, 0.5-2 parts of silane coupling agent, and 10-30 parts of solvent.

4. The chip packaging structure according to claim 1, characterized in that, A first alumina layer is disposed between the first polymer graphitized film and the first chip, and a second alumina layer is disposed between the second polymer graphitized film and the second chip.

5. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes a heat sink and ceramic screws. The heat sink is disposed on the surface of the second polymer graphitized film of the external part away from the foamed heat insulation layer. The ceramic screws pass through the heat sink and the lateral heat-conducting sheet in sequence and are connected to the heat sink block.

6. The chip packaging structure according to claim 5, characterized in that, The number of packaged chips is multiple, and the multiple packaged chips are disposed on the outer periphery of the heat sink, and the multiple packaged chips share a single transverse heat-conducting sheet. The packaged layer abuts against the outer wall of the heat sink and the heat sink. A porous metal layer is provided at the bottom of the heat sink, and the porous metal layer does not protrude from the surface of the PCB motherboard.

7. The chip packaging structure according to claim 1, characterized in that, The second chip is offset from the first chip. The first chip has a stepped surface that is not covered by the second chip. The first chip has a first pad at the stepped surface. The second chip has a second pad. The chip substrate has a third pad. The third pad and the first pad are electrically connected by a first metal line. The second pad and the first pad are electrically connected by a second metal line.

8. The chip packaging structure according to claim 1, characterized in that, The bottom surface of the chip substrate is provided with a plurality of solder balls, and the chip substrate is electrically connected to the PCB motherboard through the solder balls.

9. The method for fabricating a chip packaging structure according to any one of claims 1 to 8, characterized in that, The following steps are included: S1. Apply foamed resin coating to the surface of the first polymer graphitized film, then cover the surface of the foamed resin coating with the second polymer graphitized film, and perform heating curing and foaming treatment to obtain a transverse heat-conducting sheet. S2. The first chip, the lateral heat-conducting sheet and the second chip are stacked in sequence and pre-fixed on the chip substrate. The chip substrate, the first chip and the second chip are wired. The first chip, the lateral heat-conducting sheet and the second chip on the chip substrate are packaged to form a package layer to obtain a packaged chip. A portion of the lateral heat-conducting sheet extends out of the package layer to form an external part. S3. The packaged chip is attached to the PCB motherboard with the heat sink embedded, so that the first polymer graphitized film of the external part comes into contact with the heat sink for heat conduction.

10. The method for fabricating a chip packaging structure according to claim 9, characterized in that, This also includes the following operations: S4. Place the heat sink on the surface of the external part away from the heat sink block, so that the heat sink contacts the second polymer graphitized film, and fix the heat sink and the heat sink block with ceramic screws, with the external part clamped between the heat sink and the heat sink block.

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