Package substrate with lines embedded in two sides and preparation method of package substrate

Abstract

The invention provides a package substrate with lines embedded in two sides and a preparation method of the package substrate. According to the packaging substrate and the preparation method thereof, the first circuit layer of the outer-layer substrate is embedded into the base material layer, and the outer-layer substrate is pressed on the two surfaces of the inner-layer substrate, so that double-sided embedded circuits are realized, the line width and the line distance of the embedded first circuit layer can be smaller, and the wiring density can be improved. In addition, the first circuit layer comprises the electric conduction and heat conduction layer, so that the heat conduction efficiency and the heat dissipation effect of the packaging substrate are improved. In addition, the conductive performance and the structural strength of the conductive holes formed by the solder paste and the connecting pads (copper) are remarkably improved, and the reliability of the packaging substrate is improved.

Description

Technical Field

[0001] This application relates to a packaging substrate with double-sided embedded circuitry and a method for preparing the same. Background Technology

[0002] Existing packaging substrates typically employ embedded traces (ETS) fabrication technology, where embedded traces are fabricated on one side of the substrate, while the other side can only accommodate non-embedded traces. Compared to non-embedded traces, embedded traces have smaller linewidths and spacing, allowing for increased wiring density. Therefore, the wiring density of existing packaging substrates with embedded traces on only one side needs further improvement. Summary of the Invention

[0003] In view of this, this application proposes a packaging substrate with double-sided embedded circuitry and a method for preparing the same, in order to improve wiring density.

[0004] One embodiment of this application provides a method for preparing a packaging substrate with double-sided embedded circuitry, comprising the following steps:

[0005] An outer substrate is provided, the outer substrate including a first copper foil layer, a first circuit layer located on the surface of the first copper foil layer, a substrate layer, and a second circuit layer formed on the surface of the substrate layer opposite to the first copper foil layer, wherein the first circuit layer is embedded in the substrate layer, and a portion of the surface of the second circuit layer is provided with a raised connection pad.

[0006] An inner layer substrate is provided, wherein a through hole is formed on the inner layer substrate, and solder paste is disposed in the through hole and protrudes from the surface of the inner layer substrate;

[0007] Two outer substrates are pressed onto the opposite surfaces of the inner substrate, so that the connecting pad extends into the solder paste of the through hole. The solder paste surrounds the connecting pad to form a conductive hole that electrically connects the two outer substrates.

[0008] Remove the first copper foil layer.

[0009] In one embodiment, the first circuit layer includes a metal layer and a conductive and thermally conductive layer, wherein the conductive and thermally conductive layer is located between the first copper foil layer and the metal layer.

[0010] In one embodiment, the metal layer comprises copper, and the conductive and thermally conductive layer comprises carbon nanotubes.

[0011] In one embodiment, the preparation method further includes: providing a protective layer on the surface of the substrate layer facing away from the second circuit layer, the protective layer having a plurality of grooves, and a portion of the surface of the first circuit layer facing away from the second circuit layer being exposed from the grooves.

[0012] In one embodiment, the method for fabricating the outer substrate includes the following steps: depositing a conductive and thermally conductive layer on a first copper-clad laminate; wherein the first copper-clad laminate includes a dielectric layer and copper foil layers located on opposite surfaces of the dielectric layer, each copper foil layer including a first copper foil layer and a second copper foil layer, and the conductive and thermally conductive layer is located on the surface of the first copper foil layer opposite to the second copper foil layer; depositing a metal layer on the surface of the conductive and thermally conductive layer opposite to the first copper foil layer, the metal layer and the conductive and thermally conductive layer together forming a first circuit layer; and laminating a second copper-clad laminate onto the surface of the first circuit layer; wherein the second copper-clad laminate includes a substrate layer and a layer located on the substrate layer. A third copper foil layer is formed on the surface of the first circuit layer, which is embedded within the substrate layer. A blind via is formed on the second copper-clad laminate, and a portion of the surface of the first circuit layer is exposed through the blind via. A copper plating layer is formed on the surface of the third copper foil layer away from the substrate layer and inside the blind via. The third copper foil layer and the copper plating layer on its surface are used together to form a second circuit layer. A portion of the surface of the second circuit layer is provided with raised connecting pads. The blind via and the copper plating layer inside it form a conductive via. The first circuit layer and the second circuit layer are electrically connected through the conductive via. The first copper foil layer and the second copper foil layer are separated to obtain the outer substrate.

[0013] In one embodiment, the method for preparing the inner layer substrate includes the following steps: providing a third copper-clad laminate, the third copper-clad laminate including an insulating adhesive layer and a fourth copper foil layer located on the surface of the insulating adhesive layer; forming a through hole in the third copper-clad laminate, the through hole penetrating the third copper-clad laminate along the thickness direction of the third copper-clad laminate; removing the fourth copper foil layer; and distributing solder paste in the through hole and making the solder paste protrude from the surface of the insulating adhesive layer to obtain the inner layer substrate.

[0014] One embodiment of this application provides a packaging substrate with double-sided embedded circuitry, including an inner substrate and two outer substrates located on opposite surfaces of the inner substrate.

[0015] Each outer substrate includes a first circuit layer, a substrate layer, and a second circuit layer. The first circuit layer is embedded in the substrate layer, and the second circuit layer is located between the substrate layer and the inner substrate. The portion of the second circuit layer facing away from the first circuit layer has a protruding connecting pad, which is formed of copper.

[0016] The inner substrate has a conductive hole that penetrates the inner substrate. The two connecting pads of the two outer substrates are located in the conductive hole. Solder paste is also provided in the conductive hole and is arranged around the connecting pad. The conductive hole is electrically connected to the two outer substrates.

[0017] In one embodiment, the first circuit layer includes a metal layer and a conductive and thermally conductive layer, wherein the conductive and thermally conductive layer is located on the surface of the metal layer opposite to the second circuit layer.

[0018] In one embodiment, the metal layer comprises copper, and the conductive and thermally conductive layer comprises carbon nanotubes.

[0019] In one embodiment, the packaging substrate further includes a protective layer located on the surface of the substrate layer facing away from the second circuit layer. The protective layer has a plurality of grooves, and a portion of the surface of the first circuit layer facing away from the second circuit layer is exposed from the grooves.

[0020] This application achieves double-sided embedded wiring by embedding the first circuit layer of the outer substrate within the substrate layer and laminating an outer substrate onto both surfaces of the inner substrate. The embedded first circuit layer allows for a smaller linewidth and spacing, thus increasing wiring density. Furthermore, the first circuit layer includes a conductive and thermally conductive layer, improving the thermal conductivity and heat dissipation of the packaging substrate. In addition, the conductive vias formed by solder paste and connecting pads (copper) exhibit significantly improved conductivity and structural strength, enhancing the reliability of the packaging substrate. Attached Figure Description

[0021] Figures 1A to 1G This is a cross-sectional view of the preparation of the outer layer substrate according to an embodiment of this application.

[0022] Figures 2A to 2C This is a cross-sectional view of the preparation of an inner layer substrate according to an embodiment of this application.

[0023] Figure 3 To be Figure 1G The outer substrate shown and Figure 2C The cross-sectional view shown is of the inner layer substrate after lamination.

[0024] Figure 4 To be Figure 3 A cross-sectional view of the structure shown after the first copper foil layer has been removed.

[0025] Figure 5 In order to be in Figure 4 A cross-sectional view of the encapsulation substrate obtained after the protective layer is applied to the structure shown in one embodiment.

[0026] Explanation of main component symbols

[0027] Packaging substrate 100

[0028] Outer substrate 10

[0029] First copper-clad laminate 11

[0030] Dielectric layer 12

[0031] First copper foil layer 13

[0032] Second copper foil layer 14

[0033] Conductive and thermal conductive layer 20

[0034] Metal layer 30

[0035] First line layer 15

[0036] Second copper-clad laminate 16

[0037] Substrate layer 17

[0038] Third copper foil layer 18

[0039] Second line layer 19

[0040] Inner substrate 40

[0041] Third copper-clad laminate 41

[0042] Insulating adhesive layer 42

[0043] Fourth copper foil layer 43

[0044] Solder paste 44

[0045] Protective layer 50

[0046] Groove 501

[0047] Blind hole 160

[0048] Through hole 161

[0049] Connecting pad 191

[0050] Through hole 410

[0051] Conductive hole 411

[0052] The following detailed description, in conjunction with the accompanying drawings, further illustrates the embodiments of this application. Detailed Implementation

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application pertain. The terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the embodiments of this application. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0054] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0055] It will be understood that when a layer is referred to as "on" another layer, it can be directly on that other layer or there may be an intermediate layer in between. Conversely, when a layer is referred to as "directly on" another layer, there is no intermediate layer. When a component is referred to as "fixed to," "mounted to," or "set on" another component, it can be directly on that other component or there may be an intermediate component. The term "and / or" as used herein includes all and any combination of one or more of the associated listed items.

[0056] Embodiments of this application are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments (and intermediate configurations) of this application. Therefore, variations in the shapes illustrated due to manufacturing processes and / or tolerances are foreseeable. Consequently, embodiments of this application should not be construed as limited to the specific shapes of the areas illustrated herein, but should include, for example, deviations in shape due to manufacturing processes. The areas shown in the figures are merely illustrative, and their shapes are not intended to represent the actual shapes of the illustrated devices, nor are they intended to limit the scope of this application.

[0057] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0058] Please see Figures 1A to 5 The first aspect of this application provides a method for fabricating a double-sided embedded circuit packaging substrate 100, including steps S10 to S50. It is understood that the numbering of the steps is intended to clearly describe the specific fabrication method and does not imply a limitation on the order of the steps. For example, steps S10 (providing an outer substrate) and S20 (providing an inner substrate) can be performed with S10 first and then S20, or S20 can be performed first and then S10, or S10 and S20 can be performed simultaneously.

[0059] Please see Figures 1A to 1G Step S10: Provide an outer substrate 10. In some embodiments, the outer substrate 10 may be prepared by steps S11 to S17.

[0060] S11, such as Figure 1AAs shown, a first copper-clad laminate 11 is provided. The first copper-clad laminate 11 may include a dielectric layer 12 and copper foil layers located on opposite surfaces of the dielectric layer 12. Each copper foil layer includes a first copper foil layer 13 and a second copper foil layer 14, with the second copper foil layer 14 located between the first copper foil layer 13 and the dielectric layer 12. The first copper foil layer 13 and the second copper foil layer 14 are bonded together in a peelable state, and the first copper foil layer 13 can be manually peeled off from the second copper foil layer 14.

[0061] In some embodiments, the dielectric layer 12 may be made of, but is not limited to, polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate dimethyl acid glycol ester (PEN), polydimethylsiloxane (PDMS), liquid crystal polymer (LCP), modified polyimide (MPI), and other materials.

[0062] S12, as Figure 1B As shown, a conductive and thermally conductive layer 20 can be formed on the first copper-clad laminate 11 by means of spraying, printing, etc. The conductive and thermally conductive layer 20 has electrical conductivity and high thermal conductivity, which can improve the heat dissipation effect. In this embodiment, the conductive and thermally conductive layer 20 is located on two opposite surfaces of the first copper-clad laminate 11; in other embodiments, the conductive and thermally conductive layer 20 is located on only one surface of the first copper-clad laminate 11. Regardless of whether the conductive and thermally conductive layer 20 is located on one or both surfaces of the first copper-clad laminate 11, the conductive and thermally conductive layer 20 is located on the surface of the first copper foil layer 13 facing away from the second copper foil layer 14, and only covers the part of the surface of the first copper foil layer 13 facing away from the second copper foil layer 14. The part of the surface of the second copper foil layer 14 close to the first copper foil layer 13 can be exposed from the conductive and thermally conductive layer 20.

[0063] In some embodiments, the conductive and thermally conductive layer 20 may be nano-carbon. The carbon atoms in the nano-carbon coating have high thermal radiation efficiency, which can convert heat energy into infrared radio frequency and radiate heat into the surrounding space, thereby achieving a highly efficient heat dissipation effect. The structure composed of nano-carbon and the first copper foil layer 13 is also referred to as nano-carbon copper foil.

[0064] S13, as Figure 1CAs shown, a metal layer 30 can be formed on the surface of the conductive and thermally conductive layer 20 facing away from the first copper foil layer 13 by means of electroplating, but not limited to electroplating. The wiring pattern of the metal layer 30 is completely consistent with that of the conductive and thermally conductive layer 20, and the metal layer 30 and the conductive and thermally conductive layer 20 together form the first circuit layer 15. A portion of the surface of the first copper foil layer 13 facing away from the second copper foil layer 14 can be exposed from the first circuit layer 15. The metal layer 30 can be made of copper.

[0065] S14, as Figure 1D As shown, a second copper-clad laminate 16 is laminated onto the surface of the first circuit layer 15. The second copper-clad laminate 16 includes a substrate layer 17 and a third copper foil layer 18 located on one surface of the substrate layer 17. After lamination, the first circuit layer 15 is embedded within the substrate layer 17, and the substrate layer 17 can cover the surface of the first copper foil layer 13 exposed from the first circuit layer 15. In this embodiment, there are two first circuit layers 15, located on the upper and lower surfaces of the first copper-clad laminate 11 respectively. Therefore, a second copper-clad laminate 16 is laminated onto the upper and lower surfaces of the first copper-clad laminate 11 respectively. In other embodiments, there is only one first circuit layer 15, so only one second copper-clad laminate 16 needs to be laminated.

[0066] In some embodiments, the material of the substrate layer 17 may be, but is not limited to, PI, PET, PEN, PDMS, LCP, MPI, etc.

[0067] S15, such as Figure 1E As shown, a plurality of blind vias 160 can be formed on the second copper-clad laminate 16 by means of, but not limited to, laser. The blind vias 160 penetrate the third copper foil layer 18 and a portion of the substrate layer 17 along the thickness direction of the second copper-clad laminate 16. A portion of the surface of the first circuit layer 15 facing away from the first copper foil layer 13 can be exposed through the blind vias 160.

[0068] S16, as Figure 1F As shown, a copper plating layer (not shown) can be formed on the surface of the third copper foil layer 18 away from the substrate layer 17 and inside the blind via 160 by means of electroplating, but not limited to electroplating. The blind via 160 and the copper plating layer inside it form a via 161. The third copper foil layer 18 and the copper plating layer on its surface are used together to form the second circuit layer 19. The second circuit layer 19 can be formed by steps such as lamination, exposure, development, etching, and film removal. The first circuit layer 15 and the second circuit layer 19 are electrically connected through the via 161. After the second circuit layer 19 is fabricated, copper can be electroplated on a portion of the surface of the second circuit layer 19 to form raised connecting pads 191, which are electrically connected to the second circuit layer 19. The connecting pads 191 can also be formed when the copper plating layer is set, and then the third copper foil layer 18 and the copper plating layer on its surface are used to form the second circuit layer 19.

[0069] S17, as shown Figure 1GAs shown, the first copper foil layer 13 and the second copper foil layer 14 are separated, and the structure of the first copper foil layer 13 and its surface forms the outer substrate 10. The outer substrate 10 includes the first copper foil layer 13, a first circuit layer 15 located on the surface of the first copper foil layer 13, a substrate layer 17, and a second circuit layer 19 formed on the surface of the substrate layer 17 opposite to the first copper foil layer 13. The first circuit layer 15 is embedded in the substrate layer 17, and a portion of the surface of the second circuit layer 19 is provided with raised connecting pads 191.

[0070] Please see Figures 2A to 2C In step S20, an inner layer substrate 40 is provided. In some embodiments, the inner layer substrate 40 may be prepared by steps S21 to S24.

[0071] S21, as Figure 2A As shown, a third copper-clad laminate 41 is provided. The third copper-clad laminate 41 includes an insulating adhesive layer 42 and a fourth copper foil layer 43 located on opposite surfaces of the insulating adhesive layer 42. The insulating adhesive layer 42 may be, but is not limited to, a prepreg (PP).

[0072] S22, as Figure 2B As shown, through-holes 410 can be formed on the third copper-clad laminate 41 by means of laser, but not limited to laser engraving. The through-holes 410 penetrate the third copper-clad laminate 41 along its thickness direction, that is, they penetrate the two fourth copper foil layers 43 and the insulating adhesive layer 42. There can be multiple through-holes 410.

[0073] S23, as Figure 2C As shown, the fourth copper foil layer 43 can be removed by etching.

[0074] S24, see further. Figure 2C Solder paste 44 is provided in the through hole 410 and protrudes from both ends of the through hole 410, that is, protrudes from the surface of the insulating adhesive layer 42, to obtain the inner layer substrate 40.

[0075] like Figure 2C As shown, the inner substrate 40 mainly includes an insulating adhesive layer 42. A through hole 410 is formed on the insulating adhesive layer 42, and solder paste 44 is disposed in the through hole 410. The solder paste 44 protrudes from the two opposite surfaces of the insulating adhesive layer 42.

[0076] Step S30, please refer to Figure 3With the second circuit layer 19 of the outer substrate 10 facing the inner substrate 40, two outer substrates 10 are respectively stacked on two opposing surfaces of the inner substrate 40 along its thickness direction. The connecting pads 191 of the outer substrates 10 are roughly corresponding to the through-holes 410 and solder paste 44 of the inner substrate 40. Then, the outer substrates 10 and the inner substrate 40 are pressed together, so that the connecting pads 191 of the outer substrates 10 extend into the through-holes 410 of the inner substrate 40. The solder paste 44 in the through-holes 410 surrounds (covers) the connecting pads 191, and the two connecting pads 191 of the upper and lower outer substrates 10 are connected by the solder paste 44. The solder paste 44 and the connecting pads 191 in the through-holes 410 form conductive holes 411 that electrically connect the two outer substrates 10.

[0077] By filling the solder paste 44 and the connecting pad 191 (copper), the conductivity of the conductive hole 411 is significantly improved, which can better meet the needs of high-speed signal transmission, reduce signal interference and attenuation, and also enhance the structural strength of the conductive hole 411, reducing the risk of breakage caused by external pressure or vibration and improving reliability.

[0078] For step S40, please refer to... Figure 4 The first copper foil layer 13 can be removed by etching. After the first copper foil layer 13 is removed, the conductive and thermally conductive layer 20 in the first circuit layer 15 can be exposed from the substrate layer 17. The surface of the conductive and thermally conductive layer 20 facing away from the metal layer 30 is flush with the surface of the substrate layer 17 facing away from the second circuit layer 19.

[0079] For step S50, please refer to... Figure 5 A protective layer 50 is formed on the surface of the substrate layer 17 facing away from the second circuit layer 19. The protective layer 50 has multiple grooves 501, through which a portion of the surface of the first circuit layer 15 facing away from the second circuit layer 19 can be exposed, that is, a portion of the surface of the conductive and thermally conductive layer 20 facing away from the metal layer 30 can be exposed through the grooves 501. During packaging, the grooves 501 can be used to accommodate components such as chips to reduce the overall thickness (height) of the package structure. In addition, since the bottom of the groove 501 is the conductive and thermally conductive layer 20, which has high flatness, it can prevent the problem of inconsistent groove depth caused by etching.

[0080] In some embodiments, the protective layer 50 is a solder resist layer (also known as green paint or green oil), while in other embodiments, the protective layer 50 is a cover film layer (CVL).

[0081] Please continue reading. Figure 5 The second aspect of this application provides a packaging substrate 100 prepared by the above-described preparation method, which includes an inner substrate 40 and two outer substrates 10 located on opposite surfaces of the inner substrate 40.

[0082] Each outer substrate 10 includes a first circuit layer 15, a substrate layer 17, and a second circuit layer 19. The first circuit layer 15 is embedded within the substrate layer 17. The second circuit layer 19 is located on the surface of the substrate layer 17 and between the substrate layer 17 and the inner substrate 40. A protruding connecting pad 191, formed of copper, is provided on the portion of the second circuit layer 19 facing away from the first circuit layer 15. The first circuit layer 15 and the second circuit layer 19 can be electrically connected through a via 161.

[0083] The inner substrate 40 mainly includes an insulating adhesive layer 42, on which conductive holes 411 are formed. The conductive holes 411 electrically connect the second circuit layers 19 of the two outer substrates 10. Two connecting pads 191 of the two outer substrates 10 are located within the conductive holes 411. Solder paste 44 is also disposed within the conductive holes 411, surrounding the connecting pads 191 and completely covering them. By filling the conductive holes 411 with solder paste 44 and connecting pads 191 (copper), the conductivity of the conductive holes 411 is significantly improved, better meeting the requirements of high-speed signal transmission, reducing signal interference and attenuation, and enhancing the structural strength of the conductive holes 411, reducing the risk of breakage due to external pressure or vibration, and improving reliability.

[0084] In some embodiments, such as Figure 5 As shown, the first circuit layer 15 includes a metal layer 30 and a conductive and thermally conductive layer 20, with the conductive and thermally conductive layer 20 located on the surface of the metal layer 30 facing away from the second circuit layer 19. The metal layer 30 may be, but is not limited to, copper, and the conductive and thermally conductive layer 20 may be, but is not limited to, nano-carbon.

[0085] In some embodiments, such as Figure 5 As shown, the packaging substrate 100 also includes a protective layer 50, which is located on the surface of the substrate layer 17 facing away from the second circuit layer 19. The protective layer 50 has a plurality of grooves 501, and a portion of the surface of the first circuit layer 15 facing away from the second circuit layer 19 can be exposed from the grooves 501, that is, a portion of the surface of the conductive and thermally conductive layer 20 facing away from the metal layer 30 can be exposed from the grooves 501.

[0086] The packaging substrate 100 and its fabrication method in this application embodiment achieve double-sided embedded circuitry by embedding the first circuit layer 15 of the outer substrate 10 within the substrate layer 17 and bonding an outer substrate 10 to both surfaces of the inner substrate 40. This allows for a smaller linewidth and spacing of the embedded first circuit layer 15, thus increasing wiring density. Furthermore, the first circuit layer 15 includes a conductive and thermally conductive layer 20, improving the thermal conductivity and heat dissipation of the packaging substrate 100. In addition, the conductive vias 411 formed by the solder paste 44 and the connecting pads 191 (copper) significantly improve both conductivity and structural strength, enhancing the reliability of the packaging substrate 100.

[0087] The above description describes some specific embodiments of this application, but in actual applications, the application should not be limited to these embodiments. For those skilled in the art, other modifications and alterations made based on the technical concept of this application should fall within the protection scope of this application.

Claims

1. A method for fabricating a packaging substrate with double-sided embedded circuitry, characterized in that, Includes the following steps: An outer substrate is provided, the outer substrate including a first copper foil layer, a first circuit layer located on the surface of the first copper foil layer, a substrate layer, and a second circuit layer formed on the surface of the substrate layer opposite to the first copper foil layer, wherein the first circuit layer is embedded in the substrate layer, and a portion of the surface of the second circuit layer is provided with a raised connection pad. An inner layer substrate is provided, wherein a through hole is formed on the inner layer substrate, and solder paste is disposed in the through hole and protrudes from the surface of the inner layer substrate; Two outer substrates are pressed onto the opposite surfaces of the inner substrate, so that the connecting pad extends into the solder paste of the through hole. The solder paste surrounds the connecting pad to form a conductive hole that electrically connects the two outer substrates. Remove the first copper foil layer.

2. The preparation method according to claim 1, characterized in that, The first circuit layer includes a metal layer and a conductive and thermally conductive layer, wherein the conductive and thermally conductive layer is located between the first copper foil layer and the metal layer.

3. The preparation method according to claim 2, characterized in that, The metal layer comprises copper, and the conductive and thermally conductive layer comprises nano-carbon.

4. The preparation method according to claim 1, characterized in that, The preparation method further includes: providing a protective layer on the surface of the substrate layer facing away from the second circuit layer, the protective layer having a plurality of grooves, and a portion of the surface of the first circuit layer facing away from the second circuit layer being exposed from the grooves.

5. The preparation method according to claim 1, characterized in that, The method for preparing the outer substrate includes the following steps: A conductive and thermally conductive layer is provided on a first copper-clad laminate; wherein, the first copper-clad laminate includes a dielectric layer and copper foil layers located on opposite surfaces of the dielectric layer, each copper foil layer includes a first copper foil layer and a second copper foil layer, and the conductive and thermally conductive layer is located on the surface of the first copper foil layer away from the second copper foil layer; A metal layer is disposed on the surface of the conductive and thermally conductive layer opposite to the first copper foil layer, and the metal layer and the conductive and thermally conductive layer together form a first circuit layer; A second copper-clad laminate is laminated onto the surface of the first circuit layer; wherein the second copper-clad laminate includes a substrate layer and a third copper foil layer located on the surface of the substrate layer, and the first circuit layer is embedded in the substrate layer; A blind via is formed on the second copper-clad laminate, and a portion of the surface of the first circuit layer is exposed through the blind via; A copper plating layer is provided on the surface of the third copper foil layer away from the substrate layer and inside the blind hole. The third copper foil layer and the copper plating layer on its surface are used together to form a second circuit layer. A portion of the surface of the second circuit layer is provided with a raised connecting pad. The blind hole and the copper plating layer inside it form a through hole. The first circuit layer and the second circuit layer are electrically connected through the through hole. The first copper foil layer and the second copper foil layer are separated to obtain the outer substrate.

6. The preparation method according to claim 1, characterized in that, The method for preparing the inner layer substrate includes the following steps: A third copper-clad laminate is provided, the third copper-clad laminate including an insulating adhesive layer and a fourth copper foil layer located on the surface of the insulating adhesive layer; A through hole is formed on the third copper-clad laminate, and the through hole penetrates the third copper-clad laminate along the thickness direction of the third copper-clad laminate; Remove the fourth copper foil layer; Solder paste is applied inside the through-hole and protrudes from the surface of the insulating adhesive layer to obtain the inner layer substrate.

7. A packaging substrate with double-sided embedded circuitry, characterized in that, It includes an inner substrate and two outer substrates located on opposite surfaces of the inner substrate. Each outer substrate includes a first circuit layer, a substrate layer, and a second circuit layer. The first circuit layer is embedded in the substrate layer, and the second circuit layer is located between the substrate layer and the inner substrate. The portion of the second circuit layer facing away from the first circuit layer has a protruding connection pad, which is formed of copper. The inner substrate has a conductive hole that penetrates the inner substrate. The two connecting pads of the two outer substrates are located in the conductive hole. Solder paste is also provided in the conductive hole and is arranged around the connecting pad. The conductive hole is electrically connected to the two outer substrates.

8. The packaging substrate as described in claim 7, characterized in that, The first circuit layer includes a metal layer and a conductive and thermally conductive layer, wherein the conductive and thermally conductive layer is located on the surface of the metal layer opposite to the second circuit layer.

9. The packaging substrate as described in claim 8, characterized in that, The metal layer comprises copper, and the conductive and thermally conductive layer comprises nano-carbon.

10. The packaging substrate as claimed in claim 7, characterized in that, The packaging substrate further includes a protective layer located on the surface of the substrate layer opposite to the second circuit layer. The protective layer has multiple grooves, and a portion of the surface of the first circuit layer opposite to the second circuit layer is exposed from the grooves.

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