Integrated circuit substrate and preparation method and application thereof
By using photolithography and electroplating processes with temporary carriers and photosensitive insulating layers in the fabrication of integrated circuit substrates, the traditional process flow is simplified, and the problems of complexity and low precision of traditional processes are solved, thus achieving efficient and low-cost fabrication of integrated circuit substrates.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-27
- Publication Date
- 2026-03-24
AI Technical Summary
Traditional integrated circuit substrate fabrication processes are complex, costly, and have low precision, making it difficult to meet the demands for miniaturization, thinness, and high performance. Furthermore, the etching process suffers from lateral corrosion, which affects signal integrity and soldering quality.
By using a temporary carrier board and a photosensitive insulating layer, embedded pins and conductor layers are formed through photolithography and selective electroplating processes, simplifying the process flow, eliminating multi-layer lamination and etching steps, and improving accuracy and production efficiency.
It enables high-precision, low-cost integrated circuit substrate fabrication, simplifies the process flow, improves production efficiency and product yield, and avoids environmental pollution and material waste caused by etching.
Smart Images
Figure CN121729089A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, specifically to an integrated circuit substrate, its fabrication method, and its application. Background Technology
[0002] Integrated circuit packaging is a crucial part of modern electronic product manufacturing, serving functions such as protecting the chip, providing mechanical support, enabling electrical interconnection, and heat dissipation. The integrated circuit substrate, as the core carrier of the package, directly determines the size, electrical characteristics, reliability, and cost of the final package through its performance and manufacturing process. With the rapid development of electronic products towards miniaturization, thinner profiles, and higher performance, the demands for increasing wiring density, shrinking pin pitch, and ever-increasing signal transmission speeds are constantly rising. This places higher requirements on integrated circuit substrates, while simultaneously requiring simplified manufacturing processes to control costs.
[0003] In traditional integrated circuit substrate fabrication processes, copper-clad laminate (CCL) subtractive manufacturing methods are commonly used. A typical process includes: laminating metal foils onto both sides of a substrate; forming preliminary circuit patterns through photolithography and etching; forming conductive vias connecting upper and lower layers through drilling and electroplating; constructing multiple insulating and circuit layers, and achieving complex interconnect structures through repeated patterning, lamination, and etching steps; finally, fabricating pads and solder mask layers on the substrate surface and completing surface treatment.
[0004] However, this traditional manufacturing method usually has many inherent technical defects. First, the process is extremely long and complex, involving multiple photolithography, etching, and lamination cycles, which not only results in a long production cycle, but also the accumulated industrial deviations affect the precision and yield of the final product. Second, the etching process in building material manufacturing consumes a large amount of metal materials and generates corresponding chemical waste liquid, which is not economical or environmentally friendly. Most importantly, the etching process itself has the problem of lateral corrosion, which limits the ultimate precision and spacing of the circuit and makes it difficult to meet the needs of high-density interconnection. For example, when the pin spacing needs to reach the micrometer level, the etching process cannot guarantee the verticality and dimensional uniformity of the pin sidewalls, which can easily lead to signal integrity problems and soldering defects.
[0005] Furthermore, the formation of embedded leads or conductive pillars in traditional methods typically requires first preparing a metal pillar, then embedding it in an insulating medium during subsequent lamination, and finally creating a via through laser ablation or mechanical drilling, followed by electroplating of metal within the via to achieve the connection between the upper and lower layers. This process is cumbersome, and the precision and alignment of laser drilling pose challenges, increasing both the complexity and cost of the process.
[0006] Therefore, there is an urgent need for a high-precision, high-reliability, and low-cost method for fabricating integrated circuit substrates. Summary of the Invention
[0007] To address the shortcomings of existing technologies, this invention provides an integrated circuit substrate, its fabrication method, and its application, thus solving the problems mentioned in the background section.
[0008] To achieve the above objectives, the present invention provides the following technical solution: According to a first aspect of the present invention, a method for fabricating an integrated circuit substrate is provided, comprising the following steps: a. Provide a temporary carrier board; b. A first photosensitive insulating layer is formed on the first surface of the temporary carrier plate; c. Expose and develop the first photosensitive insulating layer to form multiple pin pattern openings; d. Electroplating a first metal layer in the opening of the pin pattern to form an embedded pin; e. A second photosensitive insulating layer is formed on the first photosensitive insulating layer, and the second photosensitive insulating layer is exposed and developed to form a conductor layer pattern; f. Electroplating a second metal layer in the conductor layer pattern to form a conductor layer and conductive contacts; g. Form a solder resist layer on the embedded pins and conductor layer; h. Remove the temporary carrier board to expose the lower surface of the embedded pins; i. A third metal layer is formed on the lower surface of the embedded pins to obtain the integrated circuit substrate.
[0009] Preferably, the temporary carrier is selected from water-soluble polymers or heat-release tapes, and the removal method of water-soluble polymers or heat-release tapes is by water-soluble or heat-release peeling, which is simple and gentle.
[0010] Preferably, the first photosensitive insulating layer and the second photosensitive insulating layer are independently selected from photosensitive polyimide or photosensitive epoxy resin, and the thickness of the first photosensitive insulating layer and the second photosensitive insulating layer is 5~50μm, achieving micron-level pattern precision through photolithography.
[0011] Preferably, the first, second, and third metal layers are independently selected from copper, silver, gold, or nickel. The metal layers are primarily plated using pulse electroplating to improve uniformity and precision.
[0012] Preferably, the solder resist layer is formed by photolithography or inkjet printing, and the material of the solder resist layer is photosensitive solder resist ink with a thickness of 10~30μm.
[0013] Preferably, a protective film is also attached to the surface of the third metal layer, and the protective film is a high-temperature resistant tape.
[0014] According to a second aspect of the present invention, an integrated circuit substrate obtained according to the above-described preparation method is provided, comprising a photosensitive insulating substrate having a first surface and a second surface; Multiple embedded pins are embedded in the photosensitive insulating substrate and exposed from the second surface; The conductive layer and conductive contacts are located on the first surface of the photosensitive insulating substrate; A solder mask layer that covers the embedded pins and part of the conductor layer; A third metal layer covers the lower surface of the embedded pin.
[0015] Preferably, the surface of the third metal layer is provided with a protective film.
[0016] According to a third aspect of the present invention, an application of an integrated circuit substrate in an integrated circuit package is provided. Beneficial effects
[0017] This invention provides an integrated circuit substrate, its fabrication method, and its application. It offers the following advantages: (1) The method for preparing an integrated circuit substrate provided in this solution introduces a temporary carrier and a photosensitive insulating layer. Through photolithography patterning and selective electroplating, the traditional subtractive etching and multilayer lamination steps can be fundamentally avoided. The process has high precision and is simple.
[0018] (2) The method for preparing an integrated circuit substrate provided by this solution is to form a wire by etching a pattern on a photosensitive insulating layer and electroplating it in one step, which can save the complicated steps of copper plating, copper etching and chemical copper plating in the traditional process, resulting in a shorter process flow and higher production efficiency.
[0019] (3) The integrated circuit substrate provided by this solution has a compact structure, high pin and wire precision, and can be directly used for chip mounting and injection molding. Attached Figure Description
[0020] Figure 1-10 This is a schematic diagram of the integrated circuit substrate fabrication process according to an embodiment of the present invention; Figure 11 This is a schematic diagram of an integrated circuit substrate with a protective film according to another embodiment of the present invention; In the figure, 100 is a temporary carrier board; 101 is the first photosensitive insulating layer; 102 is the pin pattern opening; 103 is the embedded pin; 104 is the second photosensitive insulating layer; 105 is the wire pattern; 106 is the wire layer; 107 is the conductive contact; 108 is the solder mask layer; 109 is the third metal layer; and 110 is the protective film. Detailed Implementation
[0021] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting the invention.
[0022] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” and their derivatives should be interpreted as referring to the directions described in the discussion or in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.
[0023] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a diagram or a series of diagrams. "First," "second," "third," etc., are not intended to describe the corresponding components.
[0024] Figure 1-10 This is a flowchart of the integrated circuit substrate fabrication process according to an embodiment of the present invention. Figure 1 In this process, a temporary carrier plate 100 with a thickness of 100μm is provided. The temporary carrier plate is selected from water-soluble polymers or heat-release tapes. It is removed by water-soluble or hot glass methods to achieve gentle and low mechanical stress peeling. This not only avoids mechanical damage to the already formed delicate and fragile pin and wire structures, but also ensures the yield of the product.
[0025] Figure 2 In this process, a first photosensitive insulating layer 101 with a thickness of 5~50μm is formed on a temporary carrier by spin coating. The first photosensitive insulating layer 102 is selected from photosensitive polyimide or photosensitive epoxy resin. It not only has excellent insulation and photolithography patterning capabilities, but can also directly form high-precision pattern openings through exposure and development without additional photoresist and resist removal steps. By controlling the thickness of the photosensitive insulating layer to 5~50μm, not only can sufficient insulation strength be guaranteed, but also extremely high line density can be achieved. At the same time, the overall mechanical strength and rigidity of the substrate can be guaranteed, preventing warping or breakage during processing, while providing sufficient wrapping and support for the embedded pins.
[0026] Figure 3 In the process, after the first photosensitive insulating layer 101 is exposed and developed, a pin pattern opening 102 with a diameter of 30μm is formed.
[0027] Figure 4In this process, a first metal layer is filled into the pin pattern opening 102 using pulse electroplating to form an embedded pin 103. The material of the first metal layer can be any one of copper, silver, gold or nickel. The embedded pin 103 is formed by filling the pin pattern opening 102 with the first metal.
[0028] Figure 5 In this process, a second photosensitive insulating layer 104 is formed on the first photosensitive insulating layer 101. The material of the second photosensitive insulating layer 104 can be the same as the material of the first photosensitive insulating layer 101 or it can be different from the material of the first photosensitive insulating layer 101. As a preferred approach, the material of the second photosensitive insulating layer 104 is the same as the material of the first photosensitive insulating layer 101.
[0029] Figure 6 In the process, the wire pattern 105 is formed after exposure and development of the second photosensitive insulating layer 104.
[0030] Figure 7 In this process, a conductor layer 106 and a conductive contact 107 are formed by electroplating. The conductor layer 106 and the conductive contact 107 are integrally formed in a one-step electroplating process. The conductor layer 106 and the conductive contact 107 formed are complete metal crystal structures, and there are no interface or bonding force problems. They have excellent conductivity and mechanical reliability.
[0031] Figure 8 In this process, a 10-30 μm solder resist layer 108 is formed on the surface of the embedded pin 103 and the conductor layer 106 using photolithography. The solder resist layer is formed by photolithography or inkjet printing, which can achieve precise windowing to accurately expose the conductive contacts that need to be soldered, while perfectly covering the delicate conductors that need to be protected to prevent bridging.
[0032] Figure 9 In the middle, the temporary carrier board 100 is removed, exposing the lower surface of the embedded pin 103.
[0033] Figure 10 In this process, a third metal layer 109 is formed on the lower surface of the embedded pin 103 to obtain an integrated circuit substrate.
[0034] In a specific embodiment, such as Figure 11 As shown, a protective film 110 is also attached to the surface of the third metal layer 109. By attaching the protective film 110, additional mechanical support and stress balance can be provided for the integrated circuit substrate, which can effectively suppress warping that is prone to occur due to the mismatch of the thermal expansion coefficients of the materials. For large-area, thin integrated circuit substrates, the yield during the packaging process can be greatly improved.
[0035] The technical solution of the present invention will be further described in detail below with reference to specific embodiments.
[0036] Example 1
[0037] An integrated circuit substrate is prepared by the following method: S1. Provide a water-soluble polymer temporary carrier plate with a thickness of 100μm; S2. A first photosensitive polyimide layer with a thickness of 20 μm is formed on a water-soluble polymer temporary carrier by spin coating; S3. After exposing and developing the first photosensitive polyimide layer, a pin pattern opening with a diameter of 30μm is formed. S4. Use pulse electroplating to fill the opening in the pin pattern with copper to form an embedded pin; S5. A second photosensitive polyimide layer with a thickness of 15 μm is formed on the first photosensitive polyimide layer; S6. After exposure and development of the second photosensitive polyimide layer, a wire pattern is formed. S7. A conductor layer and conductive contacts are formed by copper electroplating. S8. A solder resist layer with a thickness of 25μm is formed on the surface of the embedded pins and conductor layer using photolithography. S9. Remove the temporary carrier board to expose the lower surface of the embedded pins; S10. A third metal layer is formed on the lower surface of the embedded pins to obtain an integrated circuit substrate.
[0038] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A method for fabricating an integrated circuit substrate, characterized in that: Includes the following steps: a. Provide a temporary carrier board; b. A first photosensitive insulating layer is formed on the first surface of the temporary carrier plate; c. Expose and develop the first photosensitive insulating layer to form multiple pin pattern openings; d. Electroplating a first metal layer in the opening of the pin pattern to form an embedded pin; e. A second photosensitive insulating layer is formed on the first photosensitive insulating layer, and the second photosensitive insulating layer is exposed and developed to form a conductor layer pattern; f. Electroplating a second metal layer in the conductor layer pattern to form a conductor layer and conductive contacts; g. Form a solder resist layer on the embedded pins and conductor layer; h. Remove the temporary carrier board to expose the lower surface of the embedded pins; i. A third metal layer is formed on the lower surface of the embedded pins to obtain the integrated circuit substrate.
2. The method for preparing an integrated circuit substrate according to claim 1, characterized in that: The temporary carrier plate is selected from water-soluble polymers or heat-release tapes.
3. The method for fabricating an integrated circuit substrate according to claim 1, characterized in that: The first photosensitive insulating layer and the second photosensitive insulating layer are independently selected from photosensitive polyimide or photosensitive epoxy resin, and the thickness of the first photosensitive insulating layer and the second photosensitive insulating layer is 5~50μm.
4. The method for fabricating an integrated circuit substrate according to claim 1, characterized in that: The first metal layer, the second metal layer, and the third metal layer are independently selected from any one of copper, silver, gold, or nickel.
5. The method for fabricating an integrated circuit substrate according to claim 1, characterized in that: The solder resist layer is formed by photolithography or inkjet printing, and the material of the solder resist layer is photosensitive solder resist ink with a thickness of 10~30μm.
6. The method for fabricating an integrated circuit substrate according to claim 1, characterized in that: A protective film, which is a high-temperature resistant tape, is also attached to the surface of the third metal layer.
7. An integrated circuit substrate obtained by the fabrication method according to any one of claims 1 to 6, characterized in that: It includes a photosensitive insulating substrate having a first surface and a second surface; Multiple embedded pins are embedded in the photosensitive insulating substrate and exposed from the second surface; The conductive layer and conductive contacts are located on the first surface of the photosensitive insulating substrate; A solder mask layer that covers the embedded pins and part of the conductor layer; A third metal layer covers the lower surface of the embedded pin.
8. An integrated circuit substrate according to claim 7, characterized in that: The surface of the third metal layer is provided with a protective film.
9. The application of an integrated circuit substrate as described in claim 7 or 8 in an integrated circuit package.