Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided are a semiconductor device capable of maximizing the height of a side electrode, and a method for manufacturing the semiconductor device. According to one embodiment, a semiconductor device includes a first frame, a second frame, a first semiconductor element, a wire, and a package member. The second frame is disposed so as to face the first frame in the first direction, and has a stepped portion at an end portion on the first frame side of the upper surface. The first semiconductor element is disposed on the bottom surface of the step portion. The line electrically connects the first semiconductor element and the first frame. The package member covers a portion of each of the first frame and the second frame, and seals the first semiconductor element and the line. A lower surface of the first frame and a side surface of the first frame in the first direction are exposed from the package member. A lower surface of the second frame and a side surface of the second frame in the first direction are exposed from the package member.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2024-163645 (filed on September 20, 2024). This application incorporates all the contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0004] A semiconductor device is known to include a lead frame on which semiconductor elements are mounted. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor device capable of maximizing the height of the side electrodes and a method for manufacturing the semiconductor device.

[0006] One embodiment of a semiconductor device includes a first frame, a second frame, a first semiconductor element, a wire, and a packaging component. The second frame is disposed opposite the first frame in a first direction and has a stepped portion at its end on the first frame side of its upper surface. The first semiconductor element is disposed on the bottom surface of the stepped portion of the second frame. The wire electrically connects the first semiconductor element to the first frame. The packaging component covers a portion of both the first and second frames and seals the first semiconductor element and the wire. The lower surface of the first frame and a first side of the first frame farther from the second frame in the first direction are exposed from the packaging component. The lower surface of the second frame and a second side of the second frame farther from the first frame in the first direction are exposed from the packaging component.

[0007] A method for manufacturing a semiconductor device includes the following steps: forming a stepped portion at the end of the upper surface of a lead frame substrate, which includes a first substrate and a second substrate disposed opposite to the first substrate in a first direction, on the first substrate side; forming a first semiconductor element on the bottom surface of the stepped portion of the second substrate; connecting the first semiconductor element to the first substrate using a wire; covering a portion of each of the first substrate and the second substrate using an encapsulation component, and sealing the first semiconductor element and the wire using the encapsulation component; forming a plating layer on the lower surface and side surface of the first substrate exposed from the encapsulation component and on the lower surface and side surface of the second substrate exposed from the encapsulation component; and dicing the lead frame substrate and the encapsulation component. Attached Figure Description

[0008] Figure 1 This is a perspective view showing an example of the external shape of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a perspective view showing an example of the external shape of the semiconductor device according to the first embodiment.

[0010] Figure 3 This is a perspective view showing an example of the structure of the semiconductor device according to the first embodiment.

[0011] Figure 4 This is a top view showing an example of the structure of the semiconductor device according to the first embodiment.

[0012] Figure 5 This is a bottom view showing an example of the structure of the semiconductor device according to the first embodiment.

[0013] Figure 6 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0014] Figure 7 This is a cross-sectional view showing the structure of an installation example of the semiconductor device according to the first embodiment.

[0015] Figure 8 This is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0016] Figure 9 This is a diagram illustrating the steps in the manufacturing method of the semiconductor device according to the first embodiment.

[0017] Figure 10 This is a diagram illustrating the steps in the manufacturing method of the semiconductor device according to the first embodiment.

[0018] Figure 11 This is a diagram illustrating the steps in the manufacturing method of the semiconductor device according to the first embodiment.

[0019] Figure 12 This is a diagram illustrating the steps in the manufacturing method of the semiconductor device according to the first embodiment.

[0020] Figure 13 This is a diagram illustrating the steps in the manufacturing method of the semiconductor device according to the first embodiment.

[0021] Figure 14 This is a diagram illustrating the steps in the manufacturing method of the semiconductor device according to the first embodiment.

[0022] Figure 15 This is a diagram illustrating the steps in the manufacturing method of the semiconductor device according to the first embodiment.

[0023] Figure 16 This is a perspective view showing an example of the structure of the semiconductor device according to the second embodiment.

[0024] Figure 17 This is a top view showing an example of the structure of the semiconductor device according to the second embodiment.

[0025] Figure 18 This is a bottom view showing an example of the structure of the semiconductor device according to the second embodiment.

[0026] Figure 19 This is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0027] Figure 20 This is a top view showing an example of the structure of the semiconductor device according to the third embodiment.

[0028] Figure 21 This is a bottom view showing an example of the structure of the semiconductor device according to the third embodiment.

[0029] Figure 22 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the third embodiment.

[0030] Figure 23 This is a top view showing an example of the structure of the semiconductor device according to the fourth embodiment.

[0031] Figure 24 This is a bottom view showing an example of the structure of the semiconductor device according to the fourth embodiment. Detailed Implementation

[0032] The embodiments will now be described with reference to the accompanying drawings. The dimensions and scale of the drawings are not necessarily identical to reality. Furthermore, in the following description, constituent elements having substantially the same function and structure are labeled with the same reference numerals, and repeated descriptions are sometimes omitted. In particular, when distinguishing elements having the same structure from each other, different words or numbers may be appended to the end of the same reference numerals. Moreover, all descriptions of a particular embodiment may be applied to the description of another embodiment unless explicitly stated or clearly excluded.

[0033] 1. First Implementation Method

[0034] The semiconductor device of the first embodiment will be described. Hereinafter, a semiconductor device having a wettable flank (WF) structure will be used as an example for description. The semiconductor device of this embodiment is, for example, suitable for automotive semiconductor packages.

[0035] 1.1 Structure of Semiconductor Devices

[0036] First, use Figures 1-6The structure of the semiconductor device is described. The semiconductor device 1 includes a semiconductor element, a lead frame, and bonding wires, and has a package structure in which the semiconductor element and bonding wires are sealed by a package component.

[0037] Figure 1 as well as Figure 2 This is a perspective view showing an example of the external shape of semiconductor device 1. Figure 1 This describes the structure of semiconductor device 1 as viewed from the top surface side. Figure 2 This describes the configuration of semiconductor device 1 as viewed from the lower surface side.

[0038] like Figure 1 as well as Figure 2 As shown, the semiconductor device 1 includes lead frames 20 and 30, and a package component 50.

[0039] The lead frame 20 has surfaces exposed from the encapsulation component 50, namely a first surface (lower surface) S1, a second surface (side surface) S2, a third surface S3, and a fourth surface S4. The first surface S1 is in contact with the second surface S2. The second surface S2 has a height H1. The height H1 is, for example, 150 μm or more and 200 μm or less. The third surface S3 is opposite to the fourth surface S4. The first surface S1 and the second surface S2 are terminals (electrodes) of the lead frame 20. The first surface S1 and the second surface S2 function as external connection terminals for connection to the outside. The third surface S3 and the fourth surface S4 are suspension pins. The suspension pins are connecting parts used to connect the part formed as the lead frame 20 to the part formed as the lead frame 30 when the lead frame 20 and 30 are in the state of the lead frame substrate during manufacturing. During manufacturing, the lead frame 20 is separated from the lead frame substrate by dicing, which will be described later. The surfaces cut out by the slicing of the suspension pin are the third surface S3 and the fourth surface S4.

[0040] The lead frame 30 has surfaces exposed from the encapsulation component 50, namely, a fifth surface (lower surface) S5, a sixth surface (side surface) S6, a seventh surface S7, and an eighth surface S8. The fifth surface S5 is in contact with the sixth surface S6. The sixth surface S6 has a height H2. The height H2 is approximately the same as the height H1. The height H2 is, for example, 150 μm or more and 200 μm or less. The seventh surface S7 is opposite to the eighth surface S8. The fifth surface S5 and the sixth surface S6 are terminals (electrodes) of the lead frame 30. The fifth surface S5 and the sixth surface S6 function as external connection terminals for external connection. The seventh surface S7 and the eighth surface S8 are suspension pins. During manufacturing, the lead frame 30 is separated from the lead frame substrate by dicing. The surfaces of the suspension pins that are cut out by dicing are the seventh surface S7 and the eighth surface S8.

[0041] Hereinafter, the height H1 of the second face S2 and the height H2 of the sixth face S6 will also be referred to as the "WF length".

[0042] The lower surface of the semiconductor device 1 is the surface where the terminals of the lead frame 20 (first surface S1) and the terminals of the lead frame 30 (fifth surface S5) are exposed from the packaging component 50. It is the surface on which the semiconductor device 1 is mounted to the main substrate, i.e., the mounting surface of the semiconductor device 1.

[0043] Furthermore, in the following description, an XYZ orthogonal coordinate system is used. The X direction is parallel to the surface of the leader frame 20, for example, corresponding to the direction from the leader frame 20 toward the leader frame 30. The Y direction is parallel to the surface of the leader frame 20, for example, corresponding to the direction from the third surface S3 of the leader frame 20 toward the fourth surface S4. The Z direction corresponds to the direction perpendicular to the surface of the leader frame 20, i.e., the up-down direction. Additionally, the expression "up" and its related terms indicate the position of a larger coordinate on the Z-axis, and the expression "down" and its related terms indicate the position of a smaller coordinate on the Z-axis.

[0044] Figure 3 This is a perspective view showing an example of the structure of semiconductor device 1. Figure 3 Shown in Figure 1 The structure of the semiconductor device 1 can be observed from the top surface side through the packaging component 50. Figure 4 as well as Figure 5 These are top and bottom views illustrating an example of the structure of semiconductor device 1. Figure 4 Shown in Figure 1 The structure of the semiconductor device 1 can be observed from the top surface side through the packaging component 50. Figure 5 Shown in Figure 2 The structure of the semiconductor device 1 can be observed from the lower surface side through the packaging component 50.

[0045] like Figures 3-5 As shown, the semiconductor device 1 includes a semiconductor element 10, lead frames 20 and 30, and a bonding wire 40.

[0046] Semiconductor element 10 may be, for example, a diode, a field-effect transistor, a bipolar transistor, or an IGBT (Insulated Gate Bipolar Transistor). The following explanation will use a diode as an example of semiconductor element 10.

[0047] Semiconductor element 10 is, for example, a semiconductor chip (or, bare die, bare dies). Semiconductor element 10 includes element portion 11 and pads (or, nodes, terminals) 12.

[0048] The component section 11 includes, for example, a semiconductor layer on which a diode is formed. The semiconductor layer is, for example, silicon, silicon carbide, silicon germanium, gallium nitride, or gallium arsenide.

[0049] The pad 12 is provided on the upper surface of the component section 11. The pad 12 is electrically connected to the anode (not shown) of the semiconductor element 10, for example, via a conductive component (not shown) formed by curing a conductive paste. The pad 12 may contain a metal layer such as aluminum or copper. Alternatively, depending on the internal structure of the component section 11, the pad 12 may also be electrically connected to the cathode of the semiconductor element 10.

[0050] The lead frame 20 includes a base 21 and protrusions 22, 23a, 23b, 24a and 24b.

[0051] The base 21 has, for example, a generally cuboid shape and a recessed portion on its upper surface (hereinafter referred to as "step 25"). That is, the base 21 includes a step 25 on its upper surface.

[0052] The protrusions 22, 23a, 23b, 24a, and 24b are, for example, generally cuboid in shape. The protrusions 22, 23a, 23b, 24a, and 24b are portions that protrude from the base 21. In other words, the protrusions 22, 23a, 23b, 24a, and 24b are respectively connected to the base 21.

[0053] Protrusion 22 protrudes from the side of the base 21 in the X direction that is farther from the lead frame 30. The height of protrusion 22 is, for example, the same as the height of the base 21. Protrusion 23a protrudes from one of the two sides of the base 21 in the Y direction. Protrusion 23b protrudes from the other side of the two sides of the base 21 in the Y direction. Protrusions 23a and 23b are separated from each other and opposite each other in the Y direction. The height of each of protrusions 23a and 23b is, for example, lower than the height of the base 21. The height of protrusion 23a is, for example, the same as the height of protrusion 23b. Protrusions 24a and 24b protrude from the side of the base 21 in the X direction that is closer to the lead frame 30. Protrusions 24a and 24b are separated from each other and opposite each other in the Y direction. The height of each of protrusions 24a and 24b is, for example, lower than the height of the base 21. The height of protrusion 24a is, for example, the same as the height of protrusions 23a, 23b and 24b.

[0054] The lower surface of the base 21 and the lower surface of the protrusion 22 correspond to the first surface S1. The side of the protrusion 22 that does not connect with the base 21 in the X direction corresponds to the second surface S2. The height of the protrusion 22 corresponds to the height H1 of the second surface S2. The side of the protrusion 23a that does not connect with the base 21 in the Y direction corresponds to the third surface S3. The side of the protrusion 23b that does not connect with the base 21 in the Y direction corresponds to the fourth surface S4.

[0055] A stepped portion 25 is provided on the upper surface of the base 21. More specifically, the stepped portion 25 is provided at the end of the upper surface of the base 21 on the side of the lead frame 30. The stepped portion 25 has a generally rectangular shape, for example, when viewed from above. The stepped portion 25 includes a bottom surface 25a and side walls 25b, 25c, and 25d. The bottom surface 25a and the side walls 25b, 25c, and 25d are included in the base 21. The bottom surface 25a serves as an external connection terminal and functions as an assembly portion on which the semiconductor element 10 is mounted.

[0056] The lead frame 30 includes a base 31 and protrusions 32, 33a, 33b and 34.

[0057] The base 31, for example, has a generally rectangular parallelepiped shape.

[0058] The protrusions 32, 33a, 33b, and 34 are, for example, generally cuboid in shape. The protrusions 32, 33a, 33b, and 34 are portions that protrude from the base 31. In other words, the protrusions 32, 33a, 33b, and 34 are respectively connected to the base 31.

[0059] Protrusion 32 protrudes from the side of the base 31 in the X direction that is furthest from the lead frame 20. The height of protrusion 32 is, for example, the same as the height of the base 31. Protrusion 33a protrudes from one of the two sides of the base 31 in the Y direction. Protrusion 33b protrudes from the other side of the two sides of the base 31 in the Y direction. Protrusions 33a and 33b are separated from each other and opposite each other in the Y direction. The height of each of protrusions 33a and 33b is, for example, lower than the height of the base 31. The height of protrusion 33a is, for example, the same as the height of protrusion 33b. Protrusion 34 protrudes from the side of the base 31 in the X direction that is closer to the lead frame 20. The height of protrusion 34 is, for example, lower than the height of the base 31 and the same as the height of each of protrusions 33a and 33b.

[0060] The lower surface of the base 31 and the lower surface of the protrusion 32 correspond to the fifth surface S5. The side of the protrusion 32 that does not connect with the base 31 in the X direction corresponds to the sixth surface S6. The height of the protrusion 32 corresponds to the height H2 of the sixth surface S6. The side of the protrusion 33a that does not connect with the base 31 in the Y direction corresponds to the seventh surface S7. The side of the protrusion 33b that does not connect with the base 31 in the Y direction corresponds to the eighth surface S8.

[0061] The lead frames 20 and 30 are separated from each other and arranged opposite each other in the X direction.

[0062] A semiconductor element 10 is provided on the bottom surface 25a of the stepped portion 25. A portion of the semiconductor element 10 is opposite to the lead frame 20. The stepped portion 25 has a sidewall 25b in the X direction. The stepped portion 25 has opposing sidewalls 25c and 25d in the Y direction. The three sides of the semiconductor element 10 are surrounded by the sidewalls 25b, 25c, and 25d of the stepped portion 25. The bottom surface 25a of the stepped portion 25 is electrically connected to the cathode (not shown) of the semiconductor element 10, for example, via a conductive member (not shown) formed by curing a conductive paste. Alternatively, depending on the internal configuration of the element portion 11, the bottom surface 25a of the stepped portion 25 may also be electrically connected to the anode of the semiconductor element 10.

[0063] One end of a bonding wire 40 is connected to the upper surface of the pad 12. The other end of the bonding wire 40 is connected to the upper surface of the base 31 of the lead frame 30. The bonding wire 40 electrically connects the pad 12 of the semiconductor element 10 to the base 31 of the lead frame 30.

[0064] Figure 6 This is a cross-sectional view showing an example of the structure of semiconductor device 1. Figure 6 Show Figure 4 as well as Figure 5 The cross-sectional structure of semiconductor device 1 along the Sa-Sa line.

[0065] like Figure 6 As shown, an encapsulation component (or sealing component, resin body, molding resin, encapsulating resin) 50 is disposed on the semiconductor element 10, the lead frame 20, and the lead frame 30. The encapsulation component 50 covers a portion of each of the lead frames 20 and 30, and covers the semiconductor element 10 placed on the bottom surface 25a of the step portion 25 of the lead frame 20, sealing the semiconductor element 10 and the bonding wire 40. The encapsulation component 50 is also disposed in the space surrounded by the semiconductor element 10 and the lead frames 20 and 30. The encapsulation component 50 is an insulator, such as an insulating resin or ceramic, or polyimide.

[0066] The protrusion 22 of the lead frame 20 has a notch NP at its end on the side that does not connect with the base 21 on the lower surface. A plating layer 41 is provided on the lower surface of the base 21 of the lead frame 20, the lower surface of the protrusion 22 of the lead frame 20, and the notch NP of the protrusion 22. The plating layer 41 contains, for example, tin or solder. Hereinafter, the lower surface of the plating layer 41 that connects with the base 21 and the protrusion 22 will be referred to as the first surface S1 of the lead frame 20. The side of the protrusion 22 of the lead frame 20 that does not connect with the base 21 and the side of the plating layer 41 that does not connect with the protrusion 22 will be referred to as the second surface S2 of the lead frame 20. The first surface S1 and the second surface S2 of the lead frame 20 are exposed from the package member 50. The height H1 of the second surface S2 of the lead frame 20 is the height from the lower surface of the plating layer 41 to the upper surface of the protrusion 22 of the lead frame 20.

[0067] The protrusion 32 of the lead frame 30 has a notch NP at its end on the side that does not connect with the base 31 on the lower surface. A plating layer 41 is provided on the lower surface of the base 31 of the lead frame 30, the lower surface of the protrusion 32 of the lead frame 30, and the notch NP of the protrusion 32. Hereinafter, the lower surface of the plating layer 41 that connects with the base 31 and the protrusion 32 will be referred to as the fifth surface S5 of the lead frame 30. The side surface of the protrusion 32 of the lead frame 30 that does not connect with the base 31 and the side surface of the plating layer 41 that does not connect with the protrusion 32 will be referred to as the sixth surface S6 of the lead frame 30. The fifth surface S5 and the sixth surface S6 of the lead frame 30 are exposed from the encapsulation member 50. The height H2 of the sixth surface S6 of the lead frame 30 is the height from the lower surface of the plating layer 41 to the upper surface of the protrusion 32 of the lead frame 30.

[0068] Thus, in semiconductor device 1, the terminals of lead frame 20 (first surface S1 and second surface S2) and the terminals of lead frame 30 (fifth surface S5 and sixth surface S6) have WF structures.

[0069] The height H3 (hereinafter referred to as "height H3 of step portion 25") from the lower surface of lead frame 20 to the bottom surface 25a of step portion 25 of lead frame 20 is designed, for example, taking into account the thickness of semiconductor device 10. The height H3 of step portion 25 is lower than the height H1. That is, the height H3 is different from the height H1. In order to make semiconductor device 1 thinner, the height H3 is preferably less than half of the height H1. During manufacturing, due to the half-etching described later, the height H3 is, for example, about half of the height H1.

[0070] The height H4 from the lower surface of the lead frame 20 to the upper surface of the notch NP of the protrusion 22 of the lead frame 20, and the height H5 from the lower surface of the lead frame 30 to the upper surface of the notch NP of the protrusion 32 of the lead frame 30, are designed, for example, with consideration of the identifiability of the solder pads when the semiconductor device 1 is mounted on the main substrate using the solder pads described later. Height H5 is approximately the same as height H4. Heights H4 and H5 are, for example, 100 μm or more.

[0071] The length L1 of the protrusion 22 of the lead frame 20 in the X direction is designed, for example, to account for the possibility of damage to the package component 50 due to cutting during manufacturing. The length L2 of the protrusion 32 of the lead frame 30 in the X direction is also designed in the same way as the length L1. The lengths L1 and L2 are, for example, 50 μm or more.

[0072] The length L3 of the base 21 of the lead frame 20 in the X direction, from the position where it connects with the protrusion 22 to the step 25, is designed to be more than half or more than one-third of the thickness of the half-etched portion.

[0073] The length L4 of the bottom surface 25a of the step portion 25 of the lead frame 20 in the X direction is designed, for example, taking into account the size of the first surface S1 of the lead frame 20. The length L4 is, for example, 30 μm or more.

[0074] The semiconductor element 10 is positioned on the bottom surface 25a of the step portion 25 of the lead frame 20 with a predetermined positional accuracy. When the area of ​​the lower surface of the semiconductor element 10, which is placed on (in contact with) the bottom surface 25a, is relatively small, the connection between the semiconductor element 10 and the lead frame 20 may be insufficient. Therefore, the area of ​​the portion of the semiconductor element 10 that contacts the bottom surface 25a of the step portion 25 of the lead frame 20 is preferably at least half the area of ​​the lower surface of the element portion 11.

[0075] 1.2 Installation Example of Semiconductor Device

[0076] Next, an example of installing semiconductor device 1 will be described. Figure 7 This is a cross-sectional view showing the structure of an example of mounting semiconductor device 1. Figure 7 The structure of the semiconductor device 1 mounted on the main substrate 60 is shown.

[0077] like Figure 7 As shown, leadframe 20 is disposed on pads (e.g., wiring or terminals) 61 of the main substrate 60 via conductive member 63. Conductive member 63 is disposed between the first surface S1 of leadframe 20 and pad 61. Since leadframe 20 has a WF (wireless-free) structure, conductive member 63 is also disposed on the second surface S2 of leadframe 20. This conductive member 63 is also referred to as a solder foot. Solder foot 63 contacts the first surface S1 of leadframe 20 and pad 61, electrically connecting the first surface S1 of leadframe 20 to pad 61. Conductive member (or solder foot) 63, for example, contains solder. Pad 61 is disposed on the mounting surface of the main substrate 60. Pad 61, for example, contains copper or aluminum.

[0078] The leadframe 30 is disposed on the pad (e.g., wiring or terminal) 62 of the main substrate 60 via a conductive component 63. The conductive component 63 is disposed between the fifth surface S5 of the leadframe 30 and the pad 62. Since the leadframe 30 has a WF (wireless-free) structure, the conductive component 63 is also disposed on the sixth surface S6 of the leadframe 30. The solder pad 63 contacts the fifth surface S5 of the leadframe 30 and the pad 62, electrically connecting the fifth surface S5 of the leadframe 30 to the pad 62. The pad 62 is disposed on the mounting surface of the main substrate 60. The pad 62 may contain, for example, copper or aluminum.

[0079] 1.3 Semiconductor Device Manufacturing Method

[0080] Next, use Figures 8-15 The manufacturing method of semiconductor device 1 will be described. Figure 8This is a flowchart illustrating an example of a method for manufacturing semiconductor device 1. Figure 8 The main steps in the manufacturing method of semiconductor device 1 are shown in the figure. Figures 9-15 This is a diagram showing the steps in the manufacturing method of semiconductor device 1. Figure 9 This is a top view taken from the upper surface of the lead frame substrate. Figures 10-15 yes Figure 9 A cross-sectional view along the Sb-Sb line.

[0081] First, such as Figure 9 As shown, a lead frame substrate 100 is prepared (S101). The lead frame substrate 100 is formed, for example, using a mold. The lead frame substrate 100 includes portions (hereinafter referred to as "frame portions FP") corresponding to the semiconductor device 1 containing lead frames 20 and 30. The lead frame substrate 100 includes a plurality of frame portions FP. In the lead frame substrate 100, the plurality of frame portions FP are arranged along the X and Y directions.

[0082] The lead frame substrate 100 (frame portion FP) includes a substrate 120 (hereinafter referred to as "substrate 120") corresponding to the lead frame 20 and a substrate 130 (hereinafter referred to as "substrate 130") corresponding to the lead frame 30. In the frame portion FP, substrate 120 and substrate 130 are arranged opposite each other in the X direction. Substrate 120 and substrate 130 are connected by connecting portions 201a and 201b. Connecting portions 201a and 201b correspond to suspension pins.

[0083] In the X direction, the frame portion FP on the left side of the paper and the frame portion FP on the right side of the paper are connected by the connecting portion 202. The connecting portion 202 is an external lead.

[0084] In the Y direction, the upper frame portion FP and the lower frame portion FP of the paper are connected by a connecting portion 203. The connecting portion 203 includes a connecting portion 201a for the upper frame portion FP and a connecting portion 201b for the lower frame portion FP.

[0085] In the frame portion FP, the dashed lines in rectangular shape on the outside of the substrates 120 and 130 represent the scribing cut surface SDC.

[0086] like Figure 10As shown, in the frame portion FP, the substrate 120 has notches NP at both ends of its lower surface (hereinafter referred to as "surface 121"). In the substrate 120, the notch NP on the side closer to the substrate 130 includes a side surface (hereinafter referred to as "surface 122") that connects to the right end of face 121 and a lower surface (hereinafter referred to as "surface 123") that connects to the upper end of face 122. In the substrate 120, the notch NP on the side farther from the substrate 130 includes a side surface (hereinafter referred to as "surface 124") that connects to the left end of face 121 and a lower surface (hereinafter referred to as "surface 125") that connects to the upper end of face 124.

[0087] In the frame portion FP, the substrate 130 has notches NP at both ends of its lower surface (hereinafter referred to as "surface 131"). In the substrate 130, the notch NP closer to the substrate 120 includes a side surface (hereinafter referred to as "surface 132") that connects to the left end of face 131 and a lower surface (hereinafter referred to as "surface 133") that connects to the upper end of face 132. In the substrate 130, the notch NP farther from the substrate 120 includes a side surface (hereinafter referred to as "surface 134") that connects to the right end of face 131 and a lower surface (hereinafter referred to as "surface 135") that connects to the upper end of face 134. In two adjacent frame portions FP in the X direction, face 135 of the frame portion FP on the left side of the paper and face 125 of the frame portion FP on the right side of the paper are one face.

[0088] The lead frame substrate 100, for example, contains copper (or aluminum). The thickness of the lead frame substrate 100 is, for example, 150 μm or more and 200 μm or less. The height H6 from surface 121 to the upper surface of the notch NP and the height H7 from surface 131 to the upper surface of the notch NP are lower than the height from the lower surface to the upper surface of the lead frame substrate 100 (the thickness of the lead frame substrate 100). Height H7 is approximately the same as height H6. Heights H6 and H7 are, for example, 100 μm or more.

[0089] Next, as Figure 11 As shown, a step portion 25 is formed on the upper surface of the lead frame substrate 100 (S102). More specifically, the step portion 25 is formed at the end of the upper surface of the substrate 120 of the lead frame substrate 100 on the substrate 130 side. Specifically, for example, a half-etch is performed on the end of the upper surface of the substrate 120 of the lead frame substrate 100 on the substrate 130 side. At this time, etching is performed such that the substrate 120 remains on both sides of the step portion 25 in the Y direction. As a result, a step portion 25 is formed having a sidewall 25b in the X direction and opposing sidewalls 25c and 25d in the Y direction.

[0090] Next, as Figure 12As shown, a semiconductor element 10 is mounted onto the lead frame substrate 100 (S103). Specifically, for example, the semiconductor element 10 is formed on the bottom surface 25a of the step portion 25 of the substrate 120 of the lead frame substrate 100 via a conductive member (not shown). Next, a wire bond is formed between the semiconductor element 10 and the lead frame substrate 100 (S104). Specifically, for example, a bonding wire 40 is formed between the pad 12 of the semiconductor element 10 and the substrate 130 of the lead frame substrate 100. Thus, the pad 12 of the semiconductor element 10 and the substrate 130 are electrically connected via the bonding wire 40.

[0091] Next, as Figure 13 As shown, an encapsulation component 50 is formed on the lead frame substrate 100 (S105). Specifically, for example, a backing tape 300 is first adhered to the lower surface of the lead frame substrate 100. The backing tape 300 is provided to prevent resin leakage to surfaces 121 and 131 of the lead frame substrate 100 during the formation of the encapsulation component 50. Next, the encapsulation component 50 is formed on the upper surface of the lead frame substrate 100, which is provided with semiconductor elements 10 and bonding wires 40, and in the space surrounded by semiconductor elements 10, substrates 120 and 130. The encapsulation component 50 is formed, for example, using a mold. The encapsulation component 50 is injected from the injection port of the mold, filling the space between the lead frame substrate 100 and the mold. Thus, the encapsulation component 50 is formed on the upper surface of the lead frame substrate 100 and in the space surrounded by semiconductor elements 10, substrates 120 and 130. That is, a portion of each of the substrates 120 and 130 of the lead frame substrate 100 is covered by the encapsulation component 50. The semiconductor element 10 and bonding wire 40 on the lead frame substrate 100 are sealed by the package component 50. After the package component 50 is formed, the back strip 300 is removed.

[0092] Next, as Figure 14 As shown, an external plating layer is applied to the terminals of the lead frame substrate 100 (S106). Specifically, for example, an electroplating method is used to form a plating layer 41 on the lower surface and side surfaces (surfaces 121, 124, and 125) of the substrate 120 of the lead frame substrate 100 exposed from the encapsulation member 50, and on the lower surface and side surfaces (surfaces 131, 134, and 135) of the substrate 130 of the lead frame substrate 100 exposed from the encapsulation member 50. The plating layer 41 may contain, for example, tin or solder.

[0093] Next, as Figure 15As shown, the lead frame substrate 100 and the package component 50 are diced (S107). Specifically, for example, a dicing tape 400 is first adhered to the upper surface of the package component 50. The dicing tape 400 is provided to hold the multiple semiconductor devices 1 after monolithization when the lead frame substrate 100 is monolithized into multiple semiconductor devices 1 by dicing. Next, using a dicing blade, the lead frame substrate 100 and the package component 50 are diced from the lower surface side of the lead frame substrate 100 on the dicing cutting surface SDC. After dicing, the dicing tape 400 is removed. Thus, the lead frame substrate 100 is monolithized into multiple semiconductor devices 1, and a solution is obtained. Figure 6 The semiconductor device 1 is as shown. Based on the above description, the manufacturing process of the semiconductor device 1 is complete.

[0094] In the future, if Figure 7 As shown, for example, a reflow soldering process is used to mount the semiconductor device 1 onto the main substrate 60. Solder feet 63 are formed on the side of the semiconductor device 1. The solder feet 63 fix the semiconductor device 1 to the main substrate 60, and electrically connect the first surface S1 of the lead frame 20 to the pad 61 of the main substrate 60, and electrically connect the fifth surface S5 of the lead frame 30 to the pad 62 of the main substrate 60.

[0095] Furthermore, various inspections, such as Automated Optical Inspection (AOI), are then performed on the semiconductor device 1 on the main substrate 60 using a testing device. For example, the shape of the solder pads 63 formed on the lead frames 20 and 30 is inspected by AOI. As a result, the quality of the bonding state between the semiconductor device 1 and the main substrate 60 is determined.

[0096] After various inspections, the main substrate 60 with the semiconductor device 1 of this embodiment installed, or the equipment containing the semiconductor device 1 of this embodiment, is shipped to the market or to users.

[0097] In a semiconductor device with a wire frame (WF) structure mounted on a main substrate, generally, a longer WF results in better solder joint (side solder joint) identification. Therefore, increasing the WF length, i.e., the lead frame thickness, is considered. However, in thin semiconductor packages, there are limitations on the overall height, including the lead frame thickness, the semiconductor element thickness, and the looping wires, as well as the gap between this height and the package thickness. Therefore, it is difficult to increase the lead frame thickness beyond the required amount. Thus, in the manufacturing process of a semiconductor device with a WF structure, there is a trade-off between thinning the semiconductor device and thickening the lead frame. In a semiconductor device mounted on a main substrate with a WF length equal to the lead frame thickness, there is a possibility of reduced solder joint identification.

[0098] In the semiconductor device 1 of this embodiment, a stepped portion 25 is provided at the end of the upper surface of the lead frame 20 on the lead frame 30 side. A semiconductor element 10 is provided on the bottom surface 25a of the stepped portion 25. Therefore, according to this embodiment, the WF length (height of the side electrode), i.e., the height H1 of the second surface S2 of the lead frame 20 and the height H2 of the sixth surface S6 of the lead frame 30, can be maximized without increasing the thickness of the semiconductor device 1. Therefore, the height H4 from the lower surface of the lead frame 20 to the upper surface of the notch NP of the protrusion 22 of the lead frame 20 and the height H5 from the lower surface of the lead frame 30 to the upper surface of the notch NP of the protrusion 32 of the lead frame 30 can be relatively high, and the height of the plating layer 41 can also be increased. According to the above description, during the mounting of the semiconductor device 1 to the main substrate 60, the solder pad 63 is formed to the height of the plating layer 41. Therefore, the recognizability of the solder pad 63 can be improved. That is, the installation status of the semiconductor device 1 based on AOI can be easily inspected. Therefore, the accuracy of the installation status inspection can be improved in the semiconductor device 1 of this embodiment. Consequently, the reliability of the main substrate 60 or the device including the semiconductor device 1 of this embodiment can be improved.

[0099] Furthermore, during the dicing and cutting of the lead frame substrate and the packaging components, stress can cause peeling between the substrate and the packaging components corresponding to the lead frame, starting from the outer periphery.

[0100] In the semiconductor device 1 of this embodiment, the step portion 25 has a sidewall 25b in the X direction and opposing sidewalls 25c and 25d in the Y direction. The three sides of the semiconductor element 10 are surrounded by the sidewalls 25b, 25c, and 25d of the step portion 25. Therefore, the progress of peeling between the substrate 120 and the package member 50, caused by stress generated during dicing, starting from the outer periphery, stops at the step portion 25. Thus, the progress of peeling between the substrate 120 and the package member 50 can be suppressed. Based on the above description, the reduction in moisture resistance in the semiconductor device 1 can be prevented, and the reliability of the semiconductor device 1 can be improved.

[0101] As described above, the semiconductor device 1 and its manufacturing method according to this embodiment can maximize the WF length (height of the side electrode) of the semiconductor device 1 and improve the reliability of mounting the semiconductor device 1 to the main substrate 60. Furthermore, the reliability of the semiconductor device 1 can be improved.

[0102] 2. Second Implementation Method

[0103] The semiconductor device according to the second embodiment will be described. In the semiconductor device 1A of the second embodiment, the structure of the lead frame 20 and the manufacturing method of the semiconductor device 1A are different from those of the first embodiment. Hereinafter, the differences from the first embodiment will be described.

[0104] 2.1 Structure of Semiconductor Devices

[0105] use Figures 16-18 The structure of semiconductor device 1A will be described. Figure 16 This is a perspective view showing an example of the structure of semiconductor device 1A. Figure 16 As shown in the first embodiment Figure 3 Similarly, the structure of the semiconductor device 1A is shown as viewed through the package component 50 from the top surface side. Figure 17 as well as Figure 18 These are top and bottom views illustrating an example of the structure of semiconductor device 1A. Figure 17 As shown in the first embodiment Figure 4 Similarly, the structure of the semiconductor device 1A is shown as viewed through the package component 50 from the top surface side. Figure 18 As shown in the first embodiment Figure 5 Similarly, the structure of the semiconductor device 1A is shown as viewed through the package component 50 from the lower surface side.

[0106] like Figures 16-18 As shown, semiconductor device 1A includes semiconductor element 10, lead frames 20 and 30, and bonding wire 40.

[0107] The stepped portion 25 of the lead frame 20 includes a bottom surface 25a and a sidewall 25b. The stepped portion 25 has a sidewall 25b in the X direction. The bottom surface 25a of the stepped portion 25 has grooves 25e and 25f. Grooves 25e and 25f have V-shaped shapes when viewed from the X direction. Grooves 25e and 25f extend along the X direction from the sidewall 25b to the end of the bottom surface 25a on the lead frame 30 side. Grooves 25e and 25f are separated from each other in the Y direction. A semiconductor element 10 is disposed between grooves 25e and 25f. The semiconductor element 10 is opposite to the sidewall 25b in the X direction.

[0108] The base 21 of the lead frame 20 has a roughly L-shaped shape when viewed from the Y direction. The upper surfaces of the protrusions 23a and 23b of the lead frame 20 are on the same surface as the bottom surface 25a of the step portion 25. Protrusions 24a and 24b are removed from the lead frame 20.

[0109] The upper surfaces of the protrusions 33a and 33b of the lead frame 30 are at the same height as the upper surfaces of the protrusions 23a and 23b of the lead frame 20.

[0110] The three-dimensional and planar structures of the semiconductor device 1A other than those described above are the same as those shown in the first embodiment. Figures 3-5 same.

[0111] Figure 17 as well as Figure 18 The cross-sectional structure of the semiconductor device 1A along the Sa-Sa line is the same as that shown in the first embodiment. Figure 6 same.

[0112] 2.2 Manufacturing Method of Semiconductor Devices

[0113] use Figure 19 The manufacturing method of semiconductor device 1A is described. Figure 19 This is a flowchart illustrating an example of a manufacturing method for semiconductor device 1A. Figure 19 The main steps in the manufacturing method of semiconductor device 1A are shown in the figure.

[0114] exist Figure 19 In the flowchart shown, the first embodiment is shown Figure 8 In the flowchart, S102 is replaced with S102A, S103 is replaced with S103A, and S108 is added between S102A and S103A. S102A, S103A, and S108 are not the same as those shown in the first embodiment. Figure 8 The flowcharts are the same.

[0115] After performing S101 in the same manner as in the first embodiment, in S102A, a step portion 25 is formed on the upper surface of the lead frame substrate 100. More specifically, the step portion 25 is formed at the end of the upper surface of the substrate 120 of the lead frame substrate 100 on the substrate 130 side. Specifically, for example, a half-etch is performed on the end of the upper surface of the substrate 120 of the lead frame substrate 100 on the substrate 130 side. At this time, etching is performed in such a way that no substrate 120 remains on either side of the step portion 25 in the Y direction. As a result, a step portion 25 having a sidewall 25b in the X direction is formed.

[0116] After the step portion 25 is formed, two grooves are formed in the step portion 25 of the lead frame substrate 100 (S108). More specifically, grooves 25e and 25f are formed on the bottom surface 25a of the step portion 25 of the lead frame substrate 100. Specifically, for example, the bottom surface 25a of the step portion 25 of the lead frame substrate 100 is embossed. As a result, grooves 25e and 25f are formed that are separated from each other in the Y direction and extend from the sidewall 25b to the end of the lead frame 30 side of the bottom surface 25a in the X direction, respectively.

[0117] After forming grooves 25e and 25f, in S103A, a semiconductor element 10 is assembled onto the lead frame substrate 100. Specifically, for example, the semiconductor element 10 is formed between grooves 25e and 25f in the bottom surface 25a of the step portion 25 of the substrate 120 of the lead frame substrate 100 via a conductive component (not shown).

[0118] S104 to S107 are then performed in the same manner as in the first embodiment.

[0119] According to the semiconductor device 1A and its manufacturing method in this embodiment, similar to the first embodiment, the WF length (height of the side electrode) of the semiconductor device 1A can be maximized, and the reliability of the semiconductor device 1A in mounting to the main substrate 60 can be improved.

[0120] Furthermore, in the semiconductor device 1A of this embodiment, the stepped portion 25 has a sidewall 25b in the X direction. The bottom surface 25a of the stepped portion 25 has grooves 25e and 25f. Grooves 25e and 25f extend from the sidewall 25b along the X direction to the end of the lead frame 30 side of the bottom surface 25a. Grooves 25e and 25f are separated from each other in the Y direction. A semiconductor element 10 is disposed between grooves 25e and 25f. The semiconductor element 10 is opposite to the sidewall 25b in the X direction. As a result, the progress of peeling between the substrate 120 and the package member 50 caused by stress generated during dicing, starting from the outer periphery, stops at grooves 25e and 25f. Therefore, the progress of peeling between the substrate 120 and the package member 50 can be suppressed. According to the above description, the reduction of moisture resistance in the semiconductor device 1 can be prevented, and the reliability of the semiconductor device 1A can be improved. As described above, the reliability of the semiconductor device 1A and its manufacturing method according to this embodiment can be improved.

[0121] 3. Third Implementation Method

[0122] The semiconductor device according to the third embodiment will be described. The semiconductor device 1B of the third embodiment differs from the first embodiment in that it includes a semiconductor element 70. Furthermore, the construction of the lead frame 30 and the manufacturing method of the semiconductor device 1B in the third embodiment differ from those in the first embodiment. The differences from the first embodiment will be explained below.

[0123] 3.1 Structure of Semiconductor Devices

[0124] use Figures 20-22 The structure of semiconductor device 1B will be described. Figure 20 as well as Figure 21 These are top and bottom views illustrating an example of the structure of semiconductor device 1B. Figure 20 As shown in the first embodimentFigure 4 Similarly, the structure of the semiconductor device 1B is shown as viewed through the package component 50 from the top surface side. Figure 21 As shown in the first embodiment Figure 5 Similarly, the structure of the semiconductor device 1B is shown as viewed through the package component 50 from the lower surface side. Figure 22 This is a cross-sectional view showing an example of the structure of semiconductor device 1B. Figure 22 Show Figure 20 as well as Figure 21 The cross-sectional structure of semiconductor device 1B along the Sa-Sa line.

[0125] like Figures 20-22 As shown, semiconductor device 1B includes semiconductor elements 10 and 70, lead frames 20 and 30, bonding wires 40, and packaging components 50.

[0126] Semiconductor element 70 has the same structure as semiconductor element 10. Semiconductor element 70 includes element portion 71 and pads (or nodes, terminals) 72. Element portion 71 corresponds to element portion 11. Pad 72 corresponds to pad 12.

[0127] The lead frame 30 has the same structure as the lead frame 20. The lead frame 30 includes a base 31 and protrusions 32, 33a, 33b, 34a, and 34b. The base 31 corresponds to the base 21. Protrusions 32, 33a, 33b, 34a, and 34b correspond to protrusions 22, 23a, 23b, 24a, and 24b, respectively. The base 31 has a stepped portion 35. The stepped portion 35 corresponds to the stepped portion 25. The lead frame 30 has a stepped portion 35 at its end on the lead frame 20 side of its upper surface. The stepped portion 35 has a bottom surface 35a and side walls 35b, 35c, and 35d. The side walls 35b, 35c, and 35d are not shown in the diagram. The bottom surface 35a and the side walls 35b, 35c, and 35d correspond to the bottom surface 25a and the side walls 25b, 25c, and 25d, respectively.

[0128] A semiconductor element 70 is provided on the bottom surface 35a of the stepped portion 35.

[0129] The other end of the bonding wire 40 is connected to the upper surface of the pad 72. The bonding wire 40 electrically connects the pad 12 of the semiconductor element 10 to the base 31 of the lead frame 30 via the pad 72 of the semiconductor element 70.

[0130] The planar and cross-sectional structures of the semiconductor device 1B other than those described above are the same as those shown in the first embodiment. Figures 4-6 same.

[0131] 3.2 Manufacturing Method of Semiconductor Devices

[0132] The manufacturing method of semiconductor device 1B is described.

[0133] In the manufacturing method of semiconductor device 1B, as shown in the first embodiment Figure 8 In flowchart S102, a stepped portion 35 is formed at the end of the upper surface of the substrate 130 on the substrate 120 side, similar to the substrate 120. Figure 8 In flowchart S103, a semiconductor element 70 is formed on the bottom surface 35a of the stepped portion 35 of the substrate 130, similar to that of the substrate 120. Figure 8 In S104 of the flowchart, the bonding line 40 is bonded between the pad 12 of the semiconductor element 10 and the pad 72 of the semiconductor element 70.

[0134] The procedures other than those described above are the same as those in the first embodiment.

[0135] According to this embodiment, it achieves the same effect as the first embodiment.

[0136] 4. Fourth Implementation Method

[0137] The semiconductor device according to the fourth embodiment will be described. The semiconductor device 1C of the fourth embodiment differs from that of the second embodiment in that it includes a semiconductor element 70. Furthermore, the construction of the lead frame 30 and the manufacturing method of the semiconductor device 1C in the fourth embodiment differ from those in the second embodiment. The differences from the second embodiment will be explained below.

[0138] 4.1 Structure of Semiconductor Devices

[0139] use Figure 23 as well as Figure 24 The structure of semiconductor device 1C is described. Figure 23 as well as Figure 24 These are top and bottom views illustrating an example of the structure of a semiconductor device 1C. Figure 23 As shown in the first embodiment Figure 4 Similarly, the structure of the semiconductor device 1C is shown as viewed through the package component 50 from the top surface side. Figure 24 As shown in the first embodiment Figure 5 Similarly, the structure of the semiconductor device 1C is shown as viewed through the package component 50 from the lower surface side.

[0140] like Figure 23 as well as Figure 24 As shown, semiconductor device 1B includes semiconductor elements 10 and 70, lead frames 20 and 30, and bonding wires 40.

[0141] Semiconductor element 70 has the same structure as semiconductor element 10. Semiconductor element 70 includes element portion 71 and pads (or nodes, terminals) 72. Element portion 71 corresponds to element portion 11. Pad 72 corresponds to pad 12.

[0142] The lead frame 30 has the same structure as the lead frame 20. The lead frame 30 includes a base 31 and protrusions 32, 33a, and 33b. The base 31 corresponds to the base 21. Protrusions 32, 33a, and 33b correspond to protrusions 22, 23a, and 23b, respectively. The base 31 has a stepped portion 35. The stepped portion 35 corresponds to the stepped portion 25. The lead frame 30 has a stepped portion 35 at its end on the lead frame 20 side of its upper surface. The stepped portion 35 has a bottom surface 35a and a side wall 35b. (The side wall 35b is not shown in the diagram.) The bottom surface 35a and the side wall 35b correspond to the bottom surface 25a and the side wall 25b, respectively. The bottom surface 35a has grooves 35e and 35f. Grooves 35e and 35f correspond to grooves 25e and 25f, respectively.

[0143] A semiconductor element 70 is provided between grooves 35e and 35f on the bottom surface 35a of the stepped portion 35.

[0144] The other end of the bonding wire 40 is connected to the upper surface of the pad 72. The bonding wire 40 electrically connects the pad 12 of the semiconductor element 10 to the base 31 of the lead frame 30 via the pad 72 of the semiconductor element 70.

[0145] The planar structure of the semiconductor device 1C other than that described above is the same as that shown in the second embodiment. Figure 17 as well as Figure 18 same.

[0146] Figure 23 as well as Figure 24 The cross-sectional structure of the semiconductor device 1C along the Sa-Sa line is the same as that shown in the third embodiment. Figure 22 same.

[0147] 4.2 Manufacturing Method of Semiconductor Devices

[0148] The manufacturing method of semiconductor device 1C is described.

[0149] In the manufacturing method of semiconductor device 1C, as shown in the second embodiment Figure 19 In flowchart S102A, a stepped portion 35 is formed at the end of the upper surface of the substrate 130 on the substrate 120 side, similar to the substrate 120. Figure 19 In flowchart S108, similar to substrate 120, grooves 35e and 35f are formed on the bottom surface 35a of the stepped portion 35 of substrate 130. Figure 19In flowchart S103A, a semiconductor element 70 is formed between grooves 35e and 35f on the bottom surface 35a of the stepped portion 35 of the substrate 130, similar to that of the substrate 120. Figure 19 In S104 of the flowchart, the bonding line 40 is bonded between the pad 12 of the semiconductor element 10 and the pad 72 of the semiconductor element 70.

[0150] The procedures other than those described above are the same as those in the first embodiment.

[0151] According to this embodiment, it achieves the same effect as the second embodiment.

[0152] 5. Variations, etc.

[0153] As described above, the semiconductor device 1 of this embodiment includes a first frame 30, a second frame 20, a first semiconductor element 10, a wire 40, and a package member 50. The second frame 20 is disposed opposite to the first frame 30 in the first direction X, and has a stepped portion 25 at the end of its upper surface on the first frame side. The first semiconductor element 10 is disposed on the bottom surface 25a of the stepped portion 25 of the second frame 20. The wire 40 electrically connects the first semiconductor element 10 to the first frame 30. The package member 50 covers a portion of both the first frame 30 and the second frame 20, and seals the first semiconductor element 10 and the wire 40. The lower surface S5 of the first frame 30 and the first side surface S6 of the first frame that is farther from the second frame 20 in the first direction X are exposed from the package member 50. The lower surface S1 of the second frame 20 and the second side surface S2 of the second frame that is farther from the first frame 30 in the first direction X are exposed from the package member 50.

[0154] Furthermore, the implementation method is not limited to the method described above, and various modifications can be made.

[0155] While several embodiments of the invention have been described, these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that, have: First frame; The second frame is disposed opposite the first frame in a first direction, and the second frame has a stepped portion at the end of its upper surface on the side of the first frame. A first semiconductor element is disposed on the bottom surface of the stepped portion of the second frame; A wire is used to electrically connect the first semiconductor element to the first frame; as well as The encapsulation component covers a portion of both the first frame and the second frame, and seals the first semiconductor element and the wire. The lower surface of the first frame and the first side of the first frame, which is farther from the second frame in the first direction, are exposed from the encapsulation component. The lower surface of the second frame and the second side of the second frame on the side farther from the first frame in the first direction are exposed from the encapsulation component.

2. The semiconductor device as claimed in claim 1, characterized in that, The height of the step portion of the second frame is less than 1 / 2 of the height of the second side of the second frame.

3. The semiconductor device as claimed in claim 1, characterized in that, The area of ​​the portion where the first semiconductor element contacts the bottom surface of the stepped portion of the second frame is more than 1 / 2 of the area of ​​the lower surface of the first semiconductor element.

4. The semiconductor device as claimed in claim 1, characterized in that, A portion of the first semiconductor element is opposite the second frame.

5. The semiconductor device as claimed in claim 4, characterized in that, The stepped portion of the second frame has a first sidewall in the first direction, and has a second sidewall and a third sidewall that are opposite each other in a second direction intersecting the first direction. The three sides of the first semiconductor element are surrounded by the first sidewall to the third sidewall.

6. The semiconductor device as claimed in claim 4, characterized in that, The stepped portion of the second frame has a first sidewall in the first direction. The first semiconductor element is opposite to the first sidewall in the first direction.

7. The semiconductor device as claimed in claim 6, characterized in that, The bottom surface of the stepped portion of the second frame has two grooves. The first semiconductor element is disposed between the two slots.

8. The semiconductor device as claimed in claim 7, characterized in that, The two grooves extend along the first direction from the first sidewall to the end of the first frame side of the bottom surface of the stepped portion. The two slots are separated from each other in a second direction that intersects the first direction.

9. The semiconductor device as claimed in claim 7, characterized in that, The two grooves each have a V-shaped shape when viewed from the first direction.

10. The semiconductor device as claimed in claim 1, characterized in that, The first frame includes a first base and a first protrusion. The first protrusion extends from the first base toward the side farther from the second frame in the first direction, and has a first notch at the end of the lower surface that is not in contact with the first base. The second frame includes a second base and a second protrusion. The second protrusion extends from the second base toward the side farther from the first frame in the first direction, and has a second notch at the end of the lower surface that is not in contact with the second base. A plating layer is provided on the lower surface of the first base, the lower surface of the first protrusion, the first notch, the lower surface of the second base, the lower surface of the second protrusion, and the second notch.

11. The semiconductor device as claimed in claim 1, characterized in that, It also has a second semiconductor element. The first frame has a stepped portion at its end on the second frame side of its upper surface. The second semiconductor element is disposed on the bottom surface of the stepped portion of the first frame. The line electrically connects the first semiconductor element to the first frame via the second semiconductor element.

12. The semiconductor device as claimed in claim 11, characterized in that, The height of the stepped portion of the first frame is less than 1 / 2 of the height of the first side of the first frame.

13. The semiconductor device as claimed in claim 11, characterized in that, A portion of the second semiconductor element is opposite to the first frame.

14. The semiconductor device as claimed in claim 1, characterized in that, The height of the first side of the first frame and the height of the second side of the second frame are both 150 μm or more and 200 μm or less.

15. A method for manufacturing a semiconductor device, characterized in that, It includes the following processes: A stepped portion is formed at the end of the upper surface of the lead frame substrate, which includes a first substrate and a second substrate disposed opposite to the first substrate in a first direction, on the first substrate side. A first semiconductor element is formed on the bottom surface of the stepped portion of the second substrate; The first semiconductor element is connected to the first substrate using a wire; A portion of the first substrate and a portion of the second substrate are covered by an encapsulation component, and the first semiconductor element and the wire are sealed using the encapsulation component; A plating layer is formed on the lower surface and side surface of the first substrate exposed from the encapsulation component and on the lower surface and side surface of the second substrate exposed from the encapsulation component; as well as The lead frame substrate and the packaging component are diced.

16. The method of manufacturing a semiconductor device as claimed in claim 15, characterized in that, The process of forming the stepped portion on the upper surface of the second substrate includes: performing a half-etch on the end of the upper surface of the second substrate on the first substrate side.

17. The method of manufacturing a semiconductor device as claimed in claim 15, characterized in that, The process of forming the stepped portion on the upper surface of the second substrate includes: forming the stepped portion having a first sidewall in the first direction and having a second sidewall and a third sidewall that are opposite each other in a second direction that intersects the first direction.

18. The method of manufacturing a semiconductor device as claimed in claim 15, characterized in that, The process of forming the stepped portion on the upper surface of the second substrate includes: forming the stepped portion having a first sidewall in the first direction.

19. The method of manufacturing a semiconductor device as claimed in claim 18, characterized in that, The process of forming the stepped portion on the upper surface of the second substrate further includes the process of forming two grooves on the bottom surface of the stepped portion. The process of forming the first semiconductor element includes: forming the first semiconductor element between the two trenches.

20. The method of manufacturing a semiconductor device as claimed in claim 19, characterized in that, The process of forming the two grooves on the bottom surface of the stepped portion includes: forming two grooves that are separated from each other in a second direction intersecting the first direction and extend along the first direction from the first sidewall to the end of the bottom surface of the stepped portion on the first substrate side.

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