Super-power flat no-lead power device packaging device

Abstract

The invention relates to a semiconductor device, in particular to the technical field of chip packaging, and discloses a super-power flat no-lead power device packaging device which comprises a bonding pad substrate, a connecting part is arranged on the bonding pad substrate, an anti-seismic part is arranged on the connecting part, a semiconductor part is arranged on the anti-seismic part, and the semiconductor part is arranged on the anti-seismic part. The shock-resistant part is provided with a shock-resistant part, the semiconductor part is provided with a heat dissipation part, the heat dissipation part is provided with a packaging part, and the shock-resistant part, the semiconductor part, the heat dissipation part and the packaging part form one single-side packaging mechanism. The two single-side packaging mechanisms are both installed on the bonding pad substrate and are oppositely arranged in the vertical direction, the two single-side packaging mechanisms are arranged in a staggered mode, a copper column, conductive column and micro-boss integrated vertical path is adopted, through-silicon vias are matched with BGA solder balls for short-path butt joint, the interconnection length is greatly shortened, and the production efficiency is improved. The problem that traditional lead bonding and flip-chip bonding are high in parasitic parameters is solved, and the requirements for high-frequency and large-current transmission are met.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more specifically to the field of chip packaging technology, specifically to a packaging device for ultra-high power flat leadless power devices. Background Technology

[0002] With the rapid development of new energy, aerospace, and high-end industrial control, increasingly higher demands are being placed on the power density, integration, and reliability of power devices. Ultra-high power devices generate a large amount of heat during operation, and the parasitic parameters of the internal interconnect structure directly affect the switching characteristics and operating efficiency of the devices. Therefore, ultra-low parasitic interconnects and efficient heat dissipation have become the core research directions for ultra-high power device packaging technology.

[0003] In existing packaging technologies for ultra-high power devices, interconnect structures mainly employ traditional methods such as wire bonding and flip-chip bonding. Wire bonding suffers from long interconnect lengths and high parasitic inductance, making it difficult to meet the high-frequency, low-loss operating requirements of ultra-high power devices. While flip-chip bonding technology offers some improvement in parasitic parameter optimization, the bump interconnect density of traditional flip-chip bonding is limited, and it is difficult to integrate it with efficient heat dissipation structures, resulting in limited device heat dissipation efficiency and making it unsuitable for ultra-high power density applications.

[0004] In terms of heat dissipation structure design, existing technologies mostly employ a single bottom-mounted or top-mounted heat dissipation solution. Bottom-mounted heat dissipation is typically achieved by setting up pads, but traditional bottom pads have limited thermal conductivity and poor compatibility with interconnect structures. Top-mounted heat dissipation often uses heat sinks, heat dissipation fins, and other structures, which can improve heat dissipation to some extent, but these structures increase the overall thickness of the device, disrupting the flat design of the device and failing to meet the requirements of miniaturization and thinner packaging. In addition, existing heat dissipation structures and interconnect structures are mostly separate designs, with poor coordination between the two. This not only occupies a large amount of packaging space but also leads to significant heat loss during the transfer process, further limiting the improvement of heat dissipation efficiency.

[0005] Meanwhile, flat leadless packaging has become an important development direction for ultra-high power device packaging due to its advantages such as small size, flexible pin layout, and ease of high-density integration. However, in existing flat leadless packaging technologies, the integration of interconnect and heat dissipation structures is difficult, making it hard to ensure both a flat leadless shape and ultra-low parasitic characteristics and ultra-high heat dissipation efficiency. This limits the improvement of power density of packaged devices and fails to meet the actual application requirements of ultra-high power devices. Summary of the Invention

[0006] (a) Technical problems to be solved To address the shortcomings of existing technologies, this invention provides a packaging device for ultra-high power flat leadless power devices, which solves the problems of high parasitic parameters of interconnect structures, low heat dissipation efficiency of heat dissipation structures, poor integration of interconnect and heat dissipation structures, and the inability to simultaneously achieve ultra-low parasitic parameters and ultra-high heat dissipation in a flat leadless form factor.

[0007] (II) Technical Solution To achieve the above objectives, the present invention provides the following technical solution: a high-power flat leadless power device packaging device, comprising a pad substrate, a connecting portion disposed on the pad substrate, a shock-resistant portion disposed on the connecting portion, a semiconductor portion disposed on the shock-resistant portion, a heat dissipation portion disposed on the semiconductor portion, and a packaging portion mounted on the heat dissipation portion. The shock-resistant portion, semiconductor portion, heat dissipation portion, and packaging portion constitute a single-sided packaging mechanism. There are two single-sided packaging mechanisms, both of which are mounted on the pad substrate and are arranged oppositely in the vertical direction. The two single-sided packaging mechanisms are staggered. The shock-resistant portion of the other single-sided packaging mechanism is located at the top, and a packaging cover is mounted on the shock-resistant portion. The shock-resistant portions of the two single-sided packaging mechanisms are connected to each other.

[0008] Preferably, the connecting part includes an edge sealing positioning frame, which is embedded in the pad substrate. The pad substrate is made of oxygen-free copper, and a base contact is provided on the pad substrate. A copper pillar is fixedly connected to the base contact.

[0009] Preferably, the shock-resistant part includes a first silicon interposer and a second silicon interposer. The first silicon interposer has a first silicon through-hole corresponding to the copper pillar. A first spring is fixedly connected to the first silicon interposer. A pipe groove is formed at the bottom of the first silicon interposer. The first silicon interposer is installed on the top side of the pad substrate.

[0010] Preferably, a second silicon through-hole corresponding to the copper pillar is formed on the second silicon interposer layer, and a second spring is fixedly connected to the second silicon interposer layer. The first spring and the second spring are arranged in a horizontal array, and each first spring and the corresponding second spring are in contact with each other. The copper pillar fits through the corresponding first silicon through-hole and the second silicon through-hole.

[0011] Preferably, the semiconductor section includes a chip frame in which a semiconductor chip is mounted, and conductive pillars corresponding to copper pillars are fixedly passed through the semiconductor chip. BGA solder balls are soldered between the semiconductor chip and the second silicon interposer.

[0012] Preferably, the conductive pillar is fixedly connected to the corresponding copper pillar. The conductive pillar is a composite pillar structure consisting of a barrier layer, a seed layer, and a main conductive layer. The barrier layer is made of tantalum nitride, the seed layer is made of copper, and the main conductive layer is made of oxygen-free copper.

[0013] Preferably, the heat dissipation part includes an encapsulation base top, on which micro-protrusions corresponding to conductive pillars are installed. The micro-protrusions are made of the same material as the copper pillars, and the protrusions of the micro-protrusions are fixedly connected to the corresponding conductive pillars.

[0014] Preferably, a micro heat pipe is installed on the top of the encapsulation base, and the body of the micro heat pipe is integrally connected to a working fluid port. The structure of the pipeline groove is the same as that of the micro heat pipe and the working fluid port. The micro heat pipe is filled with a phase change heat dissipation working fluid, which is deionized water.

[0015] Preferably, the encapsulation part includes a heat dissipation sealing edge and a chip sealing edge. The heat dissipation sealing edge is mounted on the sealing edge positioning frame, and the chip sealing edge is mounted on the heat dissipation sealing edge. A heat dissipation fin is installed through the side wall of the heat dissipation sealing edge. The heat dissipation fin contacts the first spring and the second spring. A grease injection port is connected to one side of the heat dissipation sealing edge, and a pipe hole corresponding to the working fluid port is opened on the other side of the heat dissipation sealing edge. The shock-absorbing part is installed inside the heat dissipation sealing edge.

[0016] Preferably, the semiconductor part and the heat dissipation part are installed inside the chip seal edge, and a sealing plate is fixedly connected between the inner walls of the chip seal edge. The sealing plate is sealed and installed on the semiconductor part and the heat dissipation part, and a second grease injection port is connected and installed on the chip seal edge.

[0017] (III) Beneficial Effects Compared with the prior art, the present invention provides an ultra-high power flat leadless power device packaging device, which has the following beneficial effects: 1. This ultra-high power flat leadless power device package adopts an integrated vertical path of copper pillars, conductive pillars, and micro-boobs, combined with through-silicon vias and short-path docking with BGA solder balls, which greatly shortens the interconnect length and solves the problem of high parasitic parameters in traditional wire bonding and flip-chip bonding, making it suitable for high-frequency and high-current transmission requirements.

[0018] 2. This ultra-high power flat leadless power device package adopts a multi-path solution of micro heat pipe phase change heat dissipation, fin convection heat dissipation, and oxygen-free copper substrate conduction heat dissipation. Combined with the dual single-sided mechanism heat dissipation channel sharing design, it can quickly conduct and dissipate the high heat flux density generated by ultra-high power devices, avoid hot spot accumulation, and break through the efficiency bottleneck of single heat dissipation solutions.

[0019] 3. This ultra-high power flat leadless power device packaging device adopts a dual single-sided mechanism with vertical staggered integration, omitting redundant structures. While ensuring high power density integration, it maintains a flat leadless shape, meets the requirements of miniaturization and thinness packaging, and solves the problems of poor integration and large space occupation of traditional heat dissipation and interconnection structures.

[0020] 4. This ultra-high power flat leadless power device package uses a spring array to form a shock-resistant buffer and layered epoxy resin encapsulation to achieve sealing protection, effectively resisting vibration, impact and external environmental corrosion, avoiding conductive structure breakage and chip damage, and improving the stability of the device under complex working conditions.

[0021] 5. This ultra-high power flat leadless power device packaging device uses positioning frames, through-silicon vias, and channel slots to precisely adapt each component, making it compatible with semiconductor chips of different processes. It balances integration flexibility and manufacturability, providing a universal solution for ultra-high power device packaging. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall front structure of a high-power flat leadless power device packaging device proposed in this invention; Figure 2 This is a schematic diagram of the overall rear structure of the present invention; Figure 3 This is an internal structural diagram of the chip sealing edge and heat dissipation sealing edge of the present invention; Figure 4 This is a schematic diagram of the structure of the connecting part of the present invention; Figure 5 This is a schematic diagram of the structure of the first silicon interposer layer of the present invention; Figure 6 This is a schematic diagram of the bottom structure of the first silicon interposer layer of the present invention; Figure 7 This is a diagram showing the fit between the second silicon interposer and the semiconductor portion of the present invention; Figure 8 This is a schematic diagram of the heat dissipation part of the present invention; Figure 9 This is a schematic diagram of the outer wall structure of the packaging part of the present invention; Figure 10 This is a schematic diagram of the inner wall structure of the packaging part of the present invention.

[0023] In the diagram: 1. Pad substrate; 2. Connector; 21. Sealing and positioning frame; 22. Base contact; 23. Copper pillar; 3. Anti-vibration part; 31. First silicon interposer; 32. First silicon via; 33. First spring; 34. Piping groove; 35. Second silicon interposer; 36. Second spring; 4. Semiconductor part; 41. Chip frame; 42. Semiconductor chip; 43. Conductive pillar; 44. BGA solder ball; 5. Heat dissipation part; 51. Package base top; 52. Micro boss; 53. Micro heat pipe; 54. Working fluid port; 6. Package part; 61. Heat dissipation sealing edge; 62. Heat dissipation fin; 63. Grease port one; 64. Piping hole; 65. Chip sealing edge; 66. Sealing plate; 67. Grease port two; 7. Package cap. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Please see Figure 1 - Figure 10 This invention provides a high-power, flat, leadless power device packaging device, including a pad substrate 1, which serves as the device reference surface, providing the signal transmission starting point and heat dissipation foundation. It utilizes oxygen-free copper material to achieve rapid heat conduction, adapting to the heat dissipation requirements of high-power devices. A connecting portion 2 is provided on the pad substrate 1, an anti-vibration portion 3 is provided on the connecting portion 2, a semiconductor portion 4 is provided on the anti-vibration portion 3, a heat dissipation portion 5 is provided on the semiconductor portion 4, and a packaging portion 6 is mounted on the heat dissipation portion 5. The anti-vibration portion 3, the semiconductor portion 4, the heat dissipation portion 5, and the packaging portion 6 form a single-sided packaging mechanism. The single-sided packaging mechanism has multiple... There are two single-sided package mechanisms, both mounted on the pad substrate 1 and positioned opposite each other in the vertical direction. The two single-sided package mechanisms are staggered. The shock-absorbing part 3 in the other single-sided package mechanism is located at the top. A package cover 7 is installed on the shock-absorbing part 3 to seal and protect the upper shock-absorbing part 3, ensuring the integrity of the double single-sided staggered structure and maintaining the flat, leadless shape. The shock-absorbing parts 3 in the two single-sided package mechanisms are connected to each other. Below the other shock-absorbing part 3 are the heat dissipation part 5 and the semiconductor part 4, respectively. The other semiconductor part 4 is connected to the pad substrate 1.

[0026] In this embodiment, the connecting part 2 includes an edge sealing positioning frame 21, which is embedded in the pad substrate 1. The pad substrate 1 is made of oxygen-free copper and has a base contact 22. A copper pillar 23 is fixedly connected to the base contact 22. The edge sealing positioning frame 21 enables precise positioning and installation of each component. The copper pillar 23 and the base contact 22 are used to build a bottom vertical conductive link, which solves the problem of high parasitic parameters in traditional interconnects.

[0027] Furthermore, the shock-resistant part 3 includes a first silicon interposer 31 and a second silicon interposer 35. The first silicon interposer 31 has a first silicon through-hole 32 corresponding to the copper pillar 23. A first spring 33 is fixedly connected to the first silicon interposer 31. A channel groove 34 is formed at the bottom of the first silicon interposer 31. The first silicon interposer 31 is installed on the top side of the pad substrate 1. The second silicon interposer 35 has a second silicon through-hole corresponding to the copper pillar 23. A second spring 36 is fixedly connected to the second silicon interposer 35. The first spring 33 and the second spring 36 are both arranged in a horizontal array. Each first spring 33 is in contact with the corresponding second spring 36. The copper pillar 23 fits and penetrates the corresponding first silicon through-hole 32 and second silicon through-hole. The encapsulation cover 7 is installed on the top of another second silicon interposer 35. Using the silicon interposer as a carrier, an elastic buffer structure is formed by the springs. At the same time, the silicon through-hole is used to adapt to the penetration of the copper pillar 23, taking into account both shock protection and interconnect compatibility, and making up for the shortcomings of insufficient shock resistance of traditional packaging.

[0028] It is worth noting that the semiconductor section 4 includes a chip frame 41, in which a semiconductor chip 42 is mounted. A conductive post 43 corresponding to the copper post 23 is fixedly passed through the semiconductor chip 42. A BGA solder ball 44 is soldered between the semiconductor chip 42 and the second silicon interposer 35. The conductive post 43 is fixedly connected to the corresponding copper post 23. The conductive post 43 is a composite pillar structure of a barrier layer, a seed layer, and a main conductive layer. The barrier layer is made of tantalum nitride, the seed layer is made of copper, and the main conductive layer is made of oxygen-free copper. Another BGA solder ball 44 in the semiconductor section 4 is connected to the base contact 22 on the pad substrate 1. The semiconductor chip 42 is fixed by the chip frame 41. The composite structure conductive post 43 and the BGA solder ball 44 form a short-path interconnect, realizing high current and low loss transmission, and solving the problems of low density and high loss in traditional interconnects.

[0029] Furthermore, the heat dissipation unit 5 includes an encapsulation base 51, on which a micro-protrusion 52 corresponding to the conductive post 43 is mounted. The micro-protrusion 52 is made of the same material as the copper post 23. The protrusions of the micro-protrusion 52 are fixedly connected to the corresponding conductive post 43. The copper post 23, the conductive post 43, and the micro-protrusion 52 form a vertical conductive path. The copper post 23 also penetrates the encapsulation base 51 in another heat dissipation unit 5, forming a vertical conductive path for another single-sided encapsulation mechanism, realizing vertical electrical interconnection. A micro heat pipe 53 is mounted on the encapsulation base 51, and the body of the micro heat pipe 53 is integrally connected. The structure of the working fluid inlet 54 and the pipe groove 34 is the same as that of the micro heat pipe 53 and the working fluid inlet 54. The micro heat pipe 53 is filled with a phase change heat dissipation working fluid, which is deionized water. The micro heat pipe 53 in another heat dissipation part 5 is embedded in the pipe groove 34 at the bottom of the first silicon interlayer 31 in another shock-resistant part 3, and the working fluid inlet 54 is embedded in another pipe hole 64. The vertical conductive path is completed by relying on the micro protrusion 52. The phase change heat dissipation of the micro heat pipe 53 is adapted to the pipe groove 34 for installation, thus constructing an efficient heat dissipation channel and solving the pain point of low efficiency of a single heat dissipation solution.

[0030] It is worth noting that the encapsulation part 6 includes a heat dissipation sealing edge 61 and a chip sealing edge 65. The heat dissipation sealing edge 61 is mounted on the sealing edge positioning frame 21, and the chip sealing edge 65 is mounted on the heat dissipation sealing edge 61. A heat dissipation fin 62 is installed through the side wall of the heat dissipation sealing edge 61. The heat dissipation fin 62 contacts the first spring 33 and the second spring 36. A grease injection port 63 is connected to one side of the heat dissipation sealing edge 61. The grease injection port 63 is filled with epoxy resin to form a plastic seal within the two shock-absorbing parts 3. A pipe hole 64 corresponding to the working fluid port 54 is opened on the other side of the heat dissipation sealing edge 61. The shock-absorbing part 3 is installed inside the heat dissipation sealing edge 61. Semiconductor section 4 and heat dissipation section 5 are installed inside chip sealing edge 65. A sealing plate 66 is fixedly connected between the inner walls of chip sealing edge 65. The sealing plate 66 is sealed and installed on semiconductor section 4 and heat dissipation section 5. A second grease injection port 67 is connected to chip sealing edge 65. The second grease injection port 67 is filled with epoxy resin to form an independent plastic encapsulation protection for each semiconductor chip 42 between chip sealing edge 65 and sealing plate 66. The heat dissipation sealing edge 61 and chip sealing edge 65 are layered and packaged. Heat dissipation is enhanced by heat dissipation fins 62. Sealing protection is achieved by the grease injection port and sealing plate 66, taking into account both heat dissipation and structural stability.

[0031] Working principle: The pad substrate 1 serves as the signal and heat dissipation reference surface. The base contact 22 on its surface is fixedly connected to the copper pillar 23. The copper pillar 23 penetrates the first silicon via 32 of the first silicon interposer 31 and the second silicon via 35 of the second silicon interposer 35, building a bottom vertical conductive foundation. The conductive pillar 43 on the semiconductor chip 42 is fixedly connected to the copper pillar 23. At the same time, the semiconductor chip 42 is connected to the second silicon interposer 35 through the BGA solder ball 44 to achieve chip layer signal matching and high current transmission. The micro-protrusion 52 on the top of the package base 51 is made of the same material as the copper pillar 23 and is connected to the protrusion of the conductive pillar 43, forming a complete vertical conductive path from the copper pillar 23 to the conductive pillar 43 to the micro-protrusion 52. In another staggered single-sided package mechanism, the copper pillar 23 penetrates the top of the package base 51 of its heat dissipation part 5, simultaneously building a second vertical interconnection path. Finally, the dual single-sided mechanism and the pad substrate 1 are connected in a through electrical connection, reducing parasitic inductance and resistance.

[0032] The heat generated by the semiconductor chip 42 during operation is partially conducted to the oxygen-free copper pad substrate 1 through the conductive pillars 43 and copper pillars 23, where it is rapidly diffused due to the high thermal conductivity of copper. Another portion is transferred to the micro heat pipe 53 through the top of the encapsulation base 51. The deionized water phase change working fluid in the micro heat pipe 53 absorbs heat and vaporizes in the evaporation section. After the vapor migrates to the condensation section, it exchanges heat with the outside through the working fluid port 54 and liquefies and flows back, forming a circulating heat dissipation. At the same time, the micro heat pipe 53 in another single-sided encapsulation mechanism is embedded in the pipeline groove 34 at the bottom of the first silicon interposer 31 to expand the heat capture area. The heat dissipation fins 62 on the side wall of the heat dissipation sealing edge 61 are in contact with the first spring 33 and the second spring 36. The springs transfer the heat conducted by the silicon interposer to the fins, accelerating heat dissipation through convection heat transfer. The epoxy resin encapsulation layer filled by the grease port 63 helps to disperse the local heat of the shock-resistant part 3, avoids hot spot accumulation, and forms a multi-path heat dissipation closed loop.

[0033] The first spring 33 of the first silicon interposer 31 and the second spring 36 of the second silicon interposer 35 are horizontally arrayed and in contact with each other to form an elastic buffer layer. When the device is subjected to vibration or impact, the spring absorbs energy through deformation, protecting the rigid structures such as the copper pillar 23 and the conductive pillar 43 from damage. The heat dissipation sealing edge 61 is filled with epoxy resin through the first grease port 63 to encapsulate the two shock-resistant parts 3 as a whole. The chip sealing edge 65 is filled with epoxy resin through the second grease port 67. Combined with the sealing plate 66, the semiconductor part 4 and the heat dissipation part 5 are independently encapsulated to achieve layered sealing protection. The two single-sided packaging mechanisms are vertically opposite and staggered. The shock-resistant part 3 of the upper mechanism is connected to the shock-resistant part 3 of the lower mechanism. While sharing the heat dissipation channel, the overall thickness is compressed to maintain the flat leadless package form.

[0034] After the device is connected to the circuit, the heat is dissipated synchronously through three paths. The spring of the shock-resistant part 3 buffers the vibration, and the double-sealed epoxy resin achieves sealing protection. The three work together to ensure the stable operation of the device under ultra-high power conditions.

[0035] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A high-power flat leadless power device packaging device, comprising a pad substrate (1), characterized in that: A connecting part (2) is provided on the pad substrate (1), an anti-vibration part (3) is provided on the connecting part (2), a semiconductor part (4) is provided on the anti-vibration part (3), a heat dissipation part (5) is provided on the semiconductor part (4), and a packaging part (6) is installed on the heat dissipation part (5). The anti-vibration part (3), semiconductor part (4), heat dissipation part (5) and packaging part (6) form a single-sided packaging mechanism. There are two single-sided packaging mechanisms. Both single-sided packaging mechanisms are installed on the pad substrate (1) and are arranged oppositely in the vertical direction. The two single-sided packaging mechanisms are staggered. The anti-vibration part (3) in the other single-sided packaging mechanism is located at the top. A packaging cover (7) is installed on the anti-vibration part (3). The anti-vibration parts (3) in the two single-sided packaging mechanisms are connected to each other.

2. The ultra-high power flat leadless power device packaging device according to claim 1, characterized in that: The connecting part (2) includes an edge sealing positioning frame (21), which is embedded on the pad base (1). The pad base (1) is made of oxygen-free copper. A base contact (22) is provided on the pad base (1), and a copper pillar (23) is fixedly connected to the base contact (22).

3. The ultra-high power flat leadless power device packaging device according to claim 2, characterized in that: The shock-resistant part (3) includes a first silicon interposer (31) and a second silicon interposer (35). A first silicon through-hole (32) corresponding to the copper pillar (23) is opened on the first silicon interposer (31). A first spring (33) is fixedly connected to the first silicon interposer (31). A pipeline groove (34) is opened at the bottom of the first silicon interposer (31). The first silicon interposer (31) is installed on the top side of the pad substrate (1).

4. The ultra-high power flat leadless power device packaging device according to claim 3, characterized in that: The second silicon interposer (35) has a second silicon through-hole corresponding to the copper pillar (23). A second spring (36) is fixedly connected to the second silicon interposer (35). The first spring (33) and the second spring (36) are arranged in a horizontal array. Each first spring (33) is in contact with the corresponding second spring (36). The copper pillar (23) fits through the corresponding first silicon through-hole (32) and the second silicon through-hole.

5. The ultra-high power flat leadless power device packaging device according to claim 4, characterized in that: The semiconductor section (4) includes a chip frame (41), in which a semiconductor chip (42) is mounted, and a conductive post (43) corresponding to the copper post (23) is fixedly passed through the semiconductor chip (42), and a BGA solder ball (44) is soldered between the semiconductor chip (42) and the second silicon interposer (35).

6. The ultra-high power flat leadless power device packaging device according to claim 5, characterized in that: The conductive pillar (43) is fixedly connected to the corresponding copper pillar (23). The conductive pillar (43) is a composite pillar structure of a barrier layer, a seed layer and a main conductive layer. The barrier layer is made of tantalum nitride, the seed layer is made of copper, and the main conductive layer is made of oxygen-free copper.

7. The ultra-high power flat leadless power device packaging device according to claim 6, characterized in that: The heat dissipation part (5) includes a packaging base (51), on which a micro-protrusion (52) corresponding to the conductive post (43) is installed. The micro-protrusion (52) is made of the same material as the copper post (23), and the protrusion of the micro-protrusion (52) is fixedly connected to the corresponding conductive post (43).

8. The ultra-high power flat leadless power device packaging device according to claim 7, characterized in that: A micro heat pipe (53) is installed on the top (51) of the encapsulation base. The body of the micro heat pipe (53) is integrally connected to a working fluid port (54). The structure of the pipeline groove (34) is the same as that of the micro heat pipe (53) and the working fluid port (54). The micro heat pipe (53) is filled with a phase change heat dissipation working fluid, which is deionized water.

9. A high-power flat leadless power device packaging device according to claim 8, characterized in that: The encapsulation part (6) includes a heat dissipation sealing edge (61) and a chip sealing edge (65). The heat dissipation sealing edge (61) is mounted on the sealing edge positioning frame (21), and the chip sealing edge (65) is mounted on the heat dissipation sealing edge (61). A heat dissipation fin (62) is installed through the side wall of the heat dissipation sealing edge (61). The heat dissipation fin (62) is in contact with the first spring (33) and the second spring (36). A grease injection port (63) is connected to one side of the heat dissipation sealing edge (61), and a pipe hole (64) corresponding to the working fluid port (54) is opened on the other side of the heat dissipation sealing edge (61). The shock-absorbing part (3) is installed inside the heat dissipation sealing edge (61).

10. A high-power flat leadless power device packaging device according to claim 9, characterized in that: The semiconductor part (4) and the heat dissipation part (5) are installed inside the chip sealing edge (65). A sealing plate (66) is fixedly connected between the inner walls of the chip sealing edge (65). The sealing plate (66) is sealed and installed on the semiconductor part (4) and the heat dissipation part (5). A second grease injection port (67) is connected and installed on the chip sealing edge (65).

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