Glass substrate structure, preparation and packaging method thereof, electronic component and integrated circuit

Abstract

The invention relates to the technical field of semiconductors, and discloses a glass substrate structure, a preparation method and a packaging method of the glass substrate structure, an electronic component and an integrated circuit. The conductive interconnection channel penetrates through the glass core plate; the parallel plate capacitor and the first rewiring structure are positioned on the first surface of the glass core plate; wherein the parallel plate capacitor is an aluminum-based capacitor; the second re-wiring structure is positioned on the second surface of the glass core plate; wherein the second surface and the first surface are two opposite surfaces on the glass core plate; the second redistribution structure is electrically connected with the first redistribution structure through the conductive interconnection channel. The glass substrate structure has the advantages that the glass core plate is used for providing basic support, the aluminum-based capacitor is used for simplifying the process and reducing the cost, signal distribution and transmission are achieved through the first rewiring structure and the second rewiring structure, and finally based on cooperation of all the components, the glass substrate structure keeps excellent electrical performance, and meanwhile the electrical performance of the glass substrate structure is improved. And the manufacturing process is simpler and the yield is higher.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a glass substrate structure, its preparation and packaging method, and electronic components and integrated circuits. Background Technology

[0002] Glass substrates have become a key material for advanced packaging due to their excellent high-frequency electrical properties, surface flatness, and low cost potential. However, glass substrate technology in related fields has limitations such as low yield, high cost, and difficult manufacturing process, requiring a glass substrate structure with higher performance. Summary of the Invention

[0003] This application aims to at least partially solve one of the technical problems in related technologies. To this end, this application proposes a glass substrate structure, its fabrication and packaging method, and electronic components and integrated circuits thereof. The main technical solutions adopted in this application include: In a first aspect, this application provides a glass substrate structure, the glass substrate structure comprising: a glass core plate; a conductive interconnect channel penetrating the glass core plate; a parallel plate capacitor and a first rewiring structure located on a first surface of the glass core plate; wherein the parallel plate capacitor is an aluminum-based capacitor; and a second rewiring structure located on a second surface of the glass core plate; wherein the second surface and the first surface are two opposite surfaces on the glass core plate; and the second rewiring structure is electrically connected to the first rewiring structure through the conductive interconnect channel.

[0004] By using a glass core board as a basic support, signal communication between the front and back sides is achieved through conductive interconnection channels. Aluminum-based capacitors are used to simplify the process and reduce costs. Signal distribution and transmission are achieved through first and second wiring structures. Ultimately, based on the synergistic cooperation of each component, the glass substrate structure maintains excellent electrical performance while making the manufacturing process simpler and the yield higher.

[0005] Optionally, the second side also includes a pad area; wherein the pad area is used to mount at least one chip.

[0006] This method of placing the pad area on the second side avoids the risk of chip cracking caused by carrier transfer, maintains good RF performance, and simplifies the packaging process.

[0007] Optionally, both the first and second wiring structures include at least two sets of wiring film units; wherein each set of wiring film units includes a metal wiring layer and a passivation layer of a target thickness stacked sequentially; and the target thickness is no greater than 10 micrometers.

[0008] By setting at least two sets of wiring thin film units and using sequentially stacked metal wiring layers and passivation layers of target thickness, high-density signal interconnection can be achieved, while the target thickness can be controlled within the range that can be prepared in a single spin coating. This simplifies the process steps and improves the interlayer uniformity, thereby improving the fabrication yield and performance stability of the redistribution structure.

[0009] Secondly, this application provides a method for preparing a glass substrate structure, which includes: providing a glass core plate; wherein a conductive interconnect channel is formed in the glass core plate; forming a parallel plate capacitor and a first rewiring structure on a first surface of the glass core plate; wherein the parallel plate capacitor is an aluminum-based capacitor; thinning a second surface of the glass core plate; and forming a second rewiring structure on the second surface to obtain the glass substrate structure; wherein the second rewiring structure is electrically connected to the first rewiring structure through the conductive interconnect channel.

[0010] First, a glass core board containing conductive interconnect channels is provided, laying the foundation for signal interconnection on both sides. Then, aluminum-based capacitors are used to replace copper-based capacitors in related technologies, simplifying the fabrication process, reducing costs, and improving structural compatibility. Next, a temporary carrier board is bonded to the first side, and the second side is controllably thinned, providing safe and flat processing conditions for the back-side process. Finally, taking full advantage of the back-side layout, a single spin-coating process is used to further optimize the thickness of the critical passivation layer, significantly improving the fabrication yield of the glass substrate structure while ensuring the electrical performance and structural stability of the product.

[0011] Optionally, forming a parallel plate capacitor and a first superwiring structure on the first surface of the glass core plate includes: performing a deposition process on the first surface to form a parallel plate capacitor; and forming the first superwiring structure on the first surface using an additive method.

[0012] First, an aluminum-based capacitor is formed on the first side of the glass core board using a relatively simple deposition process. Then, an addition method is used to construct a multi-layer rewiring structure containing a thin passivation layer, thereby achieving the integrated integration of high-performance passive devices and high-density interconnect lines.

[0013] Optionally, the first wiring structure includes at least two sets of wiring thin film units; the wiring thin film units include a metal wiring layer and a passivation layer stacked sequentially; forming the first wiring structure on the first surface using an additive method includes: performing photolithography electroplating on the first surface to generate a metal wiring layer; and performing a single spin coating process on the metal wiring layer to generate a passivation layer.

[0014] Photolithography and electroplating are used to generate metal wiring layers, thereby forming complex metal interconnect circuits with high precision. Furthermore, the process of generating passivation layers through multiple coating processes is eliminated, simplifying the process steps, shortening production time, and improving the uniformity of passivation layer thickness, thereby enhancing the flatness and electrical performance stability of the circuit.

[0015] Optionally, the second wiring structure includes at least two sets of wiring thin film units; the wiring thin film units include a metal wiring layer and a passivation layer stacked sequentially; forming the second wiring structure on the second surface includes: performing photolithography electroplating on the second surface to generate a metal wiring layer; and performing a single spin coating process on the metal wiring layer to generate a passivation layer.

[0016] A metal wiring layer for the second wiring structure is generated through photolithography and electroplating, thereby achieving precise alignment with the conductive interconnect channels and ensuring smooth signal transmission. This also avoids interlayer alignment deviations caused by multiple spin coatings, improving the stability and yield of the redistribution structure.

[0017] Thirdly, this application provides a packaging method for a glass substrate structure, used to package the aforementioned glass substrate structure, wherein the second side of the glass substrate structure further includes a pad area. The method includes: when the glass substrate structure is placed with the second side facing upward, mounting at least one chip onto the pad area of ​​the second side using a flip-chip bonding process; forming a package on the second side to complete the packaging; wherein the package is used to cover and protect the chip.

[0018] By placing the glass substrate structure with the second side facing upwards, the pad area is directly exposed, and the entire encapsulation operation is concentrated on a single plane (the second side). This avoids the high-risk carrier transfer steps and the resulting debonding / rebonding operations in traditional solutions. This simplifies the process and fundamentally eliminates the risk of glass core board cracking due to stress concentration. It also avoids residual adhesive and bubble problems related to temporary bonding adhesive, significantly improving the yield, reliability, and production efficiency of the encapsulation.

[0019] Fourthly, this application also provides an electronic component comprising the aforementioned glass substrate structure.

[0020] Fifthly, this application also provides an integrated circuit comprising the aforementioned electronic components. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1a This is a schematic diagram of a longitudinal section of a glass substrate structure provided in related technologies; Figure 1b This is a flowchart illustrating the fabrication process of a glass substrate structure provided in related technologies; Figure 1c This is a packaging flowchart based on a glass substrate structure provided in related technologies; Figure 1d This is a longitudinal cross-sectional schematic diagram of a glass substrate structure according to an embodiment of this application; Figure 2a This is a flowchart of a method for preparing a glass substrate structure according to an embodiment of this application; Figure 2b This is a schematic diagram of the structure of a glass core plate according to an embodiment of this application; Figure 2c This is a schematic diagram of the structure of a capacitor according to an embodiment of this application; Figure 2d This is a schematic diagram of a first wiring structure provided according to an embodiment of this application; Figure 2e This is a schematic diagram of the bonded structure according to an embodiment of this application; Figure 2f This is a schematic diagram of the structure after grinding according to an embodiment of this application; Figure 2g This is a schematic diagram of a second wiring structure provided according to an embodiment of this application; Figure 3a This is a flowchart of a packaging method for a glass substrate structure according to an embodiment of this application; Figure 3b This is a schematic diagram of a wafer inversion structure according to an embodiment of this application; Figure 3c This is a schematic diagram of the chip bonding structure according to an embodiment of this application; Figure 3d This is a schematic diagram of the glass cover plate after bonding according to an embodiment of this application; Figure 3e This is a schematic diagram showing the packaged product according to one embodiment of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] Unless otherwise specified, the experimental methods used in the following examples are conventional methods. Unless otherwise specified, the materials, reagents, methods, and instruments used are all conventional materials, reagents, methods, and instruments in the art, and can be obtained commercially by those skilled in the art.

[0025] For example, the side containing the metal-insulator-metal capacitor (MIM) is considered the front side of the glass substrate structure, such as... Figure 1a As shown, the glass substrate structure in the related technology includes a front redistribution structure, a front window and metal surface treatment area, a copper-based capacitor and a glass cover bonding area on the front side, and a back redistribution structure and a back window and metal surface treatment area on the back side. The glass core board, which serves as the main supporting substrate of the glass substrate, has a glass through-hole (TGV).

[0026] Specifically, a front-side redistribution structure can refer to a wiring structure on the front side of a glass core board used for signal transmission and interconnection, including at least two front-side redistribution thin-film units, and each front-side redistribution thin-film unit includes a metal layer and a passivation layer stacked sequentially. The metal layer can be a conductive layer used for transmitting electrical signals, such as a copper layer formed by electroplating. The passivation layer can be a surface layer covering the structure to protect the internal structure from external environmental influences; its material can be a dielectric polymer such as polyimide (PI) or polybenzoxazole (PBO).

[0027] For example, taking PI as the material for the passivation layer, please continue to refer to... Figure 1a The front-side redistribution structure, from the inside out, may include a first front-side PI layer, a first front-side metal layer, a second front-side PI layer, a second front-side metal layer, a third front-side PI layer, a third front-side metal layer, and a fourth front-side PI layer stacked sequentially. Copper-based capacitors can be placed on the first front-side metal layer to provide the necessary decoupling or filtering functions. Front-side openings and metal surface treatment areas can be placed on the third front-side metal layer to expose pads in preparation for subsequent flip-chip bonding.

[0028] Furthermore, taking glass cover encapsulation as an example, a glass cover bonding area is also provided on the glass core plate on the front side. This glass cover bonding area can refer to the area used to connect with the glass cover to achieve encapsulation and sealing.

[0029] Similarly, a back-side redistribution structure refers to a circuit structure disposed on the back of a glass core board, also used for signal transmission and interconnection. It includes at least two back-side redistribution thin-film units, and each back-side redistribution thin-film unit also includes a metal layer and a passivation layer stacked sequentially. For example, again using PI as the passivation layer material, please refer to... Figure 1a The back-side redistribution structure may include a first back-side PI layer, a first back-side metal layer, a second back-side PI layer, and a second back-side metal layer.

[0030] It should be noted that the first PI layer on the back side includes a first spin coating layer and a second spin coating layer. Both spin coating layers are essentially PI dielectric, but because the thickness of a single spin coating in traditional processes is limited, and for RF performance considerations, the PI dielectric needs to meet preset thickness requirements, it is necessary to perform two spin coatings and cure them separately to stack and form the first PI layer on the back side, thus meeting the electrical performance requirements for dielectric thickness. Furthermore, the back-side opening and metal surface treatment area are located on the second metal layer on the back side, also used to expose metal pads and achieve electrical connection with external components.

[0031] In addition, multiple through-holes, or conductive interconnects, are provided in the glass core board to achieve vertical electrical interconnection on the front and back sides of the glass core board.

[0032] Furthermore, the traditional glass substrate fabrication method generally employs methods such as... Figure 1b The process is illustrated below. First, a glass wafer is used as the glass core board, and blind vias are constructed within it to form conductive interconnect channels. Then, the blind vias are fabricated and electroplated using the damascus process. Next, redistribution structures and components such as capacitors are fabricated on the front side of the glass core board. Temporary bonding adhesive is then used to bond a temporary carrier board to the front side of the glass core board to protect the completed front-side fine structure. The temporary carrier board is a rigid substrate used during the process to support the glass core board and prevent warping or breakage. Subsequently, the back side of the glass core board is thinned, and a back-side redistribution structure is fabricated there. Finally, the temporary bonding carrier board is unbonded from the front side of the glass core board and transferred to the back side to protect the back-side structure.

[0033] Furthermore, the packaging steps of traditional glass substrate solutions can be as follows: Figure 1cAs shown, the chip is first flip-chip bonded to the front side of the glass core board (i.e., the side with the redistribution structure already completed) using copper bumps. Next, a glass cover plate is bonded to the glass cover plate bonding area on the front side of the glass core board using laser melting, covering and protecting the chip. Finally, back-side debonding is performed, that is, the temporary bonding carrier on the back side of the glass core board is removed, exposing the back pads for subsequent system integration, thus completing the packaging.

[0034] Based on the above steps, the relevant technology has the following limitations: First, the yield is low. On the one hand, the temporary bonding adhesive filled in the bonding area of ​​the glass cover is prone to bonding bubbles, and adhesive residue is easily left after debonding. On the other hand, the carrier transfer process requires debonding and rebonding operations on the thinned glass core board, which causes stress concentration and easily leads to breakage of the glass core board. Second, the cost is high. On the one hand, the copper-based capacitors in the front redistribution structure are prepared using the Damascus process, which is complex, costly, and has a low yield. On the other hand, to meet the RF electrical performance requirements, the passivation layer thickness between the first and second metal layers on the back side needs to reach 20 micrometers, which exceeds the single spin coating capability and requires multiple spin coatings, increasing process time, material costs, and interlayer alignment risks. At the same time, multiple coatings result in poor uniformity of passivation layer thickness, affecting circuit accuracy and reliability. Third, the process is difficult. The thickness of the second passivation layer on the back side of the glass substrate needs to reach 15 micrometers, which exceeds the capability of current mass production processes, easily causing defects and affecting product yield and reliability. In summary, there is a need for a new glass substrate structure and its fabrication and packaging method that can simplify the process, reduce costs, and significantly improve mass production yield.

[0035] This application provides a glass substrate structure; please refer to [reference needed]. Figure 1d ,like Figure 1d As shown, the glass substrate structure includes a glass core plate 100, a conductive interconnect channel 102, a parallel plate capacitor 104, a first rewiring structure 110, and a second rewiring structure 120.

[0036] The glass core board refers to the substrate that serves as the overall structural support component. It can be made of low-dielectric-loss glass materials, such as borosilicate glass, to support the various functional layers and provide physical support. The conductive interconnect channel refers to a hollow vertical passage within the glass core board, i.e., a through-glass via (TGV). Specifically, this conductive interconnect channel penetrates the glass core board and is filled with conductive materials such as copper, enabling electrical connection between the two sides of the glass core board.

[0037] It is understandable that a glass core board has two opposing planes, referred to as the first side and the second side. The first side can be the side primarily integrating active / passive devices and internal fine wiring, while the second side is the opposite side of the glass core board. If the first side is the front, the second side can be understood as the back, located on opposite sides of the glass core board.

[0038] Specifically, the first surface of the glass core plate 100 has a parallel plate capacitor 104 and a first rewiring structure 110. Conversely, the second surface of the glass core plate 100 has a second rewiring structure 120.

[0039] The parallel plate capacitor can refer to a passive device capable of filtering or other functions, and can be a capacitor element formed by alternating stacks of metal layers and insulating layers. For example, the parallel plate capacitor can be an aluminum-based capacitor. Compared to copper-based capacitors fabricated using complex damascus processes in related technologies, aluminum-based capacitors can be formed using relatively simple processes such as plasma-enhanced chemical vapor deposition, significantly reducing fabrication complexity and cost.

[0040] It should be noted that both the first and second wiring structures can refer to thin-film structures disposed on one side of the glass core board, used for signal distribution and interconnection. The second wiring structure is electrically connected to the first wiring structure via conductive interconnect channels. That is, the metal wiring layer in the second wiring structure forms an electrical connection with the corresponding metal wiring layer in the first wiring structure through the conductive material filled within the conductive interconnect channels, thereby enabling signal exchange between the two sides.

[0041] Furthermore, both the first wiring structure 110 and the second wiring structure 120 include at least two sets of wiring film units.

[0042] The wiring film unit can refer to the basic functional layer constituting the redistribution structure, containing a conductive line and its insulating protective layer. That is, each set of wiring film units includes a metal wiring layer and a passivation layer of the target thickness stacked sequentially. The metal wiring layer is the conductive line layer that carries electrical signals, and the passivation layer of the target thickness is the dielectric layer covering the surface of the metal wiring layer to achieve interlayer insulation and structural protection. Its material can be a dielectric polymer such as PI or PBO.

[0043] Furthermore, based on design requirements, the passivation layer can be designed with different target thicknesses. However, the target thickness is no greater than 10 micrometers, and preferably 7 micrometers. This target thickness is designed because it is within the single spin-coating capability of existing processes, eliminating the need for multiple coatings, thus simplifying the process, reducing costs, and improving the uniformity of the passivation layer thickness.

[0044] For example, please continue to refer to Figure 1d Taking the first wiring structure 110, which includes three sets of wiring film units, and the second wiring structure 120, which includes two sets of wiring film units, as an example, the first wiring structure 110 includes, from the inside out, a first wiring film unit, a second wiring film unit, and a third wiring film unit.

[0045] The first wiring thin film unit includes a first metal wiring layer 111 and a first passivation layer 112, which can realize the bottom conductive interconnection and provide a connection basis for the parallel plate capacitor 104.

[0046] The second wiring film unit includes a second metal wiring layer 113 and a second passivation layer 114. The second metal wiring layer can be used to expand the density of signal lines, and the second passivation layer can isolate adjacent metal layers to avoid crosstalk, thereby constructing intermediate layer interconnection lines.

[0047] The third wiring thin film unit includes a third metal wiring layer 115 and a third passivation layer 116, and can serve as the outermost wiring and protection structure on the front side.

[0048] The second wiring layer 120, from the inside out, includes a fourth wiring film unit and a fifth wiring film unit.

[0049] The fourth wiring thin film unit includes a fourth metal wiring layer 121 and a fourth passivation layer 122. While achieving interconnection at the bottom layer of the second surface, it can also achieve electrical connection with the first surface through conductive interconnection channels.

[0050] The fifth wiring thin film unit includes a fifth metal wiring layer 123 and a fifth passivation layer 124, and the fifth metal wiring layer may have a chip mounting pad area.

[0051] It should be noted that if the first side is considered the front and the second side the back, then the target thickness of the fifth passivation layer 124, which is the outermost layer on the back, can be set to no more than 7 micrometers. This thickness is suitable for the spin-coating capabilities of existing processes, effectively reducing process difficulty and the risk of defects. Furthermore, because the chip mounting position is moved to the back, with proper wiring design (such as ensuring that RF traces avoid the wiring layer closest to the ground plane), even if the fifth passivation layer is designed to be relatively thin, the RF parasitic parameters will not deteriorate significantly, and electrical performance can still be guaranteed.

[0052] By setting at least two sets of wiring thin film units and using sequentially stacked metal wiring layers and passivation layers of target thickness, high-density signal interconnection can be achieved, while the target thickness can be controlled within the range that can be prepared in a single spin coating. This simplifies the process steps and improves the interlayer uniformity, thereby improving the fabrication yield and performance stability of the redistribution structure.

[0053] Optionally, the second side also includes a pad area.

[0054] The pad area can refer to the exposed metal area on the second wiring structure, used to mount at least one chip.

[0055] For example, let's use the first side as the front and the second side as the back. Please continue to refer to this example. Figure 1d The glass core board 100 has a pad area 106 on the back side.

[0056] Optionally, taking cover bonding as an example of subsequent packaging, a bonding area 108 can be provided on the back side of the glass core board 100. Since the chip and cover bonding area in related technologies are both located on the front side, after completing the back-side redistribution structure, a temporary bonding carrier needs to be transferred from the front side to the back side for support, and then the front side is debonded to expose the pad area. This carrier transfer process is prone to causing the glass core board to crack due to stress concentration. However, this embodiment designs the chip mounting area (pad area) and bonding area entirely on the back side, eliminating the need for front-side debonding and carrier transfer operations, thereby fundamentally eliminating the risk of glass core board cracking caused by this operation. It should be noted that this is only an example of cover bonding packaging and is not intended to limit this application.

[0057] Furthermore, since the chip mounting location has changed from the front to the back, the corresponding routing design strategy also needs to be optimized. In traditional designs, to reduce the parasitic effects of RF traces, the dielectric thickness between specific back-side routing layers (such as the first metal layer) and the reference ground plane layer (such as the second metal layer) needs to be increased (typically greater than 10 micrometers). However, in this back-side mounting design, the reference ground plane is located on the front-side routing layer, naturally creating a greater distance between it and the chip on the back. By using reasonable inter-layer routing planning, critical RF signal traces can avoid the routing layer on the back closest to the ground plane. Therefore, even if the back-side passivation layer thickness is reduced (e.g., less than or equal to 7 micrometers), it can be ensured that RF parasitic parameters will not deteriorate significantly, achieving a balance between structural performance and manufacturability.

[0058] This method of placing the pad area on the second side avoids the risk of chip cracking caused by carrier transfer, maintains good RF performance, and simplifies the packaging process.

[0059] In the above embodiments, a glass core board provides basic support, conductive interconnection channels enable signal communication between the front and back sides, aluminum-based capacitors simplify the process and reduce costs, and first and second rewiring structures enable signal distribution and transmission. Finally, through the coordinated cooperation of various components, the glass substrate structure maintains excellent electrical performance while having a simpler manufacturing process and higher yield.

[0060] This application also provides a method for preparing a glass substrate structure, used to prepare the above-mentioned glass substrate structure, such as... Figure 2a As shown, the method includes the following steps: S210, provides glass core panels.

[0061] The glass core board contains conductive interconnect channels that penetrate the entire glass core board. Specifically, a base glass substrate is first obtained. Then, through-hole conductive interconnect channels are formed within the glass substrate through processing. For example, a low-dielectric-loss glass wafer can be selected and its surface polished to serve as the base glass substrate. Subsequently, through-holes can be formed in the glass wafer using processes such as etching. Next, conductive material is filled into the through-holes using processes such as electroplating or deposition, thereby forming conductive interconnect channels (i.e., glass through-holes) that penetrate the glass. The final glass core board can be obtained by referring to... Figure 2b As shown, multiple conductive interconnect channels are formed therethrough through the glass core plate.

[0062] S220, A parallel plate capacitor and a first wiring structure are formed on the first surface of the glass core plate.

[0063] Among them, the parallel plate capacitor can be an aluminum-based capacitor.

[0064] Specifically, the following method can be used to form a parallel-plate capacitor and a first super-wiring structure on the first surface of a glass core board: First, a deposition process is performed on the first surface to form a parallel-plate capacitor. Then, an additive method is used to form the first super-wiring structure on the first surface.

[0065] For example, please refer to Figure 2c By taking the first side of the glass core as the front side, the aluminum electrode layer and dielectric layer can be deposited separately using plasma-enhanced chemical vapor deposition (PECVD). Then, the deposited layers are lithographically and etched using a patterning process to define the shape and size of the capacitor, ultimately forming an aluminum-based metal-insulator-metal (MIM) capacitor. Compared with the copper-based capacitors commonly used in related technologies, this significantly reduces the complexity and cost of fabrication.

[0066] After forming the parallel plate capacitor, a first layer of wiring structure can be formed using an additive method. Specifically, since the first layer of wiring structure includes at least two sets of wiring thin film units, and each wiring thin film unit includes a metal wiring layer and a passivation layer stacked sequentially, forming the first layer of wiring structure on the first surface using the additive method can include the following steps: First, perform photolithography and electroplating on the first surface to generate a metal wiring layer. Then, perform a single spin coating process on the metal wiring layer to generate a passivation layer.

[0067] For example, taking a first-layer wiring structure comprising three sets of wiring thin-film units as an example, photoresist is first coated on the first surface of the glass core board. The pattern of the metal wiring is defined through exposure and development processes. Then, an electroplating process is used to deposit metal material in the patterned area to form a metal wiring layer. Subsequently, after electroplating, residual photoresist is removed, and a high-dielectric material is uniformly coated onto the surface of the metal wiring layer using a spin-coating device. A passivation layer of the target thickness is formed through a single spin-coating process and curing. Repeating the above steps three times forms three sets of stacked wiring thin-film units. The final structure can be referred to [reference needed]. Figure 2d As shown.

[0068] Photolithography and electroplating are used to generate metal wiring layers, enabling the high-precision formation of complex metal interconnects. Furthermore, the need for multiple coating processes to create passivation layers is eliminated, simplifying the process, shortening production time, and improving the uniformity of passivation layer thickness, thereby enhancing the flatness and electrical performance stability of the circuitry. By first forming aluminum-based capacitors on the first surface of a glass core using a relatively simple deposition process, and then employing an additive method to construct a multi-layer rewiring structure including a thinner passivation layer, high-performance passive devices and high-density interconnects can be integrated into a single unit.

[0069] S230. Thinning treatment is performed on the second side of the glass core board.

[0070] It should be noted that before thinning the second side of the glass core board, a temporary carrier plate needs to be bonded to the first side of the glass core board. For example, a temporary bonding adhesive can be applied to the surface of the glass core board where the first-side structure (parallel plate capacitor and first rewiring structure) has already been formed. Then, a rigid carrier plate is used as the temporary carrier plate, aligned with the bonding adhesive and pressed together. This fixes the carrier plate to the first side of the glass core board via the temporary bonding adhesive, thereby protecting the delicate structure already formed on the first side and providing mechanical support during subsequent back-side processing of the fragile glass core board. The bonded structure can be referred to... Figure 2e As shown in the figure, the blue area is the bonding temporary carrier, while the purple area uniformly filled between the temporary carrier and the first surface of the glass core is the temporary bonding adhesive.

[0071] Then, please refer to Figure 2f The second side of the glass core board can be thinned using a grinding process to a predetermined thickness, exposing the conductive interconnect channels on the back side. The predetermined thickness refers to the final thickness of the glass core board determined based on the requirements of the end product and the properties of the glass material. The design must meet two core conditions: first, it cannot be less than the minimum thickness required to prevent cracking during glass wafer production, ensuring the structural strength of the thinned glass core board; second, it must match the thickness requirements of the finished product to avoid affecting product assembly due to excessive thickness.

[0072] S240, A second wiring structure is formed on the second surface to obtain a glass substrate structure.

[0073] The second wiring structure can be electrically connected to the first wiring structure via conductive interconnect channels. Specifically, the second wiring structure can also be formed using an additive method, employing the same process steps as when forming the first wiring structure. Since the second wiring structure also includes at least two sets of wiring film units, and each set of wiring film units includes sequentially stacked metal wiring layers and passivation layers, photolithography and electroplating can first be performed on the second surface to generate the metal wiring layer. Subsequently, a single spin-coating process is performed on the metal wiring layer to generate the passivation layer.

[0074] For example, taking the second wiring structure comprising two sets of wiring thin film units as an example, please refer to... Figure 2g On the second surface of the glass core board, which has been thinned and exposed to expose conductive interconnect channels, a metal wiring layer is formed sequentially through photolithography and electroplating, followed by a passivation layer formed through a single spin coating. This process is then repeated to form a second set of wiring thin film units, thus completing the construction of the second wiring structure. The metal wiring layer of the second wiring structure is generated through photolithography and electroplating, thereby achieving precise alignment with the conductive interconnect channels and ensuring smooth signal transmission. Simultaneously, it avoids interlayer alignment deviations caused by multiple spin coatings, improving the stability and yield of the rewiring structure.

[0075] In the above embodiments, a glass core board containing conductive interconnect channels is first provided, laying the foundation for signal interconnection on both sides. Subsequently, aluminum-based capacitors are used to replace copper-based capacitors in related technologies, simplifying the fabrication process, reducing costs, and improving structural compatibility. Next, a temporary carrier board is bonded to the first side, and the second side is controllably thinned, providing safe and flat processing conditions for the back-side process. Finally, taking full advantage of the back-side layout, a single spin-coating process is used to further optimize the thickness of the critical passivation layer, significantly improving the fabrication yield of the glass substrate structure while also ensuring the electrical performance and structural stability of the product.

[0076] This application also provides a packaging method for a glass substrate structure, used to package the aforementioned glass substrate structure. The second side of the glass substrate structure further includes a pad area, such as... Figure 3a As shown, the method includes the following steps: S310. When the glass substrate structure is such that the second side faces upward, at least one chip is mounted on the pad area of ​​the second side using a flip-chip bonding process.

[0077] It should be noted that since the chip mounting area is located on the second side of the glass substrate structure, the second side must be placed upwards, i.e., the wafer must be inverted, to directly expose the pad and bonding areas, providing operational space for subsequent chip mounting and glass cover bonding. For example, with the first side as the front, placing the glass substrate structure with the second side upwards represents the wafer inverted configuration. Figure 3b As shown.

[0078] Subsequently, with the glass substrate structure positioned so that the second side faces upwards, a flip-chip bonding process can be employed. For example, copper bumps (uBumps) can be first fabricated at the chip's pin locations. Then, the copper bumps on the chip are precisely aligned and mounted onto the corresponding pads in the second-side bonding pad area. Finally, a reflow soldering process is used to achieve the electrical connection and mechanical fixation between the chip and the glass substrate. The resulting flip-chip bonding structure can be as follows: Figure 3c As shown.

[0079] S320, Form a package on the second surface to complete the encapsulation.

[0080] In this context, the package refers to the protective structural layer formed on top of the chip after it has been mounted, to protect the chip from environmental influences. It serves to cover and protect the chip. Examples of packaging methods include cover bonding (glass or metal) and epoxy resin encapsulation.

[0081] For example, if the encapsulation method is plastic encapsulation, injection molding can be used to encapsulate the chip with plastic, which is then cured to form a plastic encapsulation layer as the encapsulation body. If the encapsulation method is glass cover bonding, a bonding area can also be provided on the second surface to complete the encapsulation. Specifically, the bonding area of ​​the glass cover is first precisely aligned with the bonding area on the second surface of the glass substrate, and appropriate pressure is applied to ensure tight contact. Then, the laser wavelength is adjusted to focus the laser on the glass contact interface, and the laser head is moved to perform a linear scan, heating the glass in a localized area to its melting temperature, thereby achieving bonding between the glass cover and the glass substrate, forming a sealed cavity with high airtightness, for example, a leakage rate better than 1×10⁻¹¹ Pa·m³ / s. The structural state after glass cover bonding can be as follows: Figure 3d As shown.

[0082] The next step requires front-side debonding, which involves removing the temporary carrier and temporary bonding adhesive from the first side of the glass substrate structure to complete the encapsulation. At this point, the substrate can be viewed as follows: Figure 3e As shown.

[0083] Optionally, after packaging is completed, subsequent processes such as wafer-level dicing, electrical testing, and product packaging can be performed to present the final product state for application.

[0084] In the above embodiments, the second side of the glass substrate structure is placed facing upwards, directly exposing the pad area, and the entire encapsulation operation is concentrated on a single plane (the second side). This avoids the high-risk carrier transfer steps and the resulting debonding / rebonding operations in traditional solutions. This simplifies the process flow and fundamentally eliminates the risk of glass core board cracking due to stress concentration. It also avoids residual adhesive and bubble problems related to temporary bonding adhesive, significantly improving the yield, reliability, and production efficiency of the encapsulation.

[0085] It should be understood that although the steps in the flowchart above are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart above may include multiple steps or stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0086] This application also provides an electronic component comprising the glass substrate structure described above.

[0087] For specific limitations on an electronic component, please refer to the limitations on a glass substrate structure mentioned above, which will not be repeated here.

[0088] This application also provides an integrated circuit that includes the above-described electronic components.

[0089] For specific limitations regarding an integrated circuit, please refer to the limitations regarding an electronic component mentioned above, which will not be repeated here.

[0090] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0091] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0092] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. Since they are fundamentally similar to the method embodiments, the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0094] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0095] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A glass substrate structure, characterized in that, include: Glass core board; Conductive interconnect channels penetrating the glass core plate; A parallel plate capacitor and a first rewiring structure are located on the first surface of the glass core plate; wherein, the parallel plate capacitor is an aluminum-based capacitor; A second wiring structure is located on the second side of the glass core board; wherein the second side and the first side are two opposite sides of the glass core board; the second wiring structure is electrically connected to the first wiring structure through the conductive interconnect channel.

2. The glass substrate structure according to claim 1, characterized in that, The second side also includes a pad area; wherein the pad area is used to mount at least one chip.

3. The glass substrate structure according to claim 1, characterized in that, Both the first and second wiring structures include at least two sets of wiring thin film units; wherein each set of wiring thin film units includes a metal wiring layer and a passivation layer of a target thickness stacked sequentially; and the target thickness is no greater than 10 micrometers.

4. A method for preparing a glass substrate structure, characterized in that, The method for preparing the glass substrate structure as described in any one of claims 1 to 3 includes: A glass core board is provided; wherein, a conductive interconnection channel is formed in the glass core board; A parallel plate capacitor and a first rewiring structure are formed on the first surface of the glass core plate; wherein the parallel plate capacitor is an aluminum-based capacitor; The second side of the glass core plate is thinned. A second wiring structure is formed on the second surface to obtain the glass substrate structure; wherein the second wiring structure is electrically connected to the first wiring structure through the conductive interconnect channel.

5. The preparation method according to claim 4, characterized in that, The process of forming a parallel plate capacitor and a first rewiring structure on the first surface of the glass core plate includes: A deposition process is performed on the first surface to form the parallel plate capacitor; The first super-wiring structure is formed on the first surface using an additive method.

6. The preparation method according to claim 5, characterized in that, The first wiring structure includes at least two sets of wiring film units; The wiring thin film unit includes a metal wiring layer and a passivation layer stacked sequentially; The method of forming the first rewiring structure on the first surface using an additive method includes: Photolithography and electroplating are performed on the first surface to generate the metal wiring layer; A single spin coating process is performed on the metal wiring layer to generate a passivation layer.

7. The preparation method according to claim 4, characterized in that, The second rewiring structure includes at least two sets of wiring film units; The wiring thin film unit includes a metal wiring layer and a passivation layer stacked sequentially; the formation of a second wiring structure on the second surface includes: Photolithography and electroplating are performed on the second surface to generate the metal wiring layer; A single spin coating process is performed on the metal wiring layer to generate a passivation layer.

8. A packaging method for a glass substrate structure, characterized in that, For encapsulating a glass substrate structure as described in any one of claims 1 to 3, wherein a second side of the glass substrate structure further includes a pad area, the method comprising: When the glass substrate structure is placed with the second side facing upwards, at least one chip is mounted on the pad area of ​​the second side using a flip-chip bonding process; An encapsulation body is formed on the second surface to complete the encapsulation; wherein the encapsulation body is used to cover and protect the chip.

9. An electronic component, characterized in that, It includes a glass substrate structure as described in any one of claims 1 to 3.

10. An integrated circuit, characterized in that, It includes the electronic components as described in claim 9.

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