Semiconductor device and method of manufacturing the same

Abstract

Provided are a semiconductor device capable of improving reliability and a method for manufacturing the same. According to one embodiment, a semiconductor device includes a semiconductor element (10), a lead frame (20), a package member (30), and a lead terminal (21). The semiconductor element (10) is provided on a first surface of the lead frame (20). The package member (30) is provided on the lead frame (20) and the semiconductor element (10), and has a recessed portion (31). The lead terminal (21) is disposed in the recessed portion (31) and extends in the X direction. The recessed portion (31) has a recessed shape having a first length L1 in the X direction, a second length L2 in the Z direction, and a third length L3 in the Y direction. The third length (L3) of the recessed portion (31) is shorter than the length of the package member (30) in the Y direction.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2024-163660 (filed on September 20, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0004] A semiconductor device is known to include a lead frame on which semiconductor elements are mounted. Summary of the Invention

[0005] A semiconductor device with improved reliability and a method for manufacturing the same are provided.

[0006] A semiconductor device according to an embodiment includes: a semiconductor element disposed on a first surface of a lead frame; a package component disposed on the lead frame and the semiconductor element, having a first recess; and a first terminal disposed within the first recess and extending in a first direction parallel to the first surface of the lead frame. The first recess has a recessed shape having a first length in the first direction, a second length in a second direction perpendicular to the first surface of the lead frame, and a third length in a third direction perpendicular to both the first and second directions. The third length is shorter than the third-direction length of the package component.

[0007] The method for manufacturing a semiconductor device according to the embodiment includes the following steps: preparing a leadframe substrate including terminals having recessed shapes; clamping the leadframe substrate using a mold such that a protruding guide provided in the mold is disposed in the recessed shape; filling the mold with the material of the encapsulation component, curing the material, forming the encapsulation component on the leadframe substrate, and providing a recessed portion including the recessed shape on the encapsulation component; and cutting the recessed shape of the leadframe substrate and the recessed portion of the encapsulation component by dicing to form a semiconductor device having the terminals including a portion of the recessed shape and the encapsulation component including a portion of the recessed portion. Attached Figure Description

[0008] Figure 1 This is a perspective view of the semiconductor device according to the embodiment, viewed from the top surface side.

[0009] Figure 2 This is a perspective view of the semiconductor device according to the embodiment, viewed from the lower surface side.

[0010] Figure 3 This is a top view of the semiconductor device of the embodiment viewed through the packaging components from the top surface side.

[0011] Figure 4 This is a cross-sectional view of the semiconductor device according to the embodiment.

[0012] Figure 5 This is an enlarged perspective view of the lead terminals and recesses of the semiconductor device in the embodiment.

[0013] Figure 6 This is a perspective view of the main substrate on which the semiconductor device of the embodiment is mounted, viewed from the top surface side.

[0014] Figure 7 This is a cross-sectional view of a semiconductor device mounted on a main substrate according to an embodiment.

[0015] Figure 8 This is an enlarged cross-sectional view of the lead terminals and recesses of the semiconductor device in the embodiment.

[0016] Figure 9 This is a flowchart illustrating the main steps in a method for manufacturing a semiconductor device according to an embodiment.

[0017] Figures 10-18 This is a diagram illustrating the steps in a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0018] The embodiments will be described with reference to the accompanying drawings. In the following description, constituent elements having the same function and structure are labeled with the same reference numerals. Furthermore, the embodiments shown below are intended to illustrate apparatuses and methods for embodying the technical concept of these embodiments, and do not necessarily define the materials, shapes, structures, and arrangements of the constituent parts as described below.

[0019] The following describes the semiconductor device and the method for manufacturing the semiconductor device according to the embodiments.

[0020] 1. Structure of semiconductor devices

[0021] Reference Figures 1 to 4 An example of the structure of the semiconductor device 1 according to the embodiment will be described. The semiconductor device 1 has semiconductor elements, lead frames and bonding wires, and has a packaging structure that holds or seals them by packaging components.

[0022] Figure 1 and Figure 2 This is a perspective view showing the external shape of the semiconductor device 1 according to the embodiment. Figure 1 The structure of semiconductor device 1 as viewed from the top surface side is shown. Figure 2The structure of the semiconductor device 1 as viewed from the lower surface side is shown. The lower surface of the semiconductor device 1 is the surface where the terminals of the lead frame are exposed, and it is the surface on which the semiconductor device 1 is mounted to the main substrate, i.e., the mounting surface of the semiconductor device 1.

[0023] Furthermore, in the following description, an XYZ orthogonal coordinate system is used. The X direction is parallel to the surface of the lead frame and corresponds to the direction in which the lead frame extends. The Y direction corresponds to the direction in which the lead terminals are arranged. The Z direction corresponds to the direction perpendicular to the surface of the lead frame, i.e., the up-down direction. Additionally, the term "up" and its related terms indicate a larger coordinate position on the Z-axis, while the term "down" and its related terms indicate a smaller coordinate position on the Z-axis.

[0024] Figure 3 This is a top view showing the structure of the semiconductor device 1 according to the embodiment. Figure 3 It shows in Figure 1 The structure of semiconductor device 1 can be observed from the top surface through the packaging components. Figure 4 This is a cross-sectional view showing the structure of the semiconductor device 1 according to the embodiment. Figure 4 It shows Figure 3 Cross-sectional structure of semiconductor device 1 along line IV-IV.

[0025] The semiconductor device 1 includes a semiconductor element 10, a lead frame 20, a package component 30, and a bonding wire 40.

[0026] like Figure 3 and Figure 4 As shown, the semiconductor element 10 is disposed on the lead frame 20 within the package component 30.

[0027] In the case where the semiconductor device 1 is a discrete device, the semiconductor element 10 is a field-effect transistor (e.g., a MOS field-effect transistor), a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor), or a diode. As a specific example, the semiconductor element 10 may also be a small-signal transistor for signal processing control or a power transistor for current and voltage control (e.g., a high-voltage transistor, a high-voltage transistor). The following explanation uses the case where the semiconductor element 10 is a field-effect transistor as an example.

[0028] Semiconductor element 10 is, for example, a semiconductor chip (or bare die, bare wafer). Semiconductor element 10 includes element portion 11 and multiple pads (or nodes, terminals) 12, 13, 14.

[0029] The component section 11 includes a semiconductor layer on which field-effect transistors are formed. The semiconductor layer is, for example, silicon, silicon carbide, silicon germanium, gallium nitride, or gallium arsenide.

[0030] Pads 12 and 13 are disposed on the upper surface of the component section 11. Pad 12 is connected to the gate of the field-effect transistor. Pad 13 is connected to the source of the field-effect transistor. Hereinafter, pad 12 will be referred to as gate pad 12, and pad 13 will be referred to as source pad 13.

[0031] Pad 14 is provided on the lower surface of component section 11. Pad 14 is connected to the drain of field-effect transistor. Hereinafter, pad 14 will be referred to as drain pad 14.

[0032] Furthermore, depending on the internal structure of the component section 11, pad 14 can be used as a source pad, and pad 13 can be used as a drain pad. Pads 12, 13, and 14 may contain metal layers such as aluminum or copper.

[0033] An encapsulation component (or sealing component, resin body, molding resin, encapsulating resin) 30 is disposed on the semiconductor element 10 and the lead frame 20. The encapsulation component 30 covers the semiconductor element 10 mounted on the lead frame 20, sealing the semiconductor element 10 and the bonding wires 40. The encapsulation component 30 is also disposed on the upper surface and the lower surface of the lead frame 20. The encapsulation component 30 includes an insulator, such as an insulating resin or ceramic, or polyimide.

[0034] The leadframe 20 includes multiple lead terminals (or external leads) 21 (including 21a, 21b, 21c, 21d, 21e, 21f), chip pads 22, bonding pads (or internal leads) 23, and multiple connectors 102 (including 102a, 102b, 102c, 102d, 102e). The leadframe 20 may contain copper. Hereinafter, when referred to as lead terminals 21, they will be referred to as lead terminals 21a, 21b, 21c, 21d, 21e, and 21f. Similarly, when referred to as connectors 102, they will be referred to as connectors 102a, 102b, 102c, 102d, and 102e.

[0035] The lead terminal 21, chip pad 22, and bonding pad 23 have portions exposed from the package component 30. That is, a portion of each of the lead terminal 21, chip pad 22, and bonding pad 23 is exposed from the package component 30 on the lower surface or side of the semiconductor device 1. The portions of the lead terminal 21, chip pad 22, and bonding pad 23 exposed from the package component 30 function as external connection terminals for external connection.

[0036] Chip pad 22 is adjacent to bonding pad 23 in the Y direction. Chip pad 22 serves as an external connection terminal as described above, and functions as a mounting portion on which semiconductor element 10 is to be placed.

[0037] Semiconductor element 10 is mounted on the upper surface of chip pad 22. The drain pad 14 of semiconductor element 10 is electrically connected to chip pad 22, for example, via a conductive component 41 formed by curing conductive paste.

[0038] Bonding lines 40 (including 40a and 40b) electrically connect the semiconductor element 10 to the lead terminal 21f and the bonding pad 23. Bonding line 40a is bonded between the gate pad 12 of the semiconductor element 10 and the lead terminal 21f. The gate pad 12 is electrically connected to the lead terminal 21f via bonding line 40a. Bonding line 40b is bonded between the source pad 13 of the semiconductor element 10 and the bonding pad 23. The source pad 13 is electrically connected to the bonding pad 23 via bonding line 40b.

[0039] Lead terminals 21a, 21b, and 21c are disposed at one end of the semiconductor device 1 in the X direction. Lead terminals 21a and 21b are disposed at one end of the chip pad 22 in the X direction. Lead terminals 21a and 21b are connected to the chip pad 22 via connecting portions 102a and 102b, respectively.

[0040] Lead terminal 21c is disposed at one end of bonding pad 23 in the X direction. Lead terminal 21c is connected to bonding pad 23 via connector 102c. Lead terminal 21c is electrically insulated from chip pad 22 and leads 21a, 21b, 21d, 21e, and 21f.

[0041] Lead terminals 21d, 21e, and 21f are disposed on the other end side of the semiconductor device 1 in the X direction. Lead terminals 21d and 21e are disposed on the other end side of the chip pad 22 in the X direction. Lead terminals 21d and 21e are connected to the chip pad 22 via connecting portions 102d and 102e, respectively.

[0042] Lead terminal 21f is disposed on the other end of bonding pad 23 in the X direction. Lead terminal 21f is electrically insulated from chip pad 22, bonding pad 23, and lead terminals 21a, 21b, 21c, 21d, and 21e.

[0043] Lead terminals 21a, 21b, 21d, and 21e are electrically connected to the drain pad 14 disposed on the lower surface of the semiconductor element 10 via connecting portions 102a, 102b, 102d, 102e, chip pad 22, and conductive component 41. Lead terminal 21c is electrically connected to the source pad 13 disposed on the upper surface of the semiconductor element 10 via connecting portion 102c, bonding pad 23, and bonding wire 40b. Lead terminal 21f is electrically connected to the gate pad 12 disposed on the upper surface of the semiconductor element 10 via bonding wire 40a.

[0044] For example, a plating layer 42 is provided on the portions of the chip pads 22, bonding pads 23, and lead terminals 21 that are exposed from the package component 30. In addition, the connector 102 is covered by the package component 30 in a manner that does not expose it from the package component 30.

[0045] The chip pads 22, bonding pads 23, lead terminals 21, and connectors 102 included in the lead frame 20 may contain metals such as copper or aluminum. The plating 42 may contain metals such as tin or copper.

[0046] like Figures 1 to 4 As shown, in the semiconductor device 1, the lead terminal 21 has a wettable flange (WF) structure. In the semiconductor device 1 of this embodiment, recesses (or grooves) 31a, 31b, 31c, 31d, 31e, and 31f are respectively provided in the portions where the lead terminals 21a, 21b, 21c, 21d, 21e, and 21f are disposed. Hereinafter, when referred to as recess 31, recesses 31a, 31b, 31c, 31d, 31e, and 31f are referred to respectively.

[0047] The following is for reference Figure 5 The recess 31 in the semiconductor device 1, which is provided with lead terminals 21, will be described. The recesses 31a, 31b, 31c, 31d, 31e, and 31f each have the same structure. Figure 5 This is an enlarged view of the recess 31 of the semiconductor device 1, which is equipped with lead terminals 21. Figure 5 This is a perspective view of the recess 31 viewed from the lower surface 30a side of the encapsulation component 30.

[0048] A recess 31 is provided in the portion of the encapsulation component 30 where the lead terminals 21 are disposed. The encapsulation component 30 has a lower surface 30a, an upper surface 30b, and a side surface 30c located between the lower surface 30a and the upper surface 30b, which are disposed on the lower surface side of the lead frame 20 opposite to the upper surface of the lead frame 20. The recess 31 is disposed at the intersection of the lower surface 30a and the side surface 30c of the encapsulation component 30.

[0049] The recess 31 is recessed by a distance L1 along the X direction from the side surface 30c of the package member 30 (or semiconductor device 1), and by a distance L2 along the Z direction from the lower surface 30a of the package member 30. The length (or width) of the recess 31 in the Y direction is L3. The length L3 of the recess 31 in the Y direction is shorter than the length of the package member 30 in the Y direction.

[0050] In other words, the recess 31 of the package component 30 has a shape with a recess length L1 in the X direction, a recess length L2 in the Z direction, and a recess length L3 in the Y direction in the area where the lead terminal 21 is disposed. The recess 31 is a recess with a length L1 in the X direction, a length L2 in the Z direction, and a length L3 in the Y direction at the corner of the lower surface 30a and the side surface 30c of the package component 30.

[0051] The lead terminal 21 has a shape that extends in the X direction along the lower surface 30a of the package member 30, bends along the inner surface of the recess 31, i.e., the side surface S1 and the bottom surface S2, and is further disposed along the side surface 30c of the package member 30. That is, the lead terminal 21 has a surface along the lower surface 30a of the package member 30, a surface along the side surface S1 inside the recess 31, a surface along the bottom surface S2, and a surface along the side surface 30c of the package member 30.

[0052] The length (or thickness) of the lead terminal 21 exposed from the side 30c of the package component 30 in the Z direction is set to L5, and the length (or width) of the lead terminal 21 in the Y direction is set to L6. Therefore, L5 is longer than L2, and L2 is longer than L1. That is, L5 > L2 > L1. Furthermore, the length L3 of the recessed portion 31 in the Y direction is longer than the length L6 of the lead terminal 21 in the Y direction. That is, L3 > L6.

[0053] In addition, such as Figure 2 and Figure 3 As shown, among the plurality of recesses 31 (or lead terminals 21) arranged along the Y direction, the distance between the centers of two adjacent recesses 31 (or lead terminals 21) is set as L4. Therefore, the length L3 of the recess 31 in the Y direction is shorter than the distance L4. That is, L3 < L4 holds true.

[0054] 2. Installation example of a semiconductor device

[0055] Next, refer to Figure 6 An example of mounting the semiconductor device 1 of the embodiment on the main substrate will be described. Figure 6 This is a perspective view of the main substrate on which the semiconductor device 1 is mounted, viewed from the upper surface side of the semiconductor device 1. Figure 6 The main substrate shown may exist as a device or be configured within an electrical device.

[0056] Semiconductor device 1 is disposed on the surface (hereinafter also referred to as the mounting surface) of main substrate (or motherboard, printed wiring substrate) 50. In addition, one or more other devices, such as other semiconductor devices 61 or electronic components 62, are disposed on the surface of main substrate 50.

[0057] The main substrate 50 includes a plurality of wirings 71, 72, and 73 and a plurality of terminals (e.g., connectors, sockets, or slots) 74 and 75. The wirings 71, 72, and 73 are disposed on the surface of the main substrate 50 or inside the main substrate 50. The wirings 71, 72, and 73 are respectively connected to one or more corresponding terminals among the plurality of terminals 74 and 75, or to at least one of the semiconductor devices 1, 61, and 62 on the main substrate 50. Various voltages (e.g., power supply voltage VDD or ground voltage GND) or corresponding signals are supplied to the terminals 74 and 75 respectively.

[0058] Semiconductor device 1 is connected to a plurality of wirings 71, 72 on the main substrate 50. For example, semiconductor device 1 is connected to terminal 74 via wiring 71 and to semiconductor device 61 (or electronic component 62) via wiring 72.

[0059] Semiconductor device 61 may include, for example, semiconductor integrated circuits or discrete devices. Semiconductor device 61 may also be a device modularly composed of multiple semiconductor chips and multiple passive components. Electronic component 62 may be, for example, passive components such as capacitors, inductors, resistors, and switches.

[0060] Semiconductor device 61 and electronic component 62 are connected to terminal 75 via wiring 73 and interconnected via other wiring.

[0061] Next, refer to Figure 7 and Figure 8 The lead terminals 21 and recesses 31 of the semiconductor device 1 mounted on the main substrate 50 will be described in detail. Figure 7 This is a cross-sectional view of the semiconductor device 1 mounted on the main substrate 50. Figure 7 It shows Figure 6 A cross-section of semiconductor device 1 along line VII-VII (i.e., the XZ plane). Figure 8 yes Figure 7 The enlarged view of the lead terminal 21 and the recess 31 in the cross-section shown. Since the lead terminals 21a to 21f and the recesses 31a to 31f have the same structure, therefore... Figure 8 The intermediate processing consists of lead terminal 21 and recessed portion 31.

[0062] like Figure 7 As shown, the chip pads 22 of the leadframe 20 are disposed on the pads (e.g., wiring or terminals) 51 of the main substrate 50 via conductive components 81. Thus, the chip pads 22 are electrically connected to the pads 51 of the main substrate 50 via plating 42 and conductive components 81. The pads 51 are disposed on the mounting surface of the main substrate 50. The conductive components 81, for example, contain solder. The pads 51, for example, contain copper or aluminum.

[0063] like Figure 8As shown, lead terminals 21 of semiconductor device 1 are disposed on pads (e.g., wiring or terminals) 52 of the main substrate 50 via conductive members 82. The conductive members 82 are disposed between the lead terminals 21 and the pads 52. Since the lead terminals 21 have a WF (wireless-finish) structure, the conductive members 82 are also disposed on the lower surface of the lead terminals 21 and the surface of the lead terminals 21 within the recess 31. This conductive member 82 is also referred to as a solder foot. The solder foot 82 contacts the lead terminals 21 and the pads 52, electrically connecting the lead terminals 21 and the pads 52. The conductive member (or solder foot) 82 may contain solder, for example. The pads 52 are disposed on the mounting surface of the main substrate 50. The pads 52 may contain copper or aluminum, for example.

[0064] In detail, the lead terminal 21 has a terminal surface 21aa exposed in the recess 31, a terminal surface 21ab exposed on the lower surface 30a of the package member 30, and a terminal surface 21ac exposed on the side surface 30c of the package member 30. In other words, the surface of the lead terminal is arranged along the lower surface 30a of the package member 30, the inner surface in the recess 31, and the side surface 30c of the package member 30. The terminal surfaces 21aa and 21ab of the lead terminal 21 are electrically connected to the pads 52 of the main substrate 50 via the plating layer 42 and the solder pads 82. Furthermore, as described later, the terminal surface 21ac of the lead terminal 21 is the surface exposed after the lead frame substrate 120 is cut by scribing. Therefore, the plating layer 42 is not provided on the terminal surface 21ac, but an oxide layer (not shown) is formed. Therefore, in most cases, the solder pads 82 are not provided on the terminal surface 21ac of the lead terminal 21.

[0065] The semiconductor device 1 described above has a recess 31 on the side of the package component 30, and has lead terminals 21 arranged along the inner surface (or side and bottom surface) of the recess 31. When such a semiconductor device 1 is mounted on a main substrate 50, solder pads 82 enter the recess 31 to electrically connect the lead terminals 21 to the pads 52.

[0066] Since the solder pads 82 are formed into the recesses 31, their shape and size can be formed to a specified shape and size. Therefore, the mounting strength of the solder pads 82 formed in the plurality of recesses 31 of the semiconductor device 1 can be improved, and the deviation in mounting strength can be reduced, thereby stabilizing the electrical connection between the lead terminal 21 and the pad 52. This improves the reliability of the semiconductor device 1 during installation.

[0067] 3. Manufacturing methods for semiconductor devices

[0068] Next, refer to Figures 9 to 18 The manufacturing method of the semiconductor device 1 according to the embodiment will be described. Figure 9 This is a flowchart illustrating the main processes in the manufacturing method of semiconductor device 1. Figures 10 to 18 This is a diagram showing the steps in the manufacturing method of semiconductor device 1. Figure 10 and Figure 11 This is a plan view taken from the lower surface of the lead frame substrate. Figure 12 and Figure 18 It is along Figure 11 A cross-sectional view with the upper surface of the semiconductor element 10 facing upwards, along the XII-XII line. Figures 13 to 17 It is along Figure 11 A cross-sectional view with the lower surface of semiconductor element 10 facing upwards, along line XIII-XIII.

[0069] First, such as Figure 10 As shown, a leadframe substrate 100 is prepared, which includes a terminal (S1) having a portion (or recess shape) 131 corresponding to the recess 31. The leadframe substrate 100 is formed by connecting a plurality of leadframes 20 corresponding to a plurality of semiconductor devices 1. In the region 101 of the leadframe substrate 100 corresponding to a semiconductor device 1, there is a portion 131 corresponding to the recess 31, a portion 121 corresponding to the lead terminal 21, a portion 122 corresponding to the chip pad 22, a portion 123 corresponding to the bonding pad 23, a connecting portion 102 connecting the chip pad 22 to the lead terminal 21, and a connecting portion 102 connecting the bonding pad 23 to the lead terminal 21.

[0070] The portion 131 of the lead frame substrate 100 corresponding to the recess 31 has a shape that is recessed in the Z direction. The portion 131 is formed, for example, by using a die-cutting process (or stamping process). The lead frame substrate 100 contains, for example, copper (or aluminum).

[0071] Subsequently, to simplify the accompanying drawings, such as Figure 11 As shown, a manufacturing method is illustrated using a lead frame substrate 120 containing a region 101 corresponding to a semiconductor device 1.

[0072] Next, as Figure 12 As shown, a semiconductor element 10 is mounted on the lead frame substrate 120 via a conductive member 41 (S2). Next, a bonding wire 40a is joined between the gate pad 12 of the semiconductor element 10 and the portion 121 corresponding to the lead terminal. Furthermore, a bonding wire 40b (not shown) is joined between the source pad 13 of the semiconductor element 10 and the portion 123 corresponding to the bonding pad (S3). Thus, the gate pad 12 of the semiconductor element 10 and the portion 121 corresponding to the lead terminal are electrically connected via the bonding wire 40a. Furthermore, the source pad 13 of the semiconductor element 10 and the portion 123 corresponding to the bonding pad are electrically connected via the bonding wire 40b.

[0073] Next, as Figure 13 , Figure 14 and Figure 15 As shown, a package component 30 (S4) is formed on a portion of the upper and lower surfaces of the lead frame substrate 120, on which semiconductor elements 10 and bonding lines 40a and 40b are disposed. Specifically, as... Figure 13 and Figure 14 As shown, firstly, the lead frame substrate 120 is clamped by the lower mold 201 and the upper mold 202. At this time, the protruding guide 202a provided on the upper mold 202 is positioned in the portion 131 of the lead frame substrate 120 corresponding to the recess 31. Next, resin is filled into the space between the lower mold 201 and the upper mold 202, that is, the space between the upper surface of the lead frame substrate 120 and the lower mold 201, and the space between the lower surface of the lead frame substrate 120 and the upper mold 202, and the substrate is shaped.

[0074] Therefore, as Figure 15 As shown, a package component 30 is formed on the upper surface of the lead frame substrate 120, on the semiconductor element 10, and on a portion of the lower surface of the lead frame substrate 120. At this time, a recess including portion 131 is provided in the package component 30. The semiconductor element 10, bonding wires 40a and 40b on the lead frame substrate 120 are sealed by the package component 30.

[0075] In the lead frame substrate 120, the surfaces of the portion 131 corresponding to the recess 31, the portion 121 corresponding to the lead terminal 21, the portion 122 corresponding to the chip pad 22, and the portion 123 corresponding to the bonding pad 23 are exposed from the package component 30. Furthermore, during the formation process of the package component 30, thin burrs made of the package component material are formed on the side of the portion 131 corresponding to the recess 31. These thin burrs are removed, for example, by laser irradiation and honing processes.

[0076] Next, as Figure 16 As shown, the portions 131, 121, 122, and 123 of the leadframe substrate 120 exposed from the package component 30 are externally plated (S5). Specifically, for example, an electroplating method is used to form a plating layer 42 on the portions 131 corresponding to the recess 31, 121 corresponding to the lead terminal 21, 122 corresponding to the chip pad 22, and 123 corresponding to the bonding pad 23 exposed from the package component 30. The plating layer 42 contains, for example, tin or solder.

[0077] After that, as Figure 17 As shown, the lead frame substrate 120 and the packaging component 30 are completely cut by dicing. This monolithizes the lead frame substrate 120, resulting in... Figure 18The semiconductor device 1 shown is described in step S6. Specifically, a dicing blade 203 is used to cut the central portion of the lead frame substrate 120 portion 131 and the central portion of the package member 30 corresponding to the recessed portion 31. This forms a semiconductor device 1 having a lead terminal 21 including a portion of the 131 and a package member 30 including the recessed portion 31. The manufacturing process of the semiconductor device 1 is then complete.

[0078] Then, for example, through a reflow soldering process, such as Figure 6 As shown, semiconductor device 1 is mounted on main substrate 50. Solder feet 82 are formed on the side of semiconductor device 1. Solder feet 82 fix semiconductor device 1 to main substrate 50 and electrically connect the lead terminals 21 of semiconductor device 1 to the pads 52 of main substrate 50.

[0079] Furthermore, various inspections, such as Automated Optical Inspection (AOI), are then performed on the semiconductor device 1 on the main substrate 50 using a testing device. For example, the shape of the solder pads 82 formed on the lead terminals 21 is inspected using AOI. This determines whether the bonding condition between the semiconductor device 1 and the main substrate 50 is good.

[0080] After various inspections, the main substrate 50 on which the semiconductor device 1 of the embodiment is mounted, or the device containing the semiconductor device 1 of the embodiment, is shipped to the market or to a user.

[0081] As explained above, in this embodiment, the central portion of the portion 131 corresponding to the recess 31 on the lead frame substrate 120 is cut by the dicing blade 203. Therefore, the side surface of the lead terminal 21 within the recess 31 is less susceptible to adverse effects caused by wear of the dicing blade 203. Thus, when mounting the semiconductor device 1, the shape of the solder pad 82 formed on the lead terminal 21 within the recess 31 can be stabilized.

[0082] In addition, when the semiconductor device 1 is installed, the conductive component that becomes the solder pad 82 enters into the recess 31 provided on the side of the package component 30, so that the solder pad 82 with stable shape and size can be formed.

[0083] Therefore, when mounting the semiconductor device 1 onto the main substrate 50, the mounting strength of the solder pads 82 can be improved and the deviation of the mounting strength can be reduced, thereby stabilizing the electrical connection between the lead terminal 21 and the pad 52. As a result, the reliability of the semiconductor device 1 during mounting can be improved.

[0084] Furthermore, in this embodiment, as described above, the shape and size of the solder pads 82 formed on the lead terminal 21 can be stabilized. Therefore, the mounting status of the semiconductor device 1 can be easily inspected by AOI. Consequently, the accuracy of mounting status inspection can be improved in the semiconductor device 1 of this embodiment. Therefore, the reliability of the main substrate 50 or the device including the semiconductor device 1 of this embodiment can be improved.

[0085] Furthermore, during the dicing and cutting of the lead frame substrate and the package component, delamination may occur between the lead terminals and the package component in some cases. In the semiconductor device 1 of the embodiment, on the cutting surface during dicing and cutting, a lead terminal protruding in the Z direction is provided in the portion 131 corresponding to the recess 31. That is, the lead terminal 21 provided in the portion 131 corresponding to the recess 31 is formed in a protruding shape, so the stress generated during dicing and cutting is mitigated by the protruding lead terminal. Therefore, delamination between the lead terminal 21 and the package component 30 can be reduced. As a result, the reduction of moisture resistance of the semiconductor device 1 can be prevented, and the reliability of the semiconductor device 1 can be improved.

[0086] As described above, the semiconductor device 1 and its manufacturing method according to the embodiment can improve the reliability of the semiconductor device 1 during mounting to the main substrate. Furthermore, the reliability of the semiconductor device 1 can be improved.

[0087] 4. Other

[0088] In the above embodiments, the case where the semiconductor device 1 is a field-effect transistor has been described as an example, but the semiconductor device 1 may also be a semiconductor integrated circuit, an image sensor, an optical device, or a storage device.

[0089] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor element is disposed on the first surface of the lead frame; The packaging component, disposed on the lead frame and the semiconductor element, has a first recess; and The first terminal is disposed in the first recess and extends in a first direction parallel to the first surface of the lead frame; The first recess has a recessed shape having a first length in the first direction, a second length in a second direction perpendicular to the first surface of the lead frame, and a third length in a third direction perpendicular to both the first and second directions. The third length is shorter than the third upward length of the encapsulation component.

2. The semiconductor device according to claim 1, characterized in that, The encapsulation component has: a lower surface disposed on a second side opposite to the first surface of the lead frame; an upper surface opposite to the lower surface; and a side surface located between the lower surface and the upper surface; The first recess is disposed at the portion where the lower surface of the encapsulation component intersects with the side surface.

3. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a second terminal extending along the first direction. The encapsulation component has a second recess disposed adjacent to the first recess along the third direction. The second terminal is disposed within the second recess. If the first length of the first recess is set to L1, the second length of the first recess is set to L2, the third length of the first recess is set to L3, and the distance between the center of the first recess and the center of the second recess is set to L4... Then L4 > L3 > L2 > L1 holds true.

4. The semiconductor device according to claim 1, characterized in that, The first terminal is configured to bend along the inner surface of the first recess.

5. The semiconductor device according to claim 1, characterized in that, The encapsulation component has: a lower surface disposed on a second side opposite to the first surface of the lead frame; an upper surface opposite to the lower surface; and a side surface located between the lower surface and the upper surface; The first terminal has a first terminal surface exposed from the inner surface within the first recess and a second terminal surface exposed from the side surface of the encapsulation component. The length of the second terminal face in the second direction is longer than the length of the first terminal face in the second direction, and the length of the first terminal face in the second direction is longer than the length of the first terminal face in the first direction.

6. The semiconductor device according to claim 1, characterized in that, The encapsulation component has: a lower surface disposed on a second side opposite to the first surface of the lead frame; an upper surface opposite to the lower surface; and a side surface located between the lower surface and the upper surface; The first terminal has a first terminal face exposed from the inner surface within the first recess and a second terminal face exposed from the lower surface of the encapsulation component.

7. The semiconductor device according to claim 6, characterized in that, The first terminal has a plating layer disposed on the first terminal surface and the second terminal surface.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a line connecting the semiconductor element to the first terminal.

9. A method for manufacturing a semiconductor device, characterized in that, The following steps are required: Prepare a lead frame substrate containing terminals with recessed shapes, and clamp the lead frame substrate using a mold such that protruding guides provided in the mold are configured in the recessed shapes. The encapsulation component material is filled into the mold, the material is cured, the encapsulation component is formed on the lead frame substrate, and a first recess including the recessed shape is provided on the encapsulation component; as well as A semiconductor device having a terminal including a portion of the recessed shape and a portion of the first recessed portion is formed by slicing the recessed shape of the lead frame substrate and cutting the first recessed portion of the package component.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The method for manufacturing the semiconductor device further includes the step of forming the recessed shape on the lead frame substrate before forming the package component.

11. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The method for manufacturing the semiconductor device further includes the step of forming a plating layer on the recessed shape and the terminals exposed from the package component after the package component is formed and before cutting by the dicing.

12. The method for manufacturing a semiconductor device according to claim 9, characterized in that, It also includes the following steps: Semiconductor elements are mounted on the lead frame substrate prior to forming the packaged component; and A bonding wire is formed between the semiconductor element and the terminal of the lead frame substrate.

13. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The semiconductor device includes the semiconductor device of claim 1.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The encapsulation component has: a lower surface disposed on a second side opposite to the first surface of the lead frame; an upper surface opposite to the lower surface; and a side surface located between the lower surface and the upper surface; The first recess is disposed at the portion where the lower surface of the encapsulation component intersects with the side surface.

15. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The semiconductor device has a second terminal extending along the first direction. The encapsulation component has a second recess disposed adjacent to the first recess along the third direction. The second terminal is disposed within the second recess. If the first length of the first recess is set to L1, the second length of the first recess is set to L2, the third length of the first recess is set to L3, and the distance between the center of the first recess and the center of the second recess is set to L4... Then L4 > L3 > L2 > L1 holds true.

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