Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first carrier, an encapsulant, a second carrier, and one or more supports. The first carrier has a first surface and a first side connected to the first surface. The encapsulant is on the first surface of the first carrier, and the first side of the first carrier is exposed from the encapsulant. The second carrier is disposed over the first carrier. The one or more supports are spaced apart from the first side of the first carrier and connected between the first carrier and the second carrier. The one or more supports are asymmetrically arranged with respect to a geographic center of the first carrier. The one or more supports are fully sealed in the encapsulant.

Description

[0001] This application is a divisional application of the application for patent application No. 202010249365.3, filed on April 1, 2020, entitled “Semiconductor device package and method of manufacturing the same”. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor device package, and in particular, to a semiconductor device package containing at least one support or free of any support and a method of manufacturing the same. BACKGROUND

[0003] To cater to the trend of miniaturization and increased functionality, semiconductor device packages can integrate multiple electronic devices on different substrates within the package through multi-faceted stacking (3D stacking), where the upper and lower substrates are interconnected through supports or interposers. However, the supports occupy certain areas of the substrates, which can impose considerable constraints on the areas available on the substrates of the semiconductor device package for electronic components.

[0004] In view of the above, it is desirable to design a semiconductor device package with a limited number of supports while maintaining the stability of the semiconductor device package. SUMMARY

[0005] According to some embodiments of the present disclosure, a semiconductor device package is provided. The semiconductor device package contains a first carrier, an encapsulant, a second carrier, and one or more supports. The first carrier has a first surface and a first side surface connected to the first surface. The encapsulant is located on the first surface of the first carrier, and the first side surface of the first carrier is exposed from the encapsulant. The second carrier is disposed on the first carrier. The one or more supports are spaced apart from the first side surface of the first carrier and connected between the first carrier and the second carrier. The one or more supports are asymmetrically arranged with respect to a geometric center of the first carrier. The one or more supports are completely sealed in the encapsulant.

[0006] According to some embodiments of the present disclosure, a semiconductor device package is provided. The semiconductor device package contains a first carrier, a second carrier, and an encapsulant. The first carrier has a first surface, a first side surface connected to the first surface, and a second side surface connected to the first surface. The second carrier is disposed on the first carrier. The encapsulant is located between the first carrier and the second carrier and covers the first surface of the first carrier. Each of the first side surface and the second side surface of the first carrier is exposed from the encapsulant. The encapsulant is free of supports.

[0007] According to some embodiments of the disclosure, a method of manufacturing a semiconductor device package is provided. The method includes providing a first carrier having a first surface, the first carrier including a first sub-carrier and a second sub-carrier that are separable from each other along a scribe line; and providing a support on the first surface of the first carrier, the support being spaced apart from the scribe line and being asymmetrically arranged relative to a geometric center of each of the first sub-carrier and the second sub-carrier from a perspective of a sub-carrier. BRIEF DESCRIPTION OF DRAWINGS

[0008] Aspects of the disclosure can be more readily understood, when considered in connection with the following detailed description and by reference to the following drawings, in which:

[0009] Figure 1A A cross-sectional view of a semiconductor device package according to an embodiment of the disclosure is shown.

[0010] Figure 1B A left side view of a semiconductor device package in Figure 1A is shown.

[0011] Figure 1C A right side view of a semiconductor device package in Figure 1A is shown.

[0012] Figure 2 A cross-sectional view of a semiconductor device package according to another embodiment of the disclosure is shown.

[0013] Figure 3 A cross-sectional view of a semiconductor device package according to yet another embodiment of the disclosure is shown.

[0014] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E A method for manufacturing a semiconductor device package according to some embodiments of the disclosure is shown.

[0015] Figure 5 A perspective view of a semiconductor device stack according to an embodiment of the disclosure is shown.

[0016] Figure 6 A perspective view of a semiconductor device stack according to another embodiment of the disclosure is shown.

[0017] Figure 7 A perspective view of a semiconductor device stack according to yet another embodiment of the disclosure is shown.

[0018] Figure 8AA perspective view of a semiconductor device stack according to still another embodiment of the disclosure is shown.

[0019] Figure 8B A perspective view of a semiconductor device stack according to yet still another embodiment of the disclosure is shown.

[0020] Figure 8C A perspective view of a semiconductor device stack according to still yet another embodiment of the disclosure is shown.

[0021] Figure 8D A perspective view of a semiconductor device stack according to some embodiments of the disclosure is shown. DETAILED DESCRIPTION

[0022] The present disclosure provides a semiconductor device package and a method of manufacturing the same. Embodiments of the semiconductor device package enable a thin package with reduced thickness. Further, the semiconductor device package of the present disclosure can reduce the number of support members and thus reduce the space that the support members would occupy in some existing methods. Accordingly, the semiconductor device package of the present disclosure can accommodate more electronic components while maintaining the stability of the package structure. Further, the semiconductor device package of the present disclosure can be free of any support members. The support members of the semiconductor device package of the present disclosure are not cut, thereby avoiding the oxidation problem that occurs in some existing methods.

[0023] Figure 1A A cross-sectional view of a semiconductor device package 1 according to some embodiments of the disclosure is shown. Figure 1B A left side view of a semiconductor device package 1 according to some embodiments of the disclosure is shown. Figure 1C A right side view of a semiconductor device package 1 according to some embodiments of the disclosure is shown.

[0024] REFERENCE Figure 1A , 1B And 1C, the semiconductor device package 1 includes a first carrier 11, a second carrier 12, one or more support members 13, an encapsulant 14, one or more electronic components 15, and electrical contacts 16. The semiconductor device package 1 is applied, for example, to 2.5D / 3D integration and assembly.

[0025] The first carrier 11 has an upper surface 111, a lower surface 112, a first side surface 113, and a second side surface 114 opposite to the first side surface 113. Both side surfaces 113 and 114 are connected to the upper surface 111. Similarly, the second carrier 12 has an upper surface 121, a lower surface 122, a first side surface 123, and a second side surface 124 opposite to the first side surface 123. Both side surfaces 123 and 124 are connected to the upper surface 121. The second carrier 12 is placed on top of the first carrier 11. The first side surface 113 of the first carrier 11 is flush with the first side surface 123 of the second carrier 12. In this embodiment, the second side surface 114 of the first carrier 11 is not flush with the second side surface 124 of the second carrier 12.

[0026] Each of the first carrier 11 and the second carrier 12 may include a substrate, a wafer, a printed circuit board, a panel, etc. In some embodiments, the first carrier 11 may be referred to as a motherboard or motherboard, while the second carrier 12 may be referred to as a sub-board or daughterboard.

[0027] In embodiments, the first carrier 11 and the second carrier 12 may be substrates having one or more conductive trace layers or wiring layers internally. For example, the first carrier 11 may include a rigid substrate 11s with conductive traces 11c, to which various components, one or more supports (e.g., inserts), etc., can be connected. Similarly, the second carrier 12 may include a rigid substrate 12s with conductive traces 12c, to which various components, one or more supports (e.g., inserts), etc., can be connected. The conductive traces 11c and 12c may be wholly or partially contained within the rigid substrates 11s and 12s, and may also be formed on the upper surfaces 111 and 121, respectively. The conductive traces 11c and 12c may be formed of a suitable material (e.g., copper).

[0028] The support member 13 may be, depending on the application, including but not limited to, inserts, terminals, or pillars. The support member 13 may have a cylindrical, rectangular, or spherical shape. For ease of electrical connection, at least one of the one or more support members 13 may be electrically connected between the first carrier 11 and the second carrier 12. In some embodiments, at least one of the one or more support members 13 has a through hole extending from the bottom side to the top side of the at least one support member.

[0029] like Figure 1A and 1C As shown, the support member 13 is disposed on the surface 111 of the first carrier 11 and connects the upper surface 111 of the first carrier 11 and the lower surface 122 of the second carrier 12. The support member 13 can be mounted on the first carrier 11 using surface mount technology (SMT).

[0030] The one or more support members 13 are spaced apart from the first side 113 of the first carrier 11 and are arranged asymmetrically with respect to the geometric center of the first carrier 11 or the second carrier 12. Figure 1A and 1C As shown, the support member 13 comprises a row of support members arranged along and close to the second side 114 of the first carrier 11 on the first surface 111. Figure 1A and 1B As shown, no support is installed along or near the first side 113 of the first carrier 11.

[0031] The plurality of electronic components 15 are mounted or installed on the upper surface 111 of the first carrier 11 and / or the upper surface 121 of the second carrier 12 using, for example, SMT technology. Since no support is installed along the first side 113 of the first carrier 11, the space between the first carrier 11 and the second carrier 12 for accommodating the electronic components 15 is increased. That is, additional electronic components 15 can be mounted close to the first side 113 of the first carrier 11.

[0032] The encapsulating material 14 completely covers the one or more support members 13 and the electronic component 15. The encapsulating material 14 covers at least a portion of the upper surface 121 and lower surface 122 of the second carrier 12. The encapsulating material 14 covers at least a portion of the upper surface 111 of the first carrier 11. In this embodiment, the first side 113 and second side 114 of the first carrier 11 and the first side 123 of the second carrier 12 are exposed from the encapsulating material 14. The second side 124 of the second carrier 12 is sealed within the encapsulating material 14.

[0033] The encapsulant 14 comprises a material having a relatively low dielectric constant. In some embodiments, the encapsulant 14 comprises an epoxy resin with filler, a molding material (e.g., an epoxy resin molding material or other molding material), a polyimide, a phenolic compound or material, a material wherein a silicone resin is dispersed, or a combination thereof.

[0034] Electrical contacts 16 (e.g., solder balls) are disposed on the lower surface 112 of the first carrier 11 and electrically connected to the conductive traces 11c of the first carrier 11. Electrical contacts 16 provide electrical connections between the semiconductor device package 1 and external components (e.g., external circuitry or a circuit board). In some embodiments, electrical contacts 16 include controlled-collapse chip connection (C4) bumps, ball grid arrays (BGAs), or planar grid arrays (LGAs).

[0035] Figure 2 A cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure is shown.

[0036] refer to Figure 2The semiconductor device package 2 includes a first carrier 11, a second carrier 12, one or more support members 13, encapsulating material 14, one or more electronic components 15, and electrical contacts 16. Figure 2 The semiconductor device package 2 is similar to the semiconductor device package 1 of FIG1, except that, for example, the semiconductor device package 2 further includes additional electronic components 25 mounted on the upper surface 111 of the first carrier 11.

[0037] like Figure 2 As shown, the width W2 of the second carrier 12 is shorter than the width W1 of the first carrier 11. Thus, a portion of the upper surface 111 of the first carrier 11 is exposed from the second carrier 12. Therefore, additional electronic components 25 can be mounted on the exposed portion of the upper surface 111 of the first carrier 11. That is, one or more electronic components can be mounted on the periphery of the first carrier 11 located outside the one or more supports 13. In this embodiment, the height H1 of the electronic component 25 is greater than the distance between the upper surface 111 of the first carrier 11 and the lower surface 122 of the second carrier 12. Therefore, Figure 2 The semiconductor device package 2 is adapted to mount one or more tall electronic components on or around the outer periphery of the first carrier 11 located on or around the one or more supports 13.

[0038] Since the width W2 of the second carrier 12 is shorter than the width W1 of the first carrier 11, the one or more electronic components 15 can be mounted on the periphery of the first carrier 11 located outside the one or more support members 13.

[0039] Figure 3 A cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure is shown.

[0040] refer to Figure 3 The semiconductor device package 3 includes a first carrier 11, a second carrier 12, an encapsulating material 14, one or more electronic components 15, 35 and electrical contacts 16. Figure 3 The difference between the semiconductor device package 3 shown and the semiconductor device packages 1 and 2 shown in Figures 1 and 2 is that the encapsulating material 14 of the semiconductor device package 3 does not contain any support members. The encapsulating material 14 is a relatively rigid layer that provides sufficient mechanical support between the first carrier 11 and the second carrier 12, and thus maintains structural reliability.

[0041] In this embodiment, the first side 113 and the second side 114 of the first carrier 11 are exposed from the encapsulating material 14. Similarly, the first side 123 and the second side 124 of the second carrier 12 are exposed from the encapsulating material 14. The first side 123 of the second carrier 12 is flush with the first side 113 of the first carrier 11. Likewise, the second side 124 of the second carrier 12 is flush with the second side 114 of the first carrier 11. Since no support is installed on the upper surface 111 of the first carrier 11, more electronic components (e.g., electronic component 35) can be installed close to the first side 113 and the second side 114 of the first carrier 11.

[0042] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E Methods for manufacturing semiconductor device packages according to some embodiments of the present disclosure are illustrated. In some embodiments, Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E The method described above can be used to manufacture the semiconductor device package 1 shown in Figure 1. In other embodiments, Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E The methods described can be used to manufacture other semiconductor device packages.

[0043] Reference Figure 4A A first carrier 41 is provided. The first carrier 41 has an upper surface 411, a lower surface 412 opposite to the upper surface 411, a first side surface 413, and a second side surface 414 opposite to the first side surface 413. The first carrier 41 includes sub-carriers 41A and sub-carriers 41B, which are separable from each other along a scribing line CL.

[0044] After the first carrier 41 is provided, a set of electronic components 45A, 45B are mounted on the upper surface 411 of the first carrier 41 using bonding (e.g., SMT) technology. The set of electronic components 45A, 45B includes a first subset of electronic components 45A and a second subset of electronic components 45B, which are located in positions corresponding to subcarriers 41A and 41B of the first carrier 41, respectively.

[0045] After the first carrier 41 is provided, one or more support members 431, 432 are mounted on the upper surface 411 of the first carrier 41 using bonding (e.g., SMT) technology. Figure 4AAs shown, supports 431 and 432 are spaced apart from the scribed line CL, and are arranged asymmetrically relative to each of the subcarriers 41A and 41B from the perspective of the subcarrier.

[0046] Reference Figure 4B After the supports 431 and 432 are installed, the second carrier 42 is attached to the first carrier 41. The second carrier 42 is stacked on the supports 431 and 432. The supports 431 and 432 define a space between the first carrier 41 and the second carrier 42 for accommodating the first subset electronic component 45A and the second subset electronic component 45B.

[0047] The second carrier 42 has an upper surface 421, a lower surface 422 opposite to the upper surface 421, a first side surface 423, and a second side surface 424 opposite to the first side surface 423. The second carrier 42 includes sub-carriers 42A and 42B, which are separable from each other along a scribing line CL. The sub-carriers 42A and 42B of the second carrier 42 are respectively positioned to correspond to the sub-carriers 41A and 41B of the first carrier 41.

[0048] Before stacking the second carrier 42 onto the supports 431, 432, a set of electronic components 45C, 45D are mounted on the upper surface 421 of the second carrier 42 using bonding (e.g., SMT) technology. The set of electronic components 45C, 45D includes a first subset of electronic components 45C and a second subset of electronic components 45D, which are located corresponding to sub-carriers 42A and 42B of the second carrier 42, respectively.

[0049] refer to Figure 4C After the second carrier 42 is stacked on the supports 431 and 432, the first carrier 41, the second carrier 42, the electronic components 45A, 45B, 45C and 45D, and at least a portion of the supports 431 and 432 are encapsulated with encapsulating material 14 to form an encapsulated semiconductor device stack 4C. The encapsulating material 14 can be formed by molding techniques such as transfer molding, compression molding or any other suitable process.

[0050] Supports 431 and 432 are completely sealed by encapsulant 44. Sides 423 and 424 of the second carrier 42 are completely sealed by encapsulant 44, while sides 413 and 414 of the first carrier 41 are exposed from the encapsulant 44. In this embodiment, the first side 423 of the second carrier 42 is not flush with the first side 413 of the first carrier 41. Additionally, the second side 424 of the second carrier 42 is not flush with the second side 414 of the first carrier 41. The width of the sub-carrier 42A of the second carrier 42 is shorter than the width of the sub-carrier 41A of the first carrier 41, therefore a portion of the upper surface 411 of the sub-carrier 41A is exposed from the sub-carrier 42A, which facilitates the flow of encapsulant 44 into the space between the first carrier 41 and the second substrate 42. Similarly, the width of the subcarrier 42B of the second carrier 42 is shorter than the width of the subcarrier 41B of the first carrier 41, so a portion of the upper surface 411 of the subcarrier 41B is exposed from the subcarrier 42B, which facilitates the flow of the encapsulating material 44 into the space between the first carrier 41 and the second substrate 42.

[0051] refer to Figure 4D A plurality of electrical contacts 46 are attached to the lower surface 412 of the first carrier 41 to form an encapsulated semiconductor device stack 4D. In some embodiments, the electrical contacts 46 include C4 bumps, BGAs, or LGAs.

[0052] refer to Figure 4E After attaching the electrical contact 46, the encapsulated semiconductor device stack 4D (including the first carrier 41, the second carrier 42 and the encapsulating material) is cut along the scribing line CL using, for example, laser or blade sawing techniques to form semiconductor device packages 4E and 4E'.

[0053] Specifically, the semiconductor device package 4E includes a sub-carrier 41A of a first carrier 41, a sub-carrier 42A of a second carrier 42, electronic components 45A and 45C, and a support 431. The sub-carrier 41A of the first carrier 41 includes a side 415, which is opposite to side 413 and exposed from the encapsulating material 44. The sub-carrier 42A of the second carrier 42 includes a side 425, which is opposite to side 423 and exposed from the encapsulating material 44. The side 415 of the sub-carrier 41A is flush with the side 425 of the sub-carrier 42A.

[0054] The semiconductor device package 4E' includes a sub-carrier 41B of a first carrier 41, a sub-carrier 42B of a second carrier 42, electronic components 45B and 45D, and a support 432. The sub-carrier 41B of the first carrier 41 includes a side 416 opposite to side 414 and exposed from encapsulation material 44. The sub-carrier 42B of the second carrier 42 includes a side 426 opposite to side 424 and exposed from encapsulation material 44. The side 416 of the sub-carrier 41B is flush with the side 426 of the sub-carrier 42B.

[0055] To better understand how the supports can be positioned asymmetrically relative to the geometric center of each of the first and second subcarriers, several examples are provided below to illustrate the arrangement of the supports. For simplicity, electronic components and encapsulation materials are not shown in the following examples.

[0056] Figure 5 A perspective view of a semiconductor device stack 5 according to some embodiments of the present disclosure is shown.

[0057] refer to Figure 5 The semiconductor device stack 5 includes a first carrier 51, a second carrier 52, and a plurality of supports 53a, 53b, 53c, 53d, 53e, 53f, 53g, 53h, 53i, and 53j. The first carrier 51 includes sub-carriers 51A and 51B. Sub-carriers 51A and 51B are separable from each other along a scribing line CL. The second carrier 52 includes sub-carriers 52A and 52B. Sub-carriers 52A and 52B are separable from each other along a scribing line CL. Supports 53a, 53b, 53c, 53d, and 53e, arranged in a first row, are mounted on sub-carriers 51A along a side 511 of the first carrier 51. The first row of supports 53a, 53b, 53c, 53d, and 53e extends parallel to the scribing line CL. Supports 53f, 53g, 53h, 53i, and 53j arranged in a second row are mounted on the sub-carrier 51B along the side 512 of the first carrier 51. The second row of supports 53f, 53g, 53h, 53i, and 53j extends parallel to the scribing line CL. In some embodiments, the supports 53f, 53g, 53h, 53i, and 53j do not undergo cutting during the process of separating the sub-carrier 51A from the sub-carrier 51B along the scribing line CL.

[0058] In some other embodiments, a first row of supports may be mounted along the side 513 of the first carrier 51 on both sub-carriers 51A and 51B. The first row of supports extends across the scribe line CL, but the supports are spaced apart from the scribe line CL (i.e., these supports are not arranged on the scribe line CL). Similarly, a second row of supports may be mounted along the side 514 of the first carrier 51 on both sub-carriers 51A and 51B. The second row of supports extends across the scribe line CL, but the supports are spaced apart from the scribe line CL (i.e., these supports are not arranged on the scribe line CL).

[0059] Figure 6 A perspective view of a semiconductor device stack 6 according to some embodiments of the present disclosure is shown.

[0060] refer to Figure 6The semiconductor device stack 6 includes a first carrier 61, a second carrier 62, and multiple supports 63a, 63b, 63c, 63d, 63e, 63f, 63g, 63h, 63i, and 63j. The first carrier 61 includes sub-carriers 61A, 61B, and 61C. The second carrier 62 includes sub-carriers 62A, 62B, and 62C. Figure 6 Stack 6 and Figure 5 The stack 5 is similar, except that, for example, stack 6 can be divided into three parts along the first line CL1 and the second line CL2.

[0061] After stack 6 is separated or divided, the first part of stack 6 includes subcarriers 61A and 62A, and first row inserts 63a, 63b, 63c, 63d, and 63e. The second part of stack 6 includes subcarriers 61B and 62B, and second row inserts 63f, 63g, 63h, 63i, and 63j. The third part of stack 6 includes subcarriers 61C and 62C and does not contain supports.

[0062] Figure 7 A perspective view of a semiconductor device stack 7 according to some embodiments of the present disclosure is shown.

[0063] refer to Figure 7 The semiconductor device stack 7 includes a first carrier 71, a second carrier 72, and multiple supports 73a, 73b, 73c, and 73d. The first carrier 71 includes sub-carriers 71A, 71B, 71C, and 71D. The second carrier 72 includes sub-carriers 72A, 72B, 72C, and 72D. Supports 73a, 73b, 73c, and 73d are mounted on sub-carriers 71A, 71B, 71C, and 71D, respectively. The positions of supports 73a, 73b, 73c, and 73d correspond to the four corners of the second carrier 72.

[0064] Figure 8A A perspective view of a semiconductor device stack 8A according to some embodiments of the present disclosure is shown.

[0065] The semiconductor device stack 8A includes a first carrier 81, a second carrier 82, a first row of supports 83A, and a second row of supports 83B. The first row of supports 83A is mounted along a side 811 of the first carrier 81. The first row of supports 83A extends parallel to and across scribe lines CL1 and CL2. The second row of supports 83B is mounted along a side 812 opposite to the side 811 of the first carrier 81. The second row of supports 83B extends parallel to and across scribe lines CL1 and CL2. When the semiconductor device stack 8A is divided into six sections along scribe lines CL1, CL2, and CL3, the two middle sections do not contain supports.

[0066] Figure 8B A perspective view of a semiconductor device stack 8B according to some embodiments of the present disclosure is shown.

[0067] Figure 8B Semiconductor device stacking 8B and Figure 8A The semiconductor device stack 8A is similar, and therefore the details of the structure of stack 8B will not be repeated here. Figure 8B Stacked 8B and Figure 8A The difference between the stacks 8A is that the semiconductor device stack 8B further includes a third row of supports 83C. The third row of supports 83C is mounted along the side 813 of the first carrier 81. The third row of supports 83C is parallel to scribe line CL1 and extends between scribe lines CL2 and CL3.

[0068] Figure 8C A perspective view of a semiconductor device stack 8C according to some embodiments of the present disclosure is shown.

[0069] Figure 8C Semiconductor device stacking 8C and Figure 8A The semiconductor devices stacked in the diagram are similar to those stacked in 8A, and therefore the details of the structure of stacked 8C will not be repeated here. Figure 8C Stacked 8C and Figure 8A The difference between the stacks 8A and 8C is that the semiconductor device stack 8C further includes a third row of supports 83D. The third row of supports 83D is mounted on the first carrier 81 along scribe line CL2. The third row of supports 83D is parallel to scribe lines CL2 and CL3 and extends across scribe line CL1. The first row of supports 83A, the second row of supports 83B, and the third row of supports 83D are not mounted on scribe lines CL1, CL2, and CL3.

[0070] Figure 8D A perspective view of a semiconductor device stack 8D according to some embodiments of the present disclosure is shown.

[0071] The semiconductor device stack 8D includes a first carrier 81, a second carrier 82, and four rows of supports 83E, 83F, 83G, and 83H. One row of supports 83E is mounted along the side 811 of the first carrier 81. The row of supports 83E extends parallel to scribe lines CL2 and CL3. One row of supports 83F is mounted along the side 813 of the first carrier 81. The row of supports 83F extends parallel to scribe line CL1. One row of supports 83G is mounted along the side 812 of the first carrier 81. The row of supports 83G extends parallel to scribe lines CL2 and CL3 and does not cross scribe line CL1. One row of supports 83H is mounted along the side 814 of the first carrier 81. The row of supports 83H extends parallel to scribe line CL1 and does not cross scribe line CL2.

[0072] Please note that throughout this disclosure, the shapes of the first and second carriers are not limited to rectangles. The first and second carriers can have, for example, circular or square shapes. Furthermore, the supports are not limited to cylinders and can have, for example, cubic, cube, or spherical shapes. The supports can be conductive or non-conductive. The number of supports can be determined according to the actual application, provided that the supports are spaced apart from one or more scribed lines and arranged asymmetrically with respect to the geometric center of each of the first and second sub-carriers when viewed from the perspective of the sub-carriers.

[0073] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may include plural referents. In the description of some embodiments, the description of another component disposed “on” or “above” a component can cover the case where the preceding component is directly located on (e.g., in physical contact with) the following component, as well as the case where one or more intermediate components are positioned between the preceding and following components.

[0074] As used herein, the terms “conductive,” “electrically conductive,” and “electrical conductivity” refer to the ability to conduct electric current. Conductive materials generally refer to those materials that offer little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than about 10. 4 S / m, such as at least 10 5 S / m or at least 10 6 Conductive materials with conductivity of S / m. The conductivity of the material may sometimes vary with temperature. Unless otherwise stated, the conductivity of the material is measured at room temperature.

[0075] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted to include not only the numerical values ​​that are explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0076] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such depictions and illustrations are not limiting of this disclosure. Those skilled in the art will understand that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the spirit and scope of this disclosure as defined by the claims. Illustrations may not necessarily be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to variations in manufacturing processes, etc. Other embodiments of this disclosure may exist that are not specifically shown. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it will be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A semiconductor device package comprising: A first carrier having a first surface; Encapsulating material, which is located on the first surface; The second carrier is disposed on the first carrier and has a second surface facing the first carrier; as well as One or more support members, wherein the one or more support members are arranged asymmetrically with respect to the geometric center of the first carrier, and wherein the second surface contacts only the one or more support members and the encapsulating material.

2. The semiconductor device package of claim 1, wherein the encapsulating material flows between the one or more supports to completely seal the one or more supports.

3. The semiconductor device package of claim 2, wherein the first carrier has a first side surface connected to the first surface and a second side surface opposite to the first side surface, and the second carrier has a third side surface connected to the second surface and a fourth side surface opposite to the third side surface, wherein the first side surface and the third side surface are flush.

4. The semiconductor device package of claim 3, wherein the second side is not flush with the fourth side.

5. The semiconductor device package of claim 4, wherein the encapsulating material covers the fourth side and flows between the first carrier and the second carrier.

6. The semiconductor device package according to claim 1, further comprising: An electronic component is disposed on the first surface of the first carrier and adjacent to the second carrier.

7. The semiconductor device package of claim 1, wherein the second carrier has a third surface opposite to the second surface and an electrical connection disposed on the third surface.

8. The semiconductor device package of claim 1, wherein the one or more support members are arranged in a row along one side of the second carrier.

9. A semiconductor device package comprising: First carrier; A second carrier is disposed on top of the first carrier, wherein the second carrier has at least two adjacent sides that are recessed inward relative to the first carrier. and Electronic components are disposed between the first carrier and the second carrier; The first carrier has at least two adjacent edges exposed from the second carrier.

10. The semiconductor device package of claim 9, further comprising: An encapsulating material that encapsulates the second carrier and is disposed between the first carrier and the second carrier.

11. The semiconductor device package of claim 9, wherein the first carrier includes a first subcarrier and a second subcarrier separable from each other along a scribe line, and the second carrier includes a third subcarrier and a fourth subcarrier that are respectively located to the first subcarrier and the second subcarrier of the first carrier and separable from each other along the scribe line.

12. The semiconductor device package of claim 11, further comprising: The first support member connects the first carrier and the third carrier.

13. The semiconductor device package of claim 12, further comprising: The second support member connects the second carrier and the fourth carrier, and is arranged asymmetrically with respect to the geometric center of the first carrier.

14. The semiconductor device package of claim 9, wherein the first carrier has a first side and a second side opposite to the first side, and the second carrier has a third side and a fourth side opposite to the third side, wherein the first side and the third side are flush.

15. The semiconductor device package of claim 14, wherein the second side is not flush with the fourth side.

16. A semiconductor device package comprising: First carrier; A second carrier is placed on top of the first carrier, wherein the side of the second carrier is recessed relative to the side of the first carrier to expose a portion of the first carrier. The first electronic component is disposed beneath the second carrier; The second electronic component is mounted on the first carrier; A third electronic component is disposed on the exposed portion of the first carrier, wherein the height of the third electronic component is greater than the distance between the first carrier and the second carrier; and A fourth electronic component is disposed on the second carrier and between the second electronic component and the third electronic component.

17. The semiconductor device package of claim 16, further comprising: Encapsulating material, which encapsulates the third electronic component.

18. The semiconductor device package of claim 17, further comprising: A support member that connects the first carrier and the second carrier and is positioned between the first electronic component and the third electronic component.

19. The semiconductor device package of claim 18, wherein the support is completely sealed by the encapsulating material.

20. A method for manufacturing a semiconductor device package, the method comprising: A first carrier is provided, comprising a first subcarrier and a second subcarrier separable from each other along a scribing line, and having a first surface; A second carrier is provided, which includes a first subcarrier and a second subcarrier respectively located to the first carrier and a third subcarrier and a fourth subcarrier that are separable from each other along the scribing line, and has a second surface facing the first carrier. One or more supports are provided on the first surface of the first carrier, the supports being spaced apart from the scribe line and arranged asymmetrically with respect to the geometric center of the first sub-carrier and the geometric center of the second sub-carrier. as well as The second surface and the one or more supports are encapsulated with an encapsulating material, wherein the second surface only contacts the one or more supports and the encapsulating material.

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