Spacer for wafers

Abstract

The invention relates to a method for producing a coupling wafer (100), a spacer wafer (150) having a metal contact (120) for protecting a functional wafer (110), comprising the following steps: providing a functional wafer (110) having a functional layer (140), a passivation layer (130) and the metal contact (120), the passivation layer and the metal contact being arranged on the functional layer; according to the invention, a spacer wafer (150) is provided, the spacer wafer having trenches (166), an oxide layer (170), a second oxide layer (190) and a carrier substrate, the second oxide layer having a recess, each of which is surrounded by one of the trenches and is arranged and configured such that the second oxide layer (190) and the carrier substrate are electrically connected to each other. In such a way that an associated relationship is formed between the interspaces and the metal contacts (120) and all the metal contacts can be simultaneously covered by the interspaces associated with the respective metal contacts; producing a coupling wafer (100) by connecting the passivation layer to the second oxide layer in such a way that each of the metal contacts is covered by an associated void; the carrier substrate is removed and a recess is created in the spacer wafer (150) in such a way that the metal contacts are in contact with an external environment (105).

Description

TECHNICAL FIELD

[0001] The present application relates to the field of wafer processing and to a method for manufacturing a coupling wafer having a spacer holder wafer for protecting metal contacts. Furthermore, the present application also relates to a corresponding coupling wafer. BACKGROUND

[0002] US 2008 / 0303129 A1 discloses a possibility for preventing damage to sensitive surfaces in the context of a MEMS manufacturing process. To this end, it is proposed to use a chuck having a structured contact surface. A cover wafer is specifically mentioned, which is to be connected to an interposer wafer in the context of the manufacturing process. The cover wafer is positioned on the chuck, the structure being configured to avoid mechanical damage. From DE 10 2015 206 996 A1 it is known a so-called EPyC process (EPyC: epitaxial polysilicon cycle) for manufacturing microelectromechanical structures having a large vertical extension, the epitaxial polysilicon serving as functional material and as sacrificial material and building a layer structure consisting of epitaxial polysilicon layers (EpiPoly-Schichten) by means of repeated cycles. SUMMARY

[0003] According to the present application, a method for manufacturing a coupling wafer having a spacer holder wafer for protecting metal contacts of a functional wafer and a corresponding coupling wafer are proposed.

[0004] According to a first aspect of the present application, a method for manufacturing a coupling wafer having a spacer holder wafer for protecting metal contacts of a functional wafer is proposed. The method comprises providing a functional wafer, for example a MEMS wafer (MEMS: microelectromechanical system), having a functional layer (implementing the actual function of the MEMS component), which for example contains or consists of silicon, and having a passivation layer and metal contacts, wherein the passivation layer and the metal contacts are arranged on a surface of the functional layer. The metal contacts can for example be designed for establishing an electrical connection between the functional wafer and other components.

[0005] The metal pads can be metal contacts, which can for example consist of or comprise aluminum copper (AlCu), copper (Cu) and / or gold (Au). The passivation layer can preferably consist of or comprise silicon dioxide (Si02) and / or silicon nitride, for example stoichiometric silicon nitride, i.e. Si3N4, and / or non-stoichiometric silicon nitride, i.e. silicon nitride having a non-stoichiometric composition. It is conceivable in particular that the passivation layer can consist of or comprise a silicon nitride layer and also a silicon dioxide layer, wherein it is conceivable for this purpose to first apply a silicon dioxide layer or a silicon nitride layer on the functional layer. It is also possible to use a double layer as a passivation layer consisting of a layer consisting of stoichiometric silicon nitride and a layer consisting of non-stoichiometric silicon nitride. The passivation layer preferably serves as an etch stop layer for a subsequent etching of the silicon sacrificial layer, wherein for this purpose, for example, sulfur hexafluoride (SF6) and / or xenon difluoride (XeF2) can be used as etching gas.

[0006] Further provided is a spacer wafer. The spacer wafer comprises a silicon layer having trenches filled with a passivation material. The passivation material can for example be silicon dioxide, silicon nitride and / or silicon oxynitride. The spacer wafer further comprises a first oxide layer on a first surface of the silicon layer, a second oxide layer on a second surface of the silicon layer opposite the first surface and a carrier substrate arranged on the first oxide layer, the carrier substrate preferably comprising or consisting of silicon. An oxide layer is understood in the sense of the present application to mean that the oxide layer comprises or consists of silicon dioxide (Si02).

[0007] The silicon layer can in particular be an epitaxial polysilicon layer (EpiPoly-Schicht). A polysilicon layer which is grown epitaxially, i.e. under epitaxial growth conditions, is referred to as an epitaxial polysilicon layer. Such an epitaxial polysilicon layer has a thickness of typically more than 5 pm, often also several 10 pm. In the present case, the silicon layer has a thickness of preferably 10-20 pm. The thickness of the silicon layer defines the spacing between the metal contacts and a support surface, for example of a chuck. The trenches can be filled for example thermally and / or by means of chemical low pressure vapor deposition (LPCVD). The trenches preferably connect the first surface and the second surface of the silicon layer, the trenches thus preferably extending through the entire thickness of the silicon layer defined by the spacing between the first surface and the second surface.

[0008] The second oxide layer on the silicon layer also has one or more voids, which are respectively surrounded by one or more of the trenches of the silicon layer. A void is to be called surrounded by a trench of the silicon layer in this case if the trench extends so far that the void, when it is hypothetically continued inside the silicon layer perpendicular to the second surface of the silicon layer, is surrounded laterally, i.e. in all directions parallel to the second surface. If the trench connects the first surface and the second surface of the silicon layer, the trench thus also surrounds a region of the silicon layer and separates this region from the rest of the silicon layer. A trench can in the sense of the present application surround only one region of the silicon layer all the way around. If a trench structure surrounds multiple regions of the silicon layer, which are separated from one another by the trench structure, this trench structure is multiple trenches in the sense of the present application. Exemplarily, two trenches are listed, which surround two different regions in the silicon layer, but are connected to one another by another trench or a portion of another trench. This trench structure is multiple trenches, because multiple regions are surrounded.

[0009] In this case, the one or more voids are arranged and configured in such a way that an assignment is formed between the one or more voids and the metal contacts and all metal contacts are simultaneously coverable by the voids to which they are respectively assigned. Coverability of the metal contacts by the voids in the sense of the present application means that the floor of the void can be placed on the floor of the metal contact in such a way that the floor of the void surrounds the floor of the metal contact.

[0010] The one or more voids of the second oxide layer are arranged in correspondence with the arrangement of the metal contacts, whereby an assignment is formed between the voids and the metal contacts. In this case, it is also possible to assign multiple metal contacts to one single void. Thus, for example, two, three, four or five metal contacts can be assigned to one single void. It is also possible to assign all metal contacts to one single void. Preferably, the number of voids corresponds to the number of metal contacts. In this case, the voids are arranged in the same pattern as the metal contacts, i.e. the position of the voids in the second oxide layer corresponds to the position of the metal contacts on the functional layer.

[0011] The voids are preferably designed with a margin in such a way that the metal contacts are reliably accessible when wafer bonding is subsequently carried out, even in the presence of process tolerances, for example calibration deviations. The same applies to the production of the trenches in the silicon layer of the spacer wafer.

[0012] Generally, extremely different arrangements of metal contacts are conceivable, such as grid-like or asymmetrical arrangements. Similarly, different shapes of the gaps in the second oxide layer are also possible; for example, one of the one or more gaps may have a rectangular, circular, or hexagonal base. The shape of the gaps can also be adapted to the shape of the covered metal contacts. The shape of the gaps can also vary between individual gaps within the spacer wafer or all gaps may have the same shape, i.e., rectangular, circular, or hexagonal. A gap can cover multiple metal contacts, such as two, three, four, five, or more. A gap can also cover all metal contacts. In particular, the gaps can also be constructed such that, after subsequent separation, a spacer holding structure is retained for each chip or MEMS component formed from the spacer holding wafer, for example, in the form of a frame and / or a single support structure, such as at the corner of the chip or MEMS component. Therefore, continued protection of the separated chip or MEMS component can be ensured after separation. Preferably, the geometry of the void in the second oxide layer is continued by a corresponding void in the remaining portion of the spacer wafer, i.e., the other void has a bottom surface and a cross-section that are at least similar to those of the void in the second oxide layer, parallel to the second oxide layer.

[0013] Therefore, providing a spacer wafer may include, for example, the following steps: providing a silicon wafer comprising a carrier substrate; the silicon wafer preferably being thermally partially oxidized; forming a first oxide layer on the surface of the carrier substrate; growing a silicon layer, preferably as an epitaxial polysilicon layer, on the first oxide layer, wherein the layer thickness is preferably 10-20 μm; forming trenches in the silicon layer, for example by means of reactive ion etching (RIE) and / or deep reactive-ion etching (DRIE) and / or, especially in the case of a relatively thin silicon layer, by means of a plasma etching method; forming a second oxide layer on a second surface of the silicon layer and filling the trenches with a passivation material, both, for example, thermally and / or by means of LPCVD; and finally partially removing the second oxide layer to create one or more voids in the second oxide layer. In this case, the thickness of the first oxide layer is preferably selected such that the first oxide layer can function as a selective etch stop layer for subsequent removal of the carrier substrate.

[0014] Furthermore, the trenching and removal of the second oxide layer are performed such that one or more voids are respectively surrounded by one of the trenches, and the one or more voids are arranged and configured such that an affinity relationship is formed between the one or more voids and the metal contacts, and all metal contacts can be simultaneously covered by the voids respectively affinity assigned to the metal contacts. The growth of the epitaxial polycrystalline silicon layer on the first oxide layer may, in this case, include the prior application of a polycrystalline silicon initiation layer on the oxide layer, for example, by means of CVD (chemical vapor deposition), since polycrystalline silicon (polycrystalline silicon) typically cannot be epitaxially grown directly on the oxide layer.

[0015] When providing spacer wafers in this way, the carrier substrate, the first oxide layer on the surface of the carrier substrate, and the silicon layer on the first oxide layer can also be provided directly in the form of an original wafer such as an SOI wafer (SOI: Silicon-on-Insulator), and other method steps for providing spacer wafers can be performed from the SOI wafer.

[0016] The coupled wafer, comprising a functional wafer and a spacer wafer, is fabricated by connecting a passivation layer of the functional wafer and a second oxide layer of the spacer wafer. This is done such that each metal contact is covered by its associated void. The metal contacts are preferably calibrated according to their positioning relative to the void before this connection. The connection can be achieved, for example, by a direct bonding method, such as SiO2-SiO2 direct bonding. All process steps beginning with this direct bonding method should preferably be performed at temperatures below the limits typically allowed in back-end-of-line (BEOL) processes, such as 450°C.

[0017] The carrier substrate of the spacer wafer is then removed, preferably by means of grinding followed by chemical mechanical polishing (CMP). This method enables the removal of the carrier substrate with high precision. Alternatively, the removal can also be performed by plasma-free or plasma-supported silicon etching methods, such as using SF6 etching gas, or by a combination of grinding, polishing, especially CMP, and / or etching, such as when using SF6.

[0018] Finally, the voids are created in the spacer wafer such that the metal contacts come into contact with the external environment of the coupled wafer via one or more voids in the second oxide layer and the voids now created in the spacer wafer. That is, a channel leading to the metal contacts is exposed. Creating voids in the spacer wafer preferably involves partially removing the first oxide layer of the spacer wafer, for example by vapor phase etching, plasma etching, and / or wet etching, and includes immediately following the etching of the silicon layer, for example by etching using sulfur hexafluoride (SF6). In this case, the filled trenches preferably serve as etch stops. Specific materials for the metal contacts, such as AlCu, Cu, and / or Au, are particularly advantageous when etched using SF6, because these materials are not eroded by SF6 etching. As described above, the shape of the voids in the spacer wafer can continue the geometry of the voids in the second oxide layer.

[0019] The trenches used to create channels to the metal contacts can, for example, have inner walls that are parallel to each other and perpendicular to the second surface of the silicon layer. In this case, the inner wall of the trench refers to the side surface of the trench pointing inward, i.e., towards the inner region. Because the filled trenches surround voids in the oxide layer and therefore also surround regions of the silicon layer, they also each have an inner region. It is also conceivable that the trenches have inner walls that are not parallel to each other and are inclined to the second surface of the silicon layer, wherein the spacing between the inner walls increases or decreases with the increase of the spacing from the second surface. This inclined second variant results in outwardly open or closed voids in the spacer wafer and can be particularly advantageous for edge coverage of deposited layers, such as applying over-pad-metallization to the metal contacts. Furthermore, these layers can also have a positive impact on the performance of the soldering process used to solder the metal contacts.

[0020] The coupled wafer thus created enables other methodological steps for processing the metal contacts within the manufacturing process framework, based on the channels leading to the metal contacts. Simultaneously, the coupled wafer can be placed, for example, with a spacer wafer facing downwards on a support surface such as a chuck, without the risk of damaging the metal contacts or any layers that may be applied to them. Therefore, the spacer wafer processed according to the method can be used as a spacer in subsequent processing and thus for protecting the functional wafer.

[0021] After creating voids in the spacer wafer, pad metallization (OPM) can be applied to the metal contacts. The OPM can be, for example, an ENEPIG coating (ENEPIG: electroless nickel, electroless palladium, immersion gold). Here, the areas of the coupled wafer where silicon dioxide is disposed are not coated. This coating is typically performed with the metal contacts facing upwards (i.e., opposite to the direction of gravity). Pretreatment of the metal contacts can be performed before application. Pretreatment refers to cleaning and / or roughening the surfaces of the metal contacts to prepare for OPM application, where some metal contact removal may also occur. Pretreatment can be performed, for example, by O2 / Ar plasma cleaning and / or by anti-sputtering (removing material by sputtering methods) or includes these steps. During anti-sputtering, the removal of a second silicon dioxide layer can occur here.

[0022] After applying OPM, a passivation layer, preferably a silicon dioxide layer, can be applied to the pad metallization. This passivation layer serves as additional protection against potential chuck contamination and / or environmental contamination, such as that from the surrounding production equipment. In the case of a silicon dioxide layer, this layer can later be removed without residue using HF vapor phase etching, plasma etching, and / or wet chemical etching.

[0023] Subsequently, if necessary, after rotating the coupled wafer, for example, about its longitudinal axis, the coupled wafer can be placed on a support surface, such as a chuck, such that only the spacer wafer contacts the support surface. Further processing of the coupled wafer can now be performed, for example, releasing the MEMS structures present in the functional wafer. Such MEMS structures can be, for example, structures for one or more MEMS components, such as MEMS sensors and MEMS actuators, such as MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors, and / or MEMS resonators. Releasing the MEMS structures in the functional layer can be done using plasma-free and / or plasma-supported etching. Preferably, such etching is performed using sulfur hexafluoride (SF6), xenon difluoride (XeF2), chlorine trifluoride (ClF3), and / or nitrogen trifluoride (NF3).

[0024] Finally, after releasing the MEMS structure, at least partially, one or more oxide layers, such as a first oxide layer, on the spacer holder wafer can be removed, for example, by using HF vapor phase etching, plasma etching, and / or wet chemical etching. In this method step, passivation layers, such as silicon dioxide layers, and / or passivation materials for filled trenches, applied to the OPM if necessary, can also be removed. For example, the silicon dioxide layer used as a passivation layer on the OPM of the metal contacts can be removed without residue by HF vapor phase etching, plasma etching, and / or wet chemical etching. If desired, areas can be specifically protected from HF vapor phase etching by applying non-stoichiometric silicon nitride.

[0025] Furthermore, it is conceivable that metal contacts are connected to one or more components, such as electronic components, ASICs (Application-Specific Integrated Circuits), and / or MEMS components or component wafers, such as ASIC wafers or MEMS wafers, preferably for establishing electrical connections. Such a step can be performed, for example, before separating the coupled wafer into individual chips or MEMS components, and preferably after releasing the MEMS structure if necessary. Alternatively, however, such connections can also be made after the separation of the coupled wafer.

[0026] Preferably, the silicon layer contains one or more additional trenches filled with an insulating material, wherein the insulating material may be, for example, silicon dioxide, silicon nitride, and / or silicon oxynitride. In this case, the one or more additional trenches are oriented such that each additional trench surrounds a trench surrounding a void in the oxide layer. The insulating material may be consistent with the passivation material of the trench surrounding the void in the oxide layer. The additional trenches improve the electrical insulation of the metal contacts in the coupled wafer and are additionally present in addition to the trenches filled with insulating material surrounding the void in the oxide layer and used as etch stops when voids are created in the spacer wafer. Any geometry and arrangement of the one or more additional trenches is conceivable; for example, one additional trench may surround multiple voids in the oxide layer respectively.

[0027] Finally, separation of the coupled wafers, if necessary, including those already connected to the coupled wafers, can be performed to obtain, for example, individual MEMS components or chips. It is particularly advantageous to construct the gaps in the second oxide layer in this case such that, after the separation, the spacer holding structure is retained for each chip or each MEMS component constituted by the spacer holding wafer, for example in the form of a frame and / or a single support structure, such as at the corners of the MEMS component or chip. In this case, it can be ensured that at least partial protection of the chip or MEMS component is maintained after the separation, especially in this situation where the metal contacts remain open, i.e., not yet used for connection to the component or component wafer.

[0028] According to a second aspect of the invention, a coupling wafer is provided, preferably manufactured according to the aforementioned method, wherein the coupling wafer has a functional wafer, such as a MEMS wafer, having a functional layer, a passivation layer, and metal contacts, wherein the passivation layer and metal contacts are disposed on the surface of the functional layer. Furthermore, the coupling wafer includes a spacer wafer, wherein the spacer wafer includes a silicon layer having trenches filled with a passivation material, a first oxide layer on a first surface of the silicon layer, a second oxide layer on a second surface of the silicon layer opposite to the first surface, and a carrier substrate disposed on the first oxide layer, wherein the second oxide layer has one or more voids, each void being surrounded by one of the trenches, wherein the voids are arranged and configured such that the one or more voids form an affinity relationship with the metal contacts and all metal contacts can be simultaneously covered by the voids respectively affinity assigned to the metal contacts. In this case, the filled trenches can be filled, for example, with silicon dioxide, silicon nitride, and / or silicon oxynitride as the passivation material.

[0029] In this configuration, the passivation layer of the functional wafer and the second oxide layer of the spacer wafer are connected such that each metal contact is covered by the associated void, and furthermore, voids exist in the spacer wafer such that the metal contacts are in contact with the external environment of the coupling wafer via one or more voids in the second oxide layer and voids in the spacer wafer.

[0030] Advantages of the invention The advantages of this invention are multifaceted. This invention discloses a method for manufacturing a defined spacer wafer made of silicon and its integration and further processing within a chip or MEMS component fabrication framework. The spacer wafer processed according to this invention, used as a spacer, enables protection of metal contacts leading from a functional wafer, and further processing of said metal contacts through corresponding openings, particularly enabling electrical coupling to other components, such as ASICs or corresponding component wafers. Even after decoupling the coupling wafer, spacer structures can be provided for individual chips or MEMS components based on the spacer wafer.

[0031] The method described enables high flexibility in adapting precise frame conditions to accommodate the processing procedures within which the invention is to be used. For example, the height of the spacer wafer can be selected such that the coupled wafer can be operated without risk. The coupled wafer can be laid down, for example, via the spacer wafer, and thus further processed in a chuck-mounted processing apparatus without the risk of chuck or apparatus contamination. OPM can also be applied to the metal contacts without problems based on openings in the spacer wafer in the form of gaps, and the height of the spacer wafer can be adapted to the height of the OPM layer.

[0032] The method and coupled wafer according to the invention are also provided with a number of advantageous variations, which can be adapted to desired conditions respectively: For example, metal contacts may be provided with a protective silicon dioxide layer for further processing, which can be removed together with other oxide layers in a subsequent process, such as by HF vapor phase etching.

[0033] In spacer wafers, additional trenches filled with insulating material can be integrated into the silicon layer between the gaps to provide better electrical insulation for the metal contacts.

[0034] During subsequent soldering, the walls created by the gaps in the silicon layer of the spacer wafer function as a soldering stop. This prevents the uncontrolled flow of the solder used.

[0035] This invention can be used for almost any arrangement of metal contacts. Furthermore, different geometries for the gaps can be generated in the second oxide layer and generally in the spacer wafer, and these geometries can be arbitrarily varied within the arrangement of the metal contacts. Attached Figure Description

[0036] Embodiments of the present invention will be further explained with reference to the accompanying drawings and the following description.

[0037] The attached diagram shows: Figures 1A to 1 J : A schematic diagram illustrating the cross-section of a wafer used to explain the method for manufacturing a coupled wafer according to the present invention; Figure 2A , 2B A schematic diagram of the cross-section of the coupled wafer according to the present invention when using an OPM with a passivation layer; Figures 3A to 3C A schematic diagram of a coupled wafer used to explain the method according to the invention when using additional trenches for electrical insulation; Figure 4 : A schematic cross-section of the metal contacts and the walls surrounding the metal contacts in an exemplary configuration of a coupled wafer according to the invention; Figure 5 : A schematic diagram of an exemplary variant of the arrangement of metal contacts in a coupled wafer according to the present invention; Figure 6 : A schematic diagram of an exemplary possible configuration of the gaps for the metal contacts in a coupled wafer according to the invention; and Figure 7 The exemplary method according to the invention for manufacturing a coupled wafer according to the invention is illustrated schematically as a flowchart. Detailed Implementation

[0038] In the following description of embodiments of the invention, the same or similar elements are identified by the same reference numerals, wherein repeated descriptions of these elements are omitted in certain cases. The drawings are only schematically illustrating the subject matter of the invention. Furthermore, for clarity, Figures 1A to 6 The various elements shown, such as layers, trenches, and regions, are provided with reference numerals only as examples.

[0039] Figures 1A to 1 J A cross-sectional schematic diagram is shown to explain an exemplary method according to the invention for manufacturing a coupled wafer according to the invention, and such a coupled wafer is shown in cross-sectional view.

[0040] Specifically, Figure 1AThe schematic diagram shows a cross-section through a functional wafer 110 having a functional layer 140 and a passivation layer 130 on a surface 142 of the functional layer 140. The functional wafer 110 also includes metal contacts 120, which are also arranged on the surface 142 and surrounded laterally by the passivation layer 130. The metal contacts 120 are thus arranged in the voids of the passivation layer 130. The passivation layer 130 may be made of, for example, silicon dioxide and / or silicon nitride, or comprise these materials. The functional layer 140 may have a MEMS structure. For clarity, the functional layer is only partially shown with a MEMS structure in this and the following figures; conversely, the functional layer 140 is shown only in a limited area near the passivation layer 130 in most figures. This simplified illustration is represented by the wavy boundaries of the drawn functional layer 140.

[0041] Figure 1B The upper sub-figure S in the schematic diagram shows a cross-section through a spacer wafer 150 having a carrier substrate 180, for example, made of silicon. The spacer wafer 150 also includes a first oxide layer 170, for example, made of silicon dioxide and / or silicon nitride, applied to a surface 184 of the carrier substrate 180. A silicon layer 160, preferably an epitaxial polysilicon layer, is present on the first oxide layer 170, in contact with the first oxide layer 170 through a first surface 162. A trench 166 is present in the silicon layer 160, filled with a passivating material, such as silicon dioxide, silicon nitride, and / or silicon oxynitride, and surrounds a specific region 161 of the silicon layer 160 in the lateral direction, thus separating this specific region from the rest of the silicon layer 160. This is illustrated in the lower sub-figure T, which shows a cross-section through the silicon layer 160 and the trench 166, the orientation of which is marked by a dashed line T in the upper sub-figure S. As can be seen in the lower sub-figure T, trenches 166 respectively form the framework for regions 161 of silicon layer 160. For greater clarity, exemplary corresponding points in the two sub-figures S and T are connected to each other by dashed lines 168. Furthermore, dashed lines S are drawn in the lower sub-figure T, representing the position of the cross-section shown in the upper sub-figure S.

[0042] A second oxide layer 190 with voids 192 is applied to a second surface 164 of the silicon layer 160 opposite to the first surface 162. Trench 166 extends through the entire thickness of the silicon layer 160, from the first surface 162 to the second surface 164, and thus connects the first oxide layer 170 and the second oxide layer 190. In this case, the voids 192 are positioned such that they are each surrounded by one of the trenches 166. As shown, the voids 192 are also arranged and configured such that an affinity relationship is formed between the voids 192 and the metal contacts 120 of the functional wafer 110, and all metal contacts 120 can be simultaneously covered by the voids 192 respectively associated with the metal contacts.

[0043] exist Figure 1C The coupled wafer 100 is now shown, which is coupled by making the source from Figure 1A Functional wafer 110 and Figure 1B The spacer wafer 150 is formed by connecting the spacers. For this purpose, a connection is formed between the passivation layer 130 of the functional wafer 110 and the second oxide layer 190 of the spacer wafer 150. Each metal contact 120 is covered by a void 192 in the second oxide layer 190 assigned to the metal contact. A cavity 132 is defined by the voids in the passivation layer 130 and the voids 192 in the second oxide layer 190. The coupled wafer 100 is located in an external surrounding environment 105.

[0044] After manufacturing the coupled wafer 100, the coupled wafer as follows Figure 1D The process shown involves further treatment, such as removing the carrier substrate, grinding, and immediately following CMP. Etching processes, such as... Figure 1E and Figure 1F As shown, voids 152 are specifically created in the spacer wafer 150. Specifically, this is done in two steps: first, as... Figure 1E As shown, voids are created in the first oxide layer 170, for example by vapor phase etching, plasma etching, and / or wet etching, and subsequently as in Figure 1F As shown, voids are created in the silicon layer 160, for example, by SF6 etching. In the example shown, this is done directly above the metal contact 120 by removing the region 161 surrounded by the trench 166, thereby bringing the metal contact 120 into contact with the external surrounding environment 105 of the coupled wafer 100 via voids 192 in the second oxide layer 190 and voids 152 in the spacer wafer 150. The filled trench 166 serves as an etch stop when removing region 161.

[0045] The metal contacts 120 are preferably provided with an OPM coating. Therefore, the metal contacts 120 can be pre-treated beforehand. After such necessary pre-treatment, the metal contacts 120 can be processed as follows: Figure 1GAs shown, OPM122, such as ENEPIG, is applied to the pretreated metal contact 120. Then, as in... Figure 1H As shown, the coupling wafer 100 can be surrounded by Figure 1G It rotates along the longitudinal axis indicated by arrow 101 and is placed on the support surface 102 of, for example, chuck 103, with the now protected back side facing downwards, i.e., with the metal contacts 120 facing downwards.

[0046] Finally, the structures in functional layer 140, such as MEMS structure 144, can now be released. To do this, as in... Figure 1I The removal of silicon from the functional layer 140, as shown in the example using SF6, XeF2, ClF3, and / or NF3, thereby releasing the potential MEMS structure 144. To illustrate this removal of silicon in the MEMS structure 144, in... Figure 1H and Figure 1I The MEMS structure 144 is shown in a different shaded line. The remaining portion of the first oxide layer 170 and the passivation material of the trench 166 can then be removed, for example, by means of HF vapor phase etching. Figure 1J The result of such an etching process is shown in the upper part. To prevent unwanted areas of the oxide layer from being etched, these unwanted areas could be provided with silicon nitride and passivated relative to HF. In the illustrated example, this approach is abandoned, and therefore the portion 131 of layers 130, 190 surrounding the metal contact 120 is removed by HF vapor phase etching, wherein, for the purposes of the figures shown, it should be assumed that, in addition to the second oxide layer 190, the passivation material of the passivation layer 130 and the filled trench 166 is also at least partially composed of silicon dioxide and is etched by hydrogen fluoride HF vapor phase etching.

[0047] The coupled wafer 100, thus processed, can ultimately be connected to other components, such as ASICs, or also to wafers used for those components. Figure 1J The diagram illustrates how a coupled wafer 100 is brought into contact with metal contacts 120, which are provided with OPM 122, and metal contacts 126, of a component wafer 104, such as an ASIC wafer, to establish an electrical connection between the functional wafer 110 and the component wafer 104. Such a connection between the metal contacts 120 and the electrical contacts 126 can be achieved, for example, by a soldering process. In this case, a residual portion of the silicon layer 160 serves as a solder stop.

[0048] Figure 2A and Figure 2B A schematic diagram of the cross-section is shown from... Figures 1A to 1 J Variations of the method according to the invention and corresponding variations of the coupled wafer 100 according to the invention having OPM (pad metallization) 122. In this variation, as in Figure 2AAs shown, a passivation layer 124, such as a silicon dioxide layer, is applied to the pad metallization 122. This passivation layer 124 resists chuck contamination and / or environmental contamination through the pad metallization 122, for example, by... Figure 2B As shown in the figure, the coupled wafer 100 is placed on the support surface 102 of the chuck 103. Such a passivation layer 124 can be removed without residue later, for example by means of HF vapor phase etching, in the case of a silicon dioxide layer.

[0049] Figures 3A to 3C A schematic diagram is shown from Figures 1A to 1 J The method according to the invention and another possible variation of the coupled wafer 100 according to the invention. In this variation, additional trenches 166 filled with an insulating material for electrical insulation are used. For example, silicon dioxide, silicon nitride, and / or silicon oxynitride can be used as the insulating material, similar to the passivation material for the filled trenches 166. For clarity, Figure 3A A schematic top view of a portion of coupled wafer 100 illustrates the overall concept of the placement of these additional trenches 167 relative to the metal contacts 120, OPM 122, and voids 192 in the second oxide layer 190. For better understanding, elements essential to this concept are drawn, even though these elements are not actually visible in the top view. It can be seen that in this example, the additional trenches 167 are centrally arranged in a grid-like manner between the metal contacts 120. However, this is not necessarily the case; any geometry and arrangement of these additional trenches are conceivable, as is the possibility of an additional trench surrounding multiple voids 192 in the second oxide layer 190. Figure 3B and Figure 3C This shows a cross-sectional view of the coupled wafer 100 constructed according to this concept, on the one hand... Figure 3B The diagram shows metal contacts 120 oriented upwards and equipped with OPM 122, on the other hand... Figure 3C The diagram illustrates the application of a coupling wafer onto the ASIC wafer 104. It can be seen that an additional trench 67 extends through the entire thickness of the silicon layer 160. Figure 3C In the coupled wafer 100 shown, compared to in Figure 3B In the coupled wafer 100, the passivation material of the first oxide layer 170 and trench 166 is removed. However, the additional trench 167 in the silicon layer 160 remains filled to ensure electrical insulation.

[0050] Figure 4Exemplary examples, illustrated in sub-figures A and B as cross-sections, show two variations of trenches 466a and 466b used to create channels to metal contacts 420a and 420b of functional wafers 410a and 410b within the framework of the coupled wafer according to the invention. The coupled wafer, including functional wafers 410a and 410b and spacer holding wafers 450a and 450b, is only partially shown in the regions surrounding metal contacts 420a and 420b in both sub-figures A and B. The illustrated metal contacts 420a and 420b are provided with OPMs 422a and 422b. Furthermore, as shown in the aforementioned figures, as part of the coupling wafer according to the present invention, it includes functional wafers 410a and 410b and passivation layers 430a and 430b and functional layers 440a and 440b of functional wafer 410a. The spacer wafers 450a and 450b have silicon layers 460a and 460b, trenches 466a and 466b in the silicon layers 460a and 460b, first oxide layers 470a and 470b, and second oxide layers 490a and 490b having voids 492a and 492b.

[0051] As in Figure 4 As shown in sub-Figure A, the spacer wafer 450a may have walls 467a that are parallel to each other and perpendicular to the second surface 464a of the silicon layer 460a, said walls being defined by trenches 466a. Conversely, sub-Figure B shows trenches 466b that are obliquely oriented relative to the second surface 464b of the silicon layer 460b. In this case, the spacing between said walls increases with the spacing relative to the second surface 464b. Thus, the two variations result in different voids 452a, 452b in their respective spacer wafers 450a, 450b, which, together with voids 492a, 492b in the second oxide layers 490a, 490b, function as channels to the metal contacts 420a, 420b. The variation in sub-Figure B with the obliquely oriented trenches 466b can be particularly advantageous when applying OPM 422a, 422b and performing the soldering process.

[0052] Figure 5 In sub-figures A and B, exemplary variations of the arrangement of metal contacts 520a, 520b and the gaps 592a, 592b associated with the metal contacts in the coupled wafers 500a, 500b according to the invention are shown in purely schematic form. Specifically, the schematic diagrams show portions of the coupled wafers 500a, 500b in top view, wherein only components necessary for clarity are shown schematically, namely, the second oxide layers 590a, 590b, the metal contacts 520a, 520b, the OPM 522a, 522b, and the gaps 592a, 592b in the second oxide layers 590a, 590b. In this case,Figure 5 Sub-figure A shows metal contacts 520a arranged in a grid pattern, and sub-figure B shows a completely free, asymmetrical arrangement of metal contacts 520b. Furthermore, Figure 5 An example illustrates this situation: multiple metal contacts 520b, namely two metal contacts 520b on one hand and four metal contacts 520b on the other hand, are respectively assigned to and covered by a common gap 592b.

[0053] Figure 6 The diagram schematically illustrates four exemplary configurations, from A to D, for the gaps in the metal contacts 620a, 620b, 620c, and 620d in the coupling wafer according to the present invention. Figure 5 Similarly, these schematic diagrams are limited to simplified and partial top views. The individual second oxide layers 690a, 690b, 690c, 690d, metal contacts 620a, 620b, 620c, 620d, OPM 622a, 622b, 622c, 622d, and voids 692a, 692b, 692c, 692d within the second oxide layers 690a, 690b, 690c, 690d are schematically shown. Different shapes of voids 692a, 692b, 692c, 692d are shown; more precisely, void 692a has a rectangular base, void 692b has a circular base, void 692c has a hexagonal base, and void 692d has a hexagonal base and covers two metal contacts 620d. The shape of the voids can be arbitrarily changed within the arrangement of the electrical contacts.

[0054] Figure 7 Finally, an exemplary method according to the invention for manufacturing a coupled wafer having a MEMS structure in a functional wafer is illustrated schematically as a flowchart. In this case, a functional wafer having a functional layer, a passivation layer, and metal contacts is provided in step 710. The functional layer has a MEMS structure, wherein the passivation layer and metal contacts are disposed on the surface of the functional layer. Furthermore, a spacer wafer is provided at step 715, wherein the spacer wafer includes a silicon layer having trenches filled with a passivation material, a first oxide layer on a first surface of the silicon layer, a second oxide layer on a second surface of the silicon layer opposite to the first surface, and a carrier substrate disposed on the first oxide layer. In this case, the second oxide layer has voids, each void being surrounded by one of the trenches, wherein the voids are arranged and configured such that an affinity relationship is formed between the voids and the metal contacts, and all metal contacts can be simultaneously covered by the voids respectively affixed to the metal contacts.

[0055] In step 720, a coupled wafer comprising the functional wafer and the spacer wafer is manufactured by connecting the passivation layer of the functional wafer to the second oxide layer of the spacer wafer. This is done such that each of the metal contacts is covered by its assigned void. Next, the carrier substrate is removed (725), and voids (730) are created in the spacer wafer such that the metal contacts are in contact with the external environment of the coupled wafer via the voids in the second oxide layer and the voids in the spacer wafer.

[0056] To improve electrical contact with connected components, the pretreatment 735 of the metal contacts can be performed by anti-spatting and then applying pad metallization 740 to the pretreated metal contacts.

[0057] Finally, to release the MEMS structure in the functional layer of the 750 functional wafer, the coupled wafer can be placed on the support surface such that only the spacer wafer contacts the support surface. After releasing the MEMS structure at 750, the oxide layer no longer needed at 755 can be removed from the spacer wafer, preferably by means of HF vapor phase etching. Silicon nitride passivation is conceivable here, used for protection against HF. The released coupled wafer can then be connected to a component wafer, such as an ASIC wafer, or a single component, such as an ASIC, in step 760. Separation can then be performed to obtain individual MEMS components, each generated from the spacer wafer via the spacer structure. Alternatively, separation can be performed before connecting to the component wafer or individual component.

[0058] The invention is not limited to the embodiments described herein and the aspects highlighted therein. Rather, various modifications that are within the scope of the claims are possible and are of skill to those skilled in the art.

Claims

1. A method for manufacturing coupled wafers (100, 500a, 500b), said coupled wafers having spacer wafers (150, 450a, 450b) for protecting metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) of functional wafers (110, 410a, 410b), said method comprising the steps of: a. Provide (710) a functional wafer (110, 410a, 410b) having functional layers (140, 440a, 440b), passivation layers (130, 430a, 430b) and metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d), wherein the passivation layers (130, 430a, 430b) and the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) are disposed on the surface (142) of the functional layers (140, 440a, 440b); b. Providing (715) spacer holding wafers (150, 450a, 450b), wherein the spacer holding wafers (150, 450a, 450b) comprise: - Silicon layers (160, 460a, 460b) with trenches (166, 466a, 466b) filled with passivation material. - A first oxide layer (170, 470a, 470b) on the first surface (162) of the silicon layers (160, 460a, 460b). -A second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) on a second surface (164, 464a, 464b) opposite to the first surface (162) of the silicon layer (160, 460a, 460b); and - Carrier substrate (180) disposed on the first oxide layer (170, 470a, 470b). The second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) has one or more voids (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d), which are surrounded by one of the trenches (166, 466a, 466b) and are arranged and configured such that the one or more voids (192, 492a, 492b, 592a, 592b, 692a, 80d) are surrounded by one of the trenches (166, 466a, 466b) in such a way that the one or more voids (192, 492a, 492b, 592a, 592b, 692a, 80d) are surrounded by one of the trenches (166, 466a, 466b) are surrounded by one of the trenches (166, 466a, 466b) in a way that the one or more voids are surrounded by one of the trenches (192, 492a, 492b, 592a, 592b, 692a, 80d ... 692b, 692c, 692d) and the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) form an assignment relationship, and all metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) can be simultaneously covered by the gaps (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) respectively assigned to the metal contacts; c. By connecting the passivation layers (130, 430a, 430b) of the functional wafers (110, 410a, 410b) to the second oxide layers (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) of the spacer wafers (150, 450a, 450b), a structure comprising the functional wafers (110, 410a, 410b) is thus manufactured (720). The coupling wafers (100, 500a, 500b) of the spacer wafers (150, 450a, 450b) and the spacer wafers (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) are such that each of the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) is covered by the associated voids (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d); d. Remove (725) the carrier substrate (180); and e. In the spacer wafers (150, 450a, 450b), gaps (152, 452a, 452b) are created in such a way that the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) pass through the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b) The one or more gaps (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) in the spacer wafers (150, 450a, 450b) and the gaps (152, 452a, 452b) in the spacer wafers (150, 450a, 450b) are in contact with the external surrounding environment (105) of the coupled wafers (100, 500a, 500b).

2. The method according to claim 1, wherein, After creating (730) the gaps (152, 452a, 452b) in the spacer wafers (150, 450a, 450b), the pad metallization (122, 422a, 422b, 522a, 522b, 622a, 622b, 622c, 622d) is applied (740) to the metal contacts (120, 420a, 420b, 520a, 520b, 622c, 622d). On 0a, 620b, 620c, 620d), wherein, before applying (740) the metallization of the pads (122, 422a, 422b, 522a, 522b, 622a, 622b, 622c, 622d), it is preferable to perform pretreatment of the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d).

3. The method according to claim 2, wherein, After applying the pad metallization (122, 422a, 422b, 522a, 522b, 622a, 622b, 622c, 622d) described in (740), a passivation layer (124), preferably a silicon dioxide layer, is applied to the pad metallization (122, 422a, 422b, 522a, 522b, 622a, 622b, 622c, 622d).

4. The method according to any one of the preceding claims, comprising the following additional steps: - The coupling wafers (100, 500a, 500b) are positioned (745) on the support surface (102) such that only the spacer wafers (150, 450a, 450b) are in contact with the support surface (102); and / or -Release (750) the MEMS structure (144) in the functional layers (140, 440a, 440b), preferably by means of plasma-free and / or plasma-supported etching and / or using SF6, XeF2, ClF3 and / or NF3.

5. The method according to claim 4, wherein, After releasing (750) the MEMS structure (144), it is preferable to remove (755) one or more oxide layers (170, 470a, 470b) from the spacer wafer (150, 450a, 450b) at least partially by means of HF vapor phase etching.

6. The method according to any one of the preceding claims, wherein, Make connections (760) between the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) and one or more components and / or a component wafer (104).

7. The method according to any one of the preceding claims, wherein, The silicon layer (160, 460a, 460b) includes one or more additional trenches (167) filled with a second insulating material, wherein each of the one or more additional trenches (167) surrounds a trench (166, 466a, 466b) surrounding a void (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) in the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 692c, 692d).

8. The method according to any one of the preceding claims, wherein, The trenches (166, 466a, 466b): - An inner wall (467a) having an inner wall (467a) that is parallel to and perpendicular to the second surfaces (164, 464a) of the silicon layers (160, 460a); or - Inner walls (467b) having a second surface (464b) that is not parallel to each other and is inclined to the silicon layer (460b), wherein the spacing between the inner walls (467b) increases or decreases as the spacing with respect to the second surface (464b) increases.

9. The method according to any one of the preceding claims, wherein, At least one of the one or more voids (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) in the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 692c, 692d), preferably each void having a rectangular bottom surface, a circular bottom surface, or a hexagonal bottom surface.

10. The method according to any one of the preceding claims, wherein, Providing the spacer holding wafer (150, 450a, 450b) as described in (715) includes the following steps: - Provide a silicon wafer including the carrier substrate (180), partially oxidize the silicon wafer to form the first oxide layer (170, 470a, 470b) on the surface (184) of the carrier substrate (180), and grow the silicon layer (160, 460a, 460b) on the first oxide layer (170, 470a, 470b), preferably as an epitaxial polycrystalline silicon layer; or A raw wafer is provided, the raw wafer comprising the carrier substrate (180), a first oxide layer (170, 470a, 470b) on the surface (184) of the carrier substrate (180), and a silicon layer (160, 460a, 460b) on the first oxide layer (170, 470a, 470b). - The trenches (166, 466a, 466b) are formed in the silicon layers (160, 460a, 460b). - A second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) is formed on the second surface (164, 464a, 464b) of the silicon layers (160, 460a, 460b), and the trenches (166, 466a, 466b) are filled with the passivation material; and - Partially remove the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) to create one or more voids (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) in the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d). The trenches (166, 466a, 466b) are formed, and the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) are removed, such that the one or more voids (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) are surrounded by one of the trenches (166, 466a, 466b), and the one or more voids (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) are arranged and configured such that, in the One or more gaps (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) are associated with the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d), and all the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) can be covered by the gaps (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) respectively associated with the metal contacts.

11. A coupled wafer (100, 500a, 500b), preferably manufactured by the method according to any one of claims 1 to 10, the coupled wafer comprising: - A functional wafer (110, 410a, 410b) having functional layers (140, 440a, 440b), passivation layers (130, 430a, 430b), and metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d), wherein the passivation layers (130, 430a, 430b) and the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) are disposed on the surface (142) of the functional layers (140, 440a, 440b); and - Spacer wafers (150, 450a, 450b), wherein the spacer wafers (150, 450a, 450b) include a silicon layer (160, 460a, 460b) having trenches (166, 466a, 466b) filled with passivation material, a first oxide layer (170, 470a, 470b) on a first surface (162) of the silicon layer (160, 460a, 460b), and a spacer wafer (150, 450a, 450b) on the silicon layer (160, 460a, 460b). b) A second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) on a second surface (164, 464a, 464b) opposite to the first surface (162) and a carrier substrate (180) disposed on the first oxide layer (170, 470a, 470b), wherein the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) 0c, 80d) have one or more gaps (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d), which are respectively surrounded by one of the grooves (166, 466a, 466b) and are arranged and configured such that the metal contact (12) is between the one or more gaps (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) and the metal contact (12). A relationship of attribution is formed between 0, 420a, 420b, 520a, 520b, 620a, 620b, 620c, and 620d, and all metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, and 620d) can be covered by the gaps (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, and 692d) respectively assigned to the metal contacts. In this configuration, the passivation layers (130, 430a, 430b) of the functional wafers (110, 410a, 410b) are connected to the second oxide layers (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) of the spacer wafers (150, 450a, 450b) such that each metal contact (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) is covered by the corresponding voids (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d), and also within the spacer wafers (150, 450a, 450b). The existence of gaps (152, 452a, 452b) allows the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) to be in contact with the external environment (105) of the coupled wafers (100, 500a, 500b, 60c, 80d) via one or more gaps (192, 492a, 492b, 592a, 592b, 692a, 692b, 60c, 80d) in the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) and the gaps (152, 452a, 452b) in the spacer wafers (150, 450a, 450b).

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