Liquid ejecting apparatus and capacitive load driving circuit

Abstract

The invention relates to a liquid ejecting apparatus and a capacitive load driving circuit. In a liquid ejecting apparatus, a capacitive load drive circuit that outputs a drive signal for displacing a capacitive load includes: a first gate drive circuit that outputs a first gate drive signal corresponding to a modulation signal output by a modulation circuit; a second gate driving circuit outputting a second gate driving signal corresponding to the modulation signal; an amplifier circuit that outputs an amplified modulation signal by driving a first transistor driven according to the first gate drive signal and a second transistor driven according to the second gate drive signal; and a demodulation circuit that outputs a drive signal obtained by demodulating the amplified and modulated signal, the first transistor and the second transistor including gallium nitride, and the first gate drive circuit and the first transistor are housed in one package and constitute a first semiconductor device. The second gate drive circuit and the second transistor are accommodated in a package and constitute a second semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to a liquid ejecting apparatus and a capacitive load driving circuit. BACKGROUND

[0002] In a liquid ejecting apparatus that ejects liquid by driving a capacitive load such as a piezoelectric element, as a capacitive circuit driving circuit that outputs a driving signal that drives a capacitive load, a so-called D-class amplification circuit structure is known in which a driving signal is generated by modulating a signal waveform specified by a base driving signal that is a basis of the driving signal, amplifying the modulated signal, and demodulating the amplified signal. In a capacitive load driving circuit using such a D-class amplification circuit, compared to a capacitive load driving circuit using an A-class amplification circuit, a B-class amplification circuit, and an AB-class amplification circuit, there is an advantage that power consumption can be reduced.

[0003] For example, in Patent Literature 1, a liquid ejecting apparatus is disclosed that has a driving signal output circuit that is a capacitive load driving circuit that outputs a driving signal that drives a piezoelectric element that is a capacitive load, and includes a D-class amplification circuit.

[0004] Patent Literature 1: Japanese Patent Application Publication No. 2022-117051

[0005] With the recent rise in market demand for increased productivity of liquid ejecting apparatuses, in liquid ejecting apparatuses, shortening of the ejection period of liquid, that is, high frequency of a driving signal that drives a capacitive load to eject liquid, is being sought.

[0006] However, in a liquid ejecting apparatus as described in Patent Literature 1, in the case where the frequency of a driving signal output by a capacitive load driving circuit (driving signal output circuit) that includes a D-class amplification circuit is made high speed, it is necessary to increase the driving frequency of an amplification circuit that amplifies a modulated signal that is modulated from a signal waveform specified by a base driving signal, and in the case where the driving frequency of the amplification circuit is increased, loss in the amplification circuit increases, and one of the advantages of a capacitive load driving circuit using a D-class amplification circuit that can reduce power consumption can be impaired.

[0007] In particular, in a case where the liquid ejecting apparatus is configured to drive a capacitive load by a drive signal and to control the position of a meniscus of an ejecting portion by the driving of the capacitive load, thereby controlling the ejection amount of liquid, since the waveform accuracy of the drive signal greatly contributes to the ejection accuracy of liquid, a drive signal including a signal waveform in which a voltage value sharply changes is sought to be output with high waveform accuracy in the capacitive load driving circuit. Therefore, in order to realize the high frequency of the drive signal while maintaining the high waveform accuracy, it is necessary to further increase the driving frequency of an amplification circuit which the capacitive load driving circuit has, as a result, the loss in the amplification circuit further increases, and the power consumption of the capacitive load driving circuit further increases.

[0008] That is, in the viewpoint of increasing the frequency of the drive signal output by the capacitive load driving circuit using the Class-D amplification circuit, the technology described in Patent Document 1 is not sufficient, and there is room for further improvement. SUMMARY

[0009] A liquid ejecting apparatus according to an embodiment of the present application includes:

[0010] a capacitive load that is displaced by being supplied with a drive signal;

[0011] an ejecting portion that ejects liquid in accordance with the displacement of the capacitive load; and

[0012] a capacitive load driving circuit that outputs the drive signal,

[0013] the capacitive load driving circuit includes:

[0014] a modulation circuit that outputs a modulation signal obtained by modulating a base drive signal that is a basis of the drive signal;

[0015] a first gate driving circuit that outputs a first gate drive signal corresponding to the modulation signal;

[0016] a second gate driving circuit that outputs a second gate drive signal corresponding to the modulation signal;

[0017] an amplification circuit including a first transistor that is driven in accordance with the first gate drive signal and a second transistor that is driven in accordance with the second gate drive signal, the amplification circuit outputting an amplified modulation signal by driving the first transistor and the second transistor; and

[0018] a demodulation circuit that outputs the drive signal obtained by demodulating the amplified modulation signal,

[0019] the first transistor includes gallium nitride,

[0020] The second transistor includes gallium nitride,

[0021] The first gate drive circuit and the first transistor are housed in one package and constitute a first semiconductor device,

[0022] The second gate drive circuit and the second transistor are housed in one package and constitute a second semiconductor device.

[0023] One embodiment of a capacitive load drive circuit according to the present application is,

[0024] The capacitive load drive circuit outputs a drive signal to a capacitive load that is displaced by being supplied with the drive signal to eject liquid from an ejection portion, and has:

[0025] A modulation circuit that outputs a modulation signal obtained by modulating a base drive signal that is a basis of the drive signal;

[0026] A first gate drive circuit that outputs a first gate drive signal corresponding to the modulation signal;

[0027] A second gate drive circuit that outputs a second gate drive signal corresponding to the modulation signal;

[0028] An amplification circuit that includes a first transistor driven in accordance with the first gate drive signal and a second transistor driven in accordance with the second gate drive signal, and outputs an amplified modulation signal through driving of the first transistor and the second transistor; and

[0029] A demodulation circuit that outputs the drive signal obtained by demodulating the amplified modulation signal,

[0030] The second transistor includes gallium nitride,

[0031] The second transistor includes gallium nitride,

[0032] The first gate drive circuit and the first transistor are housed in one package and constitute a first semiconductor device,

[0033] The second gate drive circuit and the second transistor are housed in one package and constitute a second semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 FIG. 1 is a diagram showing an example of a schematic configuration of a liquid ejection apparatus.

[0035] Figure 2 FIG. 2 is a diagram showing an example of a functional configuration of a liquid ejection apparatus.

[0036] Figure 3 is a diagram showing a simple configuration of one of the ejection portions 600.

[0037] Figure 4 is a diagram showing an example of signal waveforms of the drive signals COMA, COMB, and COMC.

[0038] Figure 5 is a diagram showing an example of the structure of the selection control circuit and the selection circuit.

[0039] Figure 6 is a diagram showing an example of the decoding contents in the decoder.

[0040] Figure 7 is a diagram showing an example of the structure of the selection circuit.

[0041] Figure 8 is a diagram for explaining the operation of the selection control circuit and the selection circuit.

[0042] Figure 9 is a diagram showing an example of the structure of the drive circuit.

[0043] Figure 10 is a diagram showing an example of the configuration of the transistor M1.

[0044] Figure 11 is a diagram showing an example of the structure of the drive circuit of the second embodiment.

[0045] Figure 12 is a diagram showing an example of the structure of the drive circuit of the third embodiment.

[0046] Explanation of Reference Numerals

[0047] 1 liquid ejecting apparatus, 2 ink container, 10 control unit, 20 head unit, 21 carriage, 30 moving unit, 31 carriage motor, 32 endless belt, 40 conveying unit, 41 conveying motor, 42 conveying roller, 50, 50a, 50b, 50c drive circuit, 52 reference voltage output circuit, 60 piezoelectric element, 100 control circuit, 210 selection control circuit, 212 shift register, 214 latch circuit, 216 decoder, 230 selection circuit, 232a, 232b, 232c inverter, 234a, 234b, 234c transmission gate, 500, 500a, 500b integrated circuit device, 510 modulation circuit, 512, 513 adder, 514 comparator, 515 inverter, 516 integral attenuator, 517 attenuator, 520 gate driver circuit, 521, 522 gate driver, 550 amplification circuit, 560 demodulation circuit, 570, 572 feedback circuit, 600 ejecting portion, 601 piezoelectric body, 611, 612 electrode, 621 vibration plate, 631 cavity, 632 nozzle plate, 641 reservoir, 651 nozzle, 661 supply port, 701 to 705 layer, 710 semiconductor substrate, 720 buffer layer, 730 electron transport layer, 740 electron supply layer, 750 gate layer, 760 source electrode, 770 gate electrode, 780 drain electrode, 790 two-dimensional electron gas, C1 to C5 capacitor, D1 diode, L1 coil, M1, M2 transistor, P dielectric, R1 to R6 resistor. DETAILED DESCRIPTION

[0048] Hereinafter, a preferred embodiment of the present application will be described with reference to the accompanying drawings. The drawings used herein are for the purpose of illustration only. It is noted that the embodiments described below do not limit the present application in any manner. In addition, not all of the structures described below are essential components of the present application.

[0049] 1. First Embodiment

[0050] 1.1 Overview of Liquid Ejecting Apparatus

[0051] Figure 1is an example of a schematic configuration of a liquid ejecting apparatus 1. The liquid ejecting apparatus 1 is an inkjet printer of a serial printing method that forms a desired image on a medium P by reciprocating a carriage 21 on which a head unit 20 that ejects ink as an example of a liquid is mounted along a scanning axis, and ejecting ink onto the medium P that is transported along a transport direction. As the medium P used by such a liquid ejecting apparatus 1, any printing object such as a printing paper, a resin film, cloth, or the like can be used. Note that the liquid ejecting apparatus 1 is not limited to an inkjet printer of a serial printing method, and can be an inkjet printer of a line printing method. In addition, the liquid ejecting apparatus 1 is not limited to an inkjet printer, and can be a color material ejecting apparatus used in the manufacture of a color filter of a liquid crystal display or the like, an electrode material ejecting apparatus used in the formation of an electrode of an organic EL display, a FED (Field Emission Display), or the like, a biological organic material ejecting apparatus used in the manufacture of a biochip, a stereolithography apparatus, a dyeing apparatus, or the like.

[0052] As shown in Figure 1 , the liquid ejecting apparatus 1 includes an ink container 2, a control unit 10, the head unit 20, a moving unit 30, and a transport unit 40.

[0053] A plurality of kinds of ink to be ejected to the medium P is stored in the ink container 2. As the color of the ink stored in the ink container 2, black, cyan, magenta, yellow, red, gray, or the like can be cited. As the ink container 2 in which such ink is stored, an ink cartridge, a bag-shaped ink bag formed of a flexible film, an ink tank that enables replenishment of ink, or the like can be used.

[0054] The control unit 10 includes, for example, a processing circuit such as a CPU (Central Processing Unit), an FPGA (Field Programmable Gate Array), a storage circuit such as a semiconductor memory, and other various circuits, and controls each element of the liquid ejecting apparatus 1 including the head unit 20.

[0055] The head unit 20 is mounted on the carriage 21. In addition, the carriage 21 is fixed to a ring-shaped belt 32 included in the moving unit 30. Note that the ink container 2 can be mounted on the carriage 21 in addition to the head unit 20.

[0056] A control signal Ctrl-H for controlling the head unit 20, which is output by the control unit 10, is input to the head unit 20 mounted on the carriage 21. In addition, ink stored in the ink container 2 is supplied to the head unit 20 via a pipe not shown. Then, the head unit 20 ejects the ink supplied from the ink container 2 based on the input control signal Ctrl-H.

[0057] The moving unit 30 includes a carriage motor 31 and a ring belt 32. The carriage motor 31 is driven based on a control signal Ctrl-C input from the control unit 10. The ring belt 32 rotates with the driving of the carriage motor 31. Thereby, the carriage 21 fixed to the ring belt 32 moves reciprocally along a scan axis. That is, the liquid discharge device 1 is provided with the carriage 21 that moves reciprocally along the scan axis, which intersects with a transport direction of the medium P on which the ink discharged from the head unit 20 lands, described later.

[0058] The transport unit 40 includes a transport motor 41 and a transport roller 42. The transport motor 41 is driven based on a control signal Ctrl-T input from the control unit 10. The transport roller 42 rotates with the driving of the transport motor 41. With the rotation of the transport roller 42, the medium P is transported in a transport direction.

[0059] In the liquid discharge device 1 configured as described above, in conjunction with the transport of the medium P based on the transport unit 40 and the reciprocating movement of the carriage 21 based on the moving unit 30, the head unit 20 mounted on the carriage 21 discharges the ink to the medium P. Thereby, the ink discharged from the head unit 20 lands on an arbitrary position of the surface of the medium P. As a result, a desired image is formed on the medium P.

[0060] A specific example of the functional structure of the liquid discharge device 1 configured as described above is described. Figure 2 is a diagram showing an example of the functional structure of the liquid discharge device 1. As shown in Figure 2 The liquid discharge device 1 has a control unit 10, a head unit 20, a moving unit 30, and a transport unit 40.

[0061] The control unit 10 has a control circuit 100.

[0062] The control circuit 100 generates various control signals corresponding to an image signal input from an external device such as a host computer, and outputs to the corresponding structures, by inputting the image signal from the external device.

[0063] Specifically, the control circuit 100 generates the control signal Ctrl-T and the control signal Ctrl-C by performing a printing process to the medium P by being input with an image signal. The control signal Ctrl-T output from the control circuit 100 is input to the conveyance motor 41 included in the conveyance unit 40. The conveyance motor 41 is driven in accordance with the control signal Ctrl-T. The medium P is conveyed in the conveyance direction by the driving force of the conveyance motor 41. In addition, the control signal Ctrl-C output from the control circuit 100 is input to the carriage motor 31 included in the movement unit 30. The carriage motor 31 is driven in accordance with the control signal Ctrl-C. The carriage 21 on which the head unit 20 is mounted reciprocates along the scanning axis by the driving force of the carriage motor 31. Note that the conveyance unit 40 can include one or more conveyance rotors in addition to the conveyance motor 41. In addition, the conveyance unit 40 can include a conveyance motor driver circuit for converting the control signal Ctrl-T into a predetermined signal for driving the conveyance motor 41. In addition, the movement unit 30 can include a carriage motor driver circuit for converting the control signal Ctrl-C into a predetermined signal for driving the carriage motor 31.

[0064] In addition, the control circuit 100 generates the clock signal SCK, the print data signal SI, the latch signal LAT, and the digital base driving signals dA, dB, and dC as the control signal Ctrl-H on the basis of an image signal input from an external device, and outputs them to the head unit 20.

[0065] The head unit 20 includes the driving circuits 50a, 50b, 50c, a reference voltage output circuit 52, a selection control circuit 210, a plurality of selection circuits 230, and a plurality of ejection portions 600. In addition, the plurality of ejection portions 600 are provided corresponding to each of the plurality of selection circuits 230.

[0066] In other words, the carriage 21 mounts the head unit 20 including the piezoelectric element 60, the ejection portion 600, and the driving circuits 50a, 50b, 50c.

[0067] The base drive signal dA is input to the drive circuit 50a. The drive circuit 50a generates and outputs a drive signal COMA as the drive signal COM by performing digital / analog conversion on the input base drive signal dA and performing D-stage amplification on the converted analog signal. The base drive signal dB is input to the drive circuit 50b. The drive circuit 50b generates and outputs a drive signal COMB as the drive signal COM by performing digital / analog conversion on the input base drive signal dB and performing D-stage amplification on the converted analog signal. The base drive signal dC is input to the drive circuit 50c. The drive circuit 50c generates and outputs a drive signal COMC as the drive signal COM by performing digital / analog conversion on the input base drive signal dC and performing D-stage amplification on the converted analog signal.

[0068] The reference voltage output circuit 52 generates and outputs a constant direct current voltage, i.e., a reference voltage signal VBS, having a voltage value of 5.5 V, 6 V, or the like, by boosting or stepping down a power supply voltage that is not shown. The reference voltage signal VBS functions as a reference potential for driving the piezoelectric element 60 of the ejection section 600 described later. Note that the voltage value of the reference voltage signal VBS is not limited to 5.5 V, 6 V, and can be a ground potential.

[0069] The clock signal SCK, the print data signal SI, and the latch signal LAT are input to the selection control circuit 210. The selection control circuit 210 generates a selection signal S corresponding to each of the plurality of selection circuits 230 based on the input clock signal SCK, print data signal SI, and latch signal LAT, and outputs to the corresponding selection circuit 230.

[0070] The drive signals COMA, COMB, COMC, and the corresponding selection signal S output by the selection control circuit 210 are input to each selection circuit 230. The selection circuit 230 generates a drive signal VOUT corresponding to each of the plurality of ejection sections 600 by setting each of the drive signals COMA, COMB, COMC to selected or non-selected based on the input selection signal S, and supplies to the corresponding ejection section 600.

[0071] The plurality of ejection sections 600 each include a piezoelectric element 60. One end of the piezoelectric element 60 included in each of the plurality of ejection sections 600 is supplied with a drive signal VOUT output by the corresponding selection circuit 230. In addition, the other end of the piezoelectric element 60 included in each of the plurality of ejection sections 600 is commonly supplied with a reference voltage signal VBS output by the reference voltage output circuit 52. Then, the piezoelectric element 60 is driven in accordance with a potential difference between the drive signal VOUT supplied to the one end and the reference voltage signal VBS supplied to the other end. An amount of ink corresponding to the driving of the piezoelectric element 60 is ejected from the ejection section 600.

[0072] Here, an example of the configuration of the ejection section 600 possessed by the head unit 20 will be described. Figure 3 is a diagram showing a brief configuration of one of the plurality of ejection sections 600 possessed by the head unit 20. As shown in Figure 3 , the ejection section 600 includes a piezoelectric element 60, a vibration plate 621, a cavity 631, and a nozzle 651.

[0073] The cavity 631 is filled with ink supplied from an ink reservoir 641. In addition, ink is introduced to the ink reservoir 641 from the ink container 2 via an unillustrated ink tube and a supply port 661. That is, the cavity 631 is filled with ink stored in the corresponding ink container 2.

[0074] The vibration plate 621 is displaced due to the driving of the piezoelectric element 60 provided on the upper surface in Figure 3 . Also, as the vibration plate 621 is displaced, the internal volume of the cavity 631 filled with ink expands and contracts. That is, the vibration plate 621 functions as a diaphragm that changes the internal volume of the cavity 631.

[0075] The nozzle 651 is provided to a nozzle plate 632, and is an aperture that communicates with the cavity 631. By the internal volume of the cavity 631 changing, an amount of ink corresponding to the change in the internal volume is ejected from the nozzle 651.

[0076] The piezoelectric element 60 is of a configuration in which a piezoelectric body 601 is sandwiched by a pair of electrodes 611, 612. The piezoelectric body 601 of such a configuration flexes the central portion of the electrodes 611, 612 together with the vibration plate 621 in the up-and-down direction in accordance with a potential difference of a signal supplied to the electrodes 611, 612.

[0077] For example, a drive signal VOUT is supplied to one end of the piezoelectric element 60, i.e., one of electrodes 611 and 612, and a reference voltage signal VBS is supplied to the other end of the piezoelectric element 60, i.e., the other of electrodes 611 and 612. If the voltage value of the drive signal VOUT increases, the piezoelectric element 60 flexes upward. Furthermore, by flexing the piezoelectric element 60 upward, the vibrating plate 621 is displaced, and the internal volume of the cavity 631 expands. As a result, ink is introduced from the reservoir 641. On the other hand, if the voltage value of the drive signal VOUT decreases, the piezoelectric element 60 flexes downward. Furthermore, by flexing the piezoelectric element 60 downward, the vibrating plate 621 is displaced, and the internal volume of the cavity 631 shrinks. As a result, an amount of ink corresponding to the degree of shrinkage is ejected from the nozzle 651.

[0078] That is, the ejection section 600 includes a piezoelectric element 60 driven by a drive signal VOUT based on the drive signal COM, and ink is ejected by being driven by the piezoelectric element 60. In other words, the head unit 20 ejects ink according to the drive signals COMA, COMB, and COMC.

[0079] In this embodiment of the liquid ejection device 1, from the viewpoint of increasing the speed of image formation on the medium P, i.e., increasing the productivity of the liquid ejection device 1, it is assumed that the head unit 20 has more than 3,000 ejection sections 600, and the drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC to more than 3,000 ejection sections 600. That is, it is assumed that the head unit 20 has more than 3,000 piezoelectric elements 60, and the drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC to more than 3,000 piezoelectric elements 60. As a result, the amount of ink that can be ejected at one time, i.e., the number of dots that can be formed on the medium P at one time, increases, thereby increasing the speed of image formation on the medium P, i.e., increasing the productivity of the liquid ejection device 1. In other words, the head unit 20 includes more than 3,000 piezoelectric elements 60, and these more than 3,000 piezoelectric elements 60 are driven by the drive signal COM output by the drive circuit 50.

[0080] It should be noted that the construction of the piezoelectric element 60 is not limited to... Figure 3 The example shown is one that can eject ink from the ejection section 600. Therefore, the structure of the piezoelectric element 60 is not limited to the bending vibration structure described above; for example, it could also be a structure using longitudinal vibration. Furthermore, the piezoelectric element 60 could also be structured such that it flexes downwards when the voltage value of the drive signal VOUT increases, and flexes upwards when the voltage value of the drive signal VOUT decreases.

[0081] As above, the liquid ejecting apparatus 1 of the present embodiment has: the piezoelectric element 60 that is displaced by being supplied with the drive signal VOUT based on the drive signals COMA, COMB, COMC; the ejecting section 600 that ejects ink in accordance with the displacement of the piezoelectric element 60; the drive circuit 50a that outputs the drive signal COMA, the drive circuit 50b that outputs the drive signal COMB, and the drive circuit 50c that outputs the drive signal COMC.

[0082] 1.2 Signal waveforms of drive signals

[0083] Next, an example of the respective signal waveforms of the drive signals COMA, COMB, COMC output by the drive circuits 50a, 50b, 50c will be described. Figure 4 is a view that shows an example of the signal waveforms of the drive signals COMA, COMB, COMC. As shown in Figure 4 each of the drive signals COMA, COMB, COMC includes a drive waveform Adp, Bdp, Cdp that is arranged within a period tp from the rise of a latch signal LAT to the rise of the next latch signal LAT. Also, the selection control circuit 210 and the selection circuit 230 select any one of the drive signals COMA, COMB, COMC, that is, any one of the drive waveforms Adp, Bdp, Cdp, and output it as the drive signal VOUT based on the clock signal SCK and the print data signal SI within each period tp.

[0084] As shown in Figure 4 the drive waveform Adp drives the corresponding piezoelectric element 60 by changing the voltage value between the voltage va1 and the voltage va5 within the period tp. By the driving of this piezoelectric element 60, a predetermined amount of ink is ejected from the corresponding nozzle 651. That is, the drive waveform Adp included in the drive signal COMA is a signal waveform for driving the corresponding piezoelectric element 60 so that a predetermined amount of ink is ejected from the ejecting section 600. Here, in the following description, it is assumed that the voltage va1 is 36 V, the voltage va2 is 15 V, the voltage va3 is 12 V, the voltage va4 is 8 V, and the voltage va5 is 5 V, but the values of the voltage va1 to the voltage va5 are not limited thereto.

[0085] Specifically, at the timing of the start of the period tp at which the latch signal LAT rises, the voltage value of the drive waveform Adp becomes constant at the voltage va3. Thereafter, the voltage value of the drive waveform Adp starts to rise at the time ta1, and becomes constant at the voltage vai at the time ta2. Then, the voltage value of the drive waveform Adp starts to decrease at the time ta3, and becomes constant at the voltage va2 at the time ta4, and then starts to decrease again at the time tas, and becomes constant at the voltage va5 at the time ta6. Thereafter, the voltage value of the drive waveform Adp starts to rise at the time ta7, and becomes constant at the voltage va4 at the time ta8, and then starts to rise again at the time ta9, and becomes constant at the voltage va3 at the time taio. Thereafter, the latch signal LAT rises, and thus the period tp ends.

[0086] In the ejection section 600 to which the above drive waveform Adp is supplied, at the timing at which the latch signal LAT rises, the ink stored in the ink container 2 is supplied to the chamber 631 via the supply port 661. At this time, the position of the tip end portion of the ink stored in the interior of the nozzle 651 possessed by the ejection section 600, that is, the position of the meniscus in the nozzle 651, becomes substantially the same position as the position of the tip end of the nozzle 651. Then, at the time ta1, if the voltage value of the drive waveform Adp rises, in the ejection section 600 to which the drive waveform Adp is supplied, the piezoelectric element 60 is deflected in the upward direction as shown by the arrow, and the internal volume of the chamber 631 increases. Thus, the ink stored in the interior of the nozzle 651 possessed by the ejection section 600 is introduced into the chamber 631, and the position of the meniscus in the nozzle 651 moves in the upward direction as shown by the arrow. Figure 3 Figure 3

[0087] Thereafter, at the time ta2, the position of the meniscus in the nozzle 651 possessed by the ejection section 600 is maintained by the voltage value of the drive waveform Adp becoming constant, and then, at the time ta3, if the voltage value of the drive waveform Adp decreases, in the ejection section 600 to which the drive waveform Adp is supplied, the piezoelectric element 60 is deflected in the downward direction as shown by the arrow, and the internal volume of the chamber 631 decreases. Thus, the ink stored in the chamber 631 is pressurized, and moves toward the corresponding nozzle 651. At this time, the central portion of the meniscus formed by the ink stored in the interior of the nozzle 651 is pushed out, and a liquid column extending in the downward direction as shown by the arrow is formed. Figure 3 Figure 3

[0088] At the time ta4, if the voltage value of the drive waveform Adp becomes constant, the liquid column formed in the central portion of the meniscus desires to move in the upward direction as shown by the arrow due to the inertial force, but the liquid column is restrained by the wall surface of the chamber 631, and thus the liquid column is maintained in the downward direction as shown by the arrow. Figure 3 ​​​​The curve extends downwards as shown. Then, at time ta5, the voltage value of the driving waveform Adp decreases, the internal volume of cavity 631 decreases, thereby pressurizing the ink stored in cavity 631. As a result, the ink separates from the liquid column and is ejected as droplets.

[0089] Subsequently, at time ta6, the voltage value of the driving waveform Adp becomes constant, and from time ta7 to time ta10, the voltage value of the driving waveform Adp increases until the voltage va3 becomes constant. As a result, the displacement of the piezoelectric element 60 in the ejector section 600 supplied with the driving waveform Adp, and the internal volume of the cavity 631, become a state where the latch signal LAT rises. At this time, an amount of ink corresponding to the amount of ink ejected is supplied from the ink container 2 to the cavity 631 via the supply port 661 through capillary action. Therefore, at the timing of the rise of the latch signal LAT, the position of the meniscus in the nozzle 651 of the ejector section 600 becomes approximately the same as the position of the tip of the nozzle 651.

[0090] In addition, such as Figure 4 As shown, the driving waveform Bdp drives the corresponding piezoelectric element 60 by varying the voltage value between voltages vb1 and vb5 within the period tp. Driven by this piezoelectric element 60, a smaller amount of ink than the predetermined amount is ejected from the corresponding nozzle 651. That is, the driving waveform Bdp included in the driving signal COMB is a signal waveform used to drive the corresponding piezoelectric element 60 so that a smaller amount of ink is ejected from the ejection section 600 than the predetermined amount. In the following description, voltages vb1 are assumed to be 36V, voltage vb2 to be 20V, voltage vb3 to be 12V, voltage vb4 to be 10V, and voltage vb5 to be 7V, but the values ​​of voltages vb1 to vb5 are not limited to these values.

[0091] Specifically, at the timing of the rise of the latch signal LAT, i.e., the start of period tp, the voltage value of the drive waveform Bdp becomes constant at voltage vb3. Then, the voltage value of the drive waveform Bdp begins to rise at time tb1, and becomes constant at voltage vb1 at time tb2. Next, the voltage value of the drive waveform Bdp begins to decrease at time tb3, becomes constant at voltage vb4 at time tb4, begins to rise at time tb5, becomes constant at voltage vb2 at time tb6, then begins to decrease at time tb7, and becomes constant at voltage vb5 at time tb8. Then, the voltage value of the drive waveform Bdp begins to rise at time tb9, and becomes constant at voltage vb3 at time tb10. Afterwards, the latch signal LAT rises, thus ending period tp.

[0092] In the ejector section 600 supplied with the aforementioned drive waveform Bdp, at the timing of the rise of the latch signal LAT, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the tip of the ink stored inside the nozzle 651 of the ejector section 600, i.e., the position of the meniscus in the nozzle 651, becomes approximately the same as the position of the tip of the nozzle 651. Then, at time tb1, if the voltage value of the drive waveform Bdp rises, the piezoelectric element 60 propels the ink towards the ejector section 600 supplied with the drive waveform Bdp. Figure 3 As shown, the upward flexing increases the internal volume of cavity 631. Consequently, the ink stored inside the nozzle 651 of the ejection section 600 is introduced into cavity 631, and the position of the meniscus in nozzle 651 is towards... Figure 3 It moves upwards as shown.

[0093] Then, at time tb2, the voltage value of the driving waveform Bdp becomes constant, thereby maintaining the position of the meniscus in the nozzle 651 of the ejection section 600. Then, at time tb3, if the voltage value of the driving waveform Bdp decreases, the piezoelectric element 60 in the ejection section 600 supplied with the driving waveform Bdp... Figure 3 As shown, the downward flexing reduces the internal volume of cavity 631. Consequently, the ink stored in cavity 631 is pressurized and moves towards the corresponding nozzle 651. At this time, the central portion of the meniscus formed by the ink stored inside nozzle 651 is pushed out, forming a... Figure 3 The liquid column extends downwards as shown.

[0094] At time tb4, if the voltage value of the driving waveform Bdp becomes constant, the liquid column formed in the center of the meniscus will tend to move towards the center due to inertial force. Figure 3 The downward extension is shown. Furthermore, at time tb5, if the voltage value of the driving waveform Bdp increases, the internal volume of cavity 631 increases, and due to inertial force, it will tend to extend downwards. Figure 3 A downward-extending liquid column is introduced. At time tb6, after the voltage value of the driving waveform Bdp becomes constant, at time tb7, the voltage value of the driving waveform Bdp decreases, thereby reducing the internal volume of cavity 631. The ink stored in cavity 631 is pressurized, and the ink separates from the liquid column, being ejected as droplets. At this time, at time tb5, due to inertial force, it tends to... Figure 3 After the downward-extending liquid column shown is introduced, at time tb7, the ink droplets separated from the liquid column by pressure are ejected, so that the amount of ink ejected from the ejection section 600 supplied with the driving waveform Bdp is less than the amount of ink ejected from the ejection section 600 supplied with the driving waveform Adp.

[0095] Subsequently, at time tb8, the voltage value of the driving waveform Bdp becomes constant, and at times tb9-tb10, the voltage value of the driving waveform Bdp rises until voltage vb3 becomes constant. As a result, the displacement of the piezoelectric element 60 in the ejector section 600, which is supplied with the driving waveform Bdp, and the internal volume of the cavity 631 reach a state where the latch signal LAT rises. At this time, an amount of ink corresponding to the amount of ink ejected is supplied from the ink container 2 to the cavity 631 via the supply port 661 through capillary action. Therefore, at the timing of the rise of the latch signal LAT, the position of the meniscus in the nozzle 651 of the ejector section 600 becomes approximately the same as the position of the tip of the nozzle 651.

[0096] In addition, such as Figure 4 As shown, the driving waveform Cdp drives the corresponding piezoelectric element 60 by varying the voltage value between voltage vc1 and voltage vc2 within the period tp. Driven by this piezoelectric element 60, ink is not ejected from the corresponding nozzle 651, and the ink near the opening of the nozzle 651 vibrates. This reduces the risk of increased viscosity of the ink near the opening of the nozzle 651. In other words, the driving waveform Cdp included in the driving signal COMC is a signal waveform used to drive the piezoelectric element 60 to cause the ink near the opening of the nozzle 651 of the ejection section 600 to vibrate when no ink is ejected from the ejection section 600. Here, in the following description, voltage vc1 is assumed to be 15V and voltage vc2 to be 12V, but the values ​​of voltage vc1 and voltage vc2 are not limited to these values.

[0097] Specifically, at the timing of the rise of the latch signal LAT, which is the beginning of period tp, the voltage value of the drive waveform Cdp becomes constant at voltage vc2. Then, the voltage value of the drive waveform Cdp begins to rise at time tc1 and becomes constant at voltage vc1 at time tc2. Next, the voltage value of the drive waveform Cdp begins to decrease at time tc3 and becomes constant at voltage vc1 at time tc4. Afterwards, the latch signal LAT rises, thus ending period tp.

[0098] In the ejector section 600 supplied with the aforementioned drive waveform Cdp, at the timing of the rise of the latch signal LAT, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the tip of the ink stored inside the nozzle 651 of the ejector section 600, i.e., the position of the meniscus in the nozzle 651, becomes approximately the same as the position of the tip of the nozzle 651. Then, at time tc1, if the voltage value of the drive waveform Cdp rises, the piezoelectric element 60 propels the drive waveform Cdp into the ejector section 600 supplied with the drive waveform Cdp. Figure 3The upper direction is deflected as shown, and the internal volume of the chamber 631 increases. Thus, the ink stored in the interior of the nozzle 651 of the ejection section 600, the position of the meniscus in the nozzle 651 being moved toward Figure 3 The upper direction is deflected as shown. Thereafter, at time tc2, the voltage value of the drive waveform Bdp becomes constant, and thus the position of the meniscus in the nozzle 651 of the ejection section 600 is maintained. Thereafter, at time tc3, if the voltage value of the drive waveform Cdp decreases, in the ejection section 600 to which the drive waveform Cdp is supplied, the piezoelectric element 60 is deflected in the lower direction as shown. Figure 3 The upper direction is deflected as shown, and the internal volume of the chamber 631 increases. Thus, the ink stored in the interior of the nozzle 651 of the ejection section 600, the position of the meniscus in the nozzle 651 being moved toward Figure 3 The upper direction is deflected as shown, and the internal volume of the chamber 631 increases. Thus, the ink stored in the interior of the nozzle 651 of the ejection section 600, the position of the meniscus in the nozzle 651 being moved toward

[0099] Further, at time tc4, the voltage value of the drive waveform Cdp becomes constant at voltage vc2, and thus the displacement of the piezoelectric element 60 of the ejection section 600 to which the drive waveform Cdp is supplied and the internal volume of the chamber 631 become the rising state of the latch signal LAT.

[0100] As above, the drive circuit 50a outputs a drive signal COMA including a drive waveform Adp that drives the piezoelectric element 60 to cause a predetermined amount of ink to be ejected from the ejection portion 600, the drive circuit 50b outputs a drive signal COMB including a drive waveform Bdp that drives the piezoelectric element 60 to cause a smaller amount of ink than the predetermined amount to be ejected from the ejection portion 600, and the drive circuit 50c outputs a drive signal COMC including a drive waveform Cdp that drives the piezoelectric element 60 to cause the ink in the vicinity of the opening portion of the corresponding nozzle 651 to vibrate without causing ink to be ejected from the ejection portion 600. In the following description, the amount of ink ejected from the corresponding ejection portion 600 in a case where the drive waveform Adp is supplied to one end of the piezoelectric element 60 is sometimes referred to as a large degree amount, and the amount of ink ejected from the corresponding ejection portion 600 in a case where the drive waveform Bdp is supplied to one end of the piezoelectric element 60 is sometimes referred to as a small degree amount. In addition, the operation of causing the ink in the vicinity of the nozzle opening portion of the corresponding ejection portion 600 to vibrate in a case where the drive waveform Cdp is supplied to one end of the piezoelectric element 60 is sometimes referred to as micro-vibration.

[0101] Here, in the liquid ejection device 1 of the present embodiment, from the viewpoint of improving the speed of forming an image on the medium P, that is, improving the production rate in the liquid ejection device 1, a case is assumed in which the period tp in which ink is ejected from the ejection portion 600 by the drive signals COMA, COMB, and COMC is 10 μs or less. That is, a case is assumed in which the frequency of the drive signals COMA, COMB, and COMC output by the drive circuits 50a, 50b, and 50c, that is, the frequency of the period tp is 100 kHz or more. Thus, in the liquid ejection device 1 of the present embodiment, it is possible to improve the speed of forming an image on the medium P, that is, to improve the production rate in the liquid ejection device 1.

[0102] 1.3 Structure and operation of selection control circuit and selection circuit

[0103] Next, the structure and operation of the selection control circuit 210 and the selection circuit 230 that generate the drive signal VOUT by setting the signal waveforms included in the drive signals COMA, COMB, and COMC to selected or non-selected and output to the corresponding ejection portion 600 will be described. Figure 5 is a view showing an example of the structure of the selection control circuit 210 and the selection circuit 230. Note that in the following description, the 3000 or more piezoelectric elements 60 included in the head unit 20 will be described as n piezoelectric elements 60.

[0104] The selection control circuit 210 is inputted with a clock signal SCK, a print data signal SI, and a latch signal LAT. Further, in the selection control circuit 210, a shift register (S / R) 212, a latch circuit 214, and a group of decoders 216 are provided in correspondence with each of the n piezoelectric elements 60. That is, the selection control circuit 210 includes n shift registers 212, n latch circuits 214, and n decoders 216.

[0105] The print data signal SI is inputted to the selection control circuit 210 in synchronization with the clock signal SCK. Further, the print data signal SI includes 2 bits of print data [SIH, SIL] for selecting any one of the "large dot LD", "small dot SD", "non-recording ND", and "micro-vibration BSD" in series in correspondence with each of the n piezoelectric elements 60. The print data [SIH, SIL] included in the print data signal SI is held in the n shift registers 212 corresponding to the n piezoelectric elements 60. Specifically, the n shift registers 212 corresponding to the piezoelectric elements 60 are cascaded with each other, and the print data signal SI inputted in series is sequentially transferred to the shift register 212 at the next stage in accordance with the clock signal SCK. Then, the print data [SIH, SIL] is held in the corresponding shift register 212, whereby the clock signal SCK is stopped. Thus, the print data [SIH, SIL] included in the print data signal SI is held in the corresponding shift register 212. Note that, in the Figure 5 n shift registers 212, the numbers 1, 2,..., n are sequentially assigned from the upstream side where the print data signal SI is inputted.

[0106] Each of the n latch circuits 214 latches the print data [SIH, SIL] held in the corresponding shift register 212 in conjunction with the rise of the latch signal LAT. Then, the print data [SIH, SIL] latched by the latch circuit 214 is inputted to the corresponding decoder 216. Figure 6 is a view showing an example of the decoding contents in the decoder 216. The decoder 216 outputs selection signals S1, S2, S3 as selection signals S of the logic levels prescribed by the inputted print data [SIH, SIL] in the period tp. For example, in the case where the print data [SIH, SIL] = [1, 0] is inputted to the decoder 216, the decoder 216 outputs the selection signal S1 of the L level, the selection signal S2 of the H level, and the selection signal S3 of the L level in the period tp.

[0107] The selection signals S1, S2, S3 outputted from the decoder 216 are inputted to the selection circuit 230. The selection circuit 230 is provided in correspondence with each of the n ejection portions 600. Figure 7is a diagram showing an example of the structure of the selection circuit 230. As shown in Figure 7 The selection circuit 230 includes inverters 232a, 232b, 232c that are NOT circuits, and transmission gates 234a, 234b, 234c.

[0108] The selection signal S1 is input to the positive control terminal in the transmission gate 234a on which no circle mark is marked, and is also input to the negative control terminal in the transmission gate 234a on which a circle mark is marked after the logic level is inverted by the inverter 232a. In addition, the input terminal of the transmission gate 234a is supplied with the drive signal COMA. Then, the transmission gate 234a sets the input terminal and the output terminal to be conductive in the case where the selection signal S1 of the high level is input, and sets the input terminal and the output terminal to be non-conductive in the case where the selection signal S1 of the low level is input. That is, the transmission gate 234a outputs the drive waveform Adp included in the drive signal COMA from the output terminal in the case where the logic level of the selection signal S1 is the high level, and does not output the drive waveform Adp included in the drive signal COMA from the output terminal in the case where the logic level of the selection signal S1 is the low level.

[0109] The selection signal S2 is input to the positive control terminal in the transmission gate 234b on which no circle mark is marked, and is also input to the negative control terminal in the transmission gate 234b on which a circle mark is marked after the logic level is inverted by the inverter 232b. In addition, the input terminal of the transmission gate 234b is supplied with the drive signal COMB. Then, the transmission gate 234b sets the input terminal and the output terminal to be conductive in the case where the selection signal S2 of the high level is input, and sets the input terminal and the output terminal to be non-conductive in the case where the selection signal S2 of the low level is input. That is, the transmission gate 234b outputs the drive waveform Bdp included in the drive signal COMB from the output terminal in the case where the logic level of the selection signal S2 is the high level, and does not output the drive waveform Bdp included in the drive signal COMB from the output terminal in the case where the logic level of the selection signal S2 is the low level.

[0110] The selection signal S3 is input to the positive control terminal of the transmission gate 234c not marked with a circle mark, and is also input to the negative control terminal of the transmission gate 234c marked with a circle mark after the logic level is inverted by the inverter 232c. In addition, the input terminal of the transmission gate 234c is supplied with the drive signal COMC. Then, the transmission gate 234c makes the input terminal and the output terminal conductive in the case where the selection signal S3 of a high level is input, and makes the input terminal and the output terminal non-conductive in the case where the selection signal S3 of a low level is input. That is, the transmission gate 234c outputs the drive waveform Cdp included in the drive signal COMC from the output terminal in the case where the logic level of the selection signal S3 is a high level, and does not output the drive waveform Cdp included in the drive signal COMC from the output terminal in the case where the logic level of the selection signal S3 is a low level.

[0111] Also, in the selection circuit 230, the output terminal of the transmission gate 234a, the output terminal of the transmission gate 234b, and the output terminal of the transmission gate 234c are commonly connected. The signal at the connection point where the output terminal of the transmission gate 234a, the output terminal of the transmission gate 234b, and the output terminal of the transmission gate 234c are commonly connected is output as the drive signal VOUT.

[0112] Here, the drive signal VOUT is used as the drive signal for driving the piezoelectric element 60. Figure 8 The operation of the selection control circuit 210 and the selection circuit 230 will be described. Figure 8 is a view for explaining the operation of the selection control circuit 210 and the selection circuit 230. The print data signal SI is input to the selection control circuit 210 as a serial signal synchronized with the clock signal SCK, and is sequentially transferred to the n shift registers 212 corresponding to the n piezoelectric elements 60 in synchronization with the clock signal SCK. After that, if the input of the clock signal SCK is stopped, the print data [SIH, SIL] corresponding to each of the n piezoelectric elements 60 is held in the shift registers 212. Note that the print data signal SI is input in the order corresponding to the piezoelectric elements 60 of the n stage, …, 2 stage, 1 stage of the shift registers 212.

[0113] Also, if the latch signal LAT rises, each of the latch circuits 214 latches the print data [SIH, SIL] held in the shift registers 212. Note that the print data [SIH, SIL] is latched by the latch circuit 214 corresponding to the 1 stage, 2 stage, …, n stage of the shift registers 212. Figure 8 The LT1, LT2, …, LTn shown in the drawing show the print data [SIH, SIL] latched by the latch circuit 214 corresponding to the 1 stage, 2 stage, …, n stage of the shift registers 212.

[0114] The decoder 216 outputs selection signals S1, S2, S3 of the logic levels specified by the latched print data [SIH, SIL] for each period tp. Then, the selection circuit 230 sets the drive signals COMA, COMB, COMC to selected or non-selected in accordance with the logic levels of the selection signals S1, S2, S3 output by the decoder 216, thereby generating the drive signal VOUT.

[0115] Specifically, in the case where the print data [SIH, SIL] = [1, 1] is input to the decoder 216, the decoder 216 sets the logic levels of the selection signals S1, S2, S3 for the period tp to the H, L, L levels. Thereby, the selection circuit 230 supplies the drive signal VOUT including the drive waveform Adp to the piezoelectric element 60 possessed by the corresponding ejecting section 600 for the period tp. As a result, a large amount of ink is ejected from the corresponding ejecting section 600. The large amount of ink ejected from the ejecting section 600 lands on the medium P, thereby forming a large dot LD on the medium P.

[0116] In addition, in the case where the print data [SIH, SIL] = [1, 0] is input to the decoder 216, the decoder 216 sets the logic levels of the selection signals S1, S2, S3 for the period tp to the L, H, L levels. Thereby, the selection circuit 230 supplies the drive signal VOUT including the drive waveform Bdp to the piezoelectric element 60 possessed by the corresponding ejecting section 600 for the period tp. As a result, a small amount of ink is ejected from the corresponding ejecting section 600. The small amount of ink ejected from the ejecting section 600 lands on the medium P, thereby forming a small dot SD on the medium P.

[0117] In addition, in the case where the print data [SIH, SIL] = [0, 1] is input to the decoder 216, the decoder 216 sets the logic levels of the selection signals S1, S2, S3 for the period tp to the L, L, L levels. Thereby, the selection circuit 230 does not select any of the drive waveforms Adp, Bdp, Cdp for the period tp. At this time, the piezoelectric element 60 possessed by the corresponding ejecting section 600 is supplied with a signal of a constant voltage value held by the capacitive component of the piezoelectric element 60. That is, the selection circuit 230 supplies the drive signal VOUT of the constant voltage value to the piezoelectric element 60 possessed by the corresponding ejecting section 600 for the period tp. As a result, the piezoelectric element 60 possessed by the corresponding ejecting section 600 is not driven, and no ink is ejected from the ejecting section 600. Thus, no ink lands on the medium P, and no dot is formed on the medium P, and non-recording ND is performed.

[0118] In addition, in a case where the print data [SIH, SIL] = [0, 0] is input to the decoder 216, the decoder 216 sets the logic levels of the selection signals S1, S2, S3 in the period tp to the L, L, H levels. Thereby, the selection circuit 230 supplies the drive signal VOUT including the drive waveform Cdp to the piezoelectric element 60 possessed by the corresponding ejecting portion 600 in the period tp. As a result, the micro-vibration BSD in which the ink in the vicinity of the opening portion of the nozzle 651 possessed by the corresponding ejecting portion 600 is vibrated without ejecting the ink from the corresponding ejecting portion 600 is performed.

[0119] As above, the signal waveforms of the drive signals COMA, COMB, COMC output from the drive circuit 50a, 50b, 50c are set to be selected or non-selected by the selection control circuit 210 and the selection circuit 230, and the drive signal VOUT is generated and output to the piezoelectric element 60 possessed by the corresponding ejecting portion 600.

[0120] 1.4 Structure and operation of drive circuit

[0121] Next, the structure and operation of the drive circuit 50a, 50b, 50c possessed by the liquid ejecting apparatus 1 of the present embodiment will be described. Here, the drive circuits 50a, 50b, 50c are the same structure except for the input signals and the output signals. Therefore, in the following description, the drive circuits 50a, 50b, 50c are not distinguished and are simply referred to as the drive circuit 50. At this time, it is assumed that the base drive signal dO as the base drive signal dA, dB, dC is input to the drive circuit 50, and the drive circuit 50 outputs the drive signal COM as the drive signal COMA, COMB, COMC, and the description will be made.

[0122] Figure 9 is a diagram showing an example of the structure of the drive circuit 50. As shown in Figure 9 , the drive circuit 50 has a DAC (Digital to Analog Converter: digital analog converter) 511, a modulation circuit 510, a gate driver circuit 520, an amplification circuit 550, a demodulation circuit 560, feedback circuits 570, 572, and other circuit elements.

[0123] A digital signal, the base drive signal dO, is input to the DAC511, which defines the waveform of the drive signal COM. The DAC511 converts the input base drive signal dO into a base drive signal aO, which is then output to the modulation circuit 510. The amplified signal of the base drive signal aO output by the DAC511 is equivalent to the drive signal COM. In other words, the base drive signal aO is the target signal before the amplification of the drive signal COM, and the base drive signal dO is the target signal before the amplification of the drive signal COM, and it is a digital signal that defines the shape of the waveform of the drive signal COM. For example, the voltage amplitude of the base drive signal aO output by the DAC511 is set to 1V~2V.

[0124] The modulation circuit 510 generates a modulation signal Ms using the modulation base drive signal aO and outputs it to the gate driver circuit 520. The modulation circuit 510 includes adders 512 and 513, comparator 514, inverter 515, integrator attenuator 516, and attenuator 517.

[0125] The integrator attenuator 516 attenuates and integrates the signal corresponding to the voltage value of the drive signal COM input via the feedback circuit 570 (described later), and outputs the integrated signal to the input terminal on the - side of the adder 512. A base drive signal aO is input to the input terminal on the + side of the adder 512. The adder 512 generates a signal by subtracting the voltage value of the signal input to the - side from the voltage value of the signal input to the + side, and then integrates the result, and outputs this signal to the input terminal on the + side of the adder 513. Here, the maximum value of the voltage amplitude of the base drive signal aO is approximately 2V, as described above; however, the voltage value of the drive signal COM sometimes exceeds 40V at its maximum value. When calculating the deviation, the integrator attenuator 516 attenuates the drive signal COM input via the feedback circuit 570 (described later) to match the range of the voltage amplitude of the base drive signal aO with the range of the voltage amplitude of the drive signal COM.

[0126] The attenuator 517 supplies a voltage after attenuating the high-frequency component of the drive signal COM input via the feedback circuit 572 described later to the -side input terminal of the adder 513. The +side input terminal of the adder 513 is input with the signal output from the adder 512. The adder 513 generates a voltage signal As by subtracting the voltage value of the signal input to the -side input terminal from the voltage value of the signal input to the +side input terminal and outputs it to the comparator 514. That is, the voltage signal As is a signal after subtracting the voltage value of the signal input via the feedback circuit 570 described later from the voltage value of the base drive signal aO and subtracting the voltage value of the signal input via the feedback circuit 572 described later. Therefore, the voltage signal As becomes a signal in which the deviation after subtracting the attenuated voltage of the drive signal COM from the voltage value of the base drive signal aO targeted is corrected with the high-frequency component of the drive signal COM.

[0127] The comparator 514 pulse-modulates the voltage signal As and outputs it as a modulation signal Ms. Specifically, the comparator 514 outputs a modulation signal Ms in which, during the period in which the voltage value of the voltage signal As rises, it becomes an H level if the voltage value of the voltage signal As becomes equal to or higher than a predetermined threshold value Vth1, and, during the period in which the voltage value of the voltage signal As falls, it becomes an L level if the voltage value of the voltage signal As becomes lower than a predetermined threshold value Vth2. Here, the threshold values Vth1, Vth2 are set to a relationship of threshold value Vth1 > threshold value Vth2. The frequency and duty of this modulation signal Ms vary in synchronization with the base drive signals dO, aO. That is, by adjusting the modulation gain corresponding to the sensitivity of the attenuator 517, it is possible to adjust the amount of variation in the frequency and duty of the modulation signal Ms.

[0128] The modulation signal Ms is input to the gate driver 521 included in the gate driver circuit 520. In addition, the modulation signal Ms is also input to the gate driver 522 included in the gate driver circuit 520 after the logic level is inverted by the inverter 515. That is, the gate driver 521 and the gate driver 522 are input with signals whose logic levels become exclusive of each other.

[0129] Here, it can also be that the timing is controlled so that the logic levels of the signals input to the gate drivers 521, 522 do not become H levels at the same time. That is, the above-described "exclusive relationship of the logic levels" means that the logic level of the signal input to the gate driver 521 and the logic level of the signal input to the gate driver 522 do not become H levels at the same time, and includes the case in which the logic level of the signal input to the gate driver 521 and the logic level of the signal input to the gate driver 522 become L levels at the same time.

[0130] The gate driver circuit 520 includes a gate driver 521 and a gate driver 522.

[0131] The gate driver 521 generates and outputs a gate signal Hgd by performing level shifting on the modulation signal Ms output by the comparator 514. The high potential side in the power supply voltage of the gate driver 521 is electrically connected to one end of the capacitor C5 and the cathode of the diode Dl. The other end of the capacitor C5 is electrically connected to the connection point of the source terminal of the transistor Ml and the drain terminal of the transistor M2. The anode of the diode Dl is supplied with a voltage signal Vm of, for example, a direct current voltage of 7.5 V generated by a power supply circuit not shown. Thus, a potential difference approximately equal to the voltage value of the voltage signal Vm is generated across the capacitor C5. The low potential side in the power supply voltage of the gate driver 521 is electrically connected to the connection point of the source terminal of the transistor Ml and the drain terminal of the transistor M2. Thus, the gate driver 521 generates and outputs a gate signal Hgd in which the voltage value of the H level is larger than the voltage value of the connection point of the source terminal of the transistor Ml and the drain terminal of the transistor M2 by the voltage value of the voltage signal Vm, and the voltage value of the L level becomes the voltage value of the connection point of the source terminal of the transistor Ml and the drain terminal of the transistor M2, in accordance with the logic level of the input modulation signal Ms.

[0132] The gate driver 522 operates at a lower potential side than the gate driver 521. The gate driver 522 generates and outputs a gate signal Lgd by performing level shifting on a signal in which the logic level of the modulation signal Ms output by the comparator 514 is inverted by the inverter 515. The high potential side in the power supply voltage of the gate driver 522 is supplied with the voltage signal Vm, and the low potential side in the power supply voltage of the gate driver 522 is supplied with the ground potential. Thus, the gate driver 522 generates and outputs a gate signal Lgd in which the voltage value of the H level is the voltage value of the voltage signal Vm and the voltage value of the L level is the ground potential, in accordance with the logic level of the input signal.

[0133] Here, as described above, the gate signal Hgd is a signal in which the voltage value of the modulation signal Ms is level-shifted, and the gate signal Lgd is a signal in which the logic level of the modulation signal Ms is inverted and then the voltage value of the inverted signal is level-shifted. In view of this, the gate signal Hgd and the gate signal Lgd output by the gate driver circuit 520 can also be regarded as signals obtained by modulating the base drive signals dO and aO.

[0134] The amplification circuit 550 includes a transistor pair composed of the transistor Ml and the transistor M2.

[0135] A voltage signal VHV of, for example, a direct current voltage of 42 V is supplied to the drain terminal of the transistor Ml. Note that the voltage value of the voltage signal VHV can be larger than the maximum voltage value of the drive signal COM output from the drive circuit 50, and is not limited to 42 V. The gate terminal of the transistor Ml is electrically connected to one end of the resistor Rl. The gate signal Hgd is input to the other end of the resistor Rl. That is, the gate signal Hgd is input to the gate terminal of the transistor Ml via the resistor Rl. The source terminal of the transistor Ml is electrically connected to the drain terminal of the transistor M2. Thus, in the transistor Ml, the conduction state between the drain terminal and the source terminal is controlled by the gate signal Hgd input to the gate terminal.

[0136] The drain terminal of the transistor M2 is electrically connected to the source terminal of the transistor Ml. The gate terminal of the transistor M2 is electrically connected to one end of the resistor R2. The other end of the resistor R2 is input with the gate signal Lgd. That is, the gate signal Lgd is input to the gate terminal of the transistor M2 via the resistor R2. The source terminal of the transistor M2 is supplied with a ground potential. Thus, in the transistor M2, the conduction state between the drain terminal and the source terminal is controlled by the gate signal Lgd input to the gate terminal.

[0137] Here, in the following description, the case where the conduction state between the drain terminal and the source terminal of the transistors Ml, M2 is controlled to be on is referred to as on, and the case where the conduction state between the drain terminal and the source terminal of the transistors Ml, M2 is controlled to be off is referred to as off.

[0138] In the amplification circuit 550 configured as described above, in a case where the transistor Ml is controlled to be off and the transistor M2 is controlled to be on, the voltage value of the connection point of the source terminal of the transistor Ml and the drain terminal of the transistor M2 becomes the ground potential. At this time, the high potential side in the power supply voltage of the gate driver 521 is supplied with the voltage signal Vm. On the other hand, in a case where the transistor Ml is controlled to be on and the transistor M2 is controlled to be off, the voltage value of the connection point of the source terminal of the transistor Ml and the drain terminal of the transistor M2 becomes the voltage signal VHV. At this time, the high potential side in the power supply voltage of the gate driver 521 is supplied with a signal of the voltage value of the sum of the voltage value of the voltage signal VHV and the voltage value of the voltage signal Vm. That is, the gate driver 521 that drives the transistor Ml uses the capacitor C5 as a floating power supply, and the voltage value of the other terminal of the capacitor C5, that is, the connection point of the source terminal of the transistor Ml and the drain terminal of the transistor M2, changes to the ground potential or the voltage value of the voltage signal VHV depending on the operation of the transistor Ml and the transistor M2, and thus the gate driver 521 generates a gate signal Hgd in which the L level is the voltage value of the voltage signal VHV and the H level becomes the sum of the voltage value of the voltage signal VHV and the voltage value of the voltage signal Vm, and supplies the gate signal Hgd to the gate terminal of the transistor Ml.

[0139] On the other hand, the gate driver 522 that drives the transistor M2 generates a gate signal Lgd in which the L level is the ground potential and the H level is the voltage value of the voltage signal Vm, regardless of the operation of the transistor Ml and the transistor M2, and supplies the gate signal Lgd to the gate terminal of the transistor M2.

[0140] As described above, in the amplification circuit 550, the transistor Ml and the transistor M2 operate according to the gate signals Hgd and Lgd, and thus the modulation signal Ms obtained by modulating the base drive signals dO and aO based on the voltage signal VHV is amplified. Then, the amplification circuit 550 outputs the amplified signal as an amplified modulation signal AMs from the connection point at which the source terminal of the transistor Ml and the drain terminal of the transistor M2 are commonly connected.

[0141] The demodulation circuit 560 demodulates the amplified modulation signal AMs by smoothing the amplified modulation signal AMs, and generates a drive signal COM. Then, the demodulation circuit 560 outputs the generated drive signal COM from the drive circuit 50.

[0142] The demodulation circuit 560 includes the coil L1 and the capacitor C1. One end of the coil L1 is electrically connected to the source terminal of the transistor M1 and the drain terminal of the transistor M2. Thus, the amplified modulation signal AMs is input to one end of the coil L1. In addition, the other end of the coil L1 is connected to the terminal Out that is the output of the drive circuit 50. In addition, the other end of the coil L1 is also connected to one end of the capacitor C1. Further, the other end of the capacitor C1 is supplied with a ground potential. That is, the coil L1 and the capacitor C1 constitute a low-pass filter. Then, by the low-pass filter constituted in the demodulation circuit 560, the amplified modulation signal AMs is smoothed, thereby generating the drive signal COM.

[0143] The feedback circuit 570 includes the resistors R3 and R4. One end of the resistor R3 is connected to the terminal Out from which the drive signal COM is output, and the other end of the resistor R3 is connected to the integral attenuator 516 possessed by the modulation circuit 510 and one end of the resistor R4. The other end of the resistor R4 is supplied with the voltage signal VHV. Thus, the drive signal COM that has passed through the feedback circuit 570 from the terminal Out is fed back to the integral attenuator 516 possessed by the modulation circuit 510 in a state of being pulled up.

[0144] The feedback circuit 572 includes the capacitors C2, C3, C4 and the resistors R5, R6. One end of the capacitor C2 is connected to the terminal Out from which the drive signal COM is output, and the other end of the capacitor C2 is connected to one end of the resistor R5 and one end of the resistor R6. The other end of the resistor R5 is supplied with a ground potential. Thus, the capacitor C2 and the resistor R5 function as a high-pass filter.

[0145] In addition, the other end of the resistor R6 is connected to one end of the capacitor C4 and one end of the capacitor C3. The other end of the capacitor C3 is supplied with a ground potential. Thus, the resistor R6 and the capacitor C3 function as a low-pass filter.

[0146] As described above, the feedback circuit 572 is constituted to have a high-pass filter and a low-pass filter. Thus, the feedback circuit 572 functions as a band-pass filter that passes a predetermined frequency range of the drive signal COM. Further, the other end of the capacitor C4 included in the feedback circuit 572 is connected to the attenuator 517 possessed by the modulation circuit 510. Thus, to the attenuator 517 possessed by the modulation circuit 510, a signal in which a direct current component is cut off from a high frequency component of the drive signal COM that has passed through the feedback circuit 572 functioning as a band-pass filter that passes a predetermined frequency component is fed back.

[0147] However, the drive signal COM output from the terminal Out is a signal obtained by the demodulation circuit 560 demodulating the amplified modulation signal AMs based on the base drive signal dO by smoothing. Also, the drive signal COM output from the demodulation circuit 560 is fed back to the adder 512 after being integrated and attenuated via the feedback circuit 570. Thus, the drive circuit 50 self-oscillates at a frequency determined by the delay of the feedback and the transfer function of the feedback. However, if the amount of delay is large only via the feedback path of the integral attenuator 516 possessed by the modulation circuit 510, and if the feedback is only via the integral attenuator 516 possessed by the modulation circuit 510, there is a case where the frequency of the self-oscillation cannot be increased to a degree at which the accuracy of the drive signal COM can be sufficiently ensured.

[0148] The drive circuit 50 of the present embodiment has a path that feeds back the high-frequency component of the drive signal COM via the feedback circuit 572 and the attenuator 517 possessed by the modulation circuit 510 separately from the path via the integral attenuator 516 possessed by the modulation circuit 510. Thus, in the drive circuit 50 of the present embodiment, the delay in the case where the circuit as a whole constituting the drive circuit 50 is taken as a whole is small, and the frequency of the voltage signal As can be increased to a degree at which the accuracy of the drive signal COM can be sufficiently ensured.

[0149] As described above, the drive circuit 50 of the present embodiment has: the modulation circuit 510 that outputs the modulation signal Ms obtained by modulating the base drive signal dO, aO that is the basis of the drive signal COM; the gate driver circuit 520 that includes the gate driver 521 that outputs the gate signal Hgd corresponding to the modulation signal Ms and the gate driver 522 that outputs the gate signal Lgd corresponding to the modulation signal Ms; the amplification circuit 550 that includes the transistor M1 that is driven in accordance with the gate signal Hgd and the transistor M2 that is driven in accordance with the gate signal Lgd, and that outputs the amplified modulation signal AMs by the driving of the transistor M1 and the transistor M2; the demodulation circuit 560 that outputs the drive signal COM obtained by demodulating the amplified modulation signal AMs; and the feedback circuit 570, 572 that feeds back the drive signal COM to the modulation circuit 510.

[0150] Here, if the oscillation frequency of the self-excited oscillation of the drive circuit 50, i.e., the drive frequency of transistors M1 and M2, becomes higher, the switching losses generated by transistors M1 and M2 increase, resulting in increased heat generation from transistors M1 and M2. Furthermore, if the heat generation from transistors M1 and M2 increases, the stability of the operation of the drive circuit 50, including transistors M1 and M2, decreases, and the waveform accuracy of the drive signal COM output by the drive circuit 50 decreases. In particular, the switching losses generated by transistors M1 and M2 significantly contribute to the turn-on and turn-off times of transistors M1 and M2, as well as the drain current flowing through transistors M1 and M2. Therefore, as in the liquid ejection device 1 of this embodiment, when the drive circuit 50 supplies a high-frequency drive signal COM of 100 kHz or higher to numerous piezoelectric elements 60, i.e., more than 3000 piezoelectric elements 60, the current flowing through transistors M1 and M2 sometimes increases, and the drive frequency of transistors M1 and M2 exceeds 8 MHz, thus significantly increasing the switching losses of transistors M1 and M2. As a result, the risk of increased heat generation in transistors M1 and M2 is further increased, as is the risk of decreased stability in the operation of the drive circuit 50.

[0151] To address this problem, by setting the driving frequencies of transistors M1 and M2 to the same driving frequencies as when the frequency of the driving signal COM is below 100kHz, the risk of increased switching losses and increased heat generation of transistors M1 and M2 can be reduced. However, in the case of the liquid ejection device 1 shown in this embodiment, which controls the position of the meniscus of the ejection section 600 and the amount of ink ejected from the ejection section 600 by driving the piezoelectric element 60, from the viewpoint of detailed control of the ink ejection amount, it is necessary to carefully control the driving of the piezoelectric element 60 within the period tp, and the voltage value of the driving signal COM needs to be as follows: Figure 4 As shown, the voltage of the drive signal COM changes significantly within a short period of time. When the frequency of the drive signal COM is high, above 100kHz, there are cases where the voltage value of the drive signal COM changes abruptly by more than 20V per 1μs, and there are also cases where the voltage value of the drive signal COM remains constant for less than 0.25μs. Therefore, in the drive circuit 50 that outputs the drive signal COM, if the drive frequencies of transistors M1 and M2 are set to the same level as when the frequency of the drive signal COM is below 100kHz, a sufficient number of samples cannot be guaranteed to maintain the waveform accuracy of the drive signal COM, and there is a risk of reduced waveform accuracy of the output drive signal COM and reduced ink ejection accuracy.

[0152] That is, in terms of improving the productivity in the liquid ejecting apparatus 1, when the drive circuit 50 supplies the high frequency drive signal COM of 100 kHz or more to the large number of piezoelectric elements 60, that is, 3,000 or more piezoelectric elements 60, in order to maintain the high waveform accuracy of the drive signal COM, the drive frequency of the transistors M1, M2 needs to be further increased in speed, and thus, even when the drive frequency of the transistors M1, M2 is increased in the drive circuit 50, it is required to reduce the amount of heat generated by the drive circuit 50 and reduce the risk of the waveform accuracy of the output drive signal COM being reduced.

[0153] In this regard, in the past, it might have been possible to select a transistor with low switching loss from among transistors using silicon as the main material. However, the switching loss and the conduction loss in a transistor are in a trade-off relationship with each other, and thus, when a transistor with low switching loss is selected, the conduction loss increases, and it is not possible to reduce the amount of heat generated by the drive circuit 50. That is, the drive circuit 50 of the liquid ejecting apparatus 1 requires a transistor in which both the conduction loss and the switching loss are reduced in order to supply the high frequency drive signal COM of 100 kHz or more to the large number of piezoelectric elements 60, that is, 3,000 or more piezoelectric elements 60. Therefore, a transistor that exceeds the Baliga figure of merit of a transistor using silicon as the main material is required.

[0154] Therefore, in the drive circuit 50 of the present embodiment, the transistors M1, M2 have a characteristic configuration, and thus, even when the transistors M1, M2 are driven at a high frequency, the loss generated in the transistors M1, M2 is reduced. Thus, even when the drive circuit 50 supplies the high frequency drive signals COMA, COMB, COMC of 100 kHz or more to the large number of piezoelectric elements 60, that is, 3,000 or more piezoelectric elements 60, it is possible to reduce the amount of heat generated by the drive circuit 50 and reduce the risk of the waveform accuracy of the output drive signal COM being reduced.

[0155] An example of the configuration of the transistor M1 and the transistor M2 will be described. Here, the transistor M1 and the transistor M2 have the same configuration. Therefore, in the following description, only the configuration of the transistor M1 will be described, and the illustration and description of the configuration of the transistor M2 will be omitted or simplified.

[0156] Figure 10 is a view showing an example of the configuration of the transistor M1. When the configuration of the transistor M1 is described, the X axis and the Y axis that are orthogonal to each other are used for the description. In the following description, the start side of the arrow of the X axis shown in the view is sometimes referred to as the -X side, and the tip side is referred to as the +X side. The start side of the arrow of the Y axis shown in the view is sometimes referred to as the -Y side, and the tip side is referred to as the +Y side.

[0157] As Figure 10 shown, the transistor M1 has layers 701 to 705, a source electrode 760, a gate electrode 770, and a drain electrode 780.

[0158] The layer 701 is located at a position closest to the -Y side of the transistor M1, and includes a semiconductor substrate 710. As such a semiconductor substrate 710, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, and a sapphire substrate, or the like can be used.

[0159] The layer 702 is located at a position above the layer 701, that is, on the +Y side, and includes a buffer layer 720. The buffer layer 720 is configured to include one or more nitride semiconductors. This buffer layer 720 reduces the risk of warping of the semiconductor substrate 710, generation of cracks in the transistor M1, and the like, caused by a mismatch in the coefficient of thermal expansion between the semiconductor substrate 710 and an electron transport layer 730 described later. As such a buffer layer 720, for example, it can be configured to include aluminum nitride (AIN), aluminum gallium nitride (AlGaN), and a graded AlGaN having different compositions of aluminum (Al), or the like.

[0160] The layer 703 is located at a position above the layer 702, that is, on the +Y side, and includes the electron transport layer 730. Such an electron transport layer 730 is configured to contain a nitride semiconductor such as GaN. Here, the electron transport layer 730 can also be made semi-insulating by introducing impurities to a portion thereof in order to reduce a leakage current, so as to make a region other than a surface layer region located on the +Y side.

[0161] The layer 704 is located at a position above the layer 703, that is, on the +Y side, and includes an electron supply layer 740. Such an electron supply layer 740 is a nitride semiconductor having a larger band gap than the electron transport layer 730, and is configured to contain, for example, AlGaN.

[0162] Here, the electron transport layer 730 and the electron supply layer 740 are configured from nitride semiconductors having mutually different lattice constants. Therefore, a heterojunction of a lattice mismatch system is formed between the nitride semiconductor, that is, GaN, configuring the electron transport layer 730 and the nitride semiconductor, that is, AlGaN, configuring the electron supply layer 740. At this time, due to spontaneous polarization of the electron transport layer 730 and the electron supply layer 740, and piezoelectric polarization caused by a crystal strain in the vicinity of the boundary of the heterojunction, the energy level of the transport body of the electron transport layer 730 in the vicinity of the heterojunction boundary becomes lower than the Fermi level. As a result, a two-dimensional electron gas 790 is expanded to the electron transport layer 730 in a region close to the heterojunction boundary between the electron transport layer 730 and the electron supply layer 740.

[0163] The layer 705 is positioned above the layer 704, i.e., on the +Y side, and includes a gate layer 750. Such a gate layer 750 is a nitride semiconductor containing an acceptor-type impurity, for example, configured to contain gallium nitride (p-type GaN) doped with an acceptor-type impurity. At this time, as the doped acceptor-type impurity, for example, zinc (Zn), magnesium (Mg), carbon (C), or the like can be used.

[0164] The gate electrode 770 is positioned above the gate layer 750 included in the layer 705, i.e., on the +Y side, and is electrically connected to the gate terminal of the transistor M1. Such a gate electrode 770 is one or more metal layers, for example, configured to contain titanium nitride (TiN), and forms a Schottky junction with the gate layer 750. Note that, for example, the gate electrode 770 can also be configured to include a first metal layer composed of titanium (Ti) and a second metal layer composed of TiN provided above the first metal layer.

[0165] The source electrode 760 is positioned above the layer 704, i.e., on the +Y side, at a position on the -X side of the gate layer 750 and the gate electrode 770, and is electrically connected to the source terminal of the transistor M1. In addition, the drain electrode 780 is positioned above the layer 704, i.e., on the +Y side, at a position on the +X side of the gate layer 750 and the gate electrode 770, and is electrically connected to the drain terminal of the transistor M1. Such a source electrode 760 and a drain electrode 780 are one or more metal layers, for example, can be configured by any combination of Ti, TiN, and Al, or the like. Note that the source electrode 760 and the drain electrode 780 can also be configured to include an aluminum-silicon-copper alloy (Al-Si-Cu), an aluminum-copper alloy (AlCu), or the like.

[0166] That is, the transistor M1 and the transistor M2 each include the layer 703 including the electron transport layer 730 configured to contain a nitride semiconductor such as GaN, the layer 704 including a nitride semiconductor having a larger band gap than the electron transport layer 730, for example, AlGaN, the source electrode 760 electrically connected to the source terminal of the transistor M1, the drain electrode 780 electrically connected to the drain terminal of the transistor M1, and the gate electrode 770 electrically connected to the gate terminal of the transistor M1, the layer 704 is provided above the layer 703, the source electrode 760, the gate electrode 770, and the drain electrode 780 are provided above the layer 704, and at least a part of the gate electrode 770 is positioned between the source electrode 760 and the drain electrode 780 when viewed along the Y axis.

[0167] Next, the operation of the transistors Ml, M2 configured as described above will be described. In a case where a signal of 0 V is supplied to the gate electrode 770, that is, in a case where the potential of the gate electrode 770 is the same as that of the source electrode 760, the potential of the heterojunction boundary of the electron transport layer 730, which becomes a channel, and the electron supply layer 740 is raised. Thus, the -Y-shaped transfer band of the heterojunction boundary of the electron transport layer 730 and the electron supply layer 740, which is located at the gate electrode 770, becomes higher in energy than the Fermi level. As a result, the heterojunction boundary of the electron transport layer 730, which becomes a channel, and the electron supply layer 740 is depleted. That is, in a case where a signal of 0 V is supplied to the gate electrode 770, that is, in a case where the gate electrode 770 and the source electrode 760 are at the same potential, the respective source electrode 760 and the drain electrode 780 of the transistors Ml, M2, that is, the respective drain terminal and the source terminal of the transistors Ml, M2 become non-conductive.

[0168] On the other hand, if a signal of a positive voltage value is supplied to the gate electrode 770, the voltage value of the signal is greater than a predetermined threshold voltage, the potential of the heterojunction boundary of the electron transport layer 730, which becomes a channel, and the electron supply layer 740 is lowered. At this time, electrons are generated at the heterojunction boundary of the electron transport layer 730, which becomes a channel, and the electron supply layer 740, and the transistors Ml, M2 operate in the same manner as a normal FET (Field Effect Transistor).

[0169] Furthermore, if the voltage value of the signal supplied to the gate electrode 770 increases, the voltage value of the signal is greater than the forward voltage of the pn junction, the injection of holes from the gate electrode 770 to the heterojunction boundary of the electron transport layer 730, which becomes a channel, and the electron supply layer 740 starts. At this time, due to the finite potential barrier of the heterojunction, electrons hardly flow into the gate electrode 770. Thus, in order to satisfy the charge neutrality condition, the same number of electrons as the holes injected from the gate electrode 770 are attracted to the heterojunction boundary of the electron transport layer 730, which becomes a channel, and the electron supply layer 740 from the source electrode 760. The electrons attracted from the source electrode 760 move at high speed toward the drain electrode 780 due to the voltage supplied to the drain electrode 780. On the other hand, the mobility of holes is smaller than that of electrons, so the holes mostly stay in the vicinity of the gate electrode 770. Therefore, in order to satisfy the charge neutrality condition, the same number of electrons as the holes are further generated. Thus, the ratio of the number of injected holes to the number of generated electrons becomes substantially equal to the ratio of the mobility of electrons to the mobility of holes, although the gate current hardly flows, but the drain current increases.

[0170] As described above, the transistors Ml, M2 have, by including GaN, Figure 10The GaN transistor of the HEMT configuration exhibiting the normally-off characteristic and capable of realizing a low on-resistance for a large current drive is a GaN transistor of the configuration shown, that is, a device utilizing conductivity modulation based on hole injection from the gate electrode 770. Here, the transistors M1, M2 are not limited to GaN transistors of the HEMT configuration if the normally-off characteristic can be obtained, and Figure 10 The structure shown, for example, can also be a structure of a MOS-FET having a common source and common gate connection in place of the gate layer 750 included in the replacement layer 705.

[0171] Here, the GaN transistor is a compound semiconductor using GaN as a semiconductor material, and the band gap, dielectric breakdown field strength, electron mobility, and saturated electron velocity of GaN used as a semiconductor material are all greater than those of Si, which is the mainstream of semiconductor materials. Thus, the Baliga performance index of GaN used as a semiconductor material, which is determined by the comprehensive evaluation of multiple physical properties such as the dielectric breakdown field strength and electron mobility, reaches "900" when Si is set to "1" as a semiconductor material. In such a GaN transistor using GaN as a semiconductor material, high-speed switching at a low on-resistance can be achieved compared to a Si transistor using Si as a semiconductor material. Moreover, by providing the GaN transistor in the HEMT configuration, high-speed movement of electrons can be achieved, and the risk of impeding high-speed switching by parasitic capacitance can be reduced, enabling even faster switching.

[0172] By using such a GaN transistor of the HEMT configuration as the transistors M1, M2 of the amplification circuit 550 included in the drive circuit 50 of the liquid ejection device 1 of the present embodiment, the loss generated in the transistors M1, M2 can also be reduced in the case where the transistors M1, M2 are driven at a high frequency. That is, even in the case where the drive circuit 50 outputs a drive signal at a high frequency of 100 kHz or more, that is, in the case where the transistors M1, M2 are driven at a high frequency of 8 MHz or more, for example, the amount of heat generated by the transistors M1, M2 is reduced, and the risk of instability in the operation of the drive circuit 50 is reduced. Thus, in terms of improving the productivity in the liquid ejection device 1, even in the case where the drive circuit 50 supplies a drive signal COM at a high frequency of 100 kHz or more to a large number of piezoelectric elements 60, that is, 3000 or more piezoelectric elements 60, the risk of a decrease in the waveform accuracy of the output drive signal COM is reduced.

[0173] Furthermore, by using GaN transistors constructed with HEMT as transistors M1 and M2, the losses generated in transistors M1 and M2 are reduced even when they are driven at high frequencies, thus reducing the power consumption of the drive circuit 50. Moreover, since transistors M1 and M2 can be driven at high frequencies, the frequency of the feedback signal fed back to the modulation circuit 510 via the feedback circuit 572 can be increased. As a result, the waveform accuracy of the drive signal COM output by the drive circuit 50 is further improved.

[0174] Furthermore, since transistors M1 and M2 can be driven at high frequencies, the frequency of the amplified modulation signal AMs output by transistors M1 and M2 also increases. This allows for miniaturization of the coil L1 in the demodulation circuit 560, enabling miniaturization of the drive circuit 50. Moreover, by reducing the product of the coil L1 and capacitor C1 in the demodulation circuit 560, the output bandwidth of the drive circuit 50 can be widened, allowing for the output of a high-waveform-precision drive signal COM even under rapidly changing voltage values.

[0175] That is, in the driving circuit 50 of this embodiment, transistors M1 and M2 have the following characteristics: Figure 10 The characteristic structure shown reduces losses in transistors M1 and M2 even when they are driven at high frequencies. Therefore, even when the drive circuit 50 supplies high-frequency drive signals COMA, COMB, and COMC at frequencies above 100 kHz to numerous piezoelectric elements 60 (i.e., more than 3000 piezoelectric elements 60), the heat generated in the drive circuit 50 is reduced, and the risk of reduced waveform accuracy of the output drive signal COM is also reduced. Therefore, in the drive circuit 50 of this embodiment, when the drive frequency of transistor M1 is set such that the shortest period within the drive cycle of transistor M1 is shorter than the shortest period within the period during which the voltage value of the drive signal COM changes, and shorter than the shortest period within the period during which the voltage value of the drive signal COM remains constant, and when the drive frequency of transistors M1 and M2 is set such that the shortest period within the drive cycle of transistor M2 is shorter than the shortest period within the period during which the voltage value of the drive signal COM changes, and shorter than the shortest period within the period during which the voltage value of the drive signal COM remains constant, even if the drive frequencies of transistors M1 and M2 exceed 8MHz during the period during which transistors M1 and M2 output the amplified modulation signal AMs, the losses generated in transistors M1 and M2 can be reduced. As a result, the heat generated in the drive circuit 50 can be reduced, and the risk of a decrease in the waveform accuracy of the output drive signal COM can also be reduced.

[0176] Here, in the semiconductor material constituting the transistors Ml, M2, in the case of focusing on the Baliga figure of merit alone, SiC, gallium oxide (Ga2O3) also have a larger Baliga figure of merit than Si as the semiconductor material. However, SiC, Ga2O3 are semiconductor materials assumed to be used in high withstand voltage of several hundred V to several kV, and have poorer switching performance in high frequency than GaN. Therefore, they are not suitable as the semiconductor material of the transistors Ml, M2 possessed by the drive circuit 50 of the liquid ejecting apparatus 1 assumed to be used in a voltage value of 100 V or less and high frequency of several MHz. Further, in the case of using GaN as the semiconductor material, in the case of adopting a vertical structure instead of an HEMT structure, use in high frequency of several MHz is hindered by a parasitic capacitance generated between the gate and the source. Therefore, as the transistors Ml, M2 of the drive circuit 50 of the liquid ejecting apparatus 1 assumed to be used in a voltage value of 100 V or less and high frequency of several MHz, not only the Baliga figure of merit of the semiconductor material but also other physical properties and structures are comprehensively considered, and it can be said that a GaN transistor using an HEMT structure is the best.

[0177] Here, the drive signal COM is an example of a drive signal, the piezoelectric element 60 is an example of a capacitive load, the drive circuit 50 is an example of a capacitive load drive circuit, the gate signal Hgd is an example of a first gate drive signal, the gate driver 521 is an example of a first gate drive circuit, the gate signal Ldg is an example of a second gate drive signal, the gate driver 522 is an example of a second gate drive circuit, the transistor Ml is an example of a first transistor, the transistor Ml is an example of a second transistor, the period tp is an example of an ejection period, and the reciprocal of the drive frequency of the transistors Ml, M2 is an example of a drive period.

[0178] 1.5 Effects

[0179] In the liquid ejecting apparatus 1 configured as described above, in the drive circuit 50, there are a modulation circuit 510 that outputs a modulation signal Ms obtained by modulating base drive signals dO, aO that are bases of the drive signals COM, a gate driver circuit 520 that includes a gate driver 521 that outputs a gate signal Hgd corresponding to the modulation signal Ms and a gate driver 522 that outputs a gate signal Lgd corresponding to the modulation signal Ms, an amplification circuit 550 that includes a transistor Ml driven in accordance with the gate signal Hgd and a transistor M2 driven in accordance with the gate signal Lgd, the amplification circuit 550 outputting an amplified modulation signal AMs by driving of the transistors Ml and M2, and a demodulation circuit 560 that outputs the drive signals COM obtained by demodulating the amplified modulation signal AMs, in a case where at least one of the transistors Ml and M2, preferably both of the transistors Ml and M2 included in the amplification circuit 550 are configured to include a layer 703 including an electron transport layer 730 configured to contain a nitride semiconductor such as GaN, a layer 704 including a nitride semiconductor having a larger band gap than the electron transport layer 730, such as AlGaN, a source electrode 760 electrically connected to a source terminal of the transistor Ml, a drain electrode 780 electrically connected to a drain terminal of the transistor Ml, and a gate electrode 770 electrically connected to a gate terminal of the transistor Ml, the layer 704 being provided above the layer 703, the source electrode 760, the gate electrode 770, and the drain electrode 780 being provided above the layer 704, and the gate electrode 770 being located at least partially between the source electrode 760 and the drain electrode 780 when viewed along the Y axis, it is possible to reduce loss generated in the transistors Ml and M2 even in a case where the transistors Ml and M2 are driven at a high frequency. Thus, in a case where the frequency of the drive signals COM output from the drive circuit 50 using a D-class amplification circuit is high, for example, in a case where the drive circuit 50 supplies a high-frequency drive signal COMA, COMB, COMC of 100 kHz or more to a large number of piezoelectric elements 60, that is, 3,000 or more piezoelectric elements 60, in response to a market demand for improvement in productivity of the liquid ejecting apparatus 1, it is possible to reduce the amount of heat generated in the drive circuit 50 and reduce the risk of a decrease in waveform accuracy of the output drive signals COM.

[0180] That is, by providing at least one of the transistors M1, M2 of the amplification circuit 550, preferably both, as a GaN transistor of HEMT configuration, it is possible to reduce the loss generated in the transistors M1, M2 even when the transistors M1, M2 are driven at a high frequency, so it is possible to reduce the amount of heat generated in the drive circuit 50 even when the drive circuit 50 supplies the plurality of piezoelectric elements 60, i.e., 3000 or more piezoelectric elements 60, with a drive signal COMA, COMB, COMC of a high frequency of 100 kHz or more in response to the market demand for increased productivity in the liquid discharge device 1, and to reduce the risk of a decrease in the waveform accuracy of the output drive signal COM.

[0181] In addition, at this time, the drive circuit 50 of the liquid discharge device 1 has a feedback circuit 570, 572 that feeds back the drive signal COM to the modulation circuit 510, so it is possible to improve the response speed of the drive circuit 50 when viewed as a system as a whole of the drive circuit 50 because the transistors M1, M2 are driven at a high frequency. Thus, it is possible to improve the waveform accuracy of the drive signal COM output by the drive circuit 50.

[0182] In addition, in the liquid discharge device 1 of the present embodiment, it is possible to reduce the loss generated in the transistors M1, M2 even when the transistors M1, M2 are driven at a high frequency, so the heat generation of the drive circuit 50 including the transistors M1, M2 is reduced. Therefore, even when the drive circuit 50 is mounted on the carriage 21 together with the discharge portion 600, the risk of a change in the physical properties of the ink discharged due to the heat generation of the drive circuit 50 including the transistors M1, M2 is reduced. In addition, at this time, by mounting the drive circuit 50 on the carriage 21 together with the discharge portion 600, it is possible to shorten the transmission path of the drive signal COM output by the drive circuit 50 until it is supplied to the discharge portion 600, the waveform accuracy of the drive signal COM supplied to the discharge portion 600 is improved, and the discharge accuracy of the ink from the discharge portion 600 is improved.

[0183] 2. Second Embodiment

[0184] Next, the liquid discharge device 1 of the second embodiment will be described. In describing the liquid discharge device 1 of the second embodiment, the same reference numerals are assigned to the same structures as those of the liquid discharge device 1 of the first embodiment, and the detailed description thereof is omitted or simplified.

[0185] Figure 11is a drawing showing an example of the structure of the drive circuit 50 of the second embodiment. In the liquid ejecting apparatus 1 of the second embodiment, in the drive circuit 50, the gate driver circuit 520 outputting the gate signals Hgd, Lgd and the transistors Ml, M2 are mounted to one integrated circuit device 500, which is different from the liquid ejecting apparatus 1 of the first embodiment in this point.

[0186] As shown in Figure 11 , the integrated circuit device 500 includes the terminals Tvm, Tsi, Td, Ts, Tout, Tbt, the gate driver circuit 520, the amplification circuit 550, the diode Dl, and the inverter 515.

[0187] The modulation signal Ms outputted by the modulation circuit 510 is inputted to the terminal Tsi. The voltage signal Vm is supplied to the terminal Tvm. The voltage signal VHV is supplied to the terminal Td. The ground potential is supplied to the terminal Ts. The terminal Tbt is electrically connected to one end of the capacitor C5. Further, the other end of the capacitor C5 is electrically connected to the terminal Tout. The terminal Tout is electrically connected to one end of the coil Ll possessed by the demodulation circuit 560.

[0188] The modulation signal Ms is inputted to the gate driver 521 included in the gate driver circuit 520 via the terminal Tsi. Further, the modulation signal Ms is inputted to the gate driver 522 included in the gate driver circuit 520 after the logic level is inverted by the inverter 515 after being inputted to the inverter 515 via the terminal Tsi. That is, the signals whose logic levels are exclusive to each other are inputted to the gate driver 521 and the gate driver 522.

[0189] The gate driver 521 generates and outputs the gate signal Hgd by level-shifting the modulation signal Ms. The high potential side in the power supply voltage of the gate driver 521 is electrically connected to the cathode of the diode Dl, and also to one end of the capacitor C5 via the terminal Tbt. The other end of the capacitor C5 is electrically connected to the terminal Tout, and the terminal Tout is electrically connected to the connection point of the source terminal of the transistor Ml and the drain terminal of the transistor M2. The voltage signal Vm is supplied to the anode of the diode Dl via the terminal Tvm. Thus, a potential difference approximately equal to the voltage value of the voltage signal Vm is generated across the capacitor C5. The low potential side in the power supply voltage of the gate driver 521 is electrically connected to the connection point of the source terminal of the transistor Ml and the drain terminal of the transistor M2, that is, the terminal Tout. Thus, the gate driver 521 generates and outputs the gate signal Hgd in which the voltage value of the H level is larger than the voltage value of the terminal Tout by the voltage value of the voltage signal Vm, and the voltage value of the L level becomes the voltage value of the terminal Tout, in accordance with the logic level of the inputted modulation signal Ms.

[0190] The gate driver 522 operates on the lower potential side than the gate driver 521. The gate driver 522 generates and outputs the gate signal Lgd by performing level shifting on a signal in which the logic level of the modulation signal Ms input via the terminal Tsi is inverted by the inverter 515. The voltage signal Vm is supplied to the high potential side in the power supply voltage of the gate driver 522 via the terminal Tvm, and the ground potential is supplied to the low potential side in the power supply voltage of the gate driver 522 via the terminal Ts. Thus, the gate driver 522 generates and outputs the gate signal Lgd in which the voltage value of the H level is the voltage value of the voltage signal Vm and the voltage value of the L level is the ground potential, in accordance with the logic level of the input signal.

[0191] The amplification circuit 550 includes a transistor pair composed of the transistor Ml and the transistor M2.

[0192] The voltage signal VHV is supplied to the drain terminal of the transistor Ml via the terminal Td. The gate signal Hgd is input to the gate terminal of the transistor Ml. The source terminal of the transistor Ml is electrically connected to the terminal Tout and the drain terminal of the transistor M2. Thus, in the transistor Ml, the conduction state between the drain terminal and the source terminal is controlled by the gate signal Hgd input to the gate terminal.

[0193] The drain terminal of the transistor M2 is electrically connected to the terminal Tout and the source terminal of the transistor Ml. The gate signal Lgd is input to the gate terminal of the transistor M2. The ground potential is supplied to the source terminal of the transistor M2 via the terminal Ts. Thus, in the transistor M2, the conduction state between the drain terminal and the source terminal is controlled by the gate signal Lgd input to the gate terminal.

[0194] In the amplification circuit 550 configured as described above, in a case where the transistor Ml is controlled to be off and the transistor M2 is controlled to be on, the voltage value of the terminal Tout becomes the ground potential. At this time, the high potential side in the power supply voltage of the gate driver 521 is supplied with the voltage signal Vm. On the other hand, in a case where the transistor Ml is controlled to be on and the transistor M2 is controlled to be off, the voltage value of the terminal Tout becomes the voltage signal VHV. At this time, the high potential side in the power supply voltage of the gate driver 521 is supplied with a signal of a voltage value that is the sum of the voltage value of the voltage signal VHV and the voltage value of the voltage signal Vm. That is, the gate driver 521 that drives the transistor Ml uses the capacitor C5 as a floating power supply, and the voltage value of the other terminal of the capacitor C5, that is, the terminal Tout, changes to the ground potential or the voltage value of the voltage signal VHV according to the operation of the transistor Ml and the transistor M2, thereby generating a gate signal Hgd in which the L level is the voltage value of the voltage signal VHV and the H level becomes the sum of the voltage value of the voltage signal VHV and the voltage value of the voltage signal Vm, and supplying the gate signal Hgd to the gate terminal of the transistor Ml.

[0195] On the other hand, the gate driver 522 that drives the transistor M2 generates a gate signal Lgd in which the L level is the ground potential and the H level is the voltage value of the voltage signal Vm, regardless of the operation of the transistor Ml and the transistor M2, and supplies the gate signal Lgd to the gate terminal of the transistor M2.

[0196] As described above, in the amplification circuit 550, the transistor Ml and the transistor M2 operate according to the gate signals Hgd and Lgd, thereby amplifying the modulation signal Ms in which the base drive signal dO, aO is modulated based on the voltage signal VHV. Then, the amplification circuit 550 outputs the amplified signal from the terminal Tout as an amplified modulation signal AMs.

[0197] Then, the demodulation circuit 560 demodulates the amplified modulation signal AMs by smoothing the amplified modulation signal AMs, and generates a drive signal COM. Then, the demodulation circuit 560 outputs the generated drive signal COM from the drive circuit 50.

[0198] In the drive circuit 50 of the second embodiment configured as described above, by the transistor Ml and the transistor M2 having the configuration as shown in FIG. 5, the same operational effects as the liquid ejection apparatus 1 of the first embodiment are also achieved. Figure 10

[0199] ​At this time, in the liquid ejecting apparatus 1 of the second embodiment, the gate driver circuit 520 outputting the gate signals Hgd, Lgd and the transistors M1, M2 constitute the integrated circuit device 500 housed in one package. Thus, the transmission paths for respectively transmitting the gate signals Hgd, Lgd can be shortened, and the waveform accuracy of the gate signal Hgd input to the transistor M1 and the waveform accuracy of the gate signal Lgd input to the transistor M2 are improved.

[0200] As described using Figure 10 As described using

[0201] However, in the case where the wiring for transmitting the gate signals Hgd, Lgd is long, there is a risk that the waveforms of the gate signals Hgd, Lgd are distorted due to the influence of the inductance component of the wiring. Thus, in the case where the wiring for transmitting the gate signals Hgd, Lgd is long, there is a risk that the driving frequencies of the transistors M1, M2 are limited by the waveform distortion of the gate signals Hgd, Lgd. In particular, in the GaN transistor of the HEMT configuration as the transistors M1, M2 possessed by the drive circuit 50 as shown in the present embodiment, since high-speed switching can be performed, such a problem becomes significant.

[0202] In contrast, in the liquid ejecting apparatus 1 of the second embodiment, since the wirings for respectively transmitting the gate signals Hgd, Lgd can be shortened, the risk that the respective signal waveforms of the gate signal Hgd input to the transistor M1 and the gate signal Lgd input to the transistor M2 are distorted is reduced. Thus, the driving frequencies of the transistors M1, M2 can be further improved, and the waveform accuracy of the drive signal COM output by the drive circuit 50 can be further improved.

[0203] 3. Third Embodiment

[0204] Next, the liquid ejecting apparatus 1 of the third embodiment will be described. In describing the liquid ejecting apparatus 1 of the third embodiment, the same reference numerals are assigned to the same structures as those of the liquid ejecting apparatuses 1 of the first and second embodiments, and the detailed description thereof will be simplified or omitted.

[0205] Figure 12 is a view showing an example of the structure of the drive circuit 50 of the third embodiment. In the liquid ejecting apparatus 1 of the third embodiment, in the drive circuit 50, the gate driver 521 outputting the gate signal Hgd and the transistor Ml are mounted on one integrated circuit device 500a, and the gate driver 522 outputting the gate signal Lgd and the transistor M2 are mounted on one integrated circuit device 500b, which is different from the liquid ejecting apparatuses 1 of the first and second embodiments in this point.

[0206] As shown in Figure 12 , the integrated circuit device 500a includes the terminal Tvma, Tsia, Tda, Tsa, the gate driver 521, and the transistor Ml, and the integrated circuit device 500b includes the terminal Tvmb, Tsib, Tdb, Tsb, the gate driver 522, and the transistor M2.

[0207] The modulation signal Ms outputted from the modulation circuit 510 is inputted to the terminal Tsia. The terminal Tvma is electrically connected to the cathode of the diode Dl and one end of the capacitor C5. The voltage signal VHV is supplied to the terminal Tda. The terminal Tsa is electrically connected to the terminal Tdb of the integrated circuit device 500b. Further, the modulation signal Ms outputted from the modulation circuit 510 is inputted to the terminal Tsib via the inverter 515. The voltage signal Vm is inputted to the terminal Tvmb. The terminal Tdb is electrically connected to the terminal Tsa of the integrated circuit device 500a. The ground potential is supplied to the terminal Tsb.

[0208] The modulation signal Ms is inputted to the gate driver 521 via the terminal Tsia. Further, the modulation signal Ms is also inputted to the gate driver 522 via the terminal Tsib after the logic level is inverted by the inverter 515. That is, the signals whose logic levels are exclusive to each other are inputted to the gate driver 521 and the gate driver 522.

[0209] The gate driver 521 generates and outputs a gate signal Hgd by level-shifting the modulation signal Ms. The high potential side in the power supply voltage of the gate driver 521 is electrically connected to the cathode of the diode Dl and one end of the capacitor C5 via the terminal Tvma. The other end of the capacitor C5 is electrically connected to the terminal Tsa which is electrically connected to the source terminal of the transistor Ml. The voltage signal Vm is supplied to the anode of the diode Dl. Thus, a potential difference substantially equal to the voltage value of the voltage signal Vm is generated across the capacitor C5. The low potential side in the power supply voltage of the gate driver 521 is electrically connected to the source terminal of the transistor Ml, i.e., the terminal Tsa. Thus, the gate driver 521 generates and outputs a gate signal Hgd whose voltage value at the H level is larger than that of the terminal Tsa by the voltage value of the voltage signal Vm and whose voltage value at the L level becomes that of the terminal Tsa, in accordance with the logic level of the inputted modulation signal Ms.

[0210] The gate driver 522 generates and outputs a gate signal Lgd by level-shifting a signal in which the logic level of the modulation signal Ms inputted via the terminal Tsib is inverted by the inverter 515. The high potential side in the power supply voltage of the gate driver 522 is supplied with the voltage signal Vm via the terminal Tvmb, and the low potential side in the power supply voltage of the gate driver 522 is supplied with the ground potential via the terminal Tsb. Thus, the gate driver 522 generates and outputs a gate signal Lgd whose voltage value at the H level is the voltage value of the voltage signal Vm and whose voltage value at the L level is the ground potential, in accordance with the logic level of the inputted signal.

[0211] The voltage signal VHV is supplied to the drain terminal of the transistor Ml via the terminal Tda. The gate signal Hgd is inputted to the gate terminal of the transistor Ml. The source terminal of the transistor Ml is electrically connected to the terminal Tsa. Thus, in the transistor Ml, the conduction state between the drain terminal and the source terminal is controlled by the gate signal Hgd inputted to the gate terminal.

[0212] The drain terminal of the transistor M2 is electrically connected to the terminal Tdb. In addition, the terminal Tdb is electrically connected to the terminal Tsa. That is, the source terminal of the transistor Ml and the drain terminal of the transistor M2 are electrically connected via the terminal Tsa and the terminal Tdb. The gate signal Lgd is inputted to the gate terminal of the transistor M2. The ground potential is supplied to the source terminal of the transistor M2 via the terminal Tsb. Thus, in the transistor M2, the conduction state between the drain terminal and the source terminal is controlled by the gate signal Lgd inputted to the gate terminal.

[0213] Also, in a case where the transistor Ml is controlled to be off and the transistor M2 is controlled to be on, the voltage value of the connection point of the terminal Tsa and the terminal Tdb becomes the ground potential. At this time, the high potential side in the power supply voltage of the gate driver 521 is supplied with the voltage signal Vm. On the other hand, in a case where the transistor Ml is controlled to be on and the transistor M2 is controlled to be off, the voltage value of the connection point of the terminal Tsa and the terminal Tdb becomes the voltage signal VHV. At this time, the high potential side in the power supply voltage of the gate driver 521 is supplied with a signal of the voltage value of the sum of the voltage value of the voltage signal VHV and the voltage value of the voltage signal Vm. That is, the gate driver 521 which drives the transistor Ml uses the capacitor C5 as a floating power supply, and the voltage value of the other terminal of the capacitor C5, that is, the connection point of the terminal Tsa and the terminal Tdb, changes to the ground potential or the voltage value of the voltage signal VHV depending on the operation of the transistor Ml and the transistor M2, thereby generating a gate signal Hgd in which the L level is the voltage value of the voltage signal VHV and the H level becomes the sum of the voltage value of the voltage signal VHV and the voltage value of the voltage signal Vm, and supplying the gate signal Hgd to the gate terminal of the transistor Ml.

[0214] On the other hand, the gate driver 522 which drives the transistor M2 generates a gate signal Lgd in which the L level is the ground potential and the H level is the voltage value of the voltage signal Vm, regardless of the operation of the transistor Ml and the transistor M2, and supplies the gate signal Lgd to the gate terminal of the transistor M2.

[0215] As described above, by the operation of the transistors Ml and M2 depending on the gate signals Hgd and Lgd, the modulation signal Ms which is obtained by modulating the base drive signal dO, aO based on the voltage signal VHV is amplified. Then, the signal amplified by the transistors Ml and M2 is output from the connection point of the terminal Tsa and the terminal Tdb as the amplified modulation signal AMs.

[0216] Then, the demodulation circuit 560 demodulates the amplified modulation signal AMs by smoothing the amplified modulation signal AMs, and generates the drive signal COM. Then, the demodulation circuit 560 outputs the generated drive signal COM from the drive circuit 50.

[0217] In the drive circuit 50 of the third embodiment configured as described above, by the transistors Ml and M2 having the configuration as shown in FIG. 6, the same operational effects as the liquid ejection apparatus 1 of the first embodiment and the second embodiment are also achieved. Figure 10

[0218] ​At this time, in the liquid ejecting apparatus 1 of the third embodiment, the gate driver 521 outputting the gate signal Hgd and the transistor Ml constitute the integrated circuit device 500a housed in one package, and the gate driver 522 outputting the gate signal Lgd and the transistor M2 constitute the integrated circuit device 500b housed in one package. Thereby, it is possible to shorten the transmission paths respectively transmitting the gate signals Hgd, Lgd, and to improve the waveform accuracy of the gate signal Hgd input to the transistor Ml and the waveform accuracy of the gate signal Lgd input to the transistor M2.

[0219] As described using Figure 10 As described using

[0220] However, in the case where the wiring length of the gate signals Hgd, Lgd is long, there is a risk that the waveforms of the gate signals Hgd, Lgd are distorted due to the influence of the inductance component of the wiring. Therefore, in the case where the wiring length of the gate signals Hgd, Lgd is long, there is a risk that the driving frequency of the transistors Ml, M2 is limited by the waveform distortion of the gate signals Hgd, Lgd. In particular, in the GaN transistor of the HEMT configuration as the transistors Ml, M2 of the drive circuit 50 shown in the present embodiment, since high-speed switching is possible, such a problem becomes significant.

[0221] In contrast, in the liquid ejecting apparatus 1 of the third embodiment, as with the liquid ejecting apparatus 1 of the second embodiment, since it is possible to shorten the wiring respectively transmitting the gate signals Hgd, Lgd, the risk that the respective signal waveforms of the gate signal Hgd input to the transistor Ml and the gate signal Lgd input to the transistor M2 are distorted is reduced. Therefore, it is possible to further improve the driving frequency of the transistors Ml, M2, and to further improve the waveform accuracy of the drive signal COM output by the drive circuit 50.

[0222] Here, integrated circuit device 500a is a first semiconductor device, and integrated circuit device 500b is a second semiconductor device.

[0223] The above description covers the implementation methods and variations, but the present invention is not limited to these implementation methods and can be implemented in various ways without departing from its spirit. For example, the above-described implementation methods can also be appropriately combined.

[0224] This invention includes structures that are substantially the same as those described in the embodiments (e.g., structures with the same function, method, and result, or structures with the same purpose and effect). Additionally, this invention includes structures after replacing non-essential parts of the structures described in the embodiments. Furthermore, this invention includes structures capable of achieving the same effect or purpose as the structures described in the embodiments. Additionally, this invention includes structures after incorporating known techniques into the structures described in the embodiments.

[0225] The following content is derived from the above implementation method.

[0226] One method of liquid ejection device includes:

[0227] A capacitive load is displaced by being supplied with a drive signal;

[0228] The ejector section ejects liquid as the capacitive load displaces; and

[0229] The capacitive load drive circuit outputs the drive signal.

[0230] The capacitive load drive circuit has:

[0231] The modulation circuit outputs a modulated signal obtained by modulating the base driving signal, which serves as the basis of the driving signal.

[0232] The first gate driving circuit outputs a first gate driving signal corresponding to the modulation signal;

[0233] The second gate driving circuit outputs a second gate driving signal corresponding to the modulation signal;

[0234] An amplifier circuit includes a first transistor and a second transistor. The first transistor is driven by a first gate drive signal, and the second transistor is driven by a second gate drive signal. The amplifier circuit outputs an amplified and modulated signal by driving the first transistor and the second transistor.

[0235] The demodulation circuit outputs the driving signal obtained by demodulating the amplified modulation signal.

[0236] The first transistor includes gallium nitride,

[0237] The second transistor includes gallium nitride,

[0238] The first gate drive circuit and the first transistor are housed in one package and constitute a first semiconductor device,

[0239] The second gate drive circuit and the second transistor are housed in one package and constitute a second semiconductor device.

[0240] In the liquid ejecting apparatus, by the first transistor and the second transistor being configured to include gallium nitride having a high Baliga figure of merit, even in a case where at least one of the first transistor and the second transistor is driven at high speed as the frequency of the output drive signal is increased, a loss based on the driving is reduced. Thus, heat generation in the amplifying circuit is reduced. As a result, the risk of a decrease in stability of the operation of the capacitive load driving circuit caused by heat generation of the amplifying circuit is reduced, and the waveform accuracy of the drive signal output from the capacitive load driving circuit is improved.

[0241] At this time, in the liquid ejecting apparatus, by the first gate drive circuit and the first transistor constituting a first semiconductor device housed in one package, and the second gate drive circuit and the second transistor constituting a second semiconductor device housed in one package, it is possible to shorten the length of the wiring that transmits the first gate signal and the second gate signal. Therefore, the risk of waveform distortion occurring in the first gate signal and the second gate signal input to the first transistor and the second transistor is reduced, the driving accuracy of the first transistor and the second transistor is improved, and the risk of the driving frequency of the first transistor and the second transistor being limited by the waveform distortion occurring in the first gate signal and the second gate signal is reduced, and further high-speed driving of the first transistor and the second transistor is enabled.

[0242] That is, in the liquid ejecting apparatus, even in a case where the driving frequency of the first transistor and the second transistor is increased as the frequency of the output drive signal is increased, the first transistor and the second transistor are able to stably drive at low loss, so the risk of a decrease in stability of the operation of the capacitive load driving circuit is reduced, and the risk of a decrease in waveform accuracy of the drive signal output from the capacitive load driving circuit is reduced.

[0243] In one embodiment of the liquid ejecting apparatus, it can also be that,

[0244] The ejection period of the liquid ejected from the ejection section is 10 μs or less.

[0245] In the liquid ejecting apparatus, the ejection period of the liquid from the ejection section is 10 μs or less, so even if the driving signal output from the capacitive load driving circuit becomes a high frequency, the first transistor and the second transistor can stably drive with low loss, so the risk of the stability of the operation of the capacitive load driving circuit decreasing is reduced, and the risk of the waveform precision of the driving signal output from the capacitive load driving circuit decreasing is reduced.

[0246] In one embodiment of the liquid ejecting apparatus, it can be that,

[0247] During the period in which the amplification circuit outputs the amplified modulation signal, the first transistor drives at a frequency of 8 MHz or more, and the second transistor drives at a frequency of 8 MHz or more.

[0248] In the liquid ejecting apparatus, even if the driving frequency of the first transistor and the second transistor is a high frequency of 8 MHz or more, the first transistor and the second transistor can stably drive with low loss, so the risk of the stability of the operation of the capacitive load driving circuit decreasing is reduced, and the risk of the waveform precision of the driving signal output from the capacitive load driving circuit decreasing is reduced.

[0249] In one embodiment of the liquid ejecting apparatus, it can be that,

[0250] The shortest period in the driving period of the first transistor is shorter than the shortest period in the period in which the voltage value of the driving signal changes, and shorter than the shortest period in the period in which the voltage value of the driving signal is constant,

[0251] The shortest period in the driving period of the second transistor is shorter than the shortest period in the period in which the voltage value of the driving signal changes, and shorter than the shortest period in the period in which the voltage value of the driving signal is constant.

[0252] In the liquid ejecting apparatus, since the shortest period in the driving period of the first transistor is shorter than the shortest period in the period in which the voltage value of the driving signal changes, and shorter than the shortest period in the period in which the voltage value of the driving signal is constant, and the shortest period in the driving period of the second transistor is shorter than the shortest period in the period in which the voltage value of the driving signal changes, and shorter than the shortest period in the period in which the voltage value of the driving signal is constant, even if the driving frequency of the first transistor and the second transistor becomes a high frequency, the first transistor and the second transistor can stably drive with low loss, so the risk of the stability of the operation of the capacitive load driving circuit decreasing is reduced, and the risk of the waveform precision of the driving signal output from the capacitive load driving circuit decreasing is reduced.

[0253] In one embodiment of the liquid ejecting apparatus, it is also possible that

[0254] The capacitive load driving circuit has a feedback circuit that feeds back the driving signal to the modulation circuit.

[0255] In the liquid ejecting apparatus, even in a case where the driving frequencies of the first transistor and the second transistor are set to high frequencies, the risk of a decrease in stability of operation of the capacitive load driving circuit is reduced, so in the capacitive load driving circuit, the responsiveness via the feedback circuit can be improved. Thus, the waveform accuracy of the driving signal output by the capacitive load driving circuit is improved.

[0256] In one embodiment of the liquid ejecting apparatus, it is also possible that

[0257] The liquid ejecting apparatus has a carriage that moves along a main scanning axis that intersects a conveyance direction of a medium on which a liquid ejected from the ejecting portion lands,

[0258] The capacitive load, the ejecting portion, and the capacitive load driving circuit are mounted on the carriage.

[0259] In the liquid ejecting apparatus, the loss based on the driving of at least one of the first transistor and the second transistor is reduced, and the heat generation in the amplification circuit is reduced, so even in a case where the capacitive load driving circuit is mounted on the carriage, the risk that the heat generation in the amplification circuit contributes to a change in characteristics of the liquid is reduced.

[0260] One embodiment of the capacitive load driving circuit is

[0261] The capacitive load driving circuit outputs a driving signal to a capacitive load that is displaced by being supplied with the driving signal to eject a liquid from an ejecting portion, and has:

[0262] a modulation circuit that outputs a modulation signal obtained by modulating a base driving signal that is a basis of the driving signal;

[0263] a first gate driving circuit that outputs a first gate driving signal corresponding to the modulation signal;

[0264] a second gate driving circuit that outputs a second gate driving signal corresponding to the modulation signal;

[0265] an amplification circuit that includes a first transistor driven in accordance with the first gate driving signal and a second transistor driven in accordance with the second gate driving signal, and outputs an amplified modulation signal through the driving of the first transistor and the second transistor; and

[0266] demodulation circuitry that outputs the drive signal by demodulating the amplified modulation signal,

[0267] the first transistor includes gallium nitride,

[0268] the second transistor includes gallium nitride,

[0269] the first gate drive circuit and the first transistor are housed in one package and constitute a first semiconductor device,

[0270] the second gate drive circuit and the second transistor are housed in one package and constitute a second semiconductor device.

[0271] In the capacitive load drive circuit, by the first transistor and the second transistor being configured to include gallium nitride having a high Baliga figure of merit, even in a case where at least one of the first transistor and the second transistor is driven at high speed as the frequency of the output drive signal is increased, a loss based on the drive is reduced. As a result, heat generation in the amplification circuit is reduced. As a result, the risk of a decrease in the stability of the operation of the capacitive load drive circuit due to heat generation by the amplification circuit is reduced, and the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved.

[0272] At this time, in the capacitive load drive circuit, by the first gate drive circuit and the first transistor constituting a first semiconductor device housed in one package, and the second gate drive circuit and the second transistor constituting a second semiconductor device housed in one package, it is possible to shorten the length of the wiring that transmits the first gate signal and the second gate signal. As a result, the risk of waveform distortion occurring in the first gate signal and the second gate signal input to the first transistor and the second transistor is reduced, the drive accuracy of the first transistor and the second transistor is improved, and the risk of the drive frequency of the first transistor and the second transistor being limited by waveform distortion occurring in the first gate signal and the second gate signal is reduced, and further high-speed driving of the first transistor and the second transistor is made possible.

[0273] That is, in the capacitive load drive circuit, even in a case where the drive frequency of the first transistor and the second transistor is increased as the frequency of the output drive signal is increased, the first transistor and the second transistor are able to stably drive at low loss, so the risk of a decrease in the stability of the operation of the capacitive load drive circuit is reduced, and the risk of a decrease in the waveform accuracy of the drive signal output by the capacitive load drive circuit is reduced.

[0274] In one embodiment of the capacitive load drive circuit, it can also be that,

[0275] The capacitive load driving circuit causes liquid to be ejected from the ejection portion at an ejection cycle of 10 μs or less.

[0276] In the capacitive load driving circuit, liquid is ejected from the ejection portion at an ejection cycle of 10 μs or less, so even if the driving signal output from the capacitive load driving circuit becomes a high frequency, the first transistor and the second transistor are able to stably drive with low loss, so the risk of a decrease in stability of operation of the capacitive load driving circuit is reduced, and the risk of a decrease in waveform precision of the driving signal output from the capacitive load driving circuit is reduced.

[0277] In one mode of the capacitive load driving circuit, it can also be that,

[0278] During a period in which the amplification circuit outputs the amplified modulation signal, the first transistor drives at a frequency of 8 MHz or more, and the second transistor drives at a frequency of 8 MHz or more.

[0279] In the capacitive load driving circuit, even if the driving frequency of the first transistor and the second transistor is a high frequency of 8 MHz or more, the first transistor and the second transistor are able to stably drive with low loss, so the risk of a decrease in stability of operation of the capacitive load driving circuit is reduced, and the risk of a decrease in waveform precision of the driving signal output from the capacitive load driving circuit is reduced.

[0280] In one mode of the capacitive load driving circuit, it can also be that,

[0281] The shortest period in the driving cycle of the first transistor is shorter than the shortest period in a period in which the voltage value of the driving signal changes, and is shorter than the shortest period in a period in which the voltage value of the driving signal is constant,

[0282] The shortest period in the driving cycle of the second transistor is shorter than the shortest period in a period in which the voltage value of the driving signal changes, and is shorter than the shortest period in a period in which the voltage value of the driving signal is constant.

[0283] In this capacitive load drive circuit, since the shortest period within the drive cycle of the first transistor is shorter than the shortest period within the period of voltage change of the drive signal, and shorter than the shortest period within the period of constant voltage of the drive signal, and the shortest period within the drive cycle of the second transistor is shorter than the shortest period within the period of voltage change of the drive signal, and shorter than the shortest period within the period of constant voltage of the drive signal, even when the drive frequencies of the first and second transistors are high, the first and second transistors can still be driven stably with low loss. Therefore, the risk of reduced stability of the operation of the capacitive load drive circuit is reduced, and the risk of reduced waveform accuracy of the drive signal output by the capacitive load drive circuit is reduced.

[0284] In one embodiment of the capacitive load drive circuit, it could also be that...

[0285] The capacitive load drive circuit has a feedback circuit that feeds the drive signal back to the modulation circuit.

[0286] In this capacitive load drive circuit, even when the driving frequencies of the first and second transistors are set to high frequencies, the risk of decreased stability in the operation of the capacitive load drive circuit is reduced. Therefore, the responsiveness via the feedback circuit can be improved in the capacitive load drive circuit. Consequently, the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved.

[0287] In one embodiment of the capacitive load drive circuit, it could also be that...

[0288] The capacitive load drive circuit is mounted on a carriage that moves along the main scanning axis, which intersects the transport direction of the medium that carries the liquid ejected from the ejection section to fall onto.

[0289] In this capacitive load drive circuit, the driving loss based on at least one of the first transistor and the second transistor is reduced, and the heat generation in the amplifier circuit is reduced. Therefore, even when the capacitive load drive circuit is mounted on the carriage, the risk of heat generation in the amplifier circuit contributing to the liquid and causing changes in the properties of the liquid is reduced.

Claims

1. A liquid ejection device, characterized in that, have: A capacitive load is displaced by being supplied with a drive signal; The ejector section ejects liquid as the capacitive load displaces; and The capacitive load drive circuit outputs the drive signal. The capacitive load drive circuit has: The modulation circuit outputs a modulated signal obtained by modulating the base driving signal, which serves as the basis of the driving signal. The first gate driving circuit outputs a first gate driving signal corresponding to the modulation signal; The second gate driving circuit outputs a second gate driving signal corresponding to the modulation signal; An amplifier circuit includes a first transistor and a second transistor. The first transistor is driven according to a first gate drive signal, and the second transistor is driven according to a second gate drive signal. The amplifier circuit outputs an amplified modulation signal by driving the first transistor and the second transistor. as well as The demodulation circuit outputs the driving signal obtained by demodulating the amplified modulation signal. The first transistor contains gallium nitride. The second transistor contains gallium nitride. The first gate drive circuit and the first transistor are housed in a package and constitute a first semiconductor device. The second gate drive circuit and the second transistor are housed in a package and constitute a second semiconductor device.

2. The liquid ejection device according to claim 1, characterized in that, The ejection cycle of the liquid ejected from the ejection section is less than 10 μs.

3. The liquid ejection device according to claim 1, characterized in that, During the period when the amplifier circuit outputs the amplified modulation signal, the first transistor is driven at a frequency of 8 MHz or higher, and the second transistor is driven at a frequency of 8 MHz or higher.

4. The liquid ejection device according to claim 1, characterized in that, The shortest period within the driving cycle of the first transistor is shorter than the shortest period within the period of voltage change of the driving signal, and shorter than the shortest period within the period of constant voltage of the driving signal. The shortest period within the driving cycle of the second transistor is shorter than the shortest period within the period during which the voltage value of the driving signal changes, and shorter than the shortest period within the period during which the voltage value of the driving signal is constant.

5. The liquid ejection device according to claim 1, characterized in that, The capacitive load drive circuit has a feedback circuit that feeds the drive signal back to the modulation circuit.

6. The liquid ejection device according to claim 1, characterized in that, The liquid ejection device includes a carriage that moves along a main scanning axis, which intersects the transport direction of the medium that carries the liquid ejected from the ejection section to land on. The capacitive load, the ejector, and the capacitive load drive circuit are mounted on the carriage.

7. A capacitive load driving circuit, characterized in that, The capacitive load driving circuit outputs a driving signal to the capacitive load, which is displaced by the supplied driving signal to eject liquid from the ejector. The capacitive load driving circuit has the following features: The modulation circuit outputs a modulated signal obtained by modulating the base driving signal, which serves as the basis of the driving signal. The first gate driving circuit outputs a first gate driving signal corresponding to the modulation signal; The second gate driving circuit outputs a second gate driving signal corresponding to the modulation signal; An amplifier circuit includes a first transistor and a second transistor. The first transistor is driven according to a first gate drive signal, and the second transistor is driven according to a second gate drive signal. The amplifier circuit outputs an amplified modulation signal by driving the first transistor and the second transistor. as well as The demodulation circuit outputs the driving signal obtained by demodulating the amplified modulation signal. The first transistor contains gallium nitride. The second transistor contains gallium nitride. The first gate drive circuit and the first transistor are housed in a package and constitute a first semiconductor device. The second gate drive circuit and the second transistor are housed in a package and constitute a second semiconductor device.

8. The capacitive load driving circuit according to claim 7, characterized in that, The capacitive load drive circuit causes the liquid to be ejected from the ejection section at an ejection cycle of less than 10 μs.

9. The capacitive load driving circuit according to claim 7, characterized in that, During the period when the amplifier circuit outputs the amplified modulation signal, the first transistor is driven at a frequency of 8 MHz or higher, and the second transistor is driven at a frequency of 8 MHz or higher.

10. The capacitive load driving circuit according to claim 7, characterized in that, The shortest period within the driving cycle of the first transistor is shorter than the shortest period within the period of voltage change of the driving signal, and shorter than the shortest period within the period of constant voltage of the driving signal. The shortest period within the driving cycle of the second transistor is shorter than the shortest period within the period during which the voltage value of the driving signal changes, and shorter than the shortest period within the period during which the voltage value of the driving signal is constant.

11. The capacitive load driving circuit according to claim 7, characterized in that, The capacitive load drive circuit has a feedback circuit that feeds the drive signal back to the modulation circuit.

12. The capacitive load driving circuit according to claim 7, characterized in that, The capacitive load drive circuit is mounted on a carriage that moves along the main scanning axis, which intersects the transport direction of the medium that carries the liquid ejected from the ejection section to fall onto.

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