Preprocessing circuit, correction device, laser radar, and vehicle

Abstract

A pre-processing circuit, a correction device, a lidar, and a vehicle are disclosed. The pre-processing circuit can be used for the lidar and comprises a clock source and a correction circuit. The clock source is configured to provide a first multi-phase clock signal, the first multi-phase clock signal comprises a first number of first clock signals, and adjacent first clock signals in the first number of first clock signals differ by a preset phase; and a correction circuit configured to receive the first multi-phase clock signal and correct the first multi-phase clock signal to a second multi-phase clock signal, where the second multi-phase clock signal includes a second number of second clock signals, the second number is half of the first number, and a duty cycle of the second clock signals is 50%.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of optical detection, and in particular to a preprocessing circuit, a correction device, a laser radar, and a vehicle. BACKGROUND

[0002] Optical detection technology detects objects by using light as a medium. Laser has the characteristics of monochromaticity and good directivity compared with ordinary light sources, and object detection by using laser as a medium has been widely applied. For example, laser radar (LiDAR) detects objects by using laser as a medium, and has been applied in the fields of intelligent driving, unmanned aerial vehicles, robot recognition, geographic mapping, and environmental monitoring. However, laser radar still has the problem of high power consumption in the application process. SUMMARY

[0003] Embodiments of the present disclosure provide a preprocessing circuit, a correction device, a laser radar, and a vehicle to reduce the power consumption of the laser radar in the application process.

[0004] In a first aspect, a preprocessing circuit for a laser radar is provided. The preprocessing circuit includes a clock source configured to provide a first multi-phase clock signal, the first multi-phase clock signal including a first number of first clock signals, adjacent first clock signals in the first number of first clock signals differing by a preset phase; and a correction circuit configured to receive the first multi-phase clock signal and correct the first multi-phase clock signal into a second multi-phase clock signal, the second multi-phase clock signal including a second number of second clock signals, the second number being half of the first number, and a duty cycle of the second clock signals being 50%.

[0005] In the above correction device, the correction circuit is used to convert two clock signals into one clock signal with a duty cycle of 50%, and then the rising edge and the falling edge of the converted clock signal can be sampled to obtain the effective information of the two clock signals. In this way, the number of clock signals connected to the sampling circuit is reduced, and the wiring requirement is reduced, so that the wiring complexity of the laser radar is reduced, the power consumption of the laser radar in use is reduced, and the cost of the laser radar is reduced. In addition, the above correction device takes into account the detection accuracy of the laser radar.

[0006] Optionally, the rising edge and the falling edge of the second clock signal differ by a second number of preset phases.

[0007] Optionally, the correction circuit comprises: a detection circuit configured to receive the first multi-phase clock signal, output a first number of pulse signals based on a first number of rising edges of the first clock signal; and a conversion circuit configured to receive the first number of pulse signals and convert the first number of pulse signals into a second number of second clock signals; wherein the first number of pulse signals comprises a first pulse signal and a second pulse signal; the first pulse signal is used to convert into a rising edge of the second clock signal, and the second pulse signal is used to convert into a falling edge of the second clock signal; or the first pulse signal is used to convert into a falling edge of the second clock signal, and the second pulse signal is used to convert into a rising edge of the second clock signal.

[0008] Optionally, the first pulse signal is generated based on rising edges of a first group of the first clock signals, the second pulse signal is generated based on rising edges of a second group of the first clock signals, the first clock signals in the first group have a first phase difference, the first clock signals in the second group have a second phase difference, and the first phase difference is equal to the second phase difference.

[0009] Optionally, the first phase difference comprises a third number of preset phases, and the third number of preset phases is such that the first pulse signal and the second pulse signal do not overlap.

[0010] Optionally, the third number is less than or equal to 1 / 4 of the first number.

[0011] Optionally, the detection circuit comprises a second number of logic circuit groups, each logic circuit group comprises a first logic circuit and a second logic circuit; the first logic circuit is coupled to a first signal and a second signal in the first group of the first clock signals, converts an overlapping region of a first value of the first signal and a second value of the second signal into a pulse duration of the first pulse signal, and outputs the first pulse signal; the second logic circuit is coupled to a third signal and a fourth signal in the second group of the first clock signals, converts an overlapping region of a first value of the third signal and a second value of the fourth signal into a pulse duration of the second pulse signal, and outputs the second pulse signal; and the conversion circuit comprises a second number of holding circuits, one holding circuit is coupled to the first pulse signal and the second pulse signal of one logic circuit group, and maintains a state of the second clock signal triggered by the first pulse signal until the second pulse signal arrives, or maintains a state of the second clock signal triggered by the second pulse signal until the first pulse signal arrives.

[0012] Optionally, the preprocessing circuit further comprises a driving circuit configured to receive the second multi-phase clock signal and provide the second multi-phase clock signal to a sampling circuit of the laser radar, and rising edges and falling edges of the second multi-phase clock signal are used to trigger sampling of the sampling circuit.

[0013] In a second aspect, a correction device is provided, comprising: an interface configured to receive a first multi-phase clock signal, the first multi-phase clock signal comprising a first number of first clock signals, adjacent first clock signals in the first number of first clock signals being separated by a preset phase; and a correction circuit configured to correct the first multi-phase clock signal into a second multi-phase clock signal, wherein the second multi-phase clock signal comprises a second number of second clock signals, the second number being half of the first number, and a duty cycle of the second clock signals being 50%.

[0014] Optionally, the rising edge and the falling edge of the second clock signal are separated by a second number of preset phases.

[0015] Optionally, the correction circuit comprises: a detection circuit configured to receive the first multi-phase clock signal and output a first number of pulse signals based on rising edges of the first number of first clock signals; and a conversion circuit configured to receive the first number of pulse signals and convert the first number of pulse signals into the second number of second clock signals, wherein the first number of pulse signals comprises a first pulse signal and a second pulse signal, the first pulse signal being used to convert into a rising edge of the second clock signal, and the second pulse signal being used to convert into a falling edge of the second clock signal, or the first pulse signal being used to convert into a falling edge of the second clock signal, and the second pulse signal being used to convert into a rising edge of the second clock signal.

[0016] Optionally, the first pulse signal is generated based on rising edges of a first group of first clock signals, the second pulse signal is generated based on rising edges of a second group of first clock signals, the first clock signals in the first group of first clock signals have a first phase difference, the first clock signals in the second group of first clock signals have a second phase difference, and the first phase difference is equal to the second phase difference.

[0017] Optionally, the first phase difference comprises a third number of preset phases, the third number of preset phases being such that the first pulse signal and the second pulse signal do not overlap.

[0018] Optionally, the third number is less than or equal to 1 / 4 of the first number.

[0019] Optionally, the detection circuit includes a second number of logic circuit groups, the logic circuit group including a first logic circuit and a second logic circuit; the first logic circuit is coupled to a first signal and a second signal in the first group of the first clock signals, converts an overlapping region of a first value of the first signal and a second value of the second signal into a pulse duration of a first pulse signal, and outputs the first pulse signal; the second logic circuit is coupled to a third signal and a fourth signal in the second group of the first clock signals, converts an overlapping region of a first value of the third signal and a second value of the fourth signal into a pulse duration of a second pulse signal, and outputs the second pulse signal; the conversion circuit includes a second number of holding circuits, one holding circuit being coupled to the first pulse signal and the second pulse signal of one logic circuit group, and maintaining a state of the second clock signal triggered by the first pulse signal until the second pulse signal arrives, or maintaining a state of the second clock signal triggered by the second pulse signal until the first pulse signal arrives.

[0020] In a third aspect, a laser radar is provided, including: a laser configured to emit a laser; a detector configured to receive a return wave of the laser, and convert the return wave into a return wave electrical signal; and a pre-processing circuit as provided in the first aspect above, connected to the detector.

[0021] In a fourth aspect, a vehicle is provided, including: a main body; and a laser radar as provided in the third aspect above, mounted on the main body. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings used in the embodiments description will be exemplarily introduced below, and the drawings in the following description are merely some of the present disclosure, and those skilled in the art can also obtain other drawings according to the provided drawings without paying creative labor. The drawings are used to provide further understanding of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure, and do not constitute a limitation on the present disclosure.

[0023] Figure 1 An example structure diagram of a laser radar provided in some embodiments of the present disclosure is shown.

[0024] Figure 2 An example structure diagram of a pre-processing circuit provided in some embodiments of the present disclosure is shown.

[0025] Figure 3 An example waveform diagram of a multi-phase clock signal provided in some embodiments of the present disclosure is shown.

[0026] Figure 4 An example structure diagram of a correction device provided in some embodiments of the present disclosure is shown.

[0027] Figure 5 An example diagram of a structure of another pre-processing circuit provided in some embodiments of the present disclosure is shown.

[0028] Figure 6 An example diagram of a structure of a correction circuit provided in some embodiments of the present disclosure is shown.

[0029] Figure 7 An example diagram of waveforms of signals of a correction circuit provided in some embodiments of the present disclosure is shown.

[0030] Figure 8 An example diagram of waveforms of signals of another correction circuit provided in some embodiments of the present disclosure is shown.

[0031] Figure 9 An example diagram of a structure of another correction circuit provided in some embodiments of the present disclosure is shown.

[0032] Figure 10 An example diagram of a structure of another correction circuit provided in some embodiments of the present disclosure is shown.

[0033] Figure 11 An example diagram of a structure of yet another correction circuit provided in some embodiments of the present disclosure is shown.

[0034] Figure 12 An example diagram of a structure of another pre-processing circuit provided in some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, specific embodiments of the present disclosure will be described below with reference to the drawings. The drawings in the following description are only some embodiments of the present disclosure, and for those of ordinary skill in the art, other drawings can be obtained from these drawings without creative labor, and other embodiments can be obtained without departing from the concept of the present disclosure, and adjustments and improvements made within the scope of the present disclosure.

[0036] In order to make the drawings simple, each drawing only schematically represents the part related to the corresponding embodiment, and it does not represent the actual structure of the product. In addition, in order to make the drawings simple and easy to understand, only some structures or components are schematically shown, and there may be more or less similar structures or components.

[0037] Lidar uses laser as medium to detect objects and has been applied in many fields. For example, lidar can be applied in intelligent driving, industrial manufacturing, unmanned aerial vehicle, robot recognition, geographic mapping, or environmental monitoring, etc. Intelligent driving can also be referred to as autonomous driving or assisted driving, including any level of autonomous driving, such as L1-L5, etc. In applications, lidar can be installed on a vehicle to provide perception data, such as point cloud data, for the vehicle, so that the vehicle uses the perception data to realize one or more functions, such as analysis, decision, or control, etc. The vehicle includes, but is not limited to, a vehicle, a manufacturing terminal, a ship, an aircraft (such as a flying vehicle or a drone, etc.), a robot (such as an industrial robot or a household robot, etc.), or a mapping device, etc.

[0038] Lidar can include, but is not limited to, a mechanical lidar, a semi-solid lidar, or a solid lidar. The semi-solid lidar can include, but is not limited to, a micro electro mechanical system (MEMS) lidar, a rotating mirror lidar, a swinging mirror lidar, or a prism lidar, etc. The solid lidar can include, but is not limited to, an optical phase array (OPA) lidar, or a flash lidar, etc. When a vehicle is installed with multiple lidars, the types of lidars can be the same or different.

[0039] Figure 1 A structural example diagram of a lidar provided in some embodiments of the present disclosure is shown. Please refer to Figure 1 The lidar 100 includes a laser emitting system 110, a laser receiving system 120, and a control and processing system 130. Optionally, the lidar 100 can also include a scanning system 140. Taking a mechanical lidar or a semi-solid lidar as an example, the scanning system 140 can include, for example, a scanner and a driver for driving the scanner to rotate, so that the laser realizes scanning of one or all of the vertical or horizontal fields of view. For example, the laser exits through the scanner, and the rotation of the scanner can change the exit path of the laser; for another example, the echo of the laser can be incident on the scanner and guided to the light receiving path through the scanner. The embodiments of the present disclosure do not limit the type of scanner, which can include, but is not limited to, a rotating mirror, a swinging mirror, a vibrating mirror, or other devices that can make the laser shoot in different directions in the environment, etc. For another example, the scanning system 140 can include a rotating platform; one or more components in the laser emitting system 110, or the laser receiving system 120, etc. can be arranged on the rotating platform, and the rotation of the rotating platform realizes scanning of one or all of the vertical or horizontal fields of view.

[0040] The laser emission system 110 can emit laser light. After the laser light encounters an object, the laser light is reflected by the surface of the object. The reflected light that is reflected back to the lidar 100 is called a return. The laser receiving system 120 can receive the return and convert the return into an electrical signal. After the electrical signal is preprocessed, return data is obtained. The return data is provided to the control and processing system 130. The control and processing system 130 processes the return data to obtain perception data, such as point cloud data.

[0041] The laser emission system 110 includes, for example, a driving circuit, a laser, and an emission optical element. The laser emits laser light under the driving of the driving circuit, and the laser light exits through the emission optical element. The laser includes, for example, a semiconductor laser, a fiber laser, or another type of laser. The semiconductor laser includes, for example, a laser emission circuit, a vertical cavity surface emitting laser (VCSEL), an edge emitting laser (EEL), a distributed feedback laser (DFB), or a similar device. The above is merely an example, and embodiments of the present disclosure do not limit the type of laser.

[0042] The laser receiving system 120 includes, for example, a receiving optical element and a detector. The receiving optical element collects the return that is reflected by an object onto a light-sensitive surface of the detector. The detector converts an optical signal into an electrical signal using a photoelectric effect. The detector includes, for example, a photodetection circuit, a PIN photo diode (PIN PD), an avalanche photo diode (APD), a single photon avalanche diode (SPAD), a Silicon photomultiplier (SiPM), or a similar device. The above is merely an example, and embodiments of the present disclosure do not limit the type of detector.

[0043] The transmitting optical element is on the transmitting path of the laser, for shaping the laser emitted by the laser and adjusting the exit path of the laser. The receiving optical element is on the receiving path of the laser, for collecting the echo reflected by the object and converging the echo to the light-sensitive surface of the detector. For example, the transmitting optical element includes one or more optical elements such as a transmitting lens, a mirror, a homogenizer, a beam splitter, etc. For example, the receiving optical element includes one or more optical elements such as a receiving lens, a mirror, a filter, a beam splitter (or a beam splitter mirror), etc. The transmitting optical element and the receiving optical element can be independent, partially multiplexed, or fully multiplexed. For example, the laser radar can include independent transmitting optical elements and receiving optical elements, such as independent transmitting lenses and receiving lenses. For example, the laser radar can include an optical element shared by the transmitting optical path and the receiving optical path, such as a beam splitter, for separating the transmitting optical path and the receiving optical path; for example, the laser radar can include a shared lens for shaping coaxial beams on the transmitting optical path and the receiving optical path.

[0044] The preprocessing includes one or more of amplification, filtering, or sampling, etc. The preprocessing can be implemented by a preprocessing circuit or a receiving circuit. The preprocessing circuit includes one or more of an amplification circuit, a filtering circuit, or a sampling circuit, etc. The amplification circuit includes an amplifier, which can amplify the electrical signal converted by the detector. The filtering circuit includes a filter, which can filter out noise or interference. The sampling circuit includes one or more of an analog-to-digital converter (ADC) or a time-to-digital converter (TDC), etc. For example, the ADC can convert the analog electrical signal into a digital signal representing the waveform of the echo by periodically sampling the output signal of the detector, to obtain the echo data. For another example, the TDC can measure the time of arrival of the echo by time sampling the output signal of the detector, to obtain the echo data. For example, the current signal output by the detector can be converted into a voltage signal and compared with a reference voltage to generate a threshold crossing signal. The TDC measures the threshold crossing time based on the received threshold crossing signal, to implement time sampling and obtain the echo data. The echo data can include data representing one or more parameters such as echo time or echo intensity.

[0045] The control and processing system 130 can process the echo data to obtain perception data. The control and processing system 130 can also send control signaling to the driving circuit to control the driving circuit to drive the laser to emit light, so as to realize the emission of the laser. When the laser radar 100 includes the scanning system 140, the control and processing system 130 can also control the motion of the scanning system 140. In some embodiments of the present disclosure, the control and processing system 130 can include one or more processors. The processor includes, for example but not limited to, an application specific integrated circuit (ASIC), a programmable logic device (PLD) implemented hardware circuit, a microcontroller unit (MCU), a microprocessor unit (MPU), a digital signal processor (DSP), or a central processing unit (CPU), etc. The PLD implemented hardware circuit can include, for example but not limited to, a field programmable gate array (FPGA), etc. When the control and processing system 130 includes multiple processors, the types of the processors can be the same or different. For example, the control and processing system 130 can include an MCU and an FPGA; or, the control and processing system 130 can include an MCU, an FPGA and a CPU; the control and processing system 130 can include an MCU, a DSP and an FPGA; or, the control and processing system 130 can include a CPU and an FPGA, etc. When the control and processing system 130 includes multiple processors, the processors can be separately arranged, or partially integrated together, or can be all integrated together. For example, the control and processing system 130 can be implemented in the form of a system on chip (SOC) or an ASIC.

[0046] The TDC time samples the clock. The clock can include a coarse clock and a fine clock. The coarse clock and the fine clock are relative concepts, and the clock period of the coarse clock is longer than that of the fine clock. For example, the clock period of the coarse clock includes 80ps, and the clock period of the fine clock includes 10ps or 20ps, etc. The above is only an example, and the embodiments of the present disclosure do not limit the clock period of the coarse clock and the fine clock.

[0047] For example, Figure 2 A structural example diagram of a pre-processing circuit provided in some embodiments of the present disclosure is shown. Please refer to Figure 2The detection pixel 10 can include one or more detectors to photoelectrically convert the received echo to output an electrical signal S. The signal S can be provided to a pre-processing circuit 200, which includes a TDC 210 to time sample based on the signal S to output echo data D.

[0048] The laser radar can include a plurality of detection pixels 10. When the detection pixel 10 includes a plurality of detectors, the accumulation of the output signals of the plurality of detectors can be used to reduce noise interference and more accurately obtain valid signals. The plurality of detectors can be arranged in an array, which can include a one-dimensional array or a two-dimensional array. A conversion circuit 30 can also be provided between the detection pixel 10 and the TDC 210, which can convert the electrical signal S output by the detection pixel 10 into a pulse signal T. The pulse signal T can trigger the sampling of the TDC 210. For example, the electrical signal output by the detection pixel 10 can include a current signal, which can be converted by the conversion circuit 30 into a voltage signal. The conversion circuit 30 can also compare the voltage signal with a reference voltage and generate a pulse signal T when the voltage signal reaches or exceeds the reference voltage. The pulse signal T can be referred to as a threshold crossing signal, which can be provided directly or after conversion to the TDC 210. The pulse signal T can also be referred to as a trigger signal for triggering the TDC 210 to perform time sampling. When the detection pixel 10 includes a plurality of detectors, the conversion circuit 30 can also output a number signal (not shown in the figure). The number signal indicates the number of detectors that are triggered at the same time or within a time period. The conversion circuit 30 can be integrated in the pre-processing circuit 200, or can be integrated in the detector array where the detection pixel 10 is located, or can be independently provided, and the embodiments of the present disclosure do not limit this.

[0049] The TDC 210 is connected to a clock source 220. The clock source 220 can include, for example, a multi-phase clock. For example, the clock source 220 can include a coarse clock signal C0 and a fine clock signal C1. The embodiments of the present disclosure do not limit the generation method of the coarse clock signal C0 and the fine clock signal C1. For example, the coarse clock signal C0 and the fine clock signal C1 can be generated by a voltage controlled oscillator (VCO). For example, the clock source 220 includes a VCO, which can include an n-stage differential structure and can output a clock signal with 2n phases, where n is a positive integer greater than 1.

[0050] Figure 3 A waveform example diagram of a multi-phase clock signal provided in some embodiments of the present disclosure is shown. Please refer to Figure 2 and Figure 3 The multi-phase clock signal includes clock signals C11-C1n and clock signals C21-C2n.

[0051] In some embodiments, clock source 220 includes a multi-phase clock signal. For example, clock source 220 includes a VCO. For each stage of the VCO, a corresponding delay unit can be set, and the delay difference is expressed as ΔT. Figure 3 As shown, among the 2n multi-phase clock signals C11 to C2n, there is a delay difference ΔT between adjacent clock signals.

[0052] In some embodiments, the first counter 231 receives a clock signal C01 provided by the clock source 220. For example, the clock signal C01 is generated based on any one of the clock signals C11 to C2n (Cx). Alternatively, any one of the clock signals C11 to C2n (Cx) can be used as the clock signal C01. Taking Cx as C11 as an example, refer to... Figure 3 In each cycle T0 of the multi-phase clock, the clock signal C11 triggers the first counter 231 to jump once. By sampling the position of the first counter 231, a coarse time with a resolution of T0 can be obtained.

[0053] If the sampling time falls on the jump edge of the first counter 231, it may be impossible to determine the position. This situation is called metastability, and sampling errors will occur. To address this, a second counter 232 can be set at a certain time interval from the first counter 231.

[0054] In some embodiments, the second counter 232 receives a clock signal C02 provided by the clock source 220. For example, the clock signal C01 is generated based on any one of the clock signals C11 to C2n. Alternatively, any one of the clock signals C11 to C2n can be used as the clock signal C01. x ≠ y. Taking C21 as an example, refer to... Figure 3 In each cycle T0 of the multi-phase clock, the clock signal C21 triggers the second counter 232 to jump once. By sampling the position of the second counter 232, a coarse time with a resolution of T0 can be obtained.

[0055] The first counter 231 and the second counter 232 switch based on different clock signals. The first counter 231 and the second counter 232 will not be in a switching state simultaneously. Sampling at least one of the first counter 231 and the second counter 232 can yield an accurate coarse time.

[0056] refer to Figure 3 The multi-phase clocks are passed sequentially with a delay difference ΔT. Clock signals C11-C1n and C21-C2n are sampled, and the time refined to a resolution of ΔT can be determined based on the phase at the sampling moment. TDC210 includes, for example, a first sampling circuit 211, a second sampling circuit 212, a decoder 214, a selection circuit 215, and a synchronization circuit 216.

[0057] The second sampling circuit 212 can sample the first counter 231 when the trigger edge of the pulse signal T arrives, to obtain data D1 reflecting the first coarse time.

[0058] The TDC 210 can further include a third sampling circuit 213. The third sampling circuit 213 can sample the second counter 232 when the trigger edge of the pulse signal T arrives, to obtain data D2 reflecting the second coarse time. A selection circuit 215 can select the data D1 or the data D2 to output to the synchronization circuit 216. For example, the selection circuit 215 can select the sampling data of the counter that does not jump, and output to the synchronization circuit 216.

[0059] The first sampling circuit 211 samples the multi-phase clock signal when the trigger edge of the pulse signal T arrives, to obtain phase data P. The phase data P can reflect the fine time. The phase data P can be provided to the decoder 214, and then provided to the data synchronization circuit 216 after decoding by the decoder 214.

[0060] The synchronization circuit 216 can generate echo data D based on the received data reflecting the coarse time and the fine time. Optionally, when the detection pixel 10 includes a plurality of detectors, the conversion circuit 30 can further send a quantity signal to the synchronization circuit 216. The synchronization circuit 216 can generate echo data based on the quantity signal and the data reflecting the coarse time and the fine time. For example, the echo data represents the number of detectors triggered at a certain time.

[0061] The above trigger edge can include a rising edge or a falling edge. The duty cycle of the multi-phase clock signal is usually not ideal 50%, so the first sampling circuit 211 only samples the rising edge of the clock signal. At this time, the first sampling circuit 211 needs to be connected with each clock signal of the multi-phase clock, resulting in high wiring and clock sampling power consumption. In addition, the laser radar can include a plurality of detection pixels 10. In order to improve the sampling efficiency, a parallel sampling structure can be used, and a plurality of TDCs are arranged in parallel to sample a plurality of detection pixels 10. The large number of sampling circuits leads to further increase in wiring complexity and clock sampling power consumption, and the cost of the laser radar is relatively high, which limits the application of the laser radar.

[0062] The embodiments of the present disclosure provide some schemes, for example, including a preprocessing circuit, a correction device, a laser radar, and a vehicle, which can reduce the power consumption and cost of the laser radar, and take into account the sampling accuracy of the echo time of the laser radar.

[0063] The embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0064] Figure 4A structural diagram of a correction device is shown. The correction device can be used in a lidar. Please refer to Figure 4 The correction device 400 includes an interface 410 and a correction circuit 420. The interface 410 can receive a first multi-phase clock signal. The first multi-phase clock signal includes a first number M of first clock signals CLK1. Adjacent first clock signals CLK1 in the first number M of first clock signals CLK1 differ by a preset phase, i.e., the first multi-phase clock signal includes M phases. The correction circuit 420 can correct the first multi-phase clock signal into a second multi-phase clock signal. The second multi-phase clock signal includes a second number N of second clock signals CLK2, i.e., the second multi-phase clock signal includes N phases. The second number N is half of the first number M, and the duty cycle of the second clock signal CLK2 is 50%.

[0065] In the above correction device, the correction circuit 420 is used to convert two clock signals into one clock signal with a 50% duty cycle, and then the rising edge and the falling edge of the converted clock signal can be sampled to obtain the effective information of the two clock signals. In this way, the number of clock signals connected to the sampling circuit is reduced, and the wiring demand is reduced, so that the wiring complexity of the lidar is reduced, the power consumption during use of the lidar is reduced, and the cost of the lidar is reduced. In addition, the above correction device takes into account the detection accuracy of the lidar.

[0066] The above detection device can be used in the preprocessing circuit of the lidar to provide a multi-phase clock signal for the TDC. The embodiments of the present disclosure do not limit the use range of the detection device, and the detection device can also be used in other positions of the lidar, which can perform time sampling based on the multi-phase clock signal. Alternatively, the detection device can also be used in other electronic devices, which include a sampling circuit and perform time sampling based on the multi-phase clock signal.

[0067] Figure 5 A structural diagram of another preprocessing circuit is shown. Relative to the preprocessing circuit shown in Figure 2 The preprocessing circuit 500 includes the above correction device 400, which is arranged between the clock source 220 and the first sampling circuit 211. The first multi-phase clock signal received by the correction device 400 includes clock signals C11-C1n and clock signals C21-C2n, and the second multi-phase clock signal output by the correction device 400 includes clock signals C31-C3n.

[0068] In some embodiments of the present disclosure, the rising edge and the falling edge of the second clock signal differ by a second preset phase quantity. For example, the rising edges of the clock signal C1x and the clock signal C2x can be corrected by the correction device 400 into the rising edge and the falling edge of the clock signal C3x, where x∈[1, n]. In this way, the rising edge and the falling edge of the second clock signal can be used for sampling of the sampling circuit. The rising edge of the second clock signal can be used to determine the fine time, and the falling edge can be used to determine the second fine time, so that the circuit of the detection device is more simple, and the cost of the lidar is further reduced.

[0069] Figure 6 An example structure diagram of a correction circuit provided in some embodiments of the present disclosure is shown. Please refer to Figure 6 The correction circuit 620 includes, for example, a detection circuit 621 and a conversion circuit 622. The detection circuit 621 can receive a first multi-phase clock signal and output a first quantity M of pulse signals based on the rising edges of the first quantity M of the first clock signals CLK1. The conversion circuit 622 can receive the first quantity M of pulse signals and convert the first quantity M of pulse signals into a second quantity N of second clock signals CLK2. The first quantity M of pulse signals includes a first pulse signal P1 and a second pulse signal P2, and the first pulse signal P1 and the second pulse signal P2 are respectively used to convert the rising edge and the falling edge of the second clock signal CLK2. The number of the first pulse signals P1 and the number of the second pulse signals P2, for example, include the second quantity N.

[0070] In some embodiments of the present disclosure, the first pulse signal P1 is generated based on the rising edges of a first group of the first clock signals, and the second pulse signal P2 is generated based on the rising edges of a second group of the first clock signals. The first clock signals in the first group have a first phase difference, and the first clock signals in the second group have a second phase difference. The first phase difference and the second phase difference are equal. Through this symmetrical design, the structure of the detection circuit and the conversion circuit can be simplified, and the cost of the lidar is further reduced. In addition, the control of the pulse duration of the first pulse signal and the second pulse signal can be realized by using the first multi-phase clock signal, without the need to additionally introduce a control signal, which further simplifies the design of the detection circuit and reduces the demand for signals, so that the cost of the lidar is further reduced.

[0071] For example, Figure 7An example diagram showing waveforms of signals of a correction circuit provided in some embodiments of the present disclosure is shown. Taking an example of a first multi-phase clock signal including clock signals C11-C1n, and clock signals C21-C2n. Two clock signals with a phase difference ph in the clock signals C11-C1n can be divided into a group, and two clock signals with the same phase difference ph in the clock signals C21-C2n can be divided into a group. For example, clock signals C11 and C1a are a group, and clock signals C21 and C2a are a group, where a∈(1,n). The rising edge of the clock signal C11 can be used to trigger the generation of a first pulse signal P1, and the rising edge of the clock signal C1a can be used to trigger the end of the first pulse signal P1. Similarly, the rising edge of the clock signal C21 can be used to trigger the generation of a second pulse signal P2, and the rising edge of the clock signal C2a can be used to trigger the end of the second pulse signal P2. The same phase difference ph can make the first pulse signal P1 and the second pulse signal P2 have the same duration. In the diagram, an example of the first pulse signal P1 and the second pulse signal P2 as negative pulses is taken, and embodiments of the present disclosure are not limited thereto. For example, the first pulse signal P1 and the second pulse signal P2 can be positive pulses. The first pulse signal P1 and the second pulse signal P2 can be converted into a second clock signal CLX2, for example, the first pulse signal P1 triggers the generation of the rising edge of the second clock signal CLX2, and the second pulse signal P2 triggers the generation of the falling edge of the second clock signal CLX2; or, the first pulse signal P1 triggers the generation of the falling edge of the second clock signal CLX2, and the second pulse signal P2 triggers the generation of the rising edge of the second clock signal CLX2.

[0072] In some embodiments of the present disclosure, the pulse duration of the first pulse signal P1 and the second pulse signal P2 can be controlled by an additional control signal. For example, Figure 7 The clock signals C1a and C2a in the above can be replaced by a control signal. The first pulse signal P1 can be generated based on the rising edge of the first clock signal C11 and the control signal, and the second pulse signal P2 can be generated based on the rising edge of the first clock signal C21 and the control signal.

[0073] In some embodiments of the present disclosure, the phase difference ph (the first phase difference or the second phase difference) includes a third number of preset phases, which makes the first pulse signal P1 and the second pulse signal P2 not overlap. For example, the third number is less than or equal to 1 / 4 of the first number M. For example, assuming that the first number M is 8, the third number includes 1 or 2. Similarly, the phase difference between the control signal and the corresponding first clock signal makes the first pulse signal P1 and the second pulse signal P2 not overlap.

[0074] For a high-precision clock source, the time interval between adjacent clock signals output may be very short. By using a first clock signal with a preset phase difference of a third number to generate a first pulse signal P1 and a second pulse signal P2, the pulse width of the first pulse signal P1 and the second pulse signal P2 can be extended, allowing the conversion circuit 622 to better respond to the first pulse signal P1 and the second pulse signal P2. This reduces the requirement for the response time of the conversion circuit 622, thereby improving the stability of the correction circuit; or, it reduces the performance requirements of the correction circuit, thereby reducing the cost of the correction circuit.

[0075] For example, Figure 8 The diagram shows an example waveform of a signal from another correction circuit provided in some embodiments of this disclosure. Again, the example uses a first multi-phase clock signal comprising clock signals C11-C1n and clock signals C21-C2n. Please refer to... Figure 8 ,and Figure 7 The difference lies in that clock signals C11 and C1b are grouped together, and clock signals C21 and C2b are grouped together, where b∈(1,n) and b is greater than a. That is, the phase difference between clock signal C1b and clock signal C11 is greater than the phase difference between clock signal C1a and clock signal C11. By setting the phase difference between the first clock signals included in the first clock signal group, the pulse width of the first pulse signal P1 and the second pulse signal P2 is extended, providing a more generous response time for the conversion circuit 622 and making the response speed of the conversion circuit 622 more favorable.

[0076] In some embodiments of this disclosure, the detection circuit can be implemented using logic circuits, and the conversion circuit can be implemented using latches. For example, Figure 9 A structural example diagram of another correction circuit provided in some embodiments of this disclosure is shown. Please refer to... Figure 9The detection circuit 921 includes, for example, a second number N of logic circuit groups 921-1 to 921-N; a logic circuit group includes a first logic circuit 9211 and a second logic circuit 9212. The first logic circuit 9211 is coupled to a first signal and a second signal (for example, clock signals C11 and C1e, or clock signals C1f and C1n) in a first group of first clock signals, performs a logic operation on the first signal and the second signal, and outputs a first pulse signal P1. The logic operation is used to convert an overlapping region of a first value of the first signal and a second value of the second signal into a pulse duration of the first pulse signal P1. Similarly, the second logic circuit 9212 is coupled to a third signal and a fourth signal (for example, clock signals C21 and C2e, or clock signals C2f and C2n) in a second group of first clock signals, performs a logic operation on the third signal and the fourth signal, and outputs a second pulse signal. The logic operation is used to convert an overlapping region of a first value of the third signal and a second value of the fourth signal into a pulse duration of the second pulse signal P2. The conversion circuit 922 includes, for example, a second number N of holding circuits 922-1 to 922-N; one holding circuit is coupled to the first pulse signal P1 and the second pulse signal P2 of one logic circuit group, and holds a state of the second clock signal CLK2 triggered by the first pulse signal P1 until the second pulse signal P2 arrives, or holds a state of the second clock signal CLK2 triggered by the second pulse signal P2 until the first pulse signal P1 arrives.

[0077] The embodiments of the present disclosure do not limit the composition of the first logic circuit and the second logic circuit, and can be adaptively designed according to the coupling of the first clock signal. For example, please continue to refer to Figure 7 and Figure 8 The values of the first clock signals C11 and C1a (or C11 and C1b) on the left side of the dashed box are both 0, the values of the first clock signals C11 and C1a (or C11 and C1b) on the right side of the dashed box are both 1; the values of the first clock signals C11 and C1a (or C11 and C1b) in the dashed box are 1 and 0 respectively, which can be distinguished from the values of the two first clock signals C11 and C1a (or C11 and C1b) outside the dashed box through a logic operation relationship, so as to obtain the first pulse signal P1. Similarly, the values of the two first clock signals C21 and C2a (or C21 and C2b) in the dashed box can be distinguished from the values of the two first clock signals outside the dashed box through a logic operation relationship, so as to obtain the second pulse signal P2.

[0078] The embodiments of the present disclosure do not limit the composition of the holding circuit, and the holding circuit may be implemented by, for example, a logic circuit, a flip-flop, or a latch. The latch is simple to implement and is conducive to reducing the cost of the conversion circuit. For example, the holding circuit includes a latch, a set end SB of the latch is coupled to the first pulse signal P1, a reset end RB of the latch is coupled to the second pulse signal P2, and the second clock signal CLK2 is output based on the first pulse signal P1 and the second pulse signal P2.

[0079] For example, Figure 10 An example of the structure of another correction circuit provided in some embodiments of the present disclosure is shown. The logic circuit includes, for example, a NAND gate and an inverter (or NOT gate). The first input end of the NAND gate is coupled to a first clock signal; the input end of the inverter is coupled to another first clock signal, the output end of the inverter is connected to the second input end of the NAND gate; and the output end of the NAND gate outputs the first pulse signal P1. The first clock signal coupled to the first input end of the NAND gate and the first clock signal coupled to the input end of the inverter are different and have a phase difference ph therebetween. The logic circuits in the same dashed box belong to the same logic circuit group, and the first logic circuit and the second logic circuit in the same logic circuit group are coupled to the first clock signals having the same phase difference therebetween. For example, Figure 10 The first clock signals coupled to the logic circuits 101 in the logic circuit group G1 have a preset phase difference therebetween. For example, the first clock signals C11 and C12 are coupled to the first logic circuit 1011 of the logic circuit group G1, and the first clock signals C21 and C22 are coupled to the second logic circuit 1012 of the logic circuit group G1. The first clock signals C12 and C13 are coupled to the first logic circuit 1021 of the logic circuit group G2, and the first clock signals C22 and C23 are coupled to the second logic circuit 1022 of the logic circuit group G2. The first clock signals C13 and C14 are coupled to the first logic circuit 1031 of the logic circuit group G3, and the first clock signals C23 and C24 are coupled to the second logic circuit 1032 of the logic circuit group G3. The first clock signals C14 and C21 are coupled to the first logic circuit 1041 of the logic circuit group G4, and the first clock signals C24 and C11 are coupled to the second logic circuit 1042 of the logic circuit group G4.

[0080] The outputs of the first logic circuit and the second logic circuit in the same logic circuit group are coupled to a latch. For example, the outputs of the logic circuit group G1 include the first pulse signal P1 and the second pulse signal P2, which are coupled to the set end SB and the reset end RB of the latch L1, respectively. The outputs of the logic circuit group G2 include the first pulse signal P1 and the second pulse signal P2, which are coupled to the set end SB and the reset end RB of the latch L2, respectively. The outputs of the logic circuit group G3 include the first pulse signal P1 and the second pulse signal P2, which are coupled to the set end SB and the reset end RB of the latch L3, respectively. The outputs of the logic circuit group G4 include the first pulse signal P1 and the second pulse signal P2, which are coupled to the set end SB and the reset end RB of the latch L4, respectively. Based on the characteristics of the latch itself, the first pulse signal P1 and the second pulse signal P2 can be converted into a plurality of second clock signals Ph<0> to Ph<4> with a duty cycle of 50%.

[0081] The number of the first clock signals, the number of the logic circuit groups, and the number of the latches are only examples and do not limit the embodiments of the present disclosure. The first multi-phase clock can include more or fewer numbers of the first clock signals. The correction circuit can include more or fewer numbers of the logic circuit groups and the latches.

[0082] In addition, in some other embodiments of the present disclosure, the phase difference between the first clock signals coupled by the logic circuit group can include more preset phases, for example, Figure 11 An example structure diagram of another correction circuit provided in some embodiments of the present disclosure is shown. Compared with the correction circuit shown in Figure 10 The difference between the correction circuits shown in the figures is that the phase difference between the first clock signals coupled by the logic circuit group includes more preset phases, Figure 11 In the example shown in the figure, two preset phases are taken as an example, but the embodiments of the present disclosure are not limited thereto and can include more preset phases, for example, three.

[0083] As described in the embodiments shown in the figures, any correction device or correction circuit provided in the embodiments of the present disclosure can be used in the preprocessing circuit of the laser radar. For example, Figure 5 As described in the embodiments shown in the figures, any correction device or correction circuit provided in the embodiments of the present disclosure can be used in the preprocessing circuit of the laser radar. For example, Figure 12 An example structure diagram of another preprocessing circuit provided in some embodiments of the present disclosure is shown. Please refer to Figure 12The preprocessing circuit 1200 can include, for example, a clock source 1210 and a correction circuit 1220. The clock source 1210 can provide a first multi-phase clock signal including a first number M of first clock signals CLK1, adjacent first clock signals CLK1 in the first number M of first clock signals CLK1 being different by a preset phase, as described above. The correction circuit 1220 is configured to receive the first multi-phase clock signal and correct the first multi-phase clock signal into a second multi-phase clock signal. The second multi-phase clock signal includes a second number N of second clock signals CLK2, the second number N being half of the first number M, and a duty cycle of the second clock signals CLK2 being 50%.

[0084] In some embodiments of the present disclosure, the preprocessing circuit can further include a driving circuit 1230 configured to receive the second multi-phase clock signal and provide the second multi-phase clock signal to a sampling circuit of the lidar. The sampling circuit of the lidar can include one or more, for example, sampling circuits S0-Sz, where z represents the number of sampling circuits, which can be, for example, the first sampling circuit 211 as shown. Figure 5 The rising and falling edges of the second multi-phase clock signal can be used to trigger sampling of the sampling circuit, the rising and falling edges of the second multi-phase clock signal including the rising and falling edges of the second number N of second clock signals CLK2.

[0085] The driving circuit 1230 can be configured in a one-to-many manner, for example, the lidar includes sampling circuits S0-Sz, and one driving circuit 1230 can provide the second multi-phase clock signal to multiple sampling circuits S0-Sz. Relative to the circuit structure shown in Figure 2 The number of connections between the driving circuit 1230 and the sampling circuits S0-Sz can be halved, thereby reducing the wiring demand, reducing the wiring complexity, and reducing the clock sampling power consumption, thereby reducing the manufacturing and use costs of the lidar.

[0086] Some embodiments of the present disclosure also provide a lidar, for example, referring to Figure 1 The lidar can include a laser and a detector. The laser can emit laser light; the detector can receive a return wave of the laser light and convert the return wave into an electrical signal; and any one of the preprocessing circuits provided in the above embodiments can be connected to the detector.

[0087] Some embodiments of the present disclosure also provide a vehicle including a main body and a lidar, which can be mounted on the main body, for example, mounted on a vehicle body, for example, mounted on a base of a manufacturing terminal, etc.

[0088] In the present disclosure, “connection” includes direct connection or indirect connection between objects: the connection between objects can be directly connected through a medium (for example, a wire, a trace, etc.), or can be indirectly connected through other elements, or can be internal communication. “Coupling” includes signal connection between objects, which can be directly connected through a medium (for example, a wire, a trace, etc.), or can be connected through other elements, etc.

[0089] In the present disclosure, unless otherwise explicitly specified and limited, ordinal words such as “first”, “second”, etc. are only used to distinguish the description of the associated objects, and cannot be understood as indicating or implying the relative importance or order between the associated objects. In addition, the ordinal words also do not represent the number of associated objects. For example, “the first laser radar” can include one laser radar, or multiple laser radars.

[0090] “Multiple” includes two or more, and other quantifiers are similar.

[0091] The term “or”, “and / or” in the present disclosure is used to describe the relationship between the associated objects, which means non-exclusive inclusion. For example, “A and / or B” and “A or B” can include: “A alone”, “B alone”, or “A and B”, where “A” and “B” can include a single object or multiple objects. For example, “A, B and / or C”, “A, B or C” and “A, B and C” can include: “A alone”, “B alone”, “C alone”, “A and B”, “A and C”, “B and C”, or “A, B and C”, where “A”, “B” and “C” can include a single object or multiple objects. In addition, “ / ” in the present disclosure is used to represent the relationship between the associated objects before and after “or”. In the present disclosure, “at least one of A or B” and “one or more of A and B” have the same meaning as “A or B” above, “one or more of A, B and C” and “at least one of A, B or C” have the same meaning as “A, B or C” above. “One or more of A, B and C” has the same meaning as “A, B or C” above.

[0092] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments. In addition, the above embodiments can be freely combined according to needs.

Claims

1. A preprocessing circuit, characterized in that, For use with lidar, the preprocessing circuit includes: A clock source is configured to provide a first multi-phase clock signal, the first multi-phase clock signal including a first number of first clock signals, wherein adjacent first clock signals in the first number of first clock signals differ by a preset phase. The correction circuit is configured to receive the first multi-phase clock signal and correct the first multi-phase clock signal to a second multi-phase clock signal, wherein the second multi-phase clock signal includes a second number of second clock signals, the second number being half of the first number, and the duty cycle of the second clock signal is 50%.

2. The preprocessing circuit according to claim 1, characterized in that, The rising and falling edges of the second clock signal differ by the second number of preset phases.

3. The preprocessing circuit according to claim 1 or 2, characterized in that, The correction circuit includes: The detection circuit is configured to receive the first multi-phase clock signal and output a first number of pulse signals based on the rising edges of the first number of first clock signals. A conversion circuit is configured to receive the first number of pulse signals and convert the first number of pulse signals into the second number of second clock signals; wherein the first number of pulse signals includes a first pulse signal and a second pulse signal; The first pulse signal is used to convert the rising edge of the second clock signal, and the second pulse signal is used to convert the falling edge of the second clock signal; or, the first pulse signal is used to convert the falling edge of the second clock signal, and the second pulse signal is used to convert the rising edge of the second clock signal.

4. The preprocessing circuit according to claim 3, characterized in that, The first pulse signal is generated based on the rising edge of the first group of first clock signals, and the second pulse signal is generated based on the rising edge of the second group of first clock signals. The first clock signals in the first group of first clock signals have a first phase difference, and the first clock signals in the second group of first clock signals have a second phase difference. The first phase difference and the second phase difference are equal.

5. The preprocessing circuit according to claim 4, characterized in that, The first phase difference includes a third number of preset phases, which ensure that the first pulse signal and the second pulse signal do not overlap.

6. The preprocessing circuit according to claim 5, characterized in that, The third quantity is less than or equal to 1 / 4 of the first quantity.

7. The preprocessing circuit according to any one of claims 4-6, characterized in that, The detection circuit includes the second number of logic circuit groups, and the logic circuit group includes a first logic circuit and a second logic circuit. The first logic circuit is coupled to the first signal and the second signal in the first group of first clock signals, converts the overlapping area of ​​the first value of the first signal and the second value of the second signal into the pulse duration of the first pulse signal, and outputs the first pulse signal; The second logic circuit is coupled to the third and fourth signals in the second group of first clock signals, converts the overlapping area of ​​the first value of the third signal and the second value of the fourth signal into the pulse duration of the second pulse signal, and outputs the second pulse signal; The conversion circuit includes the second number of holding circuits, each holding circuit being coupled to the first pulse signal and the second pulse signal of a logic circuit group, holding the state of the second clock signal triggered by the first pulse signal until the second pulse signal arrives, or holding the state of the second clock signal triggered by the second pulse signal until the first pulse signal arrives.

8. The preprocessing circuit according to any one of claims 1-7, characterized in that, Also includes: The driving circuit is configured to receive the second multi-phase clock signal and provide the second multi-phase clock signal to the sampling circuit of the lidar, wherein the rising edge and falling edge of the second multi-phase clock signal are used to trigger the sampling of the sampling circuit.

9. A calibration device, characterized in that, include: The interface is configured to receive a first multi-phase clock signal, the first multi-phase clock signal including a first number of first clock signals, wherein adjacent first clock signals in the first number of first clock signals differ by a preset phase. A correction circuit is configured to correct the first multi-phase clock signal to a second multi-phase clock signal, wherein the second multi-phase clock signal includes a second number of second clock signals, the second number being half of the first number, and the duty cycle of the second clock signal is 50%.

10. The calibration device according to claim 9, characterized in that, The rising and falling edges of the second clock signal differ by the second number of preset phases.

11. The calibration device according to claim 9 or 10, characterized in that, The correction circuit includes: The detection circuit is configured to receive the first multi-phase clock signal and output a first number of pulse signals based on the rising edges of the first number of first clock signals. A conversion circuit is configured to receive the first number of pulse signals and convert the first number of pulse signals into the second number of second clock signals; wherein the first number of pulse signals includes a first pulse signal and a second pulse signal; The first pulse signal is used to convert the rising edge of the second clock signal, and the second pulse signal is used to convert the falling edge of the second clock signal; or, the first pulse signal is used to convert the falling edge of the second clock signal, and the second pulse signal is used to convert the rising edge of the second clock signal.

12. The calibration device according to claim 11, characterized in that, The first pulse signal is generated based on the rising edge of the first group of first clock signals, and the second pulse signal is generated based on the rising edge of the second group of first clock signals. The first clock signals in the first group of first clock signals have a first phase difference, and the first clock signals in the second group of first clock signals have a second phase difference. The first phase difference and the second phase difference are equal.

13. The calibration device according to claim 12, characterized in that, The first phase difference includes a third number of preset phases, which ensure that the first pulse signal and the second pulse signal do not overlap.

14. The calibration device according to claim 13, characterized in that, The third quantity is less than or equal to 1 / 4 of the first quantity.

15. The calibration device according to any one of claims 12-14, characterized in that, The detection circuit includes the second number of logic circuit groups, and the logic circuit group includes a first logic circuit and a second logic circuit. The first logic circuit is coupled to the first signal and the second signal in the first group of first clock signals, converts the overlapping area of ​​the first value of the first signal and the second value of the second signal into the pulse duration of the first pulse signal, and outputs the first pulse signal; The second logic circuit is coupled to the third and fourth signals in the second group of first clock signals, converts the overlapping area of ​​the first value of the third signal and the second value of the fourth signal into the pulse duration of the second pulse signal, and outputs the second pulse signal; The conversion circuit includes the second number of holding circuits, each holding circuit being coupled to the first pulse signal and the second pulse signal of a logic circuit group, holding the state of the second clock signal triggered by the first pulse signal until the second pulse signal arrives, or holding the state of the second clock signal triggered by the second pulse signal until the first pulse signal arrives.

16. A lidar, characterized in that, include: A laser, configured to emit laser light; The detector is configured to receive the echo of the laser and convert the echo into an electrical signal; The preprocessing circuit as described in any one of claims 1-8 is connected to the detector.

17. A vehicle, characterized in that, include: main body; The lidar as described in claim 16 is mounted on the main body.

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