Double-feed-forward fast-pass LDO transient response improving circuit
By constructing an LDO circuit with a dual feedforward fast-pass structure, the states of NMOS and PMOS transistors are dynamically adjusted, solving the problems of slow response speed and overshoot in traditional LDO circuits. This achieves bilateral improvement of the output voltage, reduces power consumption, and simplifies circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-27
- Publication Date
- 2026-03-27
AI Technical Summary
Traditional LDO circuits have a slow response speed when the output load changes and are prone to overshoot. Furthermore, existing feedforward circuits may exacerbate overshoot or fail to improve undershoot when the load current changes, posing a risk of circuit failure.
A dual-feedforward fast-pass structure is adopted. By constructing two feedforward paths, the operating states of NMOS and PMOS transistors are dynamically adjusted, and different feedforward paths are selected to improve the transient response capability of LDO. This includes a folded common-source cascode operational amplifier structure and a feedforward capacitor. The isolation transistor is used to selectively switch the operating region under different overshoot directions.
This achieves double-sided overshoot improvement of LDO output voltage, avoids the deterioration of single-sided overshoot, reduces power consumption, simplifies circuit complexity, and saves chip cost.
Smart Images
Figure CN121742579A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a circuit for improving the transient response of an LDO using a dual feedforward fast pass. Background Technology
[0002] Low-dropout linear regulators (LDOs), along with other types of regulators such as switching regulators, driven regulators, and charge pumps, serve as stable voltage sources within the chip, and their research and development have received widespread attention. Traditional LDOs require large external capacitors to achieve their output voltage regulation effect. In recent years, due to the further reduction in chip size and power consumption, the demand for capacitorless LDO circuit designs that can meet this trend has increased dramatically. Due to the design constraints of low power consumption, the quiescent current of the LDO branch is very small, resulting in a significant decrease in the overall loop response speed. This leads to a particularly slow loop response when the output load changes, causing a large overshoot at the output. To optimize this issue, researchers and industry practitioners have developed numerous circuits and methods to improve LDO overshoot.
[0003] like Figure 1 The diagram shows a traditional Miller-compensated LDO circuit structure built with an equivalent Miller capacitance C11. It includes an error amplifier composed of transistors P12-P13 and N11-N13, a power transistor P11, and a feedback resistor RFB. The gate terminal of power transistor P11 is connected to the output of the error amplifier. Transistor N12 serves as the feedback terminal connected to the feedback voltage VFB, and transistor N11 serves as the reference terminal connected to the reference voltage VBG. While traditional Miller compensation compensates for the phase margin of the loop system, it also has some ability to suppress transient overshoot in the LDO. However, due to the excessively large equivalent Miller capacitance and the high impedance at the output of the error amplifier, a low-frequency path is formed, severely affecting the signal transmission speed. This results in a slow overshoot recovery speed and a relatively large output overshoot, with little improvement in transient response capability.
[0004] To achieve low-cost, low-power design requirements and in application scenarios where LDO overshoot is a concern, circuit designers often employ a feedforward-based approach to improve LDO output overshoot. This method is characterized by its simplicity, extremely low cost, and significant improvement effect. The specific structure of a mainstream feedforward circuit is as follows: Figure 2As shown: A simple error amplifier is constructed using five operational amplifiers (P21, P23, N21, N22, and N23). The gate terminal of power transistor P21 is connected to the output of the error amplifier. Transistor N22 serves as the feedback terminal connected to the feedback voltage VFB, and transistor N21 serves as the reference terminal connected to the reference voltage VBG. Power transistor P21 and feedback resistor RFB constitute the power stage. Feedforward capacitor C21, transistor N21, and transistor P21 form the feedforward path. At this point, the circuit has two feedback loops: the first loop, formed by feedback resistor RFB through the error amplifier and power transistor P21, and the second loop, formed by feedforward capacitor C21 and power transistor P21. When the LDO output load changes, the second feedforward fast-pass loop can quickly respond to the change and rapidly adjust the gate voltage of the power transistor, thereby enhancing the transient response. Although constructing a feedforward path using the feedforward capacitor C21 can effectively improve output overshoot when the output voltage undershoots, i.e. when the output load current increases instantaneously, the output voltage surges instantaneously when the output load current decreases instantaneously, charging the feedforward capacitor C21. This causes the source voltages of transistors N21 and N22 to rise instantaneously, and the gate-source voltage VGS of transistor N21 to decrease instantaneously, posing a risk of turn-off. In this case, not only will the output overshoot of the LDO not be improved, but the magnitude of the overshoot will also be aggravated, and there is a risk of short-term circuit failure.
[0005] Therefore, in view of the shortcomings of the traditional Miller compensation circuit and the mainstream feedforward circuit, this invention proposes an external capacitor-free LDO circuit that improves the transient response of the output voltage by constructing a dual feedforward path to solve the above problems. Summary of the Invention
[0006] The purpose of this invention is to provide a circuit for improving the transient response of an LDO using a dual feedforward fast pass. The main objective of this invention is to improve the structure of a five-transistor operational amplifier so that the feedforward fast pass loop does not improve the LDO output undershoot but worsen the overshoot. Furthermore, based on the above method which only has one feedforward fast pass loop that can improve the LDO output undershoot, an additional feedforward loop that improves the LDO output overshoot is added to achieve bilateral overshoot improvement.
[0007] To address the aforementioned technical problems, this invention provides a circuit for improving the transient response of an LDO using a dual feedforward fast pass, comprising: The error amplification stage adopts a folded common-source cascode operational amplifier structure. The power stage includes a PMOS transistor P1 and a feedback resistor Rf; the first input terminal of the error amplifier stage is connected to the reference voltage VBG, the second input terminal is connected to the feedback terminal of the power stage, and the output terminal is connected to the control terminal of the power stage. The feedforward stage includes feedforward capacitors C1 to C2; wherein feedforward capacitor C1, together with NMOS transistor N8 and PMOS transistor P1 in the error amplification stage, forms the first feedforward path; and feedforward capacitor C2, together with PMOS transistor P3 and PMOS transistor P1 in the error amplification stage, forms the second feedforward path. When the LDO experiences overshoot or undershoot, the operating states of the NMOS transistor N8 and the PMOS transistor P3 are dynamically adjusted to switch between the dual feedforward paths, thereby regulating the gate voltage of the PMOS transistor P1 to improve the transient response capability of the LDO.
[0008] Preferably, the folded common-source common-gate operational amplifier structure includes: PMOS transistors P2~P5 and NMOS transistors N1~N8; wherein the source terminals of PMOS transistors P4~P5 are connected to a power supply, and their gate terminals are connected to a bias voltage VB1; the drain terminal of PMOS transistor P4 is connected to the source terminal of PMOS transistor P2 and the drain terminal of NMOS transistor N3, the drain terminal of PMOS transistor P5 is connected to the source terminal of PMOS transistor P3 and the drain terminal of NMOS transistor N4, and the gate terminals of PMOS transistors P2~P3 are connected to a bias voltage VB2; the drain terminal of PMOS transistor P2 is connected to the drain terminal of NMOS transistor N7 and the gate terminals of NMOS transistors N5~N6, the source terminal of NMOS transistor N7 is connected to the drain terminal of NMOS transistor N5, and the gate terminals of NMOS transistors N7~N8 are connected to a bias voltage. VB3; The drain of PMOS transistor P3 is connected to the drain of NMOS transistor N8 and serves as the output terminal of the folded common-source common-gate operational amplifier structure; The source of NMOS transistor N8 is connected to the drain of NMOS transistor N6, and the sources of NMOS transistors N5~N6 are grounded; The gate of NMOS transistor N3 serves as the second input terminal and is connected to the feedback voltage VFB, and the gate of NMOS transistor N4 serves as the first input terminal and is connected to the reference voltage VBG; The sources of NMOS transistors N3~N4 are connected to the drain of NMOS transistor N2, the gate of NMOS transistor N2 is connected to the bias voltage VB3, the source of NMOS transistor N2 is connected to the drain of NMOS transistor N1, the gate of NMOS transistor N1 is connected to the bias voltage VB4, and the source of NMOS transistor N1 is grounded.
[0009] Preferably, the PMOS transistors P2~P3 and NMOS transistors N7~N8 serve as isolation transistors and are in the subthreshold operating region; the PMOS transistors P3 and NMOS transistors N8 in the subthreshold operating region can selectively switch from the subthreshold operating region to the saturation region or the cutoff region when the LDO has different overshoot directions.
[0010] Preferably, the power stage includes: a PMOS transistor P1 and a feedback resistor Rf; wherein the source terminal of the PMOS transistor P1 is connected to a power supply, the gate terminal is connected to the output terminal of the error amplification stage, and the drain terminal is connected to one end of the feedback resistor Rf and serves as the output terminal LDO_OUT of the power stage; the other end of the feedback resistor Rf is grounded, and a feedback voltage VFB is formed at the node of the feedback resistor Rf as the feedback terminal.
[0011] Preferably, the PMOS transistor P1 serves as the power drive transistor, and the feedforward capacitors C1-C2 serve as compensation capacitors. When the LDO experiences undershoot, the first feedforward path is opened and the second feedforward path is closed by turning off the PMOS transistor P3 and turning on the NMOS transistor N8, thereby rapidly adjusting the LDO's output voltage. When the LDO experiences overshoot, the second feedforward path is opened and the first feedforward path is closed by turning on the PMOS transistor P3 and turning off the NMOS transistor N8, thereby rapidly adjusting the LDO's output voltage.
[0012] Preferably, the feedforward stage includes: feedforward capacitors C1~C2; wherein one end of the feedforward capacitors C1~C2 is connected to the drain terminal of PMOS transistor P1, and the other end of the feedforward capacitors C1~C2 is connected to the source terminal of NMOS transistor N8 and the source terminal of PMOS transistor P3, respectively.
[0013] Preferably, it also includes a subthreshold bias circuit, comprising: The self-biasing module is used to provide the bias voltage V_bias for the VB3~VB4 bias generation module; The VB1~VB2 bias generation module is used to generate bias voltages VB1~VB2; The VB3~VB4 bias generation module is used to generate bias voltages VB3~VB4.
[0014] Preferably, the VB1~VB2 bias generation module includes: PMOS transistors PM1~PM3 and NMOS transistors NM1~NM4; wherein the source terminals of PMOS transistors PM1 and PM3 are connected to a power supply, the gate terminal of PMOS transistor PM1 is connected to the drain terminals of PMOS transistor PM2 and NMOS transistor NM1 to generate a bias voltage VB1; the drain terminal of PMOS transistor PM1 is connected to the source terminal of PMOS transistor PM2, the gate terminal of PMOS transistor PM2 is connected to the gate-drain terminals of PMOS transistor PM3 and the drain terminal of NMOS transistor NM3 to generate a bias voltage VB2; the gate terminals of NMOS transistors NM1 and NMOS transistor NM3 are connected to a bias voltage VB3; the source terminal of NMOS transistor NM1 is connected to the drain terminal of NMOS transistor NM2, the source terminal of NMOS transistor NM3 is connected to the drain terminal of NMOS transistor NM4; the gate terminals of NMOS transistors NM2 and NMOS transistor NM4 are connected to a bias voltage VB4, and the source terminals of NMOS transistors NM2 and NMOS transistor NM4 are grounded.
[0015] Preferably, the VB3~VB4 bias generation module includes: PMOS transistors PM4~PM5 and NMOS transistors NM5~NM8; wherein the source terminals of PMOS transistors PM4~PM5 are connected to a power supply, and the gate terminals of PMOS transistors PM4~PM5 are connected to the bias voltage V_bias; the drain terminal of PMOS transistor PM4 is connected to the drain terminal of NMOS transistor NM5 and the gate terminal of NMOS transistor NM6 to generate bias voltage VB4; the gate terminal of NMOS transistor NM5 is connected to bias voltage VB3, the source terminal of NMOS transistor NM5 is connected to the drain terminal of NMOS transistor NM6, and the source terminal of NMOS transistor NM6 is grounded; the drain terminal of PMOS transistor PM5 is connected to the gate-drain terminal of NMOS transistor NM7 and the gate terminal of NMOS transistor NM8 to generate bias voltage VB3; the source terminal of NMOS transistor NM7 is connected to the drain terminal of NMOS transistor NM8, and the source terminal of NMOS transistor NM8 is grounded.
[0016] The present invention also provides an LDO chip, including a circuit as described above for improving the transient response of the LDO using a dual feedforward fast pass.
[0017] Compared with the prior art, the present invention has the following beneficial effects: This invention achieves rapid adjustment of the power transistor gate voltage by constructing two feedforward fast-pass loops, thereby improving the output voltage overshoot of the LDO; at the same time, the isolation transistor can select a specific feedforward path in different overshoot directions, thereby avoiding the risk of mutual exclusion of paths and deterioration of unilateral overshoot. Specifically, by using appropriate bias isolation transistors N8 and P3, when the LDO experiences undershoot, transistor P3 is turned off and transistor N8 is turned on, opening the first feedforward path composed of C1, N8, and P1 to quickly adjust the LDO's output voltage and closing the feedforward path composed of C2, P3, and P1. Conversely, when the LDO experiences overshoot, transistor N8 is turned off, opening the second feedforward path composed of C2, P3, and P1 and closing the feedforward path composed of C1, N8, and P1. This method allows for effective selection of the feedforward circuit. When the output overshoot direction is different, isolation transistors P3 and N8, which are in the subthreshold operating region, can selectively switch from the subthreshold region to the saturation region or the cutoff region when the LDO experiences different overshoot directions. This achieves automatic isolation of detrimental feedforward paths and selection of favorable feedforward paths, thereby improving the transient response capability of the LDO. Attached Figure Description
[0018] Figure 1 This is the main structural diagram of a traditional Miller-compensated LDO circuit.
[0019] Figure 2 This is the main structural diagram of a traditional mainstream feedforward fast-pass LDO circuit.
[0020] Figure 3 This is a circuit diagram provided by the present invention for improving the transient response of an LDO using a dual feedforward fast pass.
[0021] Figure 4 This is a diagram of the subthreshold bias circuit provided by the present invention. Detailed Implementation
[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0023] like Figure 3 As shown, this embodiment of the invention provides a circuit for improving the transient response of an LDO using a dual feedforward fast pass, comprising: The error amplification stage adopts a folded common-source cascode operational amplifier structure. The power stage includes a PMOS transistor P1 and a feedback resistor Rf; the first input terminal of the error amplifier stage is connected to the reference voltage VBG, the second input terminal is connected to the feedback terminal of the power stage, and the output terminal is connected to the control terminal of the power stage. The feedforward stage includes feedforward capacitors C1 to C2; wherein feedforward capacitor C1, together with NMOS transistor N8 and PMOS transistor P1 in the error amplification stage, forms the first feedforward path; and feedforward capacitor C2, together with PMOS transistor P3 and PMOS transistor P1 in the error amplification stage, forms the second feedforward path. When the LDO experiences overshoot or undershoot, the operating states of the NMOS transistor N8 and the PMOS transistor P3 are dynamically adjusted to switch between the dual feedforward paths, thereby regulating the gate voltage of the PMOS transistor P1 to improve the transient response capability of the LDO.
[0024] Continue reading Figure 3 As shown, the folded common-source common-gate operational amplifier structure includes: PMOS transistors P2~P5 and NMOS transistors N1~N8; wherein the source terminals of PMOS transistors P4~P5 are connected to the power supply, and the gate terminals are connected to the bias voltage VB1; the drain terminal of PMOS transistor P4 is connected to the source terminal of PMOS transistor P2 and the drain terminal of NMOS transistor N3, the drain terminal of PMOS transistor P5 is connected to the source terminal of PMOS transistor P3 and the drain terminal of NMOS transistor N4, and the gate terminals of PMOS transistors P2~P3 are connected to the bias voltage VB2; the drain terminal of PMOS transistor P2 is connected to the drain terminal of NMOS transistor N7 and the gate terminals of NMOS transistors N5~N6, the source terminal of NMOS transistor N7 is connected to the drain terminal of NMOS transistor N5, and the gate terminals of NMOS transistors N7~N8 are connected to the bias voltage VB1. VB3; The drain of PMOS transistor P3 is connected to the drain of NMOS transistor N8 and serves as the output terminal of the folded common-source common-gate operational amplifier structure; The source of NMOS transistor N8 is connected to the drain of NMOS transistor N6, and the sources of NMOS transistors N5~N6 are grounded; The gate of NMOS transistor N3 serves as the second input terminal and is connected to the feedback voltage VFB, and the gate of NMOS transistor N4 serves as the first input terminal and is connected to the reference voltage VBG; The sources of NMOS transistors N3~N4 are connected to the drain of NMOS transistor N2, the gate of NMOS transistor N2 is connected to the bias voltage VB3, the source of NMOS transistor N2 is connected to the drain of NMOS transistor N1, the gate of NMOS transistor N1 is connected to the bias voltage VB4, and the source of NMOS transistor N1 is grounded.
[0025] Continue reading Figure 3 As shown, the power stage includes a PMOS transistor P1 and a feedback resistor Rf; wherein the source terminal of the PMOS transistor P1 is connected to the power supply, the gate terminal is connected to the output terminal of the error amplifier stage, and the drain terminal is connected to one end of the feedback resistor Rf and serves as the output terminal LDO_OUT of the power stage; the other end of the feedback resistor Rf is grounded, and a feedback voltage VFB is formed at the node of the feedback resistor Rf as the feedback terminal.
[0026] Continue reading Figure 3As shown, the feedforward stage includes: feedforward capacitors C1~C2; wherein one end of the feedforward capacitors C1~C2 is connected to the drain terminal of PMOS transistor P1, and the other end of the feedforward capacitors C1~C2 is connected to the source terminal of NMOS transistor N8 and the source terminal of PMOS transistor P3, respectively.
[0027] like Figure 4 As shown, it also includes a subthreshold bias circuit, comprising: The self-biasing module is used to provide the bias voltage V_bias for the VB3~VB4 bias generation module; The VB1~VB2 bias generation module is used to generate bias voltages VB1~VB2; The VB3~VB4 bias generation module is used to generate bias voltages VB3~VB4.
[0028] Continue reading Figure 4 As shown, the VB1~VB2 bias generation module includes: PMOS transistors PM1~PM3 and NMOS transistors NM1~NM4; wherein the source terminals of PMOS transistors PM1 and PM3 are connected to a power supply, the gate terminal of PMOS transistor PM1 is connected to the drain terminals of PMOS transistor PM2 and NMOS transistor NM1 to generate a bias voltage VB1; the drain terminal of PMOS transistor PM1 is connected to the source terminal of PMOS transistor PM2, the gate terminal of PMOS transistor PM2 is connected to the gate-drain terminals of PMOS transistor PM3 and the drain terminal of NMOS transistor NM3 to generate a bias voltage VB2; the gate terminals of NMOS transistors NM1 and NMOS transistor NM3 are connected to a bias voltage VB3; the source terminal of NMOS transistor NM1 is connected to the drain terminal of NMOS transistor NM2, the source terminal of NMOS transistor NM3 is connected to the drain terminal of NMOS transistor NM4; the gate terminals of NMOS transistors NM2 and NMOS transistor NM4 are connected to a bias voltage VB4, and the source terminals of NMOS transistors NM2 and NMOS transistor NM4 are grounded.
[0029] Continue reading Figure 4 As shown, the VB3~VB4 bias generation module includes: PMOS transistors PM4~PM5 and NMOS transistors NM5~NM8; wherein the source terminals of PMOS transistors PM4~PM5 are connected to the power supply, and the gate terminals of PMOS transistors PM4~PM5 are connected to the bias voltage V_bias; the drain terminal of PMOS transistor PM4 is connected to the drain terminal of NMOS transistor NM5 and the gate terminal of NMOS transistor NM6 to generate bias voltage VB4; the gate terminal of NMOS transistor NM5 is connected to bias voltage VB3, the source terminal of NMOS transistor NM5 is connected to the drain terminal of NMOS transistor NM6, and the source terminal of NMOS transistor NM6 is grounded; the drain terminal of PMOS transistor PM5 is connected to the gate-drain terminal of NMOS transistor NM7 and the gate terminal of NMOS transistor NM8 to generate bias voltage VB3; the source terminal of NMOS transistor NM7 is connected to the drain terminal of NMOS transistor NM8, and the source terminal of NMOS transistor NM8 is grounded.
[0030] Continue reading Figure 3 As shown, a folded cascode error amplifier structure is improved based on the traditional five-transistor error amplifier. N1 and N2 are provided with tail currents by fixed biases of VB4 and VB3, P4 and P5 are fixed biased by VB1, the gate terminals of isolation transistors N7 and N8 are provided by bias voltage VB3, and the gate terminals of isolation transistors P2 and P3 are provided by bias voltage VB2. By appropriately modulating VB3 and VB2, N7, N8, P2, and P3 are all biased in the subthreshold region. One end of the feedforward capacitor C1 is connected to the drain of power transistor P1, and the other end is connected to the source of isolation transistor N8. C1, N8, and power transistor P1 form the first feedforward path; one end of the feedforward capacitor C2 is connected to the drain of power transistor P1, and the other end is connected to the source of transistor P3; C2, P3, and power transistor P1 form the second feedforward path.
[0031] The principle of this invention is as follows: When the LDO circuit is in static operation, a folded common-source common-gate operational amplifier serves as the error amplifier, power transistor P1 and feedback resistor Rf serve as the power stage, and capacitors C1 and C2 are compensation capacitors to ensure the loop stability of the system. When a sudden increase in current occurs at the LDO output terminal, the LDO output voltage dips instantaneously. At this time, the output voltage change is coupled to the drain of transistor N6 and the source of transistor N8 through the feedforward capacitor C1, causing the voltage value at the original static operating point to drop instantaneously. At this time, transistor N8 will briefly operate in the saturation region due to the instantaneous increase in its gate-source voltage VGS. Since C1, N8 and the power transistor form a feedforward loop, the LDO output voltage change is quickly coupled to the gate of power transistor P1 through capacitor C1 and switching transistor N8, manifesting as a rapid voltage decrease. Meanwhile, the drain of transistor P1 has the opposite polarity, so its voltage rises rapidly. This quickly adjusts the LDO output voltage and improves its output undershoot. At this time, the voltage coupled from C2 to the source of P3 transistor is decreasing, causing |VGS| of P3 transistor to decrease. P3 transistor will briefly enter the cutoff region from the subthreshold region. That is, when the output voltage undershoots, the circuit only uses the fast-pass loop formed by C1, N8, and P1 for rapid adjustment. Similarly, when the load at the LDO output terminal experiences a momentary decrease in current, the LDO output voltage momentarily overshoots. At this time, the output voltage change is coupled to the drain of P5 transistor and the source of P3 transistor through the feedforward capacitor C2, causing the original quiescent operating point voltage value to increase momentarily. This forms a fast-pass loop of C2, P3, and P1. The momentarily increased voltage coupled to the gate of the power transistor through capacitor C2 is reflected as a momentary decrease at the drain of the power transistor P1, thereby compensating for the momentary overshoot of the LDO output. At this time, the voltage coupled from C1 to the source of N8 is a sudden increase, which causes the VGS of N8 to decrease. N8 will briefly enter the cutoff region from the subthreshold region, thus avoiding the single-sided overshoot deterioration caused by the pull-down input pair in the above circuit.
[0032] This invention constructs a dual-feedforward LDO circuit structure. Using appropriate bias isolation transistors N8 and P3, when the LDO experiences undershoot, transistor P3 is turned off and transistor N8 is turned on, opening the first feedforward path composed of C1, N8, and P1 to rapidly adjust the LDO's output voltage, and closing the feedforward path composed of C2, P3, and P1. Conversely, when the LDO experiences overshoot, transistor N8 is turned off, opening the second feedforward path composed of C2, P3, and P1, and closing the feedforward path composed of C1, N8, and P1. This method allows for effective selection of the feedforward circuit, choosing the most advantageous feedforward path to improve the LDO's transient response capability when the output overshoot direction is different.
[0033] In summary, the present invention has the following advantages: 1. Compared with the existing single feedforward circuit structure, the present invention improves the overshoot and undershoot of LDO output by constructing two feedforward paths, rather than improving only one side, and the improvement effect is obvious.
[0034] 2. By constructing isolation transistors N8 and P3, this invention ensures that each feedforward loop is only activated when a fast pass response is required, which can effectively avoid the adverse effects of mutual interference and exclusion between loops on the output voltage.
[0035] 3. Because the entire transient response loop regulation mechanism of the LDO is not regulated through the traditional negative feedback loop composed of feedback resistor-error amplifier-power transistor, but is directly regulated from the feedforward path, the current of each circuit branch of the LDO circuit can be significantly reduced. Therefore, the slew rate of the entire LDO loop system can be set to be extremely low, which makes it easy to design a low-power circuit system and has great advantages in low-power application scenarios.
[0036] 4. This invention does not require other complex auxiliary circuits; it only requires passive components such as capacitors, which greatly reduces circuit complexity.
[0037] 5. The LDO of this invention can enhance its transient response capability without the need for a load capacitor, which can greatly save chip or circuit costs.
[0038] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A circuit for improving the transient response of an LDO using a dual feedforward fast pass, characterized in that, include: The error amplification stage adopts a folded common-source cascode operational amplifier structure. The power stage includes a PMOS transistor P1 and a feedback resistor Rf; the first input terminal of the error amplifier stage is connected to the reference voltage VBG, the second input terminal is connected to the feedback terminal of the power stage, and the output terminal is connected to the control terminal of the power stage. The feedforward stage includes feedforward capacitors C1 to C2; wherein feedforward capacitor C1, together with NMOS transistor N8 and PMOS transistor P1 in the error amplification stage, forms the first feedforward path; and feedforward capacitor C2, together with PMOS transistor P3 and PMOS transistor P1 in the error amplification stage, forms the second feedforward path. When the LDO experiences overshoot or undershoot, the operating states of the NMOS transistor N8 and the PMOS transistor P3 are dynamically adjusted to achieve selective switching of the dual feedforward paths, thereby adjusting the gate voltage of the PMOS transistor P1 to improve the transient response capability of the LDO.
2. The circuit for improving the transient response of an LDO with dual feedforward fast pass as described in claim 1, characterized in that, The folded common-source common-gate operational amplifier structure includes: PMOS transistors P2~P5 and NMOS transistors N1~N8; wherein the source terminals of PMOS transistors P4~P5 are connected to the power supply, and the gate terminals are connected to the bias voltage VB1; the drain terminal of PMOS transistor P4 is connected to the source terminal of PMOS transistor P2 and the drain terminal of NMOS transistor N3, the drain terminal of PMOS transistor P5 is connected to the source terminal of PMOS transistor P3 and the drain terminal of NMOS transistor N4, and the gate terminals of PMOS transistors P2~P3 are connected to the bias voltage VB2; the drain terminal of PMOS transistor P2 is connected to the drain terminal of NMOS transistor N7 and the gate terminals of NMOS transistors N5~N6, the source terminal of NMOS transistor N7 is connected to the drain terminal of NMOS transistor N5, and the gate terminals of NMOS transistors N7~N8 are connected to the bias voltage VB1. 3; The drain of PMOS transistor P3 is connected to the drain of NMOS transistor N8 and serves as the output terminal of the folded common-source common-gate operational amplifier structure; the source of NMOS transistor N8 is connected to the drain of NMOS transistor N6, and the sources of NMOS transistors N5~N6 are grounded; the gate of NMOS transistor N3 serves as the second input terminal and is connected to the feedback voltage VFB, and the gate of NMOS transistor N4 serves as the first input terminal and is connected to the reference voltage VBG; the sources of NMOS transistors N3~N4 are connected to the drain of NMOS transistor N2, the gate of NMOS transistor N2 is connected to the bias voltage VB3, the source of NMOS transistor N2 is connected to the drain of NMOS transistor N1, the gate of NMOS transistor N1 is connected to the bias voltage VB4, and the source of NMOS transistor N1 is grounded.
3. The circuit for improving the transient response of an LDO with dual feedforward fast pass as described in claim 2, characterized in that, The PMOS transistors P2~P3 and NMOS transistors N7~N8 serve as isolation transistors and are in the subthreshold operating region. The PMOS transistors P3 and NMOS transistors N8, which are in the subthreshold operating region, can selectively switch from the subthreshold operating region to the saturation region or the cutoff region when the LDO has different overshoot directions.
4. The circuit for improving the transient response of an LDO with dual feedforward fast pass as described in claim 1, characterized in that, The power stage includes a PMOS transistor P1 and a feedback resistor Rf; wherein the source terminal of the PMOS transistor P1 is connected to the power supply, the gate terminal is connected to the output terminal of the error amplifier stage, and the drain terminal is connected to one end of the feedback resistor Rf and serves as the output terminal LDO_OUT of the power stage; the other end of the feedback resistor Rf is grounded, and a feedback voltage VFB is formed at the node of the feedback resistor Rf as the feedback terminal.
5. The circuit for improving the transient response of an LDO with dual feedforward fast pass as described in claim 1, characterized in that, The PMOS transistor P1 serves as the power drive transistor, and the feedforward capacitors C1-C2 serve as compensation capacitors. When the LDO experiences undershoot, the first feedforward path is opened by turning off the PMOS transistor P3 and turning on the NMOS transistor N8, while the second feedforward path is closed, thereby rapidly adjusting the LDO's output voltage. When the LDO experiences overshoot, the second feedforward path is opened by turning on the PMOS transistor P3 and turning off the NMOS transistor N8, while the first feedforward path is closed, thereby rapidly adjusting the LDO's output voltage.
6. The circuit for improving the transient response of an LDO with dual feedforward fast pass as described in claim 1, characterized in that, The feedforward stage includes: feedforward capacitors C1~C2; wherein one end of the feedforward capacitors C1~C2 is connected to the drain terminal of PMOS transistor P1, and the other end of the feedforward capacitors C1~C2 is connected to the source terminal of NMOS transistor N8 and the source terminal of PMOS transistor P3, respectively.
7. The circuit for improving the transient response of an LDO with dual feedforward fast pass as described in claim 1, characterized in that, It also includes a subthreshold bias circuit, including: The self-biasing module is used to provide the bias voltage V_bias for the VB3~VB4 bias generation module; The VB1~VB2 bias generation module is used to generate bias voltages VB1~VB2; The VB3~VB4 bias generation module is used to generate bias voltages VB3~VB4.
8. The circuit for improving the transient response of an LDO with dual feedforward fast pass as described in claim 7, characterized in that, The VB1~VB2 bias generation module includes: PMOS transistors PM1~PM3 and NMOS transistors NM1~NM4; wherein the source terminals of PMOS transistors PM1 and PM3 are connected to a power supply, the gate terminal of PMOS transistor PM1 is connected to the drain terminals of PMOS transistors PM2 and NMOS transistor NM1 to generate a bias voltage VB1; the drain terminal of PMOS transistor PM1 is connected to the source terminal of PMOS transistor PM2, the gate terminal of PMOS transistor PM2 is connected to the gate-drain terminals of PMOS transistor PM3 and the drain terminal of NMOS transistor NM3 to generate a bias voltage VB2; the gate terminals of NMOS transistors NM1 and NMOS transistor NM3 are connected to a bias voltage VB3; the source terminal of NMOS transistor NM1 is connected to the drain terminal of NMOS transistor NM2, the source terminal of NMOS transistor NM3 is connected to the drain terminal of NMOS transistor NM4; the gate terminals of NMOS transistors NM2 and NMOS transistor NM4 are connected to a bias voltage VB4, and the source terminals of NMOS transistors NM2 and NMOS transistor NM4 are grounded.
9. The circuit for improving the transient response of an LDO with dual feedforward fast pass as described in claim 7, characterized in that, The VB3~VB4 bias generation module includes: PMOS transistors PM4~PM5 and NMOS transistors NM5~NM8; wherein the source terminals of PMOS transistors PM4~PM5 are connected to a power supply, and the gate terminals of PMOS transistors PM4~PM5 are connected to the bias voltage V_bias; the drain terminal of PMOS transistor PM4 is connected to the drain terminal of NMOS transistor NM5 and the gate terminal of NMOS transistor NM6 to generate bias voltage VB4; the gate terminal of NMOS transistor NM5 is connected to bias voltage VB3, the source terminal of NMOS transistor NM5 is connected to the drain terminal of NMOS transistor NM6, and the source terminal of NMOS transistor NM6 is grounded; the drain terminal of PMOS transistor PM5 is connected to the gate-drain terminal of NMOS transistor NM7 and the gate terminal of NMOS transistor NM8 to generate bias voltage VB3; the source terminal of NMOS transistor NM7 is connected to the drain terminal of NMOS transistor NM8, and the source terminal of NMOS transistor NM8 is grounded.
10. An LDO chip, characterized in that, The circuit includes a dual feedforward fast pass circuit for improving the transient response of an LDO, as described in any one of claims 1 to 9.