Memory device performing precharging operation

Abstract

The invention relates to a memory device performing a pre-charge operation and an operating method thereof. The memory device includes: a cell block in which a plurality of sub-word lines are arranged; a control signal generation circuit that generates a landing control signal to perform a soft landing operation on the plurality of sub-word lines according to the pre-charge command; a voltage supply circuit that supplies a first supply voltage or a second supply voltage as an operating voltage according to a block selection signal for selecting one of the cell blocks and a landing control signal, the second supply voltage being smaller than the first supply voltage; and a word line driving circuit driving a sub-word line selected by the row address among the plurality of sub-word lines based on the operating voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0129785, filed on September 25, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to semiconductor design techniques, and more specifically, to memory devices including word line driving circuitry. Background Technology

[0004] As the integration level of storage devices increases, the distance between two adjacent word lines in the multiple word lines contained in the storage device decreases. As the distance between adjacent word lines decreases, the coupling effect between adjacent word lines increases.

[0005] Whenever data is input or output to a memory cell, a word line switches between an active and inactive state. Therefore, as mentioned above, the coupling effect between adjacent word lines increases, and data in memory cells connected to frequently active word lines becomes corrupted. This phenomenon is known as row hammering, and various methods to mitigate the row hammering effect are being investigated. Summary of the Invention

[0006] Embodiments of this disclosure relate to a storage device and a method of operating thereof capable of adjusting the operating voltage of a word line drive circuit after an intermediate level segment during a soft landing operation.

[0007] According to one embodiment of the present disclosure, a storage device includes: a cell block in which a plurality of sub-word lines are arranged; a control signal generation circuit configured to generate a landing control signal according to a pre-charge command to perform a soft landing operation on the plurality of sub-word lines; a voltage supply circuit configured to provide a first supply voltage or a second supply voltage as an operating voltage according to a block selection signal for selecting one of the cell blocks and the landing control signal, wherein the second supply voltage is less than the first supply voltage; and a word line driving circuit configured to drive a sub-word line selected by a row address among the plurality of sub-word lines based on the operating voltage.

[0008] According to one embodiment of the present disclosure, a storage device includes: a cell block in which a plurality of main word lines are allocated; a plurality of main word line drivers configured to drive the plurality of main word lines based on an operating voltage; and a voltage supply circuit configured to selectively provide a first supply voltage or a second supply voltage as an operating voltage to the main word line drivers driving the main word lines allocated to the cell block selected by the block selection signal, based on a landing control signal for performing a soft landing operation for pre-charging the plurality of main word lines. The second supply voltage is less than the first supply voltage.

[0009] According to an embodiment of this disclosure, an operation method for a storage device includes a cell block in which a plurality of main word lines are allocated, wherein a plurality of sub-word lines are combined to form one of the plurality of main word lines. The operation method includes: receiving a precharge command; providing a first supply voltage to the main word line allocated to the cell block including sub-word lines selected from the plurality of sub-word lines, and discharging the selected sub-word line from the first voltage level to a second voltage level for the first time; and providing a second supply voltage to the main word lines allocated to all cell blocks, and discharging the selected sub-word line from the second voltage level to a third voltage level for the second time, wherein the second supply voltage is less than the first supply voltage.

[0010] According to embodiments of this disclosure, the storage device can supply the operating voltage of the main word line driver to a voltage that is a certain level lower than the high voltage only during a preset segment of the soft landing operation, thereby reducing the leakage current of the unselected sub-word line drivers and preventing the degradation of the discharge characteristics of the selected sub-word lines. Attached Figure Description

[0011] Figure 1A and Figure 1B It is a waveform diagram used to describe a soft landing scheme.

[0012] Figure 2 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0013] Figure 3 It is used to describe Figure 2 A diagram of the storage cell area.

[0014] Figure 4 It is shown Figure 2 Detailed block diagram of the row control circuit.

[0015] Figure 5 It is shown Figure 4 Detailed circuit diagram of the voltage supply circuit.

[0016] Figure 6A and Figure 6B It is shown Figure 4 Detailed circuit diagram of the main word line driver circuit.

[0017] Figure 7A and Figure 7B It is shown Figure 4 Detailed circuit diagram of the sub-word line driving circuit.

[0018] Figure 8 It is a waveform diagram used to describe the operation of a storage device according to embodiments of the present disclosure.

[0019] Figure 9 It is a waveform diagram used to describe the effects according to embodiments of the present disclosure.

[0020] Figure 10 This is a block diagram illustrating a storage system according to an embodiment of the present disclosure. Detailed Implementation

[0021] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. The present disclosure may have different forms of embodiments and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various figures and embodiments.

[0022] It should be understood that when an element is referred to as "coupled" or "connected" to another element, it can mean that the two are directly coupled or that the two are electrically connected to each other, with another circuitry between them. It will also be understood that the terms "comprising," "including," "having," etc., as used herein specify the presence of the stated features, numbers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. In this disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0023] Figure 1A and Figure 1B This is a waveform diagram used to describe a soft landing scheme according to embodiments of the present disclosure.

[0024] See Figure 1A When an activation command ACT is applied for an access operation (such as a read operation or a write operation) of the storage device, a high voltage VPP is applied to the selected word line WL. When a precharge command PCG is applied, the selected word line WL is driven with a low voltage VBBW, which is lower than the high voltage VPP. Therefore, the voltage level of the word line WL can decrease exponentially from the high voltage (VPP) level to the low voltage (VBBW) level according to an exponential curve.

[0025] At this point, the fall time tF of the voltage level of word line WL from high voltage (VPP) to low voltage (VBBW) affects the horizontal hammer characteristics. When the voltage level changes rapidly from high voltage (VPP) to low voltage (VBBW), the horizontal hammer characteristics of adjacent word lines may deteriorate. In other words, as the fall time tF shortens, horizontal hammer characteristics deteriorate.

[0026] refer to Figure 1BA soft landing scheme (or operation) is proposed as a method to reduce the impact of line hammer during precharge operation. The soft landing scheme can reduce the line hammer effect by slowing down the precharge of word line WL during precharge operation or by maintaining or keeping word line WL at an intermediate voltage (VSL) level for a period of time and then discharging from a high voltage (VPP) level to a low voltage (VBBW) level.

[0027] In other words, for Figure 1B The soft-landing scheme described herein involves a pre-charge operation that causes the voltage level of word line WL to decrease from a high voltage (VPP) level to an intermediate voltage (VSL) level during the first segment tA, remain at the intermediate voltage (VSL) level during the second segment tB, and decrease from the intermediate voltage (VSL) level to a low voltage (VBBW) level during the third segment tC. In this operation, a larger amount in the second segment tB can improve row hammer characteristics. However, when the subsequent activation command ACT is applied, it is difficult to guarantee the amount in the third segment tC, which can lead to a failure (hereinafter referred to as "tRP logic failure") due to insufficient margin in the internal operations performed according to the pre-charge activation time tRP. Therefore, the second segment tB can be omitted or retained for a short time.

[0028] The following describes a method according to an embodiment of the present disclosure for preventing tRP logic failure and mitigating line hammering during precharge operation by reducing the operating voltage of the word line drive circuit by a certain level after the second segment tB of the soft landing operation.

[0029] Figure 2 This is a block diagram illustrating a storage device 100 according to an embodiment of the present disclosure.

[0030] refer to Figure 2 The storage device 100 may include a storage cell area 110, a row control circuit 120, a column control circuit 130, a command / address (CA) buffer 152, a command decoder 153, and an address control circuit 154.

[0031] Storage cell region 110 may include multiple storage cells MC coupled to multiple word lines WL and multiple bit lines BL, the multiple storage cells being arranged in an array. The multiple word lines WL may extend along a first direction (e.g., row direction) and may be sequentially arranged in a second direction perpendicular to the first direction (e.g., column direction). The multiple bit lines BL may extend along the column direction and may be sequentially arranged in the row direction. The multiple storage cells MC may include storage cells requiring refresh operations to ensure data retention time. Storage cell region 110 may include at least one storage bank. The number of storage banks or the number of storage cells MC may be determined based on the capacity of storage device 100. (Refer to...) Figure 3 Describes the detailed configuration of storage unit area 110.

[0032] Multiple cell blocks (or multiple cell blocks) can be arranged in the storage cell region 110. The multiple cell blocks are arranged in an array along the row and column directions. Each cell block may include multiple storage cells MC coupled between multiple word lines WL and multiple bit lines BL. In one embodiment of this disclosure, a "cell block" can be defined as a group of storage cells sharing word lines WL and bit lines BL and arranged in the same manner.

[0033] CA buffer 152 can receive command / address signals C / A from an external device (e.g., a memory controller). CA buffer 152 can sample the command / address signals C / A and output the internal command ICMD and internal address IADD.

[0034] Command decoder 153 can decode the internal command ICMD received from CA buffer 152 to generate activation command ACT, precharge command PCG, read command RD, and write command WT. Although not shown, command decoder 153 can additionally generate refresh command, mode register command, etc. by decoding the internal command ICMD.

[0035] Address control circuit 154 can classify the internal address IADD received from CA buffer 152 into a row address RADD or a column address CADD. According to an embodiment, address control circuit 154 can classify some bits of the internal address IADD into a row address RADD and the remaining bits into a column address CADD. When an activation operation is indicated as a result of decoding by command decoder 153, address control circuit 154 can classify the internal address IADD into a row address RADD, while when a read or write operation is indicated, address control circuit 154 can classify the internal address IADD into a column address CADD.

[0036] The row control circuit 120 can be coupled to the memory cell region 110 via multiple word lines WL. The row control circuit 120 can perform an activation operation to activate the word line WL selected via the row address RADD according to the activation command ACT, and can perform a pre-charge operation to pre-charge the activated word line WL according to the pre-charge command PCG. Specifically, as... Figure 1B As shown, during the pre-charge operation, the line control circuit 120 can drive the activated word line WL, causing the voltage level of the word line WL to decrease from a high voltage (VPP) level to an intermediate voltage (VSL) level during the first segment tA, remain at the intermediate voltage level VA during the second segment tB, and decrease from the intermediate voltage (VSL) level to a low voltage (VBBW) level during the third segment tC. (Refer to...) Figures 4 to 7B Describe the detailed configuration of the line control circuit 120.

[0037] Column control circuitry 130 can be coupled to memory cell region 110 via multiple bit lines BL. Column control circuitry 130 can select a predetermined number of bit lines BL corresponding to column address CADD according to read command RD or write command WT, and input and output data DQ between the selected bit lines BL and data pads. For example, column control circuitry 130 may include column selection circuitry and data input / output circuitry. Column selection circuitry can decode column address CADD to select a predetermined number of bit lines BL. Data input / output circuitry can receive data DQ to be written to memory cell region 110 during a write operation according to write command WT, and can transmit data DQ read from memory cell region 110 during a read operation according to read command RD.

[0038] Figure 3 It is used to describe Figure 2 The diagram of storage cell area 110.

[0039] See Figure 3 In the storage cell area 110, multiple cell blocks MB0 and MB1 are arranged in the column direction. A predetermined number of word lines WL can be sequentially arranged in the cell blocks MB0 and MB1 arranged in the column direction.

[0040] In the storage cell region 110, a first cell block MB0, a second cell block MB1, and a first sensing amplifier circuit 112 and a second sensing amplifier circuit 114 disposed therebetween can be provided. Subsequently, a third cell block having the same structure as the first cell block MB0 can be provided below the second cell block MB1.

[0041] The first sensing amplifier circuit 112, located between the first unit block MB0 and the second unit block MB1, may include multiple bit line sensing amplifiers (BLSAs). Each BLSA is shared by bit lines located on the first unit block MB0 and bit lines located on the second unit block MB1 to sense and amplify data transmitted through the corresponding bit lines. For example, when the word line WL of the first unit block MB0 is selected (or activated), data is transmitted to bit line "A" located on the first unit block MB0 and connected to the first sensing amplifier circuit 112. That is, bit line "A" becomes the driving bit line, while bit line "B" located on the second unit block MB and connected to the first sensing amplifier circuit 112 becomes the reference bit line. Thereafter, the first sensing amplifier circuit 112 performs an amplification operation by sensing the data transmitted through bit line "A" and the voltage level of bit line "B". This sensing amplification operation is performed in the same manner even when bit line "A" is used as the reference bit line.

[0042] To mitigate the voltage propagation delay to word lines that occurs as the number of memory cells connected to a word line increases and the distance between word lines decreases, a main word line can be divided into multiple (e.g., eight) sub-word lines, and each sub-word line can be driven using a sub-word line driver. Figure 3 In this architecture, each word line WL in a unit block can correspond to a sub-word line, and eight sub-word lines WL can be combined to form a main word line MWL. In the following embodiments, word lines WL will be referred to as sub-word lines WL. Figure 3 The illustration shows a case where one main word line (MWL) is allocated to each cell block, but the embodiment is not limited to this; multiple main word lines can be allocated to each cell block. The row control circuit 120 may include sub-word line driving circuitry for driving sub-word lines (WL) and main word line driving circuitry for driving the main word lines.

[0043] In one embodiment, for ease of explanation, the storage cell region 110 includes 16 cell blocks, each cell block having 16 main word lines, and each main word line having 8 sub-word lines. Therefore, each cell block can have 128 sub-word lines, and the storage cell region 110 can have 256 main word lines and 2048 sub-word lines.

[0044] Figure 4 It is shown Figure 2 Detailed block diagram of the row control circuit 120.

[0045] See Figure 4 The line control circuit 120 may include a line decoder 210, a control signal generation circuit 220, a voltage supply circuit 230, and a word line drive circuit 240.

[0046] The row decoder 210 can decode the row address RADD to generate the first address information BAX_M#, the second address information BAX_S#, and the block selection signal MAT_SEL<0:15>, where # represents multiple signals.

[0047] The row decoder 210 can generate the first address information BAX_M# by decoding certain bits (e.g., the high bits) of the row address RADD. For example, when the row address RADD includes 15 bits, the first address information BAX_M# may include the 8-bit signal BAX345<0:7> generated by decoding the 4th, 5th, and 6th bits of the row address RADD<0:14>, RADD<3:5>, the 8-bit signal BAX678<0:7> generated by decoding the 7th, 8th, and 9th bits of the row address RADD<0:14>, RADD<6:8>, and the 4-bit signal BAX9A<0:3> generated by decoding the 10th and 11th bits of the row address RADD<0:14>, RADD<9:10>. In this scenario, only one bit in signal BAX345<0:7> can be set to a high-order bit based on the logical values ​​of bits 4, 5, and 6 (RADD<3:5>), only one bit in signal BAX678<0:7> can be set to a high-order bit based on the logical values ​​of bits 7, 8, and 9 (RADD<6:8>), and only one bit in signal BAX9A<0:3> can be set to a high-order bit based on the logical values ​​of bits 10 and 11 (RADD<9:10>). Therefore, one of the 256 main word lines can be specified based on the 8-bit signal BAX345<0:7>, the 8-bit signal BAX678<0:7>, and the 4-bit signal BAX9A<0:3> contained in the first address information BAX_M#.

[0048] The row decoder 210 can generate the second address information BAX_S# by decoding certain bits (e.g., the low-order bits) of the row address RADD. For example, the second address information BAX_S# may include the first bit RADD of the 15-bit row address RADD<0:14>. <0> The generated 2-bit signal BAX0<0:1> and the 4-bit signal BAX12<0:3> generated by decoding the 2nd and 3rd bits of the row address RADD<0:14>, RADD<1:2>. In this case, only one bit in signal BAX0<0:1> can be set to the high-order bit according to the logical value of the first bit RADD<0:1>, and only one bit in signal BAX12<0:3> can be set to the high-order bit according to the logical values ​​of the 2nd and 3rd bits RADD<1:2>. As a result, one of the eight sub-word lines allocated to a main word line can be specified based on the 2-bit signal BAX0<0:1> and the 4-bit signal BAX12<0:3> contained in the second address information BAS_S#.

[0049] The row decoder 210 can generate a block selection signal MAT_SEL<0:15> consisting of bits corresponding to a cell block by decoding the remaining bits (e.g., the most significant bit) of the row address RADD. For example, the row decoder 210 can decode the 12th, 13th, 14th, and 15th bits (RADD<11:14>) of the 15-bit row address RADD<0:14> to activate one bit in the 16-bit block selection signal MAT_SEL<0:15>. Therefore, a cell block can be specified based on the block selection signal MAT_SEL<0:15>.

[0050] The line decoder 210 can latch the line address RADD according to the activation command ACT and the precharge command PCG, and decode the latched line address to generate first address information BAX_M#, second address information BAX_S#, and block selection signal MAT_SEL<0:15>, thereby controlling the activation timing of each signal. According to one embodiment, the line decoder 210 can generate a delayed precharge signal by delaying the precharge command PCG by a predetermined time, and latch the line address RADD according to the delayed precharge signal and the activation command ACT.

[0051] The control signal generation circuit 220 can generate a landing control signal SL_END and a word line activation signal WLOFFB according to the activation command ACT and the precharge command PCG. Specifically, the control signal generation circuit 220 can perform a soft landing operation by adjusting the activation timing of the landing control signal SL_END and the word line activation signal WLOFFB according to the precharge command PCG. The control signal generation circuit 220 can adjust the activation timing of the landing control signal SL_END and the word line activation signal WLOFFB according to the precharge command PCG to divide the soft landing operation into a first segment tA, a second segment tB, and a third segment tC. In the first segment tA, the voltage level of the word line WL drops from a high voltage (VPP) level to an intermediate voltage (VSL) level. In the second segment tB, the intermediate voltage level VA is maintained. In the third segment tC, the voltage level of the word line WL drops from the intermediate voltage (VSL) level to a low voltage (VBBW) level. The timing of the landing control signal SL_END and the word line activation signal WLOFFB can be adjusted according to the soft landing operation plan.

[0052] For example, the control signal generation circuit 220 can generate a word line activation signal WLOFFB, which is activated to a logic high level according to the activation command ACT, deactivated to a logic low level according to the precharge command PCG, and remains at a logic high level again during the second segment tB. Furthermore, the control signal generation circuit 220 can generate a landing control signal SL_END, which is activated to a logic high level according to the activation command ACT and deactivated to a logic low level after a predetermined time from the input of the precharge command PCG. The predetermined time can be the time used to specify the end point of the first segment tA of the soft landing operation. The landing control signal SL_END can distinguish the second segment tB and the third segment tC from the first segment tA. That is, the landing control signal SL_END can remain at a logic high level during the activation operation and during the first segment tA of the precharge operation, and remain at a logic low level during the second segment tB and the third segment tC.

[0053] The voltage supply circuit 230 can provide a first supply voltage or a second supply voltage as operating voltages VPPC0 to VPPC15 based on the block selection signal MAT_SEL<0:15> and the landing control signal SL_END. The first supply voltage can have a high voltage (VPP) level, while the second supply voltage can have a level (VPP-Δ) that is lower than the high voltage VPP by a preset level Δ. For example, the preset level Δ can be set to a multiple of the threshold voltage of the transistor (e.g., n*Vth, where n is an integer greater than or equal to 1). The voltage supply circuit 230 can provide the first supply voltage VPP to the main word line located on the cell block selected by the block selection signal MAT_SEL<0:15> within a first segment tA defined by the landing control signal SL_END, and provide the second supply voltage VPP-Δ to the main word line located on the unselected cell block during pre-charge operation. On the other hand, the voltage supply circuit 230 can provide a second supply voltage VPP-Δ to the main word lines located on all cell blocks during the second segment tB and the third segment tC. Detailed configuration of the voltage supply circuit 230 will be referred to... Figure 5 Describe it.

[0054] The word line driver circuit 240 can drive the sub-word lines selected from 2048 sub-word lines WL0 to WL2047 according to the row address RADD, based on the operating voltage VPPC0 to VPPC15. The word line driver circuit 240 may include a main word line (MWL) driver circuit 242, a sub-word line (SWL) control circuit 244, and a sub-word line (SWL) driver circuit 246.

[0055] The main word line driver circuit 242 can generate the main drive signal MWLB<0:255> based on the operating voltages VPPC0 to VPPC15, according to the first address information BAX_M# and the word line activation signal WLOFFB. The main word line driver circuit 242 can include 256 main word line drivers. Figure 6A The main word line drivers 242 (242_0 to 242_255) are used to drive 256 main word lines respectively. Each bit of the main drive signal MWLB<0:255> can be allocated to drive one of the 256 main word lines and to specify one of the 256 main word lines. The main word line driver circuit 242 can select one of the 256 main word line drivers 242_0 to 242_255 according to the first address information BAX_M#, and control the activation timing of the signals output from the selected main word line driver according to the word line activation signal WLOFFB. Detailed configuration of the main word line driver circuit 242 will be discussed later. Figure 6A and Figure 6B As described in the text.

[0056] The sub-word line control circuit 244 can generate a first sub-drive signal FX<0:7> and a second sub-drive signal FXB<0:7> based on the second address information BAX_S# and the word line activation signal WLOFFB. The sub-word line control circuit 244 can generate the first sub-drive signal FX<0:7> and the second sub-drive signal FXB<0:7> corresponding to the second address information BAX_S#, and control the activation timing of the first sub-drive signal FX<0:7> and the second sub-drive signal FXB<0:7> according to the word line activation signal WLOFFB. The first sub-drive signal FX<0:7> and the second sub-drive signal FXB<0:7> can be used to specify one of the eight sub-word lines allocated to a main word line.

[0057] The sub-word line driving circuit 246 can drive 2048 sub-word lines WL0 to WL2047 according to the main driving signal MWLB<0:255>, the first sub-driving signal FX<0:7>, and the second sub-driving signal FXB<0:7>. The sub-word line driving circuit 246 may include 2048 sub-word line drivers (…). Figure 7A Lines 246_0 to 246_2047 are used to drive 2048 sub-word lines WL0 to WL2047 respectively. (Refer to...) Figure 7A and Figure 7B Describe the detailed configuration of the sub-word line drive circuit 246.

[0058] Figure 5 for Figure 4 Detailed circuit diagram of voltage supply circuit 230.

[0059] See Figure 5The voltage supply circuit 230 may include first to sixteenth unit block voltage supply circuits 230_0 to 230_15, respectively, corresponding to the first to sixteenth unit blocks. Since the first to sixteenth unit block voltage supply circuits 230_0 to 230_15 have substantially the same configuration, the first unit block voltage supply circuit 230_0 will be described in detail.

[0060] The first unit block voltage supply circuit 230_0 may include a control unit 310 and a supply unit 320.

[0061] Control unit 310 can select the block selection signal MAT_SEL <0> The landing control signal SL_END generates a voltage control signal V_CTRL. For example, the control unit 310 can be implemented using a NAND gate to control the block selection signal MAT_SEL. <0> The landing control signal SL_END is used to perform a logical AND-NOT operation. With the above configuration, when the block selection signal MAT_SEL is used... <0> When the appropriate cell block is selected, the control unit 310 can reverse the landing control signal SL_END to output the voltage control signal V_CTRL. Therefore, the voltage control signal V_CTRL can be activated to a logic low level during the activation operation and the first segment tA of the pre-charge operation.

[0062] The supply unit 320 can provide a first supply voltage VPP or a second supply voltage VPP-Δ as the operating voltage VPPC0 according to the voltage control signal V_CTRL. When the voltage control signal V_CTRL is activated to a logic low level, the supply unit 320 can output the first supply voltage VPP, and when the voltage control signal V_CTRL is deactivated to a logic high level, the supply unit 320 can output the second supply voltage VPP-Δ.

[0063] The supply unit 320 may include a first PMOS transistor P11, a second PMOS transistor P12, and an NMOS transistor N11.

[0064] The first PMOS transistor P11 can be coupled between the high-voltage (VPP) node and the first node (VPPC_N), and receives a voltage control signal V_CTRL as its gate. The first PMOS transistor P11 can operate as a switching element, which is turned on according to the voltage control signal V_CTRL. The first PMOS transistor P11 can transmit the high voltage VPP to the first node VPPC_N according to the voltage control signal V_CTRL.

[0065] The first NMOS transistor N11 can be located between the high-voltage (VPP) node and the common node COM_N, and has a diode-coupled gate and drain. The second PMOS transistor P12 can be located between the common node COM_N and the first node VPPC_N, and also has a diode-coupled gate and drain. That is, the first NMOS transistor N11 and the second PMOS transistor P12 can be diode-coupled in series between the high-voltage (VPP) node and the first node VPPC_N, clamping the high voltage VPP to transfer the clamped voltage to the first node VPPC_N. When the first PMOS transistor P11 is turned off, the voltage level of the first node VPPC_N can be adjusted by the first NMOS transistor N11 and the second PMOS transistor P12 to be no lower than the voltage level calculated by subtracting the sum of the threshold voltages of the NMOS transistor and the PMOS transistor from the high voltage VPP. The operating voltage VPPC0 can be output from the first node VPPC_N.

[0066] With the above configuration, during the pre-charge operation, when the corresponding block selection signal is activated, each of the cell block voltage supply circuits 230_0 to 230_15 can provide a first supply voltage VPP as the operating voltage during the first segment tA when the first PMOS transistor P11 is turned on. Furthermore, during the pre-charge operation, each of the cell block voltage supply circuits 230_0 to 230_15 can provide a second supply voltage VPP-Δ as the operating voltage during the second segment tB and the third segment tC when the first PMOS transistor P11 is turned off.

[0067] Figure 6A and Figure 6B It is shown Figure 4 Detailed circuit diagram of the main word line driver circuit 242.

[0068] refer to Figure 6AThe main word line driver circuit 242 may include first to 256 main word line drivers 242_0 to 242_255. The first to 256 main word line drivers 242_0 to 242_255 may be selected (or enabled) according to the first address information BAX_M# to output a main drive signal MWLB<0:255> corresponding to the word line activation signal WLOFFB based on the operating voltage VPPC0 to VPPC15. The first to 256 main word line drivers 242_0 to 242_255 may receive the operating voltage in unit blocks. For example, the first to sixteenth main word line drivers 242_0 to 242_15 can receive the operating voltage VPPC0 for the first unit block MB0, while the seventeenth to thirty-first main word line drivers 242_16 to 242_31 can receive the operating voltage VPPC1 for the second unit block MB1. In this way, the 241st to 256th main word line drivers 242_240 to 242_255 can receive the operating voltage VPPC15 for the sixteenth unit block MB15.

[0069] Since the first through 256 main word line drivers 242_0 to 242_255 have substantially the same configuration, the description will take the first main word line driver 242_0 as an example. (See reference...) Figure 6B The first main word line driver 242_0 may include first to fourth PMOS transistors P21 to P24, and first to third NMOS transistors N21 to N23. The first PMOS transistor P21 and the second PMOS transistor P22 may be referred to as pull-up transistors, while the first NMOS transistor N21 may be referred to as a bias transistor.

[0070] The first PMOS transistor P21 can be coupled between the high voltage (VPP) node and the second node C_N1, and receives the word line activation signal WLOFFB through its gate. The first PMOS transistor P21 can transmit the high voltage VPP to the second node C_N1 based on the logic low level word line activation signal WLOFFB. The first NMOS transistor N21 can be coupled between the second node C_N1 and the ground voltage (VSS) node, and receives the first address information BAX_M0 through its gate. The first NMOS transistor N21 can ground the second node C_N1 according to the first address information BAX_M0, enabling the first master word line driver 242_0. The second PMOS transistor P22 can be coupled between the high voltage (VPP) node and the second node C_N1, and receives the voltage at the third node C_N2 through its gate. The second PMOS transistor P22 can transmit the high voltage VPP to the second node C_N1 based on the voltage at the third node C_N2.

[0071] The third PMOS transistor P23 and the second NMOS transistor N22 can form a first inverter INV1. The first inverter INV1 inverts the voltage at the second node C_N1 and transmits the inverted voltage to the third node C_N2. The fourth PMOS transistor P24 and the third NMOS transistor N23 can form a second inverter INV2. The second inverter INV2 can invert the voltage at the third node C_N2 and transmit the inverted voltage to the fourth node C_N3 based on the voltage level of the first node VPPC_N (i.e., the operating voltage VPPC0). Main drive signal MWLB <0> It can be output from the fourth node C_N3.

[0072] With the above configuration, one of the main word line drivers 242_0 to 242_255 can be selected based on the first address information BAX_M#. When the logic high-level word line activation signal WLOFFB is input, the selected main word line driver can drive the second node C_N1 to ground voltage VSS, and correspondingly, the main drive signal MWLB can be activated. <0> The output is at ground voltage (VSS) level. On the other hand, when the logic-low word line activation signal WLOFFB is input, the selected master word line driver can drive the second node C_N1 to a high voltage VPP, and correspondingly, the master drive signal MWLB can be activated. <0> The output is the operating voltage (VPP0) level.

[0073] Figure 7A and Figure 7B It is shown Figure 4 Detailed circuit diagram of the sub-word line drive circuit 246.

[0074] The sub-word line drive circuit 246 may include first to second 2048 sub-word line drivers (SWDs) 246_0 to 246_2047.

[0075] The first to the 2048th sub-word line drivers 246_0 to 246_2047 can drive the first to the 2048th sub-word lines WL0 to WL2047 according to the main drive signal MWLB<0:255>, the first sub-drive signal FX<0:7>, and the second sub-drive signal FXB<0:7>.

[0076] As shown in Table 1 below, the first to the 2048th sub-word line drivers 246_0 to 246_2047 can use the 256-bit main drive signal MWLB<0:255>, the 8-bit first sub-drive signal FX<0:7> and the second sub-drive signal FXB<0:7>, in a 256*8 combination to control the activation and deactivation of the first to the 2048th sub-word lines WL0 to WL2047.

[0077] Table 1

[0078] WL0 MWLB<0> FX<0>,FXB<0> WL1 MWLB<0> FX<1>,FXB<1> WL2 MWLB<0> FX<2>,FXB<2> WL3 MWLB<0> FX<3>,FXB<3> WL4 MWLB<0> FX<4>,FXB<4> WL5 MWLB<0> FX<5>,FXB<5> WL6 MWLB<0> FX<6>,FXB<6> WL7 MWLB<0> FX<7>,FXB<7> WL8 MWLB<1> FX<0>,FXB<0> WL9 MWLB<1> FX<1>,FXB<1> WL10 MWLB<1> FX<2>,FXB<2> WL11 MWLB<1> FX<3>,FXB<3> WL12 MWLB<1> FX<4>,FXB<4> WL13 MWLB<1> FX<5>,FXB<5> WL14 MWLB<1> FX<6>,FXB<6> WL15 MWLB<1> FX<7>,FXB<7> WL16 MWLB<2> FX<0>,FXB<0> WL17 MWLB<2> FX<1>,FXB<1> ... ... ... WL510 MWLB<63> FX<6>,FXB<6> WL511 MWLB<63> FX<7>,FXB<7>

[0079] Referring to Table 1, the activation and deactivation of the fourth word line WL3 can be based on the main drive signal MWLB. <0> First sub-drive signal FX <3> Second sub-drive signal FXB <3> Control, and the activation and deactivation of the eighteenth line WL17 can be based on the main drive signal MWLB. <2> First sub-drive signal FX <1> Second sub-drive signal FXB <1> Control. The number of word lines and the number of bits of the drive signal described in the above embodiments are only examples, and the embodiments are not limited to these. Multiple word lines can be driven according to the combination of bits of the drive signal.

[0080] Since the first through 2048 sub-word line drivers 246_0 to 246_2047 have essentially the same configuration, the description will focus on the first sub-word line driver 246_0. (Reference) Figure 7B The first sub-word line driver 246_0 may include a first PMOS transistor P31, a first NMOS transistor N31, and a second NMOS transistor N32.

[0081] The first PMOS transistor P31 can receive the first sub-drive signal FX. <0> The source of the receiver receives the main drive signal MWLB. <0> The gate of the transistor and the drain coupled to the first sub-word line WL0. The first PMOS transistor P31 can receive a high voltage VPP as the substrate voltage. Therefore, when the main drive signal MWLB... <0> When input is a logic low level, the first PMOS transistor P31 can respond according to the first sub-drive signal FX. <0> Drive the first sub-word line WL0 to a high voltage (VPP) level. The first NMOS transistor N31 can be coupled between the low voltage (VBBW) node and the first sub-word line WL0, and receive the main drive signal MWLB. <0> As the gate, the first NMOS transistor N31 can respond to the logic high-level main drive signal MWLB. <0> The first sub-word line WL0 is driven to a low voltage (VBBW) level. A second NMOS transistor N32 can be coupled between the first sub-word line WL0 and the low voltage (VBBW) node, and receives the second sub-drive signal FXB through its gate. <0> The second NMOS transistor N32 can respond to the logic high level of the second sub-drive signal FXB. <0> Drive the first sub-word line WL0 to a low voltage (VBBW) level.

[0082] The following will refer to Figures 2 to 8 Describes a soft landing operation of a storage device 100 according to an embodiment of the present disclosure.

[0083] Figure 8 It is a waveform diagram used to describe the operation of the storage device 100 according to an embodiment of the present disclosure.

[0084] refer to Figure 8 Before time point t0, since all bits of the block selection signal MAT_SEL<0:15> are at logic low, the voltage supply circuit 230 can provide a second supply voltage VPP-Δ as the operating voltage VPP0 to VPPC1 to all cell blocks MB0 to MB15. When the word line activation signal WLOFFB is deactivated to logic low, all main word line drivers 242_0 to 242_255 can output the main drive signal MWLB<0:255> at the second supply voltage (VPP-Δ) level.

[0085] At time point t0, the activation command ACT is input. The line decoder 210 can decode the line address RADD input along with the activation command ACT to generate a block selection signal MAT_SEL<0:15> for selecting one cell block from multiple cell blocks. Furthermore, the line decoder 210 can decode the line address RADD to generate first address information BAX_M# for specifying one of multiple master word lines and second address information BAX_S# for specifying one of eight sub-word lines assigned to a master word line. Hereinafter, the selection of the first cell block MB0 and the selection of the first sub-word line WL0 constituting the first master word line assigned to the first cell block MB0 are illustrated.

[0086] The control signal generation circuit 220 can generate a logic-high landing control signal SL_END and a logic-high word line activation signal WLOFFB according to the activation command ACT. Therefore, only the voltage control signal V_CTRL corresponding to the selected first cell block MB0 is activated to a logic-low level, and the voltage supply circuit 230 provides a first supply voltage VPP to the selected first cell block MB0 as the operating voltage VPPC0, while the second supply voltage VPP-Δ can be provided as the operating voltages VPPC1 to VPPC15 to the remaining unselected cell blocks MB1 to MB15.

[0087] The first main word line driver 242_0 can adjust the main drive signal MWLB based on the logic high-level word line activation signal WLOFFB. <0> The output is at ground voltage (VSS) level. The first sub-word line driver 246_0 can be driven by the logic high-level first sub-drive signal FX. <0> The first sub-word line WL0 is driven to a high voltage (VPP) level. On the other hand, with the second to sixteenth main word line drivers 242_1 to 242_15 located in the first cell block MB0, since the first NMOS transistor N21, which acts as a bias transistor, is turned off, the second node C_N1 is floated, while the third node C_N2 remains in its previous state, allowing the main drive signal MWLB<1:15> to be output to the first supply voltage (VPP) level. Furthermore, the main drive signal MWLB<16:255> located in an unselected cell block can maintain the second supply voltage (VPP-Δ) level. Here, the precharge signal BLEQ provided to the bit line sense amplifier BLSA is deactivated to a logic low level according to the activation command ACT; therefore, the bit line sense amplifier BLSA can be activated to perform sense amplification operation.

[0088] At time t1, the precharge command PCG is input. The control signal generation circuit 220 can deactivate the word line activation signal WLOFFB to a logic low level according to the precharge command PCG. In this case, the sub-word line control circuit 244 can activate the first sub-drive signal FX. <0> The signal is switched to a logic low level. The first master word line driver 242_0 can convert the master drive signal MWLB to a logic low level. <0> The output is at the first supply voltage (VPP) level, and the first sub-word line driver 246_0 can discharge the first sub-word line WL0 from the high voltage (VPP) level.

[0089] Subsequently, at time t2, the control signal generation circuit 220 can convert the landing control signal SL_END to a logic low level and activate the word line activation signal WLOFFB to a logic high level. The voltage control signal V_CTRL is deactivated to a logic high level based on the logic low landing control signal SL_END. The voltage supply circuit 230 can supply the second supply voltage VPP-Δ as the operating voltage VPP0 to the selected first cell block MB0. The first main word line driver 242_0 can transmit the main drive signal MWLB. <0> The output is set to ground voltage (VSS) level, and the first sub-word line driver 246_0 can be adjusted based on the logic low level of the first sub-drive signal FX. <0> The first sub-word line WL0 is maintained at the intermediate voltage (VSL) level. Therefore, a first segment tA can be defined between time point t1 and time point t2, in which the first sub-word line WL0 decreases from the high voltage (VPP) level to the intermediate voltage (VSL) level, and a second segment tB can be defined between time point t2 and time point t3, in which the first sub-word line WL0 maintains the intermediate voltage (VSL) level.

[0090] At time t3, the control signal generation circuit 220 can deactivate the word line activation signal WLOFFB to a logic low level, while the sub-word line control circuit 244 can activate the second sub-drive signal FXB. <0> The signal is converted to a logic high level. The first master word line driver 242_0 can convert the master drive signal MWLB to a logic high level. <0> The output is at the second supply voltage (VPP-Δ) level, while the first sub-word line driver 246_0 can be driven by the second sub-drive signal FXB at a logic high level. <0> The first sub-word line WL0 is discharged to a low voltage (VBBW) level. Therefore, a third segment tC can be defined between time points t3 and t4, during which the first sub-word line WL0 decreases from the intermediate voltage (VSL) level to the low voltage (VBBW) level. In this case, the precharge signal BLEQ provided to the bit line sense amplifier BLSA can be activated to a logic high level according to the precharge command PCG, thus allowing the bit line sense amplifier BLSA to precharge the bit line.

[0091] Here, as Figure 9 As shown, during the third segment tC, the main word line driver 242_x (where x is an integer between 0 and 255) can be supplied with a second supply voltage VPP-Δ through the first node VPPC_N to drive the main drive signal MWLB. <x>Therefore, the stress applied to the PMOS transistor P31 included in the sub-word line driver 246_y (where y is an integer between 0 and 2047) can be reduced. Furthermore, during the third segment tC, a current path CP is formed between the first node VPPC_N of the main word line driver 242_x and the low-voltage (VBBW) node of the sub-word line driver 246_y. Therefore, without the need for a separate leakage current circuit, the switching time from the first supply voltage (VPP) level to the second supply voltage (VPP-Δ) level can be reduced, thus improving the stabilization speed of the voltage applied to the sub-word line driver 246_y. As described above, the memory device according to embodiments of this disclosure can prevent degradation of the discharge characteristics of the selected sub-word line and reduce leakage current of the unselected sub-word line drivers by providing the operating voltage of the main word line driver at a level lower than the high voltage after the second segment tB of the soft-landing operation. Therefore, row hammering during pre-charge operation can be mitigated and tRP logic failure can be prevented.

[0092] Figure 10 This is a block diagram illustrating a storage system 1000 according to an embodiment of the present disclosure.

[0093] refer to Figure 10 The storage system 1000 may include a storage device 100 and a memory controller 200.

[0094] The memory controller 200 can control the overall operation of the storage system 1000 and the overall data exchange between the host and the storage device 100. The memory controller 200 can generate a command / address signal C / A in response to a request REQ from the host and provide the command / address signal C / A to the storage device 100. According to one embodiment, the memory controller 200 can provide a clock and the command / address signal C / A to the storage device 100. The memory controller 200 can provide the storage device 100 with data DQ corresponding to the request REQ provided from the host. The memory controller 200 can provide the host with data DQ read from the storage device 100. The command / address signal C / A provided by the memory controller 200 to the storage device 100 may include an activation command ACT, a precharge command PCG, a read command RD, and a write command WT.

[0095] The storage device 100 may have a configuration substantially the same as that of the storage device 100 in FIG. 1. By dividing the voltage level of the word line WL into a first segment tA, in which the voltage level decreases from a high voltage (VPP) level to an intermediate voltage (VSL) level; a second segment tB, in which the intermediate voltage (VSL) level is maintained; and a third segment tC, in which the voltage level of the word line WL decreases from the intermediate voltage (VSL) level to a low voltage (VBBW) level, the storage device 100 can perform a soft-landing operation for driving the word line WL. Specifically, according to one embodiment of this disclosure, the storage device 100 may provide the operating voltage of the main word line driver to a voltage lower than the high voltage during the second segment tB and the third segment tC of the soft-landing operation, thereby reducing the leakage current of the unselected sub-word line drivers and preventing degradation of the discharge performance of the selected sub-word lines. Furthermore, the storage device 100 may drive the main drive signal (or main word line) to a voltage lower than the high voltage during the third segment tC, thereby further mitigating the slope of the selected sub-word lines and reducing line hammering.

[0096] Various embodiments of this disclosure are depicted in the accompanying drawings and specification. Although specific terminology is used herein, it is only for describing embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations can be made within the spirit and scope of this disclosure. Those skilled in the art will understand that various modifications can be made beyond the embodiments disclosed herein, building upon the technical scope of this disclosure. Embodiments can be combined to form additional embodiments.

[0097] It should be noted that although the technical spirit of this disclosure has been described in conjunction with embodiments thereof, this is for descriptive purposes only and should not be construed as limiting. Those skilled in the art will understand that various modifications can be made without departing from the technical spirit of this disclosure and the following claims.

[0098] For example, the logic gates and transistors provided as examples in the above embodiments can be implemented in different positions and types according to the polarity of the input signal.< / x>

Claims

1. A storage device, comprising: A unit block, in which multiple sub-lines are arranged; Control signal generation circuit, Specifically: it generates landing control signals based on pre-charge commands to perform soft landing operations on the plurality of sub-word lines; Voltage supply circuit, Specifically: a first supply voltage or a second supply voltage is provided as the operating voltage based on a block selection signal for selecting one of the unit blocks and the landing control signal, wherein the second supply voltage is less than the first supply voltage; as well as A word line driving circuit that drives the sub-word line selected by the row address among the plurality of sub-word lines based on the operating voltage.

2. The storage device according to claim 1, wherein the control signal generation circuit: The landing control signals are generated by dividing the soft landing operation into a first segment, a second segment, and a third segment. In the first segment, the voltage level of the selected sub-word line decreases from a first voltage level to a second voltage level. In the second section, the second voltage level is maintained, and In the third segment, the voltage level of the selected sub-word line is reduced from the second voltage level to the third voltage level.

3. The storage device according to claim 2, wherein, The landing control signal distinguishes the second segment and / or the third segment from the first segment.

4. The storage device according to claim 2, in, The multiple sub-character lines combine to form the main character line.

5. The storage device according to claim 4, in, The voltage supply circuit: During the first segment, the first supply voltage is provided to the main word line allocated to the unit block including the selected sub-word line, and the second supply voltage is provided to the main word line allocated to the remaining unit blocks. During the second and third segments, the second supply voltage is provided to the main word line allocated to all cell blocks.

6. The storage device according to claim 1, in, The voltage supply circuit includes unit block voltage supply circuits corresponding to the unit blocks, and Each of the unit block voltage supply circuits includes: The control unit, which: generates a voltage control signal based on the landing control signal and the block selection signal; and The supply unit provides the first supply voltage or the second supply voltage as the operating voltage according to the voltage control signal.

7. The storage device according to claim 6, wherein, The supply department includes: A first transistor, coupled between the high-voltage node and the first node, is used to receive the voltage control signal; and One or more transistors, wherein a diode is connected in series between the high-voltage node and the first node, wherein the operating voltage is output from the first node.

8. The storage device of claim 1, wherein the word line driving circuit comprises: A main word line driving circuit, which: receives the operating voltage, and generates a main driving signal in response to first address information and a word line activation signal, wherein the first address information is included in the row address; Sub-word line control circuitry, comprising: generating a sub-drive signal in response to second address information and the word line activation signal, wherein the second address information is included in the row address; and The sub-word line driving circuit drives the selected sub-word line according to the main driving signal and the sub-driving signal.

9. The storage device according to claim 8, in, The multiple sub-character lines combine to form the main character line.

10. The storage device according to claim 9, in, The first address information includes information for selecting one of the main word lines, while the second address information includes information for selecting one of the sub-word lines assigned to the selected main word line.

11. A storage device, comprising: A unit block, in which multiple mainword lines are allocated; Multiple main word line drivers, wherein: the multiple main word lines are driven based on an operating voltage; and A voltage supply circuit that, based on a landing control signal for performing a soft landing operation to precharge the plurality of main word lines, selectively provides a first supply voltage or a second supply voltage as the operating voltage to a main word line driver that drives the main word lines of the unit blocks selected by the block selection signal, wherein the second supply voltage is less than the first supply voltage.

12. The storage device according to claim 11, further comprising: The control signal generation circuit generates the landing control signal by dividing the soft landing operation into a first segment, a second segment, and a third segment. During the pre-charge operation: The first segment corresponds to the discharge from a high voltage level to an intermediate voltage level. The second segment corresponds to maintaining the intermediate voltage level, and The third segment corresponds to discharging from the intermediate voltage level to a low voltage level.

13. The storage device according to claim 12, in, The landing control signal distinguishes the second segment and / or the third segment from the first segment.

14. The storage device of claim 12, wherein the voltage supply circuit: During the first segment, the first supply voltage is provided to the main word line allocated to the selected cell block, and the second supply voltage is provided to the main word line allocated to the remaining cell blocks. During the second and third segments, the second supply voltage is provided to the main word line allocated to all cell blocks.

15. The storage device according to claim 12, further comprising: Multiple sub-word line drivers, wherein: the drivers are combined to form a sub-word line of one of the multiple main word lines.

16. The storage device according to claim 15, in, Each of the plurality of main word line drivers includes a first type of transistor, which receives the operating voltage through a first node and drives the corresponding main word line. Each of the sub-word line drivers includes a second type of transistor coupled between the corresponding sub-word line and a ground node, and has a gate coupled to the corresponding main word line. During the third segment, a current path is formed between the first node, the first type of transistor, the second type of transistor, and the ground node.

17. A method of operating a storage device, the storage device comprising a cell block in which a plurality of main word lines are allocated, wherein a plurality of sub-word lines are combined to form one of the plurality of main word lines, the method comprising: Receive precharge command; A first supply voltage is provided to the main word line allocated to the unit block comprising sub-word lines selected from the plurality of sub-word lines, and the selected sub-word lines are discharged from the first voltage level to the second voltage level for the first time. as well as A second supply voltage is provided to the main word line allocated to all cell blocks, and the selected sub-word line is discharged from the second voltage level to a third voltage level, wherein the second supply voltage is less than the first supply voltage.

18. The operating method according to claim 17, further comprising: Maintain the second voltage level of the selected sub-word line between the first discharge and the second discharge.

19. The operating method according to claim 17, further comprising: During the initial discharge, the second supply voltage is provided to the main word line allocated to the remaining cell blocks.

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