Method for coating insulating edge of ceramic capacitor

Abstract

The invention provides a method for coating an insulating edge of a ceramic capacitor, which comprises the following steps of: sequentially depositing a titanium layer and a copper layer on a ceramic diaphragm, spin-coating photoresist on the end surface of the ceramic diaphragm, and sequentially baking, aligning and exposing, developing, etching and removing photoresist and cleaning to obtain the ceramic capacitor with the insulating edge; and the size of the insulating edge is 0.01 mm to 0.1 mm. Through the precise alignment system in the photoetching industry, the machining precision can be improved, and the offset of the electrode can be regulated and controlled; by sputtering the titanium layer and the copper layer, the wettability of subsequent welding of the ceramic capacitor can be improved. Meanwhile, the insulating edge of the ceramic capacitor is in the range of 0.01 mm-0. 1mm, so that not only can the miniaturization of the capacitor be ensured, but also the capacity of the capacitor can be ensured, and the voltage-withstanding strength of the ceramic capacitor is further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic components, and relates to a coating method of a ceramic capacitor, in particular to a coating method of an insulating edge of a ceramic capacitor. BACKGROUND

[0002] In order to maximize the capacity, in the existing process, the two end faces of the ceramic capacitor are usually covered with electrode raw materials to form electrodes on the two end faces. However, in the high-voltage field, the ceramic capacitor has a higher requirement for the voltage resistance performance, and the end face electrode coating process will reduce the voltage resistance performance of the ceramic capacitor to a certain extent. Therefore, under the premise of ensuring the miniaturization of the ceramic capacitor and without abandoning the larger capacity, the ceramic capacitor needs to retain a certain size of the insulating edge.

[0003] According to calculation, when the size of the insulating edge is within the range of 0.1 mm, the loss of the ceramic capacitor capacity will be within the range of 3%, which meets the requirement of the tolerance range. However, the size shrinkage error of the ceramic itself and the operation error of the electrode coating process are not conducive to the precise control of the size of the insulating edge.

[0004] CN106098369A discloses a processing method of an insulating edge of a ceramic dielectric capacitor, which comprises the following steps: step 1, calculating the actual dielectric constant of the ceramic substrate, and then calculating the electrode size through the actual dielectric constant to realize the adjustment of the capacity; step 2, cutting the insulating edge with a first blade, and the cutting depth is below the metal layer; step 3, cutting the insulating edge into a single grain capacitor along the center of the insulating edge with a second blade. The insulating edge of the ceramic dielectric capacitor obtained by the processing method has clear, obvious and good straightness; the capacity can be adjusted and the insulating edge has no residual metal, so that the insulating effect can be achieved; and the production cycle can be shortened, the production efficiency can be improved, the cost can be reduced, and the pollution to the environment can be reduced. However, the insulating edge is removed by using a blade, which has low precision and cannot prepare an insulating edge with a small size (less than 0.1 mm).

[0005] In the prior art, there is a problem that the insulating edge of the ceramic capacitor cannot be prepared with a small size and the size of the insulating edge cannot be precisely controlled, and therefore, how to prepare the insulating edge of the ceramic capacitor with a small size has become a problem to be solved at present. SUMMARY

[0006] To solve the above technical problems, the present application provides a coating method of an insulating edge of a ceramic capacitor, which can improve the processing precision and control the offset of the electrode through the precise alignment system of the photoetching industry; and can improve the wettability of the subsequent soldering of the ceramic capacitor through the sputtering of the titanium layer and the copper layer. Meanwhile, the insulating edge of the ceramic capacitor is within the range of 0.01 mm-0.1 mm, which can not only ensure the miniaturization of the capacitor, but also ensure the capacity of the capacitor itself and further improve the voltage resistance strength of the ceramic capacitor.

[0007] To achieve this objective, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a coating method for insulating edges of a ceramic capacitor, the coating method comprising the following steps: sequentially depositing a titanium layer and a copper layer on a ceramic diaphragm, then spin-coating photoresist on the end face of the ceramic diaphragm, and then sequentially performing baking, alignment exposure, development, etching and photoresist removal cleaning to obtain a ceramic capacitor with insulating edges; the size of the insulating edges is 0.01mm-0.1mm.

[0009] This invention utilizes a precise alignment system from the photolithography industry to improve processing accuracy and control electrode offset. By sputtering titanium and copper layers, it enhances the wettability and bonding strength of subsequent ceramic capacitor welding. Simultaneously, the insulation edge of the ceramic capacitor is within the range of 0.01mm-0.1mm, ensuring not only capacitor miniaturization but also maintaining capacitance and further improving the voltage withstand strength.

[0010] Specifically, the size of the insulating edge can be 0.01mm, 0.03mm, 0.05mm, 0.07mm, 0.09mm or 0.1mm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0011] Preferably, the thickness of the titanium layer is 0.1μm-0.3μm, for example, it can be 0.1μm, 0.15μm, 0.2μm, 0.25μm or 0.3μm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0012] By adjusting the thickness of the titanium layer, this invention can further improve the bonding force between the sputtered layer and the ceramic substrate, and further improve the withstand voltage of the ceramic capacitor.

[0013] Preferably, the deposition method of the titanium layer includes a first magnetron sputtering.

[0014] Preferably, the holding temperature of the first magnetron sputtering is 200℃-300℃, for example, it can be 200℃, 220℃, 240℃, 260℃, 280℃ or 300℃, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0015] Preferably, the holding time for the first magnetron sputtering is 10 min to 30 min, for example, it can be 10 min, 15 min, 20 min, 25 min or 30 min, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0016] Preferably, the thickness of the copper layer is 0.7μm-1μm, for example, it can be 0.7μm, 0.75μm, 0.8μm, 0.85μm, 0.9μm or 1μm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0017] By adjusting the thickness of the copper layer, this invention can further improve the bonding force between the sputtered layer and the ceramic substrate, and further improve the withstand voltage of the ceramic capacitor.

[0018] Preferably, the copper layer deposition method includes a second magnetron sputtering.

[0019] Preferably, the holding temperature of the second magnetron sputtering is 150℃-250℃, for example, it can be 150℃, 170℃, 190℃, 200℃, 220℃ or 250℃, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0020] Preferably, the holding time for the second magnetron sputtering is 10 min to 30 min, for example, it can be 10 min, 15 min, 20 min, 25 min or 30 min, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0021] Preferably, the spin coating rate of the photoresist is 2000rpm-4000rpm, for example, it can be 2000rpm, 2500rpm, 3000rpm, 3500rpm or 4000rpm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0022] Preferably, the photoresist is a positive photoresist.

[0023] Preferably, the baking temperature is 95℃-105℃, for example, it can be 95℃, 97℃, 99℃, 100℃, 103℃ or 105℃, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0024] Preferably, the baking heat preservation time is 40s-60s, for example, it can be 40s, 45s, 50s, 55s or 60s, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0025] Preferably, the duration of the alignment exposure is 40s-60s, for example, it can be 40s, 45s, 50s, 55s or 60s, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0026] Preferably, the duration of the development is 40s-60s, for example, 40s, 45s, 50s, 55s or 60s, but not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0027] Preferably, the developing solution comprises a tetramethylammonium hydroxide solution.

[0028] Preferably, the etching method includes etching using a titanium-copper etching solution.

[0029] Preferably, the titanium-copper etching solution comprises an oxidant, an inorganic acid, and a copper salt.

[0030] Preferably, the oxidant includes hydrogen peroxide.

[0031] Preferably, the inorganic acid includes sulfuric acid and / or nitric acid.

[0032] Preferably, the copper salt comprises copper sulfate and / or copper chloride.

[0033] Preferably, the adhesive removal and cleaning method includes using an oxygen plasma process for adhesive removal.

[0034] Preferably, the oxygen-containing plasma includes oxygen and / or carbon dioxide.

[0035] Preferably, the ceramic film is further surface-treated before deposition.

[0036] Preferably, the surface treatment includes polishing and cleaning in sequence.

[0037] Preferably, after polishing, the roughness of the ceramic film is 0.1μm-0.8μm, for example, it can be 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm or 0.8μm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0038] This invention can further control the bonding force between the sputtered layer and the substrate by adjusting the roughness of the ceramic diaphragm, and improve the withstand voltage of the ceramic capacitor.

[0039] Preferably, the cleaning detergent includes an alcohol-based detergent.

[0040] Preferably, the alcohol detergent comprises any one or a combination of at least two of methanol, ethanol, or isopropanol, with typical but non-limiting combinations including a combination of methanol and ethanol, or a combination of methanol, ethanol, and isopropanol.

[0041] Preferably, the cleaning time is 5-10 minutes, for example, 5 minutes, 6 minutes, 7 minutes, 8 minutes, 9 minutes or 10 minutes, but not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0042] Preferably, after cleaning, the product is also dried.

[0043] Preferably, the drying temperature is 70℃-90℃, for example, it can be 70℃, 75℃, 80℃, 85℃ or 90℃, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0044] Preferably, the drying holding time is 8-12 minutes, for example, it can be 8 minutes, 9 minutes, 10 minutes, 11 minutes or 12 minutes, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0045] As a preferred technical solution of the present invention, the preparation method includes the following steps:

[0046] (1) The ceramic diaphragm is first polished, and the roughness of the ceramic diaphragm after polishing is 0.1μm-0.8μm. Then it is ultrasonically cleaned with alcohol detergent for 5min-10min and dried to obtain the surface-treated ceramic diaphragm. The drying temperature is 70℃-90℃ and the drying time is 8min-12min.

[0047] (2) A titanium layer and a copper layer are sequentially magnetron sputtered on the end face of the surface-treated ceramic film to obtain a sputtered ceramic film; the thickness of the titanium layer is 0.1μm-0.3μm, the temperature of the first magnetron sputtering is 200℃-300℃, the time of the first magnetron sputtering is 10min-30min, the thickness of the copper layer is 0.7μm-1μm, the temperature of the second magnetron sputtering is 150℃-250℃, and the time of the second magnetron sputtering is 10min-30min.

[0048] (3) Positive photoresist is spin-coated onto the end face of the sputtered ceramic film, and then baked, aligned, exposed, developed, etched and cleaned in sequence to obtain the ceramic capacitor with an insulating edge of 0.01mm-0.1mm. The baking temperature is 95℃-105℃, the baking time is 40s-60s, the alignment exposure duration is 40s-60s, the development duration is 40s-60s, the etching method includes etching with titanium copper etching solution, and the cleaning method includes removing the photoresist with plasma process containing oxygen and / or carbon dioxide.

[0049] Compared with the prior art, the present invention has at least the following beneficial effects:

[0050] (1) The present invention can improve the processing accuracy and control the offset of the electrode by using the precise alignment system of the photolithography industry.

[0051] (2) The present invention can improve the wettability of subsequent ceramic capacitor welding by sputtering titanium and copper layers.

[0052] (3) The insulation edge of the ceramic capacitor described in this invention is in the range of 0.01mm-0.1mm, which not only ensures the miniaturization of the capacitor, but also ensures the capacitance of the capacitor itself, and further improves the withstand voltage of the ceramic capacitor. Detailed Implementation

[0053] To facilitate understanding of the present invention, the following embodiments are provided. Those skilled in the art should understand that these embodiments are merely illustrative and should not be construed as limiting the scope of the invention.

[0054] Example 1

[0055] This embodiment provides a coating method for the insulating edge of a ceramic capacitor, the coating method comprising the following steps:

[0056] (1) The ceramic diaphragm is first polished, and the roughness of the ceramic diaphragm after polishing is 0.6 μm. Then it is ultrasonically cleaned with ethanol for 8 min and dried to obtain the surface-treated ceramic diaphragm. The drying temperature is 80℃ and the drying time is 10 min.

[0057] (2) A titanium layer and a copper layer are sequentially magnetron sputtered on the end face of the surface-treated ceramic film to obtain a sputtered ceramic film; the thickness of the titanium layer is 0.2 μm, the temperature of the first magnetron sputtering is 240 °C, the time of the first magnetron sputtering is 20 min, the thickness of the copper layer is 0.8 μm, the temperature of the second magnetron sputtering is 200 °C, and the time of the second magnetron sputtering is 20 min;

[0058] (3) Positive photoresist is spin-coated onto the end face of the sputtered ceramic film, and then baked, aligned, exposed, developed, etched with titanium copper etching solution, and cleaned with photoresist in sequence to obtain the ceramic capacitor with a 0.05mm insulating edge. The baking temperature is 100℃, the baking time is 50s, the alignment exposure duration is 50s, the development duration is 50s, the titanium copper etching solution includes hydrogen peroxide, sulfuric acid and copper sulfate, and the photoresist removal method includes removing the photoresist using an oxygen plasma process.

[0059] Example 2

[0060] This embodiment provides a coating method for the insulating edge of a ceramic capacitor, the coating method comprising the following steps:

[0061] (1) The ceramic diaphragm is first polished, and the roughness of the ceramic diaphragm after polishing is 0.1 μm. Then it is ultrasonically cleaned with methanol for 5 min and dried to obtain the surface-treated ceramic diaphragm. The drying temperature is 70℃ and the drying time is 12 min.

[0062] (2) A titanium layer and a copper layer are sequentially magnetron sputtered on the end face of the surface-treated ceramic film to obtain a sputtered ceramic film; the thickness of the titanium layer is 0.1 μm, the temperature of the first magnetron sputtering is 200 °C, the time of the first magnetron sputtering is 30 min, the thickness of the copper layer is 0.7 μm, the temperature of the second magnetron sputtering is 150 °C, and the time of the second magnetron sputtering is 30 min;

[0063] (3) Positive photoresist is spin-coated onto the end face of the sputtered ceramic film, and then baked, aligned, exposed, developed, etched with titanium copper etching solution, and cleaned with photoresist in sequence to obtain the ceramic capacitor with a 0.01mm insulating edge. The baking temperature is 95℃, the baking time is 60s, the alignment exposure duration is 60s, the development duration is 60s, the titanium copper etching solution includes hydrogen peroxide, nitric acid and copper chloride, and the photoresist removal method includes using a carbon dioxide plasma process for photoresist removal.

[0064] Example 3

[0065] This embodiment provides a coating method for the insulating edge of a ceramic capacitor, the coating method comprising the following steps:

[0066] (1) The ceramic diaphragm is first polished, and the roughness of the ceramic diaphragm after polishing is 0.8 μm. Then it is ultrasonically cleaned with isopropanol for 10 min and dried to obtain the surface-treated ceramic diaphragm. The drying temperature is 90℃ and the drying time is 8 min.

[0067] (2) A titanium layer and a copper layer are sequentially magnetron sputtered on the end face of the surface-treated ceramic film to obtain a sputtered ceramic film; the thickness of the titanium layer is 0.3 μm, the temperature of the first magnetron sputtering is 300℃, the time of the first magnetron sputtering is 10 min, the thickness of the copper layer is 1 μm, the temperature of the second magnetron sputtering is 250℃, and the time of the second magnetron sputtering is 10 min;

[0068] (3) Positive photoresist is spin-coated onto the end face of the sputtered ceramic film, and then baked, aligned, exposed, developed, etched with titanium copper etching solution, and cleaned with photoresist in sequence to obtain the ceramic capacitor with a 0.1mm insulating edge. The baking temperature is 105℃, the baking time is 40s, the alignment exposure duration is 40s, the development duration is 40s, the titanium copper etching solution includes hydrogen peroxide, sulfuric acid and copper sulfate, and the photoresist removal method includes removing the photoresist using an oxygen plasma process.

[0069] Example 4

[0070] The only difference between this embodiment and Embodiment 1 is that, except that the thickness of the titanium layer in step (2) is 0.05 μm, everything else is the same as in Embodiment 1.

[0071] Example 5

[0072] The only difference between this embodiment and Embodiment 1 is that, except that the thickness of the titanium layer in step (2) is 0.35 μm, everything else is the same as in Embodiment 1.

[0073] Example 6

[0074] The only difference between this embodiment and embodiment 1 is that, except that the thickness of the copper layer in step (2) is 0.65 μm, everything else is the same as in embodiment 1.

[0075] Example 7

[0076] The only difference between this embodiment and embodiment 1 is that, except that the thickness of the copper layer in step (2) is 1.05 μm, everything else is the same as in embodiment 1.

[0077] Example 8

[0078] The only difference between this embodiment and embodiment 1 is that, except that the roughness of the ceramic diaphragm described in step (1) is 0.05 μm, everything else is the same as in embodiment 1.

[0079] Example 9

[0080] The only difference between this embodiment and embodiment 1 is that, except that the roughness of the ceramic diaphragm described in step (1) is 0.85 μm, everything else is the same as in embodiment 1.

[0081] Comparative Example 1

[0082] The only difference between this comparative example and Example 1 is that, except that the size of the insulating edge in step (3) is 0.005 mm, everything else is the same as in Example 1.

[0083] Comparative Example 2

[0084] The only difference between this comparative example and Example 1 is that, except that the size of the insulating edge in step (3) is 0.105 mm, everything else is the same as in Example 1.

[0085] Comparative Example 3

[0086] The only difference between this comparative example and Example 1 is that, except for step (3) not being performed, everything else is the same as in Example 1.

[0087] Comparative Example 4

[0088] This comparative example provides a coating method for the insulating edge of a ceramic capacitor, the coating method comprising the following steps:

[0089] (1) The ceramic diaphragm is first polished, and the roughness of the ceramic diaphragm after polishing is 0.6 μm. Then it is ultrasonically cleaned with ethanol for 8 min and dried to obtain the surface-treated ceramic diaphragm. The drying temperature is 80℃ and the holding time is 10 min.

[0090] (2) After printing copper paste on the surface-treated ceramic film using screen printing, the film is first dried at 100°C for 20 minutes and then kept at 800°C for 15 minutes to obtain the ceramic capacitor with a 0.05mm insulating edge.

[0091] Test methods

[0092] The ceramic capacitors with insulating edges prepared in Examples 1-9 and Comparative Examples 1-4 were subjected to pin soldering. The edge size and offset size were tested using a Keshiwei MX6R optical measuring microscope. The withstand voltage strength of the ceramic capacitors was tested using an LK2674A withstand voltage tester. The test results are recorded in Table 1.

[0093] Table 1

[0094]

[0095] The test results show that:

[0096] (1) As can be seen from Examples 1-9 and Comparative Examples 1-4, the present invention can improve the processing accuracy and control the electrode offset by using the precise alignment system of the photolithography industry; by sputtering titanium and copper layers, the wettability of subsequent ceramic capacitor welding can be improved. At the same time, the insulation edge of the ceramic capacitor is in the range of 0.01mm-0.1mm, which not only ensures the miniaturization of the capacitor, but also ensures the capacitance of the capacitor itself, and further improves the breakdown resistance of the ceramic capacitor.

[0097] (2) As can be seen from Examples 1 and 4-7, by further adjusting the thickness of the titanium layer and the copper layer, the present invention can further improve the bonding force between the sputtered layer and the ceramic substrate, and further improve the wettability of the ceramic capacitor welding, thereby improving the withstand voltage strength of the ceramic capacitor.

[0098] (3) As can be seen from Examples 1 and 8-9, by further adjusting the roughness of the ceramic diaphragm, the present invention can further improve the bonding force between the sputtered layer and the ceramic substrate, and further improve the wettability of the ceramic capacitor welding; at the same time, it can effectively avoid tip discharge and flashover during the use of the ceramic capacitor, thereby improving the withstand voltage strength of the ceramic capacitor.

[0099] (4) As can be seen from Example 1 and Comparative Examples 1-3, by further adjusting the size of the insulating edge, the present invention can further improve the withstand voltage of the ceramic capacitor while ensuring the ceramic capacitance.

[0100] (5) As can be seen from Example 1 and Comparative Example 4, ceramic capacitors with insulating edges are prepared by screen printing process, but the actual minimum edge size is 0, the offset size is large, the withstand voltage is low, and the consistency and stability are low.

[0101] In summary, this invention utilizes a precise alignment system from the photolithography industry to improve processing accuracy and control electrode offset. Furthermore, sputtering titanium and copper layers enhances the wettability of subsequent ceramic capacitor soldering. Simultaneously, the insulating edge of the ceramic capacitor is within the range of 0.01mm-0.1mm, ensuring both miniaturization and capacitance, while further improving its breakdown resistance.

[0102] The applicant declares that the above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.

Claims

1. A method for coating the insulating edge of a ceramic capacitor, characterized in that, The coating method includes the following steps: After depositing titanium and copper layers sequentially on a ceramic diaphragm, photoresist is spin-coated onto the end face of the ceramic diaphragm, followed by baking, alignment exposure, development, etching, and photoresist removal and cleaning to obtain a ceramic capacitor with insulating edges. The size of the insulating edge is 0.01mm-0.1mm.

2. The coating method according to claim 1, characterized in that, The thickness of the titanium layer is 0.1 μm-0.3 μm; Preferably, the deposition method of the titanium layer includes a first magnetron sputtering; Preferably, the holding temperature for the first magnetron sputtering is 200℃-300℃; Preferably, the heat preservation time for the first magnetron sputtering is 10 min to 30 min.

3. The coating method according to claim 1 or 2, characterized in that, The thickness of the copper layer is 0.7μm-1μm; Preferably, the copper layer deposition method includes a second magnetron sputtering; Preferably, the holding temperature for the second magnetron sputtering is 150℃-250℃; Preferably, the heat preservation time for the second magnetron sputtering is 10 min to 30 min.

4. The coating method according to any one of claims 1-3, characterized in that, The spin coating rate of the photoresist is 2000rpm-4000rpm; Preferably, the photoresist is a positive photoresist.

5. The coating method according to any one of claims 1-4, characterized in that, The baking temperature is 95℃-105℃; Preferably, the baking time is 40s-60s.

6. The coating method according to any one of claims 1-5, characterized in that, The duration of the alignment exposure is 40s-60s; Preferably, the development duration is 40s-60s; Preferably, the developing dissolving solution comprises a tetramethylammonium hydroxide solution.

7. The coating method according to any one of claims 1-6, characterized in that, The etching method includes etching with a titanium-copper etching solution; Preferably, the adhesive removal and cleaning method includes using an oxygen plasma process for adhesive removal.

8. The coating method according to any one of claims 1-7, characterized in that, Before deposition, the ceramic film is also subjected to surface treatment; Preferably, the surface treatment includes polishing and cleaning in sequence.

9. The coating method according to claim 8, characterized in that, After polishing, the roughness of the ceramic film is 0.1μm-0.8μm.

10. The coating method according to claim 8 or 9, characterized in that, The cleaning detergents include alcohol-based detergents; Preferably, the alcohol detergent includes any one or a combination of at least two of methanol, ethanol, or isopropanol; Preferably, the cleaning time is 5-10 minutes.

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