Driving circuit, voltage converter and control method thereof

Abstract

The driving circuit generates a first control signal and a second control signal and outputs the first control signal and the second control signal to respective control electrodes of the first power semiconductor element and the second power semiconductor element which are connected in parallel. The range of the safe operation area of the first power semiconductor element is larger than the range of the safe operation area of the second power semiconductor element. The driving circuit comprises a time delay circuit, a control logic circuit and a buffer. The time delay circuit compares a voltage level of the second control signal with a first reference voltage or compares a drain-source voltage of the first power semiconductor element with a second reference voltage, and generates a first voltage according to a comparison result. The first and second reference voltages are associated with temperatures of the first and second power semiconductor elements. The control logic circuit generates a logic signal according to the first voltage. The buffer generates a first or second control signal according to a logic signal. According to the invention, a relatively large range of a safe working area can be realized.

Description

Technical Field

[0001] This invention relates to a voltage converter, and more particularly to a drive circuit, a voltage converter, and a control method thereof. Background Technology

[0002] To achieve voltage converters with high withstand voltage, a current approach is to connect the two power semiconductor elements in the upper / lower bridge sections using a cascode connection. However, this cascode connection increases on-resistance, resulting in poor switching efficiency. Summary of the Invention

[0003] The present invention aims to provide a driving circuit for generating a first control signal and a second control signal, and respectively providing the first and second control signals to the control electrodes of a first power semiconductor element and a second power semiconductor element connected in parallel in a voltage converter. The safe operating area of ​​the first power semiconductor element is larger than that of the second power semiconductor element. The driving circuit includes a first time delay circuit, a control logic circuit, and a first buffer. The first time delay circuit performs a first comparison operation to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or compares the drain-source voltage of the first power semiconductor element with a second reference voltage and generates a corresponding second comparison result, and generates a first voltage based on the first or second comparison result. The first and second reference voltages are related to the temperature of the first and second power semiconductor elements. The control logic circuit is coupled to the first time delay circuit and generates a first logic signal based on the first voltage. The first buffer is coupled to the control logic circuit and generates one of the first and second control signals based on the first logic signal.

[0004] In some embodiments, the first reference voltage increases as the temperature of the first and second power semiconductor elements decreases, and the second reference voltage increases as the temperature of the first and second power semiconductor elements increases.

[0005] In some embodiments, a first time delay circuit performs a first comparison operation to generate a first comparison result and generate a first voltage based on the first comparison result, and a first buffer generates a first control signal based on a first logic signal. The driving circuit further includes a second time delay circuit and a second buffer. The second time delay circuit performs a second comparison operation to compare a drain-source voltage with a second reference voltage and generate a second comparison result, and generates a second voltage based on the second comparison result. A control logic circuit is coupled to the second time delay circuit and generates a second logic signal based on the second voltage. The second buffer is coupled to the control logic circuit and generates a second control signal based on the second logic signal.

[0006] In some embodiments, the first time delay circuit includes a first current source, a first resistor, and a first comparator. The first current source is connected in series with the first resistor. The negative input terminal of the first comparator is coupled to a node between the first current source and the first resistor to receive a first reference voltage. The positive input terminal of the first comparator receives a second control signal. The first comparator generates a first voltage at its output terminal based on the first comparison result.

[0007] In some embodiments, the second time delay circuit includes a second current source, a second resistor, and a second comparator. The second current source is connected in series with the second resistor. The positive input of the second comparator is coupled to a node between the second current source and the second resistor to receive a second reference voltage. The negative input of the second comparator receives a drain-source voltage. The second comparator generates a second voltage at its output based on a second comparison result.

[0008] The present invention aims to provide a voltage converter comprising a first power semiconductor element, a second power semiconductor element, a first time delay circuit, a control logic circuit, and a first buffer. The first power semiconductor element has a control electrode for receiving a first control signal. The second power semiconductor element is connected in parallel to the first power semiconductor element and has a control electrode for receiving a second control signal. The safe operating area of ​​the first power semiconductor element is larger than that of the second power semiconductor element. The first time delay circuit performs a first comparison operation to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or compares the first drain-source voltage of the first power semiconductor element with the second reference voltage and generates a corresponding second comparison result, and generates a first voltage based on the first or second comparison result. The first and second reference voltages are associated with a first temperature of the first and second power semiconductor elements. The control logic circuit is coupled to the first time delay circuit and is used to generate a first logic signal based on the first voltage and a pulse width modulation signal. The first buffer is coupled to the control logic circuit and generates one of the first and second control signals based on the first logic signal.

[0009] In some embodiments, a first time delay circuit performs a first comparison operation to generate a first comparison result and generate a first voltage based on the first comparison result, and a first buffer generates a first control signal based on a first logic signal. The voltage converter further includes a second time delay circuit and a second buffer. The second time delay circuit performs a second comparison operation to compare a first drain-source voltage with a second reference voltage and generate a second comparison result, and generates a second voltage based on the second comparison result. Control logic circuitry is coupled to the second time delay circuitry and generates a second logic signal based on the second voltage and a pulse width modulation signal. The second buffer is coupled to the control logic circuitry and generates a second control signal based on the second logic signal.

[0010] In some embodiments, the first time delay circuit includes a first comparator, the negative input of which receives a first reference voltage, the positive input of which receives a second control signal, the first comparator generating a first voltage at its output based on a first comparison result, and the first reference voltage increasing as the first temperature of the first and second power semiconductor elements decreases.

[0011] In some embodiments, the second time delay circuit includes a second comparator, the positive input of which receives a second reference voltage, the negative input of which receives a first drain-source voltage, the second comparator generating a second voltage at its output based on a second comparison result, and the second reference voltage increasing with the first temperature of the first and second power semiconductor elements.

[0012] The present invention aims to provide a control method for a voltage converter, which generates a first control signal and a second control signal to be respectively applied to the control electrodes of a first power semiconductor element and a second power semiconductor element connected in parallel in the voltage converter. The safe operating area of ​​the first power semiconductor element is larger than that of the second power semiconductor element. The control method for the voltage converter includes: receiving a pulse width modulation signal; performing a first comparison operation to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or comparing the drain-source voltage of the first power semiconductor element with a second reference voltage and generating a corresponding second comparison result, wherein the first and second reference voltages are related to the temperature of the first and second power semiconductor elements; generating a first voltage based on the first comparison result or the second comparison result; generating a first logic signal based on the first voltage; and buffering the first logic signal to generate one of the first and second control signals.

[0013] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0014] A better understanding of the invention can be obtained from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of discussion.

[0015] Figure 1 This is a circuit diagram of a voltage converter according to an embodiment of the present invention;

[0016] Figure 2 This is a signal timing diagram of a voltage converter according to an embodiment of the present invention;

[0017] Figure 3This is an example circuit diagram of a control logic circuit according to an embodiment of the present invention;

[0018] Figure 4A This is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention;

[0019] Figure 4B This is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention;

[0020] Figure 5 This is a signal timing diagram of the upper bridge portion of a voltage converter during the conduction phase according to an embodiment of the present invention;

[0021] Figure 6A This is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention;

[0022] Figure 6B This is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention;

[0023] Figure 7 This is a signal timing diagram of the upper bridge portion of a voltage converter during the turn-off phase according to an embodiment of the present invention;

[0024] Figure 8 This is another illustrative circuit diagram of a time delay circuit according to an embodiment of the present invention;

[0025] Figure 9 This is another illustrative circuit diagram of a time delay circuit according to an embodiment of the present invention;

[0026] Figure 10A This is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention;

[0027] Figure 10B This is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention;

[0028] Figure 11A This is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention;

[0029] Figure 11B This is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention;

[0030] Figure 12 This is another illustrative circuit diagram of a time delay circuit according to an embodiment of the present invention;

[0031] Figure 13 This is another illustrative circuit diagram of a time delay circuit according to an embodiment of the present invention;

[0032] Figure 14This is a circuit diagram of a voltage converter according to an embodiment of the present invention. Detailed Implementation

[0033] The embodiments of the present invention will be discussed in detail below. However, it will be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific contexts. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. The terms "first," "second," etc., as used herein, do not specifically refer to any order or sequence, but are merely used to distinguish elements or operations described using the same technical terms.

[0034] Figure 1 This is a circuit diagram of a voltage converter 1 according to an embodiment of the present invention. Figure 1 In this embodiment, voltage converter 1 is a buck converter. Voltage converter 1 includes temperature sensors 122 and 162, time delay circuits 120, 140, 160 and 180, control logic circuit 220, buffer BF, power semiconductor elements NM1 to NM4, inductor L and output capacitor Cout. Power semiconductor elements NM1 and NM2 form the upper bridge portion of voltage converter 1, and power semiconductor elements NM3 and NM4 form the lower bridge portion of voltage converter 1.

[0035] Temperature sensor 122 is positioned adjacent to power semiconductor elements NM1 and NM2 to sense the temperature of power semiconductor elements NM1 and NM2 (i.e., the temperature of the upper bridge portion) and output a sensing voltage Vtemp1 corresponding to that temperature (i.e., sensing voltage Vtemp1 indicates the temperature of power semiconductor elements NM1 and NM2). In this embodiment, as the temperature of power semiconductor elements NM1 and NM2 increases, the sensing voltage Vtemp1 also increases. For example, different values ​​of the sensing voltage Vtemp1 correspond to different temperature values ​​or different temperature ranges of power semiconductor elements NM1 and NM2. Temperature sensor 162 is positioned adjacent to power semiconductor elements NM3 and NM4 to sense the temperature of power semiconductor elements NM3 and NM4 (i.e., the temperature of the lower bridge portion) and output a sensing voltage Vtemp2 corresponding to that temperature (i.e., sensing voltage Vtemp2 indicates the temperature of power semiconductor elements NM3 and NM4). In this embodiment, as the temperature of power semiconductor elements NM3 and NM4 increases, the sensing voltage Vtemp2 also increases. For example, different voltage values ​​of the sensing voltage Vtemp2 correspond to different temperature values ​​or different temperature ranges of the power semiconductor elements NM3 and NM4.

[0036] Time delay circuits 140 and 120 are coupled to temperature sensor 122 to receive a sensed voltage Vtemp1 from temperature sensor 122, and provide or generate voltages VG1 and VG2 respectively based on the sensed voltage Vtemp1. Time delay circuits 180 and 160 are coupled to temperature sensor 162 to receive a sensed voltage Vtemp2 from temperature sensor 162, and provide voltages VG3 and VG4 respectively based on the sensed voltage Vtemp2. ​​As can be seen from the above, time delay circuits 140, 120, 180, and 160 are used to provide voltages VG1, VG2, VG3, and VG4, respectively.

[0037] Control logic circuit 220 receives a pulse-width modulation (PWM) signal SPWM and is coupled to time delay circuits 120, 140, 160, and 180 to receive voltages VG1, VG2, VG3, and VG4, respectively. For example... Figure 1 As shown, the control logic circuit 220 provides or generates logic signals SG1 to SG4 based on the PWM signal SPWM and voltages VG1 to VG4. Buffers BF buffer the logic signals SG1 to SG4 respectively. Specifically, the logic signals SG1 to SG4 are each amplified in signal strength (enhanced driving capability) via buffers BF. The amplified logic signals SG1, SG2, SG3, and SG4 serve as control signals SG10, SG20, SG30, and SG40, respectively. In other words, the control signals SG10, SG20, SG30, and SG40 are obtained from the logic signals SG1, SG2, SG3, and SG4 via buffers BF (i.e., the control signals SG10, SG20, SG30, and SG4 are derived from the logic signals SG1, SG2, SG3, and SG4, respectively). The buffer BF provides control signals SG10, SG20, SG30, and SG40 to the gates (also known as control electrodes) G1, G2, G3, and G4 of power semiconductor devices NM1, NM2, NM3, and NM4, respectively, to control or determine the on / off (on / off) states of the power semiconductor devices NM1, NM2, NM3, and NM4. Figure 1 In one embodiment, temperature sensors 122 and 162, time delay circuits 120, 140, 160 and 180, buffer BF, and control logic circuit 220 constitute a drive circuit 100, used to provide or generate control signals SG10, SG20, SG30, and SG40, thereby driving power semiconductor elements NM1, NM2, NM3, and NM4, respectively. In other embodiments, the drive circuit 100 is composed of time delay circuits 120, 140, 160 and 180, buffer BF, and control logic circuit 220, and the temperature sensors 122 and 162 are disposed outside the drive circuit 100.

[0038] The PWM signal SPWM is generated by the pre-amplifier circuit ( Figure 1 (Not shown) The PWM signal SPWM can switch or convert between a high voltage level and a low voltage level. When switched or converted to a high voltage level, the PWM signal SPWM instructs the voltage converter 1 to turn on its upper bridge section (i.e., power semiconductor elements NM1 and NM2), and at this time, the upper bridge section charges the output capacitor Cout through the inductor L. When switched or converted to a low voltage level, the PWM signal SPWM instructs the voltage converter 1 to turn on its lower bridge section (i.e., power semiconductor elements NM3 and NM4), and at this time, the lower bridge section discharges the output capacitor Cout through the inductor L. Through the charging and discharging operation of the output capacitor Cout, the voltage converter 1 generates an output voltage VOUT.

[0039] In voltage converter 1, power semiconductor element NM1 is connected in parallel with power semiconductor element NM2. Therefore, power semiconductor elements NM1 and NM2 share a common drain D1 and a common source S1. In an embodiment of the present invention, the safe operating area (SOA) of power semiconductor element NM1 is larger than that of power semiconductor element NM2. Therefore, power semiconductor element NM1 has a higher withstand voltage than power semiconductor element NM2. In an embodiment of the present invention, power semiconductor elements NM1 and NM2 are metal-oxide-semiconductor field-effect transistors (MOSFETs), but the present invention is not limited thereto.

[0040] In voltage converter 1, power semiconductor element NM3 is connected in parallel with power semiconductor element NM4. Therefore, power semiconductor elements NM3 and NM4 share a common drain D3 and a common source S3. In an embodiment of the present invention, the safe operating area (SOA) of power semiconductor element NM3 is larger than that of power semiconductor element NM4. Therefore, power semiconductor element NM3 has a higher withstand voltage than power semiconductor element NM4. In an embodiment of the present invention, power semiconductor elements NM3 and NM4 are metal-oxide-semiconductor field-effect transistors (MOSFETs), but the present invention is not limited thereto. See also Figure 1 The source S1 and the drain D3 are at the same electrode point, and the source S3 is coupled to ground GND.

[0041] In a conventional voltage converter, to increase the withstand voltage, the two power semiconductor elements in the upper bridge section (and the lower bridge section, which will not be described in detail here) are connected in a cascode configuration. However, this cascode connection increases the on-resistance of the upper bridge section, resulting in poor switching efficiency. In contrast, this invention connects the two power semiconductor elements in the upper bridge section (and the lower bridge section, which will not be described in detail here) in parallel, significantly reducing the on-resistance. Therefore, compared to the conventional voltage converter described above, the voltage converter of this invention can achieve a smaller on-resistance using the same wafer area while still achieving a higher withstand voltage, thus making it suitable for higher voltage conversion applications. Because of the smaller on-resistance, the on-loss is lower, resulting in higher switching efficiency. Furthermore, it should be understood that, given the same on-resistance as the conventional voltage converter described above and the voltage converter of this invention, the voltage converter of this invention can achieve this using a smaller wafer area, resulting in higher cost-effectiveness.

[0042] Specifically, the voltage converter of the present invention connects two power semiconductor elements with different safe operating area ranges in parallel in the upper bridge section and the lower bridge section, respectively. This can achieve a larger safe operating area (SOA) range, reduce on-resistance, reduce power loss during switching and chip area usage, thereby increasing overall performance and using lower cost.

[0043] It is worth noting that, in order for voltage converter 1 to operate properly, the switching on and off of the power semiconductor elements NM1 and NM2 in the upper bridge section and the power semiconductor elements NM3 and NM4 in the lower bridge section must follow a specific sequence. This will be explained below.

[0044] Figure 2 This is a signal timing diagram of voltage converter 1 according to an embodiment of the present invention. Figure 2As shown, time periods t1, t2, and t3 represent the processes experienced by the upper bridge portion of voltage converter 1 (i.e., power semiconductor elements NM1 and NM2) during which the voltage converter 1 is to be turned on. At the beginning of time period t1, the PWM signal SPWM switches from a low voltage level to a high voltage level, indicating an intention to turn on the upper bridge portion of voltage converter 1. Simultaneously, the logic signal SG4 switches from a high voltage level to a low voltage level to turn off power semiconductor element NM4 through the corresponding buffer BF. Next, at the beginning of time period t2, the logic signal SG3 switches from a high voltage level to a low voltage level to turn off power semiconductor element NM4 through the corresponding buffer BF. Then, at the beginning of time period t3 (i.e., time point T1), the logic signal SG1 switches from a low voltage level to a high voltage level to turn on power semiconductor element NM1 through the corresponding buffer BF. Finally, at the end of time period t3 (i.e., time point T2), the logic signal SG2 switches from a low voltage level to a high voltage level to turn on power semiconductor element NM2 through the corresponding buffer BF.

[0045] Specifically, before turning on the upper bridge section of voltage converter 1, the lower bridge section of voltage converter 1 must be turned off first. In embodiments of the present invention, because the safe operating area of ​​power semiconductor element NM3 is larger than that of power semiconductor element NM4, the turn-off time of power semiconductor element NM3 must be later than that of power semiconductor element NM4. This reduces the avalanche multiplication effect of the MOSFET. Specifically, the turn-off time of power semiconductor element NM3 must be later than that of power semiconductor element NM4 to achieve the optimal turn-off time of the lower bridge section and ensure that power semiconductor elements NM3 and NM4 are within their normal operating area and will not be damaged. Therefore, as Figure 2 As shown, the power semiconductor device NM4 will be turned off at the beginning of time period t1, and then the power semiconductor device NM3 will be turned off at the beginning of time period t2.

[0046] Furthermore, to ensure the proper operation of voltage converter 1, a time delay (i.e., time period t2) is required after the lower bridge section of voltage converter 1 is turned off before the upper bridge section of voltage converter 1 can be turned on. This prevents the upper bridge section from being turned on before the lower bridge section is turned off. Therefore, as Figure 2 As shown, after the power semiconductor device NM3 is turned off at the beginning of time period t2, there will be a time delay (i.e., time period t2), and then the power semiconductor device NM1 will be turned on at the beginning of time period t3 (i.e., time point T1).

[0047] After the lower bridge section of voltage converter 1 is turned off, the upper bridge section of voltage converter 1 is then turned on. In an embodiment of the present invention, because the safe operating area (SOA) of power semiconductor element NM1 is larger than that of power semiconductor element NM2, the turn-on timing of power semiconductor element NM1 must be earlier than that of power semiconductor element NM2 to achieve the optimal turn-on timing for the upper bridge section and ensure that power semiconductor elements NM1 and NM2 are within their normal operating range without being damaged. Therefore, as Figure 2 As shown, power semiconductor device NM1 will be turned on at the beginning of time period t3, and then power semiconductor device NM2 will be turned on at the end of time period t3.

[0048] like Figure 2 As shown, time periods t4, t5, and t6 represent the processes experienced by the lower bridge section of voltage converter 1 (i.e., power semiconductor devices NM3 and NM4) during which the voltage converter is to be turned on. At the beginning of time period t4 (i.e., time point T3), the PWM signal SPWM changes from a high voltage level to a low voltage level, indicating the intention to turn on the lower bridge section of voltage converter 1 at this point. Simultaneously, the logic signal SG2 changes from a high voltage level to a low voltage level to turn off power semiconductor device NM2 through the corresponding buffer BF. Next, at the beginning of time period t5 (i.e., time point T4), the logic signal SG1 changes from a high voltage level to a low voltage level to turn off power semiconductor device NM1 through the corresponding buffer BF. Then, at the beginning of time period t6, the logic signal SG3 changes from a low voltage level to a high voltage level to turn on power semiconductor device NM3 through the corresponding buffer BF. Then, at the end of time period t6, logic signal SG4 changes from a low voltage level to a high voltage level to turn on power semiconductor element NM4 through the corresponding buffer BF.

[0049] Specifically, before turning on the lower bridge section of voltage converter 1, the upper bridge section of voltage converter 1 must be turned off first. In embodiments of the present invention, because the safe operating region of power semiconductor element NM1 is larger than that of power semiconductor element NM2, the turn-off time of power semiconductor element NM1 must be later than the turn-off time of power semiconductor element NM2. This reduces the avalanche multiplication effect of the MOSFET. Specifically, the turn-off time of power semiconductor element NM1 must be later than the turn-off time of power semiconductor element NM2 to achieve the optimal turn-off time of the upper bridge section and ensure that power semiconductor elements NM1 and NM2 are within their normal operating range. Therefore, as Figure 2 As shown, power semiconductor device NM2 will be turned off at the beginning of time period t4, and then power semiconductor device NM1 will be turned off at the beginning of time period t5.

[0050] Furthermore, to ensure the proper operation of voltage converter 1, a time delay (i.e., time period t5) is required after the upper bridge section of voltage converter 1 is turned off before the lower bridge section of voltage converter 1 can be turned on. This prevents the lower bridge section from being turned on before the upper bridge section is turned off. Therefore, as Figure 2 As shown, after the power semiconductor device NM1 is turned off at the beginning of time period t5 (i.e., time point T4), there will be a time delay (i.e., time period t5), and then the power semiconductor device NM3 will be turned on at the beginning of time period t6.

[0051] After the upper bridge portion of voltage converter 1 is turned off, the lower bridge portion of voltage converter 1 is then turned on. In an embodiment of the present invention, because the safe operating area of ​​power semiconductor element NM3 is larger than that of power semiconductor element NM4, the turn-on time of power semiconductor element NM3 must be earlier than the turn-on time of power semiconductor element NM4. This ensures that power semiconductor element NM4 is within its normal operating range when turned on, achieving the optimal turn-on time for the lower bridge portion and ensuring that power semiconductor elements NM3 and NM4 are within their normal operating range. Therefore, as Figure 2 As shown, power semiconductor device NM3 will be turned on at the beginning of time period t6, and then power semiconductor device NM4 will be turned on at the end of time period t6.

[0052] Figure 3 This is an example circuit diagram of a control logic circuit 220 according to an embodiment of the present invention. The control logic circuit 220 includes AND gates AND1 to AND4, OR gates OR1 and OR2, and delay units DL1 and DL2. The AND gate AND1 receives the PWM signal SPWM and the inverted (e.g., ...) logic signal SG3. Figure 3 As shown, logic signal SG3 is inverted by logic signal SG4 after passing through an inverter (and then received by gate AND1). One input of gate OR1 is coupled to the output of gate AND1 via delay unit DL1 (i.e., this input of gate OR1 is coupled to the output of gate AND1), and its other input receives voltage VG1, thereby causing gate OR1 to output logic signal SG1. In other words, control logic circuit 220 provides logic signal SG1 based on voltage VG1, logic signals SG3 and SG4, and PWM signal SPWM. Delay unit DL1 provides a delay time. In one embodiment, the length of the delay time provided by delay unit DL1 is equal to... Figure 2The length of time interval t2 is specified; therefore, time interval t2 can also be called the delay time. The AND gate receives the inverted PWM signal SPWM, the inverted logic signal SG1, and the inverted logic signal SG2. One input of the OR gate OR2 is coupled to the output of the AND gate AND2 via the delay unit DL2 (i.e., this input of the OR gate OR2 is coupled to the output of the AND gate AND2), and its other input receives voltage VG3, thereby causing the OR gate OR2 to output the logic signal SG3. In other words, the control logic circuit 220 provides the logic signal SG3 based on the voltage VG3, logic signals SG1 and SG2, and the PWM signal SPWM. The delay unit DL2 provides the delay time. In one embodiment, the length of the delay time provided by the delay unit DL2 is... Figure 2 The time period t5 is the length of the interval; therefore, time period t5 can also be called the delay time. Gate AND3 receives the PWM signal SPWM and voltage VG2 and outputs the logic signal SG2 accordingly (in other words, control logic circuit 220 provides the logic signal SG2 based on the PWM signal SPWM and voltage VG2). Gate AND4 receives the inverted PWM signal SPWM and voltage VG4 and outputs the logic signal SG4 accordingly (in other words, control logic circuit 220 provides the logic signal SG4 based on the PWM signal SPWM and voltage VG4).

[0053] Figure 4A This is an example circuit diagram of a temperature sensor 122 and a time delay circuit 120 according to an embodiment of the present invention. Figure 4A As shown, the time delay circuit 120 receives a sensing voltage Vtemp1 from the temperature sensor 122. The time delay circuit 120 generates a reference voltage Vds1_adj based on the sensing voltage Vtemp1, and compares the reference voltage Vds1_adj with the drain-source voltage VDS1 of the power semiconductor element NM1 (i.e., ...). Figure 1 The voltage difference between the drain D1 and the source S1 is used to generate a comparison result, and the output voltage VG2 is generated based on the comparison result.

[0054] In detail, such as Figure 4AAs shown, the time delay circuit 120 includes a current source ITH1, a resistor Rds1_adj, and a comparator CMP1. The current source ITH1 is connected in series with the resistor Rds1_adj between the system voltage VDD and ground GND. The positive input (+) of the comparator CMP1 is coupled to the node between the current source ITH1 and the resistor Rds1_adj to receive the reference voltage Vds1_adj, and its negative input (-) receives the drain-source voltage VDS1. The comparator CMP1 compares the reference voltage Vds1_adj with the drain-source voltage VDS1. When the reference voltage Vds1_adj is greater than the drain-source voltage VDS1, the comparator CMP1 outputs or generates a high-voltage voltage VG2 based on the comparison result. When the reference voltage Vds1_adj is less than the drain-source voltage VDS1, the comparator CMP1 outputs or generates a low-voltage voltage VG2 based on the comparison result.

[0055] like Figure 4A As shown, resistor Rds1_adj receives the sensed voltage Vtemp1. In Figure 4A In this embodiment, resistor Rds1_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) responsive to the sensed voltage Vtemp1. As the sensed voltage Vtemp1 increases, the resistance value of resistor Rds1_adj also increases. The current output by current source ITH1 does not change with temperature. In other words, since the sensed voltage Vtemp1 increases with the temperature of power semiconductor elements NM1 and NM2, the resistance value of resistor Rds1_adj also increases with the temperature of power semiconductor elements NM1 and NM2. Therefore, the reference voltage Vds1_adj will increase with the temperature of power semiconductor elements NM1 and NM2.

[0056] Figure 5 This is a signal timing diagram of the upper bridge portion of the voltage converter 1 according to an embodiment of the present invention during the conduction phase. The following will be used in conjunction with... Figures 1 to 4A , Figure 5 To further explain the detailed process of the upper bridge section of voltage converter 1 during the conduction phase, firstly, before time point T1, logic signals SG1 and SG2 are both at a low voltage level (e.g., Figure 2 As shown), and the control signals SG10 and SG20 generated via the buffer BF are respectively at a low voltage level (as shown). Figure 5 As shown). Figure 1 As shown, since control signals SG10 and SG20 are supplied to the gate G1 of power semiconductor device NM1 and the gate G2 of power semiconductor device NM2 respectively, this will turn off power semiconductor devices NM1 and NM2.

[0057] Then, at time point T1, logic signal SG1 changes from a low voltage level to a high voltage level (e.g., Figure 2 As shown), this will cause the control signal SG10 to also change from a low voltage level to a high voltage level (as shown). Figure 5 As shown in the figure, the high voltage level control signal SG10 will turn on the power semiconductor element NM1.

[0058] Then, after time point T1, because power semiconductor device NM1 is turned on, the drain-source voltage VDS1 of power semiconductor device NM1 will gradually decrease (e.g., Figure 5 (As shown). Furthermore, as... Figure 4A As shown, the temperatures of power semiconductor devices NM1 and NM2 gradually rise due to the conduction of power semiconductor device NM1, which causes the reference voltage Vds1_adj to gradually increase. Until time point T2, the drain-source voltage VDS1 of power semiconductor device NM1 is less than the reference voltage Vds1_adj (as shown). Figure 5 As shown), the voltage VG2 output by comparator CMP1 will change from a low voltage level to a high voltage level. According to... Figure 2 It can be seen that at time point T2, the PWM signal SPWM is at a high voltage level. Therefore, through... Figure 3 When AND3 is operated, logic signal SG2 switches to a high voltage level at time T2, which will cause control signal SG20 to also be at a high voltage level. Therefore, the high voltage level control signal SG20 will turn on power semiconductor device NM2.

[0059] Specifically, the time delay circuit 120 controls the reference voltage Vds1_adj within the safe operating range of the power semiconductor device NM2, so as to ensure that the drain-source voltage VDS1 when the power semiconductor device NM2 is turned on is also within the safe operating range of the power semiconductor device NM2. This can ensure that the power semiconductor devices NM1 and NM2 are in the normal operating range.

[0060] This invention uses a time delay circuit 120 to dynamically adjust the time delay (time period t3) between the turn-on time of power semiconductor element NM2 (i.e., time point T2) and the turn-on time of power semiconductor element NM1 (i.e., time point T1) according to the temperature of power semiconductor elements NM1 and NM2. In other words, the aforementioned time delay is not a fixed length. Specifically, the upper bridge section of the voltage converter 1 of this invention has a mechanism for automatically adjusting its turn-on delay, which dynamically adjusts its turn-on delay according to different temperatures to achieve the optimal turn-on time of the upper bridge section.

[0061] As described above, the reference voltage Vds1_adj is related to the temperature of power semiconductor devices NM1 and NM2. Specifically, the reference voltage Vds1_adj increases with the temperature of power semiconductor devices NM1 and NM2, and is controlled within the safe operating area of ​​power semiconductor device NM2. Generally, the safe operating area of ​​a power semiconductor device changes with its operating temperature and / or process variations.

[0062] Therefore, in other embodiments of the present invention (e.g.) Figure 4B In the embodiment, voltage converter 1 may be coupled to or include a memory storing a lookup table. The memory may be located within drive circuit 100, for example, within control logic circuit 220. This lookup table includes multiple different preset sensed voltage values ​​as indexes and multiple different preset reference voltage values ​​as output values. The multiple different preset sensed voltages correspond to different temperature values ​​or different temperature ranges of the power semiconductor element, while the multiple different preset reference voltages correspond to different safe operating ranges of the power semiconductor element. In the lookup table, the multiple different preset sensed voltage values ​​may each correspond to the multiple different preset reference voltage values, i.e., each corresponds to a different safe operating range; or at least two of the multiple different preset sensed voltage values ​​may correspond to the same preset reference voltage value, i.e., correspond to the same safe operating range.

[0063] See Figure 4B In some embodiments, the time delay circuit 120 includes only the comparator CMP1 and does not include... Figure 4A The current source ITH1 resistor Rds1_adj in the embodiment. The positive input (+) of the comparator CMP1 receives the reference voltage Vds1_adj, and its negative input (-) receives the drain-source voltage VDS1. The voltage converter 1 (or by the drive circuit 100 or by the control logic circuit 220) searches the lookup table of the aforementioned memory according to the value of the sensing voltage Vtemp1 generated by the temperature sensor 122 (corresponding to a preset sensing voltage value in the lookup table above) to obtain the corresponding preset reference voltage value, which is used as the reference voltage Vds1_adj. As can be seen from the above, Figure 4B The reference voltage Vds1_adj increases with the temperature of power semiconductor devices NM1 and NM2, and corresponds to the range of the safe operating area of ​​power semiconductor device NM2 at the temperatures of power semiconductor devices NM1 and NM2.

[0064] See Figure 1 , Figure 2 , Figure 4B and Figure 5 At time point T1, logic signal SG1 changes from a low voltage level to a high voltage level (e.g., Figure 2 As shown), and the control signal SG10 subsequently changes from a low voltage level to a high voltage level (as shown). Figure 5 As shown, the power semiconductor device NM1 is turned on. In response to the turn-on of the power semiconductor device NM1, the drain-source voltage VDS1 of the power semiconductor device NM1 gradually decreases (as shown). Figure 5 (As shown). Furthermore, as... Figure 4B As shown, the temperatures of power semiconductor devices NM1 and NM2 gradually rise due to the conduction of power semiconductor device NM1, which causes the reference voltage Vds1_adj to gradually increase. Until time point T2, the drain-source voltage VDS1 is less than the reference voltage Vds1_adj (as shown). Figure 5 As shown), the voltage VG2 output by comparator CMP1 will change from a low voltage level to a high voltage level. According to... Figure 2 It can be seen that at time point T2, the PWM signal SPWM is at a high voltage level. Therefore, through... Figure 3 When AND3 is activated, logic signal SG2 switches to a high voltage level at time T2. This causes control signal SG20 to also be at a high voltage level. Therefore, the high-voltage control signal SG20 turns on power semiconductor element NM2. In this way, the time delay circuit 120 can dynamically adjust the time delay (i.e., time period t3) between the turn-on time of power semiconductor element NM2 (i.e., time T2) and the turn-on time of power semiconductor element NM1 (i.e., time T1) according to the temperature of power semiconductor elements NM1 and NM2.

[0065] Figure 6A This is an example circuit diagram of a temperature sensor 122 and a time delay circuit 140 according to an embodiment of the present invention. Figure 6A As shown, the time delay circuit 140 receives a sensed voltage Vtemp1 from the temperature sensor 122 and a control signal SG20. The time delay circuit 140 generates a reference voltage Vgs2_adj based on the sensed voltage Vtemp1, compares the reference voltage Vgs2_adj with the voltage level of the control signal SG20 to generate a comparison result, and outputs a voltage VG1 based on the comparison result.

[0066] In detail, such as Figure 6AAs shown, the time delay circuit 140 includes a current source ITH2, a resistor Rgs2_adj, and a comparator CMP2. The current source ITH2 is connected in series with the resistor Rgs2_adj between the system voltage VDD and ground GND. The negative input (-) of the comparator CMP2 is coupled to the node between the current source ITH2 and the resistor Rgs2_adj to receive the reference voltage Vgs2_adj, and its positive input (+) receives the control signal SG20. The comparator CMP2 compares the voltage level of the control signal SG20 with the reference voltage Vgs2_adj. When the voltage level of the control signal SG20 is greater than the reference voltage Vgs2_adj, the comparator CMP2 outputs or generates a high voltage level VG1 based on the comparison result. When the voltage level of the control signal SG20 is less than the reference voltage Vgs2_adj, the comparator CMP2 outputs or generates a low voltage level VG1 based on the comparison result.

[0067] like Figure 6A As shown, resistor Rgs2_adj receives the sensed voltage Vtemp1. In Figure 6A In this embodiment, resistor Rgs2_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) responsive to the sensed voltage Vtemp1. As the sensed voltage Vtemp1 decreases, the resistance of resistor Rgs2_adj increases. The current output by current source ITH2 does not change with temperature. In other words, since the sensed voltage Vtemp1 decreases as the temperature of power semiconductor elements NM1 and NM2 decreases, the resistance of resistor Rgs2_adj also increases as the temperature of power semiconductor elements NM1 and NM2 decreases. Consequently, the reference voltage Vgs2_adj will increase as the temperature of power semiconductor elements NM1 and NM2 decreases.

[0068] Figure 7 This is a signal timing diagram of the upper bridge portion of the voltage converter 1 according to an embodiment of the present invention during the turn-off phase. The following will be used in conjunction with... Figures 1 to 3 , Figure 6A and Figure 7 To further explain the detailed process of the upper bridge section of voltage converter 1 during the turn-off phase, firstly, before time point T3, logic signals SG1 and SG2 are both at a high voltage level (e.g., Figure 2 As shown), and the control signals SG10 and SG20 generated via the buffer BF are respectively at a high voltage level (as shown). Figure 7 As shown). Figure 1 As shown, since control signals SG10 and SG20 are supplied to the gate G1 of power semiconductor device NM1 and the gate G2 of power semiconductor device NM2 respectively, this will turn on power semiconductor devices NM1 and NM2.

[0069] Then, at time point T3, the logic signal SG2 changes from a high voltage level to a low voltage level (e.g., Figure 2 As shown), this will cause the control signal SG20 to gradually decrease from a high voltage level to a low voltage level (as shown). Figure 7 As shown in the figure, the control signal SG20 will gradually turn off the power semiconductor element NM2.

[0070] Furthermore, after time point T3, as power semiconductor element NM2 gradually turns off, the temperatures of power semiconductor elements NM1 and NM2 gradually decrease due to the gradual turn-off of power semiconductor element NM2, which causes the reference voltage Vgs2_adj to gradually increase. Until time point T4, the voltage level of control signal SG20 is lower than the reference voltage Vgs2_adj (e.g., ...). Figure 7 As shown), the voltage VG1 output by comparator CMP2 will change from a high voltage level to a low voltage level. According to... Figure 2 It can be seen that at time point T4, the PWM signal SPWM is at a low voltage level. Therefore, through... Figure 3 The operation of AND1 and OR1 will cause the logic signal SG1 to switch from a high voltage level to a low voltage level at time T4. This will cause the control signal SG10 to gradually decrease from a high voltage level to a low voltage level (e.g., Figure 7 As shown in the figure, the control signal SG10 will gradually turn off the power semiconductor element NM1.

[0071] Specifically, the time delay circuit 140 controls the reference voltage Vgs2_adj within the off-operation range of the power semiconductor element NM2. Furthermore, by dynamically adjusting the turn-off delay of the power semiconductor element NM1, it ensures that the power semiconductor element NM2 is indeed turned off before turning off the power semiconductor element NM1. In this way, both power semiconductor elements NM1 and NM2 can remain within their normal operating range without being damaged.

[0072] This invention uses a time delay circuit 140 to dynamically adjust the time delay (time period t4) between the turn-off point of power semiconductor element NM1 (i.e., time point T4) and the turn-off point of power semiconductor element NM2 (i.e., time point T3) according to the temperature of power semiconductor elements NM1 and NM2. In other words, the aforementioned time delay is not a fixed length. Specifically, the upper bridge section of the voltage converter 1 of this invention has a mechanism for automatically adjusting its turn-off delay, which dynamically adjusts its turn-off delay according to different temperatures to achieve the optimal turn-off point for the upper bridge section.

[0073] As described above, the reference voltage Vgs2_adj is generated by the current source ITH2 and resistor Rgs2_adj based on the sensed voltage Vtemp1, and is related to the temperature of power semiconductor devices NM1 and NM2. Specifically, the reference voltage Vgs2_adj increases as the temperature of power semiconductor devices NM1 and NM2 decreases. In other embodiments, the reference voltage Vgs2_adj represents the threshold voltage (Vth) of power semiconductor device NM2. Generally, the threshold voltage of a power semiconductor device changes with its operating temperature and / or process variations.

[0074] In other embodiments of the invention, the voltage converter 1 may be coupled to or include a memory storing a lookup table. The memory may be located within the drive circuit 100, for example, within the control logic circuit 220. This lookup table includes multiple different preset sensed voltage values ​​as indexes and multiple different preset reference voltage values ​​as output values. The multiple different preset sensed voltages correspond to different temperature values ​​or different temperature ranges of the power semiconductor element, while the multiple different preset reference voltages correspond to different threshold voltages of the power semiconductor element. In the lookup table, the multiple different preset sensed voltage values ​​may each correspond to the multiple different preset reference voltage values, i.e., each corresponds to a different threshold voltage; or at least two of the multiple different preset sensed voltage values ​​may correspond to the same preset reference voltage value, i.e., the same threshold voltage.

[0075] See Figure 6B In some embodiments, the time delay circuit 140 includes only the comparator CMP2 and does not include... Figure 6A The current source ITH2 resistor Rgs2_adj in the embodiment. The positive input (+) of comparator CMP1 receives the control signal SG20, and its negative input (-) receives the reference voltage Vgs2_adj. Voltage converter 1 (or by drive circuit 100 or by control logic circuit 220) searches the lookup table of the aforementioned memory according to the value of the sensing voltage Vtemp1 generated by temperature sensor 122 (corresponding to a preset sensing voltage value in the lookup table above) to obtain the corresponding preset reference voltage value, which is used as the reference voltage Vgs2_adj. As can be seen from the above, Figure 6B The reference voltage Vgs2_adj increases as the temperature of power semiconductor elements NM1 and NM2 decreases, and corresponds to the threshold voltage of power semiconductor element NM2 at the temperatures of power semiconductor elements NM1 and NM2.

[0076] See Figure 1 , Figure 2 , Figure 6B and Figure 7At time point T1, and at time point T3, logic signal SG2 changes from a high voltage level to a low voltage level (e.g., Figure 2 As shown), and the control signal SG20 also gradually decreases from the high voltage level to the low voltage level (as shown). Figure 7 As shown, power semiconductor element NM2 is gradually turned off. In response to the gradual turn-off of power semiconductor element NM2, the temperatures of power semiconductor elements NM1 and NM2 gradually decrease, causing the reference voltage Vgs2_adj to gradually increase. Until time point T4, the control signal SG20 is less than the reference voltage Vgs2_adj (as shown). Figure 7 As shown), the voltage VG1 output by comparator CMP2 will change from a high voltage level to a low voltage level. According to... Figure 2 It can be seen that at time point T4, the PWM signal SPWM is at a low voltage level. Therefore, through... Figure 3 The operation of AND1 and OR1 will cause the logic signal SG1 to switch from a high voltage level to a low voltage level at time T4. This will cause the control signal SG10 to gradually decrease from a high voltage level to a low voltage level (e.g., Figure 7 As shown), the control signal SG10 will gradually turn off the power semiconductor element NM1. In this way, the time delay circuit 140 can dynamically adjust the time delay (i.e., time period t4) between the turn-off time of power semiconductor element NM1 (i.e., time point T4) and the turn-off time of power semiconductor element NM2 (i.e., time point T3) according to the temperature of power semiconductor elements NM1 and NM2.

[0077] Figure 8 This is another example circuit diagram of a time delay circuit 120 according to an embodiment of the present invention. Figure 8 Time delay circuit 120 and Figure 4A The time delay circuit 120 is similar, the difference is that... Figure 4A The current source ITH1 of the time delay circuit 120 is connected to the resistor Rds1_adj. Figure 8 The time delay circuit 120 is replaced by a current source ITH1_adj and a resistor Rds1. Specifically, Figure 8 The time delay circuit 120 has the same characteristics as... Figure 4A The time delay circuit 120 has a similar function, therefore in Figure 1 The time delay circuit 120 of the illustrated embodiment can also be used Figure 8 The time delay circuit 120 is used to achieve this.

[0078] In detail, such as Figure 8As shown, the current source ITH1_adj is connected in series with the resistor Rds1 between the system voltage VDD and ground GND, and the current source ITH1_adj receives the sensed voltage Vtemp1. Figure 8 In this embodiment, the current source ITH1_adj is a voltage-controlled element (i.e., a voltage-controlled current source) that responds to the sensed voltage Vtemp1. As the sensed voltage Vtemp1 increases, the current from the current source ITH1_adj also increases. The resistance value of resistor Rds1 does not change with temperature. In other words, since the sensed voltage Vtemp1 increases with the temperature of power semiconductor elements NM1 and NM2, the current output by the current source ITH1_adj also increases with the temperature of power semiconductor elements NM1 and NM2. Consequently, the reference voltage Vds1_adj will increase with the temperature of power semiconductor elements NM1 and NM2.

[0079] Figure 9 This is another example circuit diagram of a time delay circuit 140 according to an embodiment of the present invention. Figure 9 Time delay circuit 140 and Figure 6A The time delay circuit 140 is similar, the difference is that... Figure 6A The current source ITH2 of the time delay circuit 140 is connected to the resistor Rgs2_adj. Figure 9 The time delay circuit 140 is replaced by a current source ITH2_adj and a resistor Rgs2. Specifically, Figure 9 The time delay circuit 140 has the same characteristics as... Figure 6A The time delay circuit 140 has a similar function, therefore in Figure 1 The time delay circuit 140 of the illustrated embodiment can also be used Figure 9 The time delay circuit 140 is used to implement this.

[0080] In detail, such as Figure 9 As shown, the current source ITH2_adj is connected in series with a coupling resistor Rgs2 between the system voltage VDD and ground GND, and the current source ITH2_adj receives the sensed voltage Vtemp1. Figure 9In this embodiment, the current source ITH2_adj is a voltage-controlled element (i.e., a voltage-controlled current source) that responds to the sensed voltage Vtemp1. When the sensed voltage Vtemp1 decreases, the current from the current source ITH2_adj increases accordingly. The resistance value of resistor Rgs2 does not change with temperature. In other words, since the sensed voltage Vtemp1 decreases as the temperature of power semiconductor elements NM1 and NM2 decreases, the current output by the current source ITH2_adj also increases as the temperature of power semiconductor elements NM1 and NM2 decreases. Consequently, the reference voltage Vgs2_adj will increase as the temperature of power semiconductor elements NM1 and NM2 decreases.

[0081] Figure 10A This is an example circuit diagram of a temperature sensor 162 and a time delay circuit 160 according to an embodiment of the present invention. Figure 10A As shown, the time delay circuit 160 receives the sensed voltage Vtemp2 from the temperature sensor 162. The time delay circuit 160 generates a reference voltage Vds3_adj based on the sensed voltage Vtemp2, and compares the reference voltage Vds3_adj with the drain-source voltage VDS3 of the power semiconductor element NM3 (i.e., ...). Figure 1 The voltage difference between the drain D3 and the source S3 is used to generate a comparison result, and the output voltage VG4 is based on the comparison result.

[0082] In detail, such as Figure 10A As shown, the time delay circuit 160 includes a current source ITH3, a resistor Rds3_adj, and a comparator CMP3. The current source ITH3 is connected in series with the resistor Rds3_adj between the system voltage VDD and ground GND. The positive input (+) of the comparator CMP3 is coupled to the node between the current source ITH3 and the resistor Rds3_adj to receive the reference voltage Vds3_adj, and its negative input (-) receives the drain-source voltage VDS3 of the power semiconductor element NM3. The comparator CMP3 compares the reference voltage Vds3_adj with the drain-source voltage VDS3. When the reference voltage Vds3_adj is greater than the drain-source voltage VDS3, the comparator CMP3 outputs a high-voltage level VG4 at its output terminal based on the comparison result. When the reference voltage Vds3_adj is less than the drain-source voltage VDS3, the comparator CMP3 outputs or generates a low voltage level VG4 at its output terminal based on the comparison result.

[0083] like Figure 10A As shown, resistor Rds3_adj receives the sensed voltage Vtemp2. ​​In Figure 10AIn this embodiment, resistor Rds3_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) responsive to the sensed voltage Vtemp2. ​​As the sensed voltage Vtemp2 increases, the resistance value of resistor Rds3_adj increases accordingly. The current output by current source ITH3 does not change with temperature. In other words, since the sensed voltage Vtemp2 increases with the temperature of power semiconductor elements NM3 and NM4, the resistance value of resistor Rds3_adj also increases with the temperature of power semiconductor elements NM3 and NM4. Therefore, the reference voltage Vds3_adj will increase with the temperature of power semiconductor elements NM3 and NM4. The operation of time delay circuit 160 is logically similar to... Figure 4A The operation of the time delay circuit 120 is described in detail here, but the specific operation instructions are omitted.

[0084] As described above, the reference voltage Vds3_adj is related to the temperature of power semiconductor devices NM3 and NM4. Specifically, the reference voltage Vds3_adj increases with the temperature of power semiconductor devices NM3 and NM4, and is controlled within the safe operating area of ​​power semiconductor device NM2. Generally, the safe operating area of ​​a power semiconductor device changes with its operating temperature and / or process variations.

[0085] Therefore, in other embodiments of the present invention (e.g.) Figure 10B In the embodiment, voltage converter 1 may be coupled to or include a memory that stores a lookup table. The memory may be located within drive circuit 100, for example, within control logic circuit 220. This lookup table includes multiple different preset sensed voltage values ​​as indexes and multiple different preset reference voltage values ​​as output values. The multiple different preset sensed voltages correspond to different temperature values ​​or different temperature ranges of the power semiconductor element, while the multiple different preset reference voltages correspond to different safe operating ranges of the power semiconductor element.

[0086] See Figure 10B In some embodiments, the time delay circuit 160 includes only the comparator CMP3 and does not include... Figure 10A The current source ITH3 resistor Rds3_adj in this embodiment. The positive input (+) of the comparator CMP3 receives the reference voltage Vds3_adj, and its negative input (-) receives the drain-source voltage VDS3. The voltage converter 1 (or by the drive circuit 100 or by the control logic circuit 220) searches the aforementioned memory lookup table according to the value of the sensing voltage Vtemp2 generated by the temperature sensor 162 (corresponding to a preset sensing voltage value in the lookup table above) to obtain the corresponding preset reference voltage value, which is used as the reference voltage Vds3_adj. Figure 10B The reference voltage Vds3_adj increases with the temperature of power semiconductor devices NM3 and NM4, and corresponds to the range of the safe operating area of ​​power semiconductor device NM4 at the temperatures of power semiconductor devices NM3 and NM4. Figure 10B The operation of the time delay circuit 160 is logically similar to Figure 4B The operation of the time delay circuit 120 is described in detail here, but the specific instructions are omitted. Figure 10B In one embodiment, the time delay circuit 160 can dynamically adjust the time delay (i.e., time period t6) between the turn-on time of the power semiconductor element NM4 and the turn-on time of the power semiconductor element NM3 according to the temperature of the power semiconductor elements NM3 and NM4.

[0087] In some embodiments, when simultaneously employing Figure 4B and Figure 10B In some embodiments, voltage converter 1 may be coupled to or include a memory that stores lookup tables for obtaining reference voltages Vds1_adj and Vds3_adj.

[0088] Figure 11A This is an example circuit diagram of a temperature sensor 162 and a time delay circuit 180 according to an embodiment of the present invention. Figure 11A As shown, the time delay circuit 180 receives the sensed voltage Vtemp2 from the temperature sensor 162. The time delay circuit 180 generates a reference voltage Vgs4_adj based on the sensed voltage Vtemp2, and compares the reference voltage Vgs4_adj with the voltage level of the control signal SG40 to generate a comparison result, and outputs a voltage VG3 based on the comparison result.

[0089] In detail, such as Figure 11A As shown, the time delay circuit 180 includes a current source ITH4, a resistor Rgs4_adj, and a comparator CMP4. The current source ITH4 is connected in series with the resistor Rgs4_adj between the system voltage VDD and ground GND. The negative input (-) of the comparator CMP4 is coupled to the node between the current source ITH4 and the resistor Rgs4_adj to receive the reference voltage Vgs4_adj, and its positive input (+) also receives the reference voltage Vgs4_adj. The comparator CMP4 compares the voltage level of the control signal SG40 with the reference voltage Vgs4_adj. When the voltage level of the control signal SG40 is greater than the reference voltage Vgs4_adj, the comparator CMP4 outputs or generates a high voltage level VG3 based on the comparison result. When the voltage level of the control signal SG40 is less than the reference voltage Vgs4_adj, the comparator CMP4 outputs or generates a low voltage level VG3 based on the comparison result.

[0090] like Figure 11A As shown, resistor Rgs4_adj receives the sensed voltage Vtemp2. ​​In Figure 11A In this embodiment, resistor Rgs4_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) responsive to the sensed voltage Vtemp2. ​​As the sensed voltage Vtemp2 decreases, the resistance of resistor Rgs4_adj increases. Furthermore, the current output by current source ITH4 does not change with temperature. In other words, since the sensed voltage Vtemp2 decreases as the temperature of power semiconductor elements NM3 and NM4 decreases, the resistance of resistor Rgs4_adj also increases as the temperature of power semiconductor elements NM3 and NM4 decreases. Therefore, the reference voltage Vgs4_adj will increase as the temperature of power semiconductor elements NM3 and NM4 decreases. The operation of time delay circuit 180 is logically similar to... Figure 6A The operation of the time delay circuit 140 is described in detail here, but the specific operation instructions are omitted.

[0091] As described above, the reference voltage Vgs4_adj is generated by the current source ITH4 and resistor Rgs4_adj based on the sensed voltage Vtemp2, and is related to the temperature of power semiconductor devices NM3 and NM4. Specifically, the reference voltage Vgs4_adj increases as the temperature of power semiconductor devices NM3 and NM4 decreases. In other embodiments, the reference voltage Vgs4_adj represents the threshold voltage of power semiconductor device NM4. Generally, the threshold voltage of a power semiconductor device changes with its operating temperature and / or process variations.

[0092] In other embodiments of the invention, the voltage converter 1 may be coupled to or include a memory storing a lookup table. The aforementioned memory may be located within the drive circuit 100, for example, within the control logic circuit 220. This lookup table includes a plurality of different preset sensed voltage values ​​as indexes and a plurality of different preset reference voltage values ​​as output values. The aforementioned plurality of different preset sensed voltages correspond to different temperature values ​​or different temperature ranges of the power semiconductor element, while the aforementioned plurality of different preset reference voltages correspond to different threshold voltages of the aforementioned power semiconductor element.

[0093] See Figure 11B In some embodiments, the time delay circuit 180 includes only the comparator CMP4 and does not include... Figure 11AThe current source ITH4 resistor Rgs4_adj in the embodiment. The positive input (+) of the comparator CMP4 receives the control signal SG40, and its negative input (-) receives the reference voltage Vgs4_adj. The voltage converter 1 (or by the drive circuit 100 or by the control logic circuit 220) searches the lookup table of the aforementioned memory according to the value of the sensing voltage Vtemp2 generated by the temperature sensor 162 (corresponding to a preset sensing voltage value in the lookup table above) to obtain the corresponding preset reference voltage value, which is used as the reference voltage Vgs4_adj. As can be seen from the above, Figure 11B The reference voltage Vgs4_adj increases as the temperature of power semiconductor devices NM3 and NM4 decreases, and corresponds to the threshold voltage of power semiconductor device NM4 at the temperature of power semiconductor devices NM3 and NM4. Figure 11B The operation of the time delay circuit 180 is logically similar to Figure 6B The operation of the time delay circuit 140 is described in detail here, but the specific instructions are omitted. Figure 11B In one embodiment, the time delay circuit 180 can dynamically adjust the time delay (i.e., time period t1) between the turn-off time of power semiconductor element NM3 and the turn-off time of power semiconductor element NM4 according to the temperature of power semiconductor elements NM3 and NM4.

[0094] In some embodiments, when simultaneously employing Figure 6B and Figure 11B In some embodiments, voltage converter 1 may be coupled to or include a memory that stores lookup tables for obtaining reference voltages Vgs2_adj and Vgs4_adj.

[0095] In other embodiments, when simultaneously employing Figure 4B , Figure 6B , Figure 10B and Figure 11B In one embodiment, the voltage converter 1 may be coupled to or include a memory storing two lookup tables, one for obtaining reference voltages Vds1_adj and Vds3_adj, and the other for obtaining reference voltages Vgs2_adj and Vgs4_adj. Simultaneously employing... Figure 4B , Figure 6B , Figure 10B and Figure 11B In the case of the embodiment, time periods t1, t3, t4, and t6 can be shortened, and can be omitted. Figure 3 The delay units DL1 and DL2 are used to improve the operating efficiency of voltage converter 1. (The remaining text is omitted.) Figure 3 In the case of delayers DL1 and DL2, the input of OR1 is directly coupled to the output of AND1, and the input of OR2 is directly coupled to the output of AND2.

[0096] Figure 12 This is another example circuit diagram of a time delay circuit 160 according to an embodiment of the present invention. Figure 12 Time delay circuit 160 and Figure 10A The time delay circuit 160 is similar, the difference is that... Figure 10A The time delay circuit 160's current source ITH3 and resistor Rds3_adj are in Figure 12 The time delay circuit 160 is replaced by a current source ITH3_adj and a resistor Rds3. Specifically, Figure 12 The time delay circuit 160 has the same characteristics as... Figure 10A The time delay circuit 160 has a similar function, therefore in Figure 1 The time delay circuit 160 of the illustrated embodiment can also be used Figure 12 The time delay circuit 160 is used to implement this.

[0097] In detail, such as Figure 12 As shown, the current source ITH3_adj is connected in series with the coupling resistor Rds3 between the system voltage VDD and ground GND, and the current source ITH3_adj receives the sensed voltage Vtemp2. Figure 12 In this embodiment, the current source ITH3_adj is a voltage-controlled element (i.e., a voltage-controlled current source) that responds to the sensed voltage Vtemp2. ​​As the sensed voltage Vtemp2 increases, the current from the current source ITH3_adj also increases. The resistance value of resistor Rds3 does not change with temperature. In other words, since the sensed voltage Vtemp2 increases with the temperature of power semiconductor elements NM3 and NM4, the current output by the current source ITH3_adj also increases with the temperature of power semiconductor elements NM3 and NM4. Consequently, the reference voltage Vds3_adj will increase with the temperature of power semiconductor elements NM3 and NM4.

[0098] Figure 13 This is another example circuit diagram of a time delay circuit 180 according to an embodiment of the present invention. Figure 13 Time delay circuit 180 and Figure 11A The time delay circuit is similar to 180, the difference is that... Figure 11A The time delay circuit 180's current source ITH4 and resistor Rgs4_adj are in Figure 13 The time delay circuit 180 is replaced by a current source ITH4_adj and a resistor Rgs4. Specifically, Figure 13 The time delay circuit 180 has the same characteristics as... Figure 11A The time delay circuit 180 has a similar function, therefore in Figure 1 The time delay circuit 180 of the illustrated embodiment can also be used Figure 13 The time delay circuit 180 is used to implement this.

[0099] In detail, such as Figure 13 As shown, the current source ITH4_adj is connected in series with the coupling resistor Rgs4 between the system voltage VDD and ground GND, and the current source ITH4_adj receives the sensed voltage Vtemp2. Figure 13 In this embodiment, the current source ITH4_adj is a voltage-controlled element (i.e., a voltage-controlled current source) that responds to the sensed voltage Vtemp2. ​​When the sensed voltage Vtemp2 decreases, the current from the current source ITH4_adj increases accordingly. The resistance value of resistor Rgs4 does not change with temperature. In other words, since the sensed voltage Vtemp2 decreases as the temperature of power semiconductor elements NM3 and NM4 decreases, the current output by the current source ITH4_adj also increases as the temperature of power semiconductor elements NM3 and NM4 decreases. Consequently, the reference voltage Vgs4_adj will increase as the temperature of power semiconductor elements NM3 and NM4 decreases.

[0100] The following will be coordinated Figures 1 to 4A , Figure 6A , Figure 10A , Figure 11A This section details the process of voltage converter 1 at various stages. Before the start of time period t1, logic signals SG1 and SG2 are at low voltage levels. At the start of time period t1, the PWM signal SPWM changes from a low voltage level to a high voltage level, indicating an intention to turn on the upper bridge portion of voltage converter 1 (i.e., power semiconductor elements NM1 and NM2). Therefore, the lower bridge portion of voltage converter 1 (i.e., power semiconductor elements NM3 and NM4) must be turned off first. Furthermore, because the safe operating area of ​​power semiconductor element NM3 is larger than that of power semiconductor element NM4, the turn-off time of power semiconductor element NM3 must be later than that of power semiconductor element NM4. Figure 3 As can be seen, at this time, the inverted PWM signal SPWM received by the gate AND4 changes from a high voltage level to a low voltage level. Therefore, the logic signal SG4 output by the gate AND4 will change from a high voltage level to a low voltage level.

[0101] As described above, at the beginning of time period t1, the logic signal SG4 transitions from a high voltage level to a low voltage level. This causes the control signal SG40 to gradually decrease from a high voltage level to a low voltage level during time period t1, thus gradually turning off the power semiconductor device NM4. As power semiconductor device NM4 gradually turns off, the temperature of power semiconductor devices NM3 and NM4 gradually decreases, causing the reference voltage Vgs4_adj to gradually increase. Until the end of time period t1, the control signal SG40 is lower than the reference voltage Vgs4_adj. Figure 11A The voltage VG3 output by comparator CMP4 in the time delay circuit 180 will change from a high voltage level to a low voltage level. According to... Figure 2 It can be seen that at the end of time period t1, the PWM signal SPWM is at a high voltage level, therefore according to Figure 3 The operation of AND2, DL2, and OR2 gates causes the logic signal SG3 to change from a high voltage level to a low voltage level. This causes the control signal SG30 to gradually decrease from a high voltage level to a low voltage level. Therefore, the control signal SG30 will gradually turn off the power semiconductor device NM3.

[0102] As described above, at the beginning of time period t2 (i.e., the end of time period t1), logic signal SG3 transitions from a high voltage level to a low voltage level. During time period t2, based on the operation of time delay circuit 140, output voltage VG1 is at a low voltage level, which makes OR gate OR1 dependent on the output signal of AND gate AND1. Figure 3 The operation of AND1 and OR1 involves logic signal SG3 transitioning to a low voltage level, and logic signal SG1 transitioning from a low voltage level to a high voltage level at the end of time period t2, thereby turning on power semiconductor device NM1. It is worth noting that delay circuit DL1 is coupled between AND1 and OR1 (i.e., the input of OR1 is coupled to the output of AND1 via delay circuit DL1). Therefore, after AND1's output signal transitions from a low voltage level to a high voltage level in response to logic signal SG3 transitioning from a high voltage level to a low voltage level, time period t2 (i.e., the delay time of delay circuit DL1) is required before logic signal SG1 transitions from a low voltage level to a high voltage level.

[0103] Next, during time period t3, because power semiconductor device NM1 is turned on, the drain-source voltage VDS1 of power semiconductor device NM1 will gradually decrease, and the temperature of power semiconductor devices NM1 and NM2 will rise. This will cause the reference voltage Vds1_adj to gradually increase until the end of time period t3 (time point T2), when the drain-source voltage VDS1 of power semiconductor device NM1 is less than the reference voltage Vds1_adj. Figure 4A The voltage VG2 output by comparator CMP1 in the time delay circuit 120 will change from a low voltage level to a high voltage level. Therefore, through... Figure 3 During the operation of AND3, at the end of time period t3, logic signal SG2 will change from a low voltage level to a high voltage level, thereby turning on power semiconductor device NM2.

[0104] Next, at the beginning of time period t4, the PWM signal SPWM changes from a high voltage level to a low voltage level, indicating an intention to turn on the lower bridge section of voltage converter 1 (i.e., power semiconductor devices NM3 and NM4). Therefore, the upper bridge section of voltage converter 1 (i.e., power semiconductor devices NM1 and NM2) must be turned off first. Furthermore, because the safe operating area of ​​power semiconductor device NM1 is larger than that of power semiconductor device NM2, the turn-off time of power semiconductor device NM1 must be later than that of power semiconductor device NM2. Figure 3 As can be seen, at this time, the PWM signal SPWM received by the gate AND3 changes from a high voltage level to a low voltage level. Therefore, the logic signal SG2 output by the gate AND3 will change from a high voltage level to a low voltage level.

[0105] As described above, at the beginning of time period t4 (i.e., time point T3), the logic signal SG2 transitions from a high voltage level to a low voltage level. This causes the control signal SG20 to gradually decrease from a high voltage level to a low voltage level during time period t4. Therefore, the control signal SG20 gradually turns off the power semiconductor element NM2. As the power semiconductor element NM2 gradually turns off, the temperatures of the power semiconductor elements NM1 and NM2 gradually decrease, causing the reference voltage Vgs2_adj to gradually increase. Until the end of time period t4 (i.e., time point T4), the control signal SG20 is lower than the reference voltage Vgs2_adj. Figure 6A The voltage VG1 output by comparator CMP2 of time delay circuit 140 will change from a high voltage level to a low voltage level. According to... Figure 2 It can be seen that at the end of time period t4, the PWM signal SPWM is at a low voltage level, therefore... Figure 3When the AND gate AND1 and OR gate OR1 are operated, the logic signal SG1 will change from a high voltage level to a low voltage level. This will cause the control signal SG10 to gradually decrease from a high voltage level to a low voltage level. Therefore, the control signal SG10 will gradually turn off the power semiconductor device NM1.

[0106] As described above, at the beginning of time period t5 (i.e., time point T4), logic signal SG1 transitions from a high voltage level to a low voltage level. During time period t5, based on the operation of time delay circuit 180, output voltage VG3 is at a low voltage level, which makes OR gate OR2 dependent on the output signal of AND gate AND2. Figure 3 The operation of AND2 and OR2 causes logic signal SG3 to transition from a low voltage level to a high voltage level at the end of time period t5, thereby turning on power semiconductor device NM3. It is worth noting that delay circuit DL2 is coupled between AND2 and OR2 (i.e., the input of OR2 is coupled to the output of AND2 via delay circuit DL2). Therefore, after AND2's output signal transitions from a low voltage level to a high voltage level in response to logic signal SG1's transition from a high voltage level to a low voltage level, time period t5 (i.e., the delay time of delay circuit DL2) is required before logic signal SG3 transitions from a low voltage level to a high voltage level.

[0107] Next, during time period t6, because power semiconductor device NM3 is turned on, the drain-source voltage VDS3 of power semiconductor device NM3 will gradually decrease, and the temperature of power semiconductor devices NM3 and NM4 will rise. This will cause the reference voltage Vds3_adj to gradually increase until the end of time period t6, when the drain-source voltage VDS3 of power semiconductor device NM3 is less than the reference voltage Vds3_adj. Figure 10A The voltage VG4 output by comparator CMP3 in the time delay circuit 160 will change from a low voltage level to a high voltage level. Therefore, through... Figure 3 During the operation of AND4, at the end of time period t6, logic signal SG4 will change from a low voltage level to a high voltage level, thereby turning on power semiconductor device NM4.

[0108] Figure 14 This is a circuit diagram of a voltage converter 14 according to an embodiment of the present invention. The voltage converter 14 and... Figure 1 The voltage converter shown is similar to 1, except that voltage converter 14 is a boost converter.

[0109] See Figure 14When the PWM signal SPWM is at a low voltage level, the voltage converter 14 turns on its lower bridge section (i.e., power semiconductor elements NM3 and NM4), and the current from the system voltage VDD flows through the inductor L to store energy. When the PWM signal SPWM is at a high voltage level, the voltage converter 14 turns on its upper bridge section (i.e., power semiconductor elements NM1 and NM2), and the current flowing through the inductor L charges the output capacitor Cout, thereby enabling the voltage converter 14 to output voltage VOUT.

[0110] The signal timing diagram of voltage converter 14 is also as follows Figure 2 As shown, the example circuit diagram of the control logic circuit 220 of the voltage converter 14 is also as follows. Figure 3 As shown, its operation process will not be described in detail here.

[0111] According to the above embodiments, in the control method of the voltage converter of the present invention, the control logic circuit 220 receives the PWM signal SPWM and uses the PWM signal SPWM as the base signal to control the operation of the upper bridge section and the lower bridge section of the voltage converter 1. The control method of this invention will be described below using the control of the upper bridge section as an example.

[0112] According to the control method of the present invention, a comparison operation is performed by the time delay circuit 140 to compare the voltage level of the control signal SG20 with the reference voltage Vgs2_adj and generate a corresponding comparison result, and the time delay circuit 140 generates voltage VG1 based on this comparison result. Furthermore, another comparison operation is performed by the time delay circuit 120 to compare the drain-source voltage VDS1 of the power semiconductor element NM1 with the reference voltage Vds1_adj and generate a corresponding comparison result, and the time delay circuit 120 generates voltage VG2 based on this comparison result. In embodiments of the present invention, both the reference voltage Vgs2_adj and Vds1_adj are related to the temperature of the power semiconductor elements NM1 and NM2. The control logic circuit 220 generates logic signal SG1 based on voltage VG1 and PWM signal SPWM, and logic signal SG2 based on voltage VG2 and PWM signal SPWM. The logic signals SG1 and SG2 are buffered by two buffers respectively to generate control signals SG10 and SG20. Control signals SG10 and SG20 are provided to the gates (control electrodes) of power semiconductor devices NM1 and NM2, respectively, to control their turn-on / turn-off timing.

[0113] The foregoing has outlined the features of several embodiments, thus enabling those skilled in the art to better understand the nature of the invention. Those skilled in the art will recognize that this invention can be readily used as a basis to design or modify other processes and structures, thereby achieving the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

[0114] [Symbol Explanation]

[0115] 1,14: Voltage converter

[0116] 100: Drive circuit

[0117] 120, 140, 160, 180: Time delay circuits

[0118] 122, 162: Temperature sensor

[0119] 220: Control logic circuit

[0120] AND1, AND2, AND3, AND4: and gate

[0121] BF: Buffer

[0122] CMP1, CMP2, CMP3, CMP4: Comparators

[0123] Cout: Output capacitor

[0124] D1, D3: Drain electrode

[0125] DL1, DL2: Delay units

[0126] G1, G2, G3, G4: Gate

[0127] GND: Grounding

[0128] ITH1, ITH1_adj, ITH2, ITH2_adj, ITH3, ITH3_adj, ITH4, ITH4_adj: Current sources

[0129] L: Inductance

[0130] NM1, NM2, NM3, NM4: Power semiconductor devices

[0131] OR1, OR2: OR gate

[0132] Rds1, Rds3, Rds1_adj, Rds3_adj, Rgs2, Rgs4, Rgs2_adj, Rgs4_adj: Resistance

[0133] S1, S3: Source poles

[0134] SG1, SG2, SG3, SG4: Logic signals

[0135] SG10, SG20, SG30, SG40: Control signals

[0136] SPWM: Pulse Width Modulation (PWM) signal

[0137] T1, T2, T3, T4: Time points

[0138] t1, t2, t3, t4, t5, t6: Time periods

[0139] VDD: System voltage

[0140] VDS1, VDS3: Drain-Source Voltages

[0141] Vds1_adj, Vds3_adj, Vgs2_adj, Vgs4_adj: Reference voltages

[0142] VG1, VG2, VG3, VG4: Voltage

[0143] VOUT: Output voltage

[0144] Vtemp1, Vtemp2: Sensing voltages.

Claims

1. A driving circuit, characterized in that, The driving circuit is used to generate a first control signal and a second control signal, and to respectively feed the first and second control signals to the control electrodes of a first power semiconductor element and a second power semiconductor element connected in parallel in the voltage converter. The safe operating area of ​​the first power semiconductor element is larger than the safe operating area of ​​the second power semiconductor element. A first time delay circuit performs a first comparison operation to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or compares the drain-source voltage of the first power semiconductor element with a second reference voltage and generates a corresponding second comparison result, and generates a first voltage based on the first comparison result or the second comparison result, wherein the first and second reference voltages are associated with the temperatures of the first and second power semiconductor elements; and Control logic circuitry, coupled to the first time delay circuit, and generating a first logic signal based on the first voltage; and A first buffer is coupled to the control logic circuit and generates one of the first and second control signals based on the first logic signal.

2. The driving circuit according to claim 1, characterized in that, The first reference voltage increases as the temperature of the first and second power semiconductor devices decreases, and the second reference voltage increases as the temperature of the first and second power semiconductor devices increases.

3. The driving circuit according to claim 1, characterized in that, The first time delay circuit performs the first comparison operation to generate the first comparison result and generate the first voltage based on the first comparison result, and the first buffer generates the first control signal based on the first logic signal; The driving circuit also includes: The second time delay circuit performs a second comparison operation to compare the drain-source voltage with the second reference voltage and generate the second comparison result, and generates a second voltage based on the second comparison result, wherein the control logic circuit is coupled to the second time delay circuit and generates a second logic signal based on the second voltage; as well as The second buffer is coupled to the control logic circuit and generates the second control signal based on the second logic signal.

4. The driving circuit according to claim 3, characterized in that, The first time delay circuit includes a first current source, a first resistor, and a first comparator. The first current source is connected in series with the first resistor. The negative input terminal of the first comparator is connected to the node between the first current source and the first resistor to receive the first reference voltage. The positive input terminal of the first comparator receives the second control signal. The first comparator generates the first voltage at its output terminal based on the first comparison result.

5. The driving circuit according to claim 3, characterized in that, The second time delay circuit includes a second current source, a second resistor, and a second comparator. The second current source is connected in series with the second resistor. The positive input of the second comparator is connected to the node between the second current source and the second resistor to receive the second reference voltage. The negative input of the second comparator receives the drain-source voltage. The second comparator generates the second voltage at its output based on the second comparison result.

6. A voltage converter, characterized in that, include: A first power semiconductor element has a control electrode for receiving a first control signal; A second power semiconductor element is connected in parallel to the first power semiconductor element and has a control electrode for receiving a second control signal, wherein the safe operating area of ​​the first power semiconductor element is larger than the safe operating area of ​​the second power semiconductor element. A first time delay circuit performs a first comparison operation to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or compare the first drain-source voltage of the first power semiconductor element with a second reference voltage and generate a corresponding second comparison result, and generates a first voltage based on the first comparison result or the second comparison result, wherein the first and second reference voltages are associated with the first temperature of the first and second power semiconductor elements. A control logic circuit, coupled to the first time delay circuit, is used to generate a first logic signal based on the first voltage and the pulse width modulation signal; as well as A first buffer is coupled to the control logic circuit and generates one of the first and second control signals based on the first logic signal.

7. The voltage converter according to claim 6, characterized in that, The first time delay circuit performs the first comparison operation to generate the first comparison result and generate the first voltage based on the first comparison result, and the first buffer generates the first control signal based on the first logic signal; The voltage converter also includes: The second time delay circuit performs a second comparison operation to compare the first drain-source voltage with the second reference voltage and generate the second comparison result, and generates a second voltage based on the second comparison result, wherein the control logic circuit is coupled to the second time delay circuit and generates a second logic signal based on the second voltage and the pulse width modulation signal; as well as The second buffer is coupled to the control logic circuit and generates the second control signal based on the second logic signal.

8. The voltage converter according to claim 7, characterized in that, The first time delay circuit includes a first comparator, the negative input of which receives the first reference voltage, the positive input of which receives the second control signal, the first comparator generating the first voltage at its output based on the first comparison result, and the first reference voltage increasing as the first temperature of the first and second power semiconductor elements decreases.

9. The voltage converter according to claim 7, characterized in that, The second time delay circuit includes a second comparator, the positive input of which receives the second reference voltage, the negative input of which receives the first drain-source voltage, the second comparator generating the second voltage at its output based on the second comparison result, and the second reference voltage increasing as the first temperature of the first and second power semiconductor elements increases.

10. A control method for a voltage converter, characterized in that, The voltage converter control method includes generating a first control signal and a second control signal to respectively provide control electrodes of a first power semiconductor element and a second power semiconductor element connected in parallel in the voltage converter. The safe operating area of ​​the first power semiconductor element is larger than that of the second power semiconductor element. Receive pulse width modulation signals; A first comparison operation is performed to compare the voltage level of the second control signal with the first reference voltage and generate a corresponding first comparison result, or to compare the drain-source voltage of the first power semiconductor element with the second reference voltage and generate a corresponding second comparison result, wherein the first and second reference voltages are related to the temperature of the first and second power semiconductor elements. A first voltage is generated based on the first comparison result or the second comparison result; A first logic signal is generated based on the first voltage; and The first logic signal is buffered to generate one of the first and second control signals.

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