Two-stage operational amplifier

Abstract

The invention relates to a two-stage operational amplifier. An operational amplifier includes: a first stage of a current multiplexing type; and a second stage of rail-to-rail type cascaded with the first stage. The first stage includes a first feedback component defining a first common mode feedback loop. The second stage includes a second feedback component defining a second common mode feedback loop. The first common-mode feedback loop of the first stage and the second common-mode feedback loop of the second stage are independent of each other.

Description

Cross-references to related applications

[0001] This application claims priority to Italian Patent Application No. 102024000021496, filed on September 27, 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Background Technology

[0002] This disclosure relates to an improved two-stage operational amplifier. Background Technology

[0003] Operational amplifiers are commonly used electronic components, especially in the field of analog circuits. They have many significant advantages, such as the overall closed-loop gain being dependent on external components of the amplifier and therefore almost independent of factors such as the frequency or temperature of the input signal.

[0004] An operational transconductance amplifier (OTA) is an analog electronic circuit that can be considered one of the simplest and most common implementations of an operational amplifier.

[0005] Typical and known implementations of OTA are achieved using complementary metal-oxide-semiconductor (CMOS) technology, particularly using metal-oxide-semiconductor field-effect transistor (MOSFET) devices.

[0006] One of the key parameters for OTA (Over-The-Air) operation is its noise (specifically, input noise). In fact, OTA noise is inversely proportional to the current required for its operation, and therefore also inversely proportional to its input power. This means that, typically, to reduce OTA noise, its power consumption needs to be increased.

[0007] The input noise of an over-the-air (OTA) converter primarily originates from the OTA's input differential pair and the applied electronic load. Typically, the noise at the OTA input is approximately 2 to 3 times the noise of a single transistor in the input differential pair, and is inversely proportional to the OTA's tail current (i.e., the bias current of the input differential pair).

[0008] Recently, a novel low-noise input stage for over-the-air (OTA) testing has been proposed, whose input noise is identical to that of a single transistor at the same tail current. This novel input stage is based on current reuse, that is, using the same input current to bias multiple devices to reduce overall power consumption.

[0009] This new stage with current multiplexing capability has been applied to an OTA structure known as a two-stage OTA. The first stage of the two-stage OTA features current multiplexing and is designed to ensure low noise performance; while the second stage is designed to achieve rail-to-rail output (i.e., to give the output voltage a range from near the negative supply voltage to near the positive supply voltage). Therefore, the two-stage OTA can achieve both of these advantages simultaneously.

[0010] Figure 1 A known example of OTA 10 with two levels is shown.

[0011] The first power rail of OTA 10 is set to the maximum power supply voltage V. DD The second power rail is set to the minimum power supply voltage (here, the reference voltage is equal to ground voltage GND). Therefore, in the following text, the first and second power rails will also be referred to as the first power rail V. DD and the second power rail GND.

[0012] The OTA 10 includes a first stage 12 with current multiplexing function and a non-rail-to-rail type second stage 14, which are cascaded together.

[0013] The first stage 12 includes a first inverter (or a first-stage inverter) 12a and a second inverter (or a second-stage inverter) 12b, which are connected in parallel to each other to the first power rail V. DD Between the second power rail GND.

[0014] The first inverter 12a and the second inverter 12b are fabricated using CMOS technology. In other words, the first inverter 12a includes complementary P-type MOSFETs M. P10 and N-type MOSFET M N10 Furthermore, the second inverter 12b includes complementary P-type MOSFETs M. P11 and N-type MOSFET M N11 .

[0015] Specifically, the first stage 12 also includes a first tail current generator for generating a first tail current I. tail1 Therefore, it will be referred to as the first current generator I in the following text. tail1 and N-type control MOSFET M GT1,n First current generator I tail1 Directly connected to the first power rail V DD Control MOSFET M GT1,n The source terminal is directly connected to the second power rail GND, and the first inverter 12a and the second inverter 12b are connected in parallel to each other and directly connected to the first current generator I. tail1 and control MOSFETM GT1,n Between the leaky extremes.

[0016] MOSFET M P10 and MOSFET M N10 The gate terminal is directly coupled to the positive (or non-inverting) input INp of OTA 10, and MOSFET M P11and MOSFET M N11 The gate terminal is directly coupled to the negative (or inverted) input INn of OTA 10.

[0017] MOSFET M P10 and MOSFET M P11 The source terminal is directly connected to the first current generator I. tail1 MOSFETM N10 and MOSFET M N11 The source terminal is directly connected to the control MOSFET M GT1,n The drain terminal of MOSFET M P10 and MOSFET M N10 The leaky extreme element is at the first negative (or opposite) common node C. 01n MOSFETs M are directly coupled to each other. P11 and MOSFET M N11 The leaky extreme element is at the first positive (or non-inverted) common node C. 01p They are directly coupled to each other.

[0018] Furthermore, the second stage 14 includes a first inverter (or a first-second stage inverter) 14a and a second inverter (or a second-second stage inverter) 14b, which are connected in parallel to each other to the first power rail V. DD Between the second power rail GND.

[0019] The first inverter 14a and the second inverter 14b are fabricated using CMOS technology. In other words, the first inverter 14a includes complementary P-type MOSFETs M... P01 and N-type MOSFET M N01 The second inverter 14b includes complementary P-type MOSFETs M. P02 and N-type MOSFET M N02 Therefore, the second level 14 can be viewed as being composed of difference pairs M. P01 and M P02 It is limited to having a single-ended amplifier connected in parallel and consisting of MOSFET M N01 and MOSFET M N02 form.

[0020] The second stage 14 also includes a second tail current generator, which is configured to generate a second tail current I. tail2 Therefore, it will be referred to as the second current generator I in the following text. tail2 Second current generator I tail2 Directly connected to the first power rail V DDThe first inverter 14a and the second inverter 14b are connected in parallel to each other and directly connected to the second current generator I. tail2 Between the second power rail GND.

[0021] MOSFET M P01 and MOSFET M N01 The gate terminal of the second negative (or inverted) common node C 02n The nodes are directly coupled to each other, and this node is directly coupled to the first negative common node C. 01n Short circuit; MOSFET M P02 and MOSFET M N02 The gate terminal of the second positive (or non-inverting) common node C 02p The nodes are directly coupled to each other, and this node is directly coupled to the first positive common node C. 01p Short circuit. Thus, the first common node C... 01n and C 01p The voltage at each point is used to drive the first inverter 14a and the second inverter 14b, respectively.

[0022] MOSFET M P01 and MOSFET M P02 The source terminal is directly connected to the second current generator I. tail2 MOSFETM N01 and MOSFET M N02 The source terminal of MOSFET M is directly connected to the second power rail GND. P01 and MOSFET M N01 The leaky extremes are at the third positive (or non-inverted) common node C. 03p MOSFETs M are directly coupled to each other. P02 and MOSFET M N02 The leaky extremes are at the third negative (or opposite) common node C. 03n They are directly coupled to each other.

[0023] Third positive public node C 03p Directly connected to the positive (or non-inverting) output of OTA 10, while the third negative common node C 03n Connect directly to the negative (or inverted) output of OTA 10.

[0024] In addition, the third positive public node C 03p and the third negative common node C 03n Both are connected to the adder (or summer) circuit element S1 of the second stage 14, which in turn is connected to the gain circuit element G1 of the second stage 14. Specifically, the third positive common node C 03p and the third negative common node C 03nThe corresponding inputs of adder element S1 are directly connected to each other so that the corresponding voltages are added through adder element S1. The output of adder element S1 is directly connected to the input of gain element G1, which has a gain of 0.5. Therefore, adder element S1 and gain element G1 can calculate the third positive common node C. 03p and the third negative common node C 03n The common-mode voltage at the location.

[0025] The output of gain element G1 and the common-mode reference voltage V ref,cm The difference is calculated and then amplified. Specifically, the output of gain element G1 is directly connected to the negative (or inverting) input of subtractor element (difference operation circuit) C1 in the second stage 14, while the common-mode reference voltage V... ref,cm This is then applied to the positive (or non-inverting) input of subtractor element C1. Subtractor element C1 is configured to have a gain A. s .

[0026] The output of gain element G1 is directly connected to the control MOSFET M. GT1,n The gate terminal. Thus, the output voltage of subtractor element C1 (based on the third common node C) 03p and C 03n The common-mode voltage and the common-mode reference voltage V ref,cm The difference between them is determined for use in controlling MOSFET M. GT1,n The operation is controlled to control the operation of the first level 12.

[0027] In other words, the adder element S1, the gain element G1, the subtractor element C1, and the control MOSFET M GT1,n This forms a common-mode feedback loop that electrically connects the first stage 12 and the second stage 14. The function of this loop is to connect the second stage 14 to the third common node C. 03p and C 03n The common-mode voltage at the point is adjusted to the common-mode reference voltage V. ref,cm The value of . This adjustment is a property that is typically required for fully differential amplifiers.

[0028] Figure 2 It shows Figure 1 OTA 10 system-level modeling.

[0029] Specifically, it can be seen how the first-stage amplifier 12 performs feedback control based on the output of the second-stage amplifier 14 (by the differential pair M). P01 and M P02 Formed with a single-ended amplifier connected in parallel and consisting of MOSFET M N01 and MOSFETM N02 form).

[0030] In use, level 12 is at node C. 02p and C 02n The common-mode output at the point needs to be sufficiently biased to adjust the common-mode output of the second stage 14 to the required value V. ref,cm The first stage 12 needs to be biased at its maximum gain point, and the second stage 14, as a load of the first stage 12, must not affect the bias point of the first stage 12. Furthermore, in a fully differential amplifier, the closed-loop amplifier must not be latched when turned on.

[0031] However, it has been confirmed that known two-level OTA (e.g.) Figure 1 The structure of a system does not always meet all these requirements.

[0032] Specifically, the common-mode feedback loop makes the common-mode output of the first stage 12 dependent on the common-mode output of the second stage 14. Therefore, the first stage 12 is not biased at the point of maximum gain.

[0033] Furthermore, the output common-mode voltage of the first stage 12 is equal to that of MOSFET M. N01 and MOSFET M N02 Gate-source voltage V at the static point gs Therefore, MOSFET M N01 and MOSFET M N02 A high threshold voltage V is required. t This allows the common-mode voltage of the first stage 12 to be set to a reasonable value, thereby achieving high-gain operation (ideally, the optimal common-mode voltage should be located at voltage V). DD (The intermediate value between GND and GND). This means that the manufacturing process of OTA 10 requires more lithography masks, and the robustness of OTA 10 to process-voltage-temperature (PVT) variations is reduced. Solutions that could be used to address this issue (such as source follower-based solutions) would significantly increase product complexity and final cost, and would not solve the bias problem of the first stage 12 at the maximum gain point in any way.

[0034] Furthermore, the topology of the second stage 14 is not rail-to-rail because the output is relative to the voltage V. DD The change is affected by MOSFET M P01 and MOSFET M P02 Restrictions.

[0035] Finally, the common-mode feedback loop makes OTA 10 susceptible to latching issues.

[0036] Therefore, there is a need in the art to provide an operational amplifier to overcome the shortcomings of the prior art. Summary of the Invention

[0037] In one embodiment, an operational amplifier includes: a current-reused first stage; and a rail-to-rail cascaded relative to the first stage; wherein the first stage includes a first feedback component configured to define a first feedback loop independent of the second stage.

[0038] The first feedback component has a first input, a second input, and an output. The first feedback component is configured to perform a half-sum on the corresponding voltages of the first and second inputs, and to perform a difference operation between the half-sum and a first common-mode reference voltage.

[0039] The first feedback component further includes: a first adder element having a first input defining a first input of the first feedback component, a second input defining a second input of the first feedback component, and an output, the first adder element being configured to sum the corresponding voltages at the first input and the second input; a first gain element having an input and an output, the input of the first gain element being connected to the output of the first adder element, the first gain element being configured to halve the sum of the voltages at the first input and the second input of the first adder element; and a first subtractor element having a non-inverting first input, an inverting second input, and an output, the first input of the first subtractor element being connected to the output of the first gain element, the second input of the first subtractor element being configured to receive the first common-mode reference voltage, and the output of the first subtractor element defining the output of the first feedback component, the first subtractor element being configured to perform a difference operation between the sum and the first common-mode reference voltage.

[0040] The operational amplifier is a fully differential type and has both positive and negative outputs.

[0041] The second stage includes a second feedback component configured to define a second feedback loop independent of the first stage and the first feedback loop. The second feedback component has a first input, a second input, and an output, wherein the second feedback component is configured to perform a half-sum on the corresponding voltages of the first and second inputs and calculate the difference between the half-sum and a second common-mode reference voltage.

[0042] The second feedback component further includes: a second adder element having a first input defining a first input of the second feedback component, a second input defining a second input of the second feedback component, and an output, the second adder element being configured to sum the corresponding voltages at the first input and the second input; a second gain element having an input and an output, the input of the second gain element being connected to the output of the second adder element, the second gain element being configured to halve the sum of the voltages at the first input and the second input of the second adder element; and a second subtractor element having a non-inverting first input, an inverting second input, and an output, the first input of the second subtractor element being connected to the output of the second gain element, the second input of the second subtractor element being configured to receive the second common-mode reference voltage, and the output of the second subtractor element defining the output of the second feedback component, the second subtractor element being configured to perform a difference operation between the sum and the second common-mode reference voltage. Attached Figure Description

[0043] To better understand this disclosure, preferred embodiments will now be described by way of non-limiting example only with reference to the accompanying drawings, in which:

[0044] Figure 1 A circuit diagram of a known type of two-stage operational amplifier is shown;

[0045] Figure 2 It shows Figure 1 System-level modeling of known operational amplifiers;

[0046] Figure 3 A circuit diagram of an embodiment of an improved two-stage operational amplifier is shown;

[0047] Figure 4 It shows Figure 3 System-level modeling of operational amplifiers;

[0048] Figure 5 and Figure 6 A circuit diagram of a two-stage operational amplifier according to corresponding and further embodiments is shown. Detailed Implementation

[0049] In the following description, elements common to different embodiments are indicated by the same reference numerals.

[0050] Figure 3 An embodiment of operational amplifier 30, specifically an operational transconductance amplifier (OTA), is shown. Therefore, the following description will take the case where operational amplifier 30 is an OTA as an example.

[0051] The OTA 30 is a two-stage operational amplifier.

[0052] More in detail, Figure 3In this embodiment, OTA 30 is fully differential, and therefore has two outputs (hereinafter referred to as OUT). p and OUT n ).

[0053] OTA 30 is coupled to the maximum supply voltage V. DD A first power rail (e.g., approximately 2V) and a second power rail coupled to a minimum supply voltage (here, a reference voltage equal to ground GND, e.g., approximately 0V) are biased. Therefore, in the following text, the first and second power rails are also simply referred to as the first power rail V. DD and the second power rail GND.

[0054] The OTA 30 includes a first stage 32 with current multiplexing function and a rail-to-rail type second stage 34, with the first stage 32 and the second stage 34 cascaded together.

[0055] The first stage 32 includes a first inverter (or a first-stage inverter) 32a and a second inverter (or a second-stage inverter) 32b, which are connected in parallel to each other to the first power rail V. DD Between the second power rail GND.

[0056] The first inverter 32a and the second inverter 32b are fabricated using CMOS technology. In other words, the first inverter 32a includes complementary P-type MOSFETs (or a first P-MOSFET) M. P10 and N-type MOSFET (or first N-MOSFET) M N10 The second inverter 32b includes complementary P-type MOSFETs (or a second P-MOSFET) M. P11 and N-type MOSFET (or second N-MOSFET) M N11 .

[0057] Specifically, the first stage 32 also includes a first tail current generator, which is configured to generate a first tail current I. tail1 (For example, equal to approximately 50µA), therefore it will be referred to as the first current generator I below. tail1 and P-type control MOSFET MG T1,p .

[0058] More specifically, controlling the MOSFET MG T1,p The source extremum is directly connected to the first orbital V. DD First current generator I tail1 Directly connected to the second rail GND, and the first inverter 32a and the second inverter 32b are connected in parallel to each other and directly connected to the control MOSFET MG. T1,pThe drain terminal and the first current generator I tail1 between.

[0059] MOSFET M P10 and MOSFET M N10 The gate terminal is directly coupled to the positive (or non-inverting) input INp of the OTA 30, and the MOSFET M P11 and MOSFET M N11 The gate terminal is directly coupled to the negative (or inverted) input INn of OTA 30.

[0060] MOSFET M P10 and MOSFET M P11 The source terminal is directly connected to the control MOSFET MG T1,p The drain terminal of MOSFET M N10 and MOSFET M N11 The source terminal is directly connected to the first current generator I. tail1 MOSFET M P10 and MOSFET M N10 The leaky extreme element is at the first negative (or opposite) common node C. 01n MOSFETs M are directly coupled to each other. P11 and MOSFET M N11 The leaky extreme element is at the first positive (or non-inverted) common node C. 01p They are directly coupled to each other.

[0061] Furthermore, the first stage 32 includes a first feedback component 32'. The first feedback component 32', together with the other components of the first stage 32, forms a first feedback loop, specifically a common-mode feedback loop.

[0062] Specifically, the first feedback component 32' includes a first adder (summation) circuit element S1, a first gain circuit element G1, and a first subtractor (difference operation) circuit element C1.

[0063] The first adder element S1 is connected to the first positive common node C. 01p and the first negative common node C 01n Specifically, the first positive common node C 01p and the first negative common node C 01n The corresponding inputs of the first adder element S1 are directly connected so that the first adder element S1 adds the corresponding voltages. For example, the first adder element S1 is an analog adder, especially a two-input adder.

[0064] The first adder element S1 is then connected to the first gain element G1. Specifically, the output of the first adder element S1 is directly connected to the input of the first gain element G1, which has a gain of 0.5. For example, the first gain element G1 is an amplifier with a gain of 0.5.

[0065] Therefore, the first adder element S1 and the first gain element G1 allow the calculation of the first positive common node C. 01p and the first negative common node C 01n The common-mode (i.e. half-mode) voltage at the location.

[0066] The output of the first gain element G1 is then compared with the first common-mode reference voltage V. ref,cm1 (For example, equal to the maximum power supply voltage V) DD The difference is calculated by comparing the average value between the minimum supply voltage GND and the minimum supply voltage GND (so here it is, for example, equal to about 1V). Specifically, the output of the first gain element G1 is directly connected to the positive (or non-inverting) input of the first subtractor element C1, while the first common-mode reference voltage V... ref,cm1 This is then applied to the negative (or inverting) input of the first subtractor element C1. For example, the first subtractor element C1 is an analog subtractor (e.g., a differential amplifier).

[0067] Furthermore, the first subtractor element C1 also has a first gain A1 (e.g., approximately 10). Therefore, the output of the first subtractor element C1 is equal to the voltage at the output of the first gain element G1 and the first common-mode reference voltage V. ref,cm1 The difference between them is multiplied by the first gain A1.

[0068] The output of the first subtractor element C1 is then directly connected to the control MOSFET MG. T1,p The gate terminal. Thus, the output voltage of the first subtractor element C1 (based on the first common node C) 01p and the first common node C 01n The common-mode voltage and the first common-mode reference voltage V ref,cm1 The comparison results between them are used to control the control MOSFET M. GT1,p The operation (therefore, in general, the operation of the first level 32 is controlled, especially the common mode).

[0069] The second stage 34 includes a first complementary component 34a and a second complementary component 34b, which are connected in parallel to each other on the first track V. DD Between the second track GND.

[0070] The first complementary component 34a and the second complementary component 34b are fabricated using a CMOS process. Specifically, the first complementary component 34a includes mutually complementary P-type MOSFETs (or a first pair of MOSFETs) M.P01 And N-type MOSFET (or first mirror MOSFET) M N01 The second complementary component 34b includes mutually complementary P-type MOSFETs (or a second pair of MOSFETs) M. P02 and N-type MOSFET (or second mirror MOSFET) M N02 .

[0071] The second stage 34 also includes a second tail current generator, which is used to generate a second tail current I. tail2 (For example, approximately 2µA), therefore it will be referred to as the second current generator I in the following text. tail2 Second current generator I tail2 Directly connected to the first power rail V DD Furthermore, the first complementary component 34a and the second complementary component 34b are connected in parallel to each other and directly connected to the second current generator I. tail2 Between the second power rail GND.

[0072] MOSFET M P01 and MOSFET M P02 The gate terminals are directly coupled to the first positive common node C. 01p and the first negative common node C 01n Therefore, the first negative common node C 01n The voltage at that point is used to drive MOSFET M P02 And the first positive common node C 01p The voltage at that point is used to drive MOSFET M P01 .

[0073] MOSFET M P01 and MOSFET M P02 The source terminal is directly connected to the second current generator I. tail2 And MOSFET M N01 and M N02 The source extremum is directly connected to the second track GND.

[0074] MOSFET M P01 and MOSFET M N01 The leaky extreme element is at the second negative (or opposite) common node C. 02n They are directly coupled to each other, and MOSFET M P02 and MOSFET M N02 The leaky extreme element is at the second positive (or non-inverted) common node C. 02p They are directly coupled to each other.

[0075] MOSFET M N01The gate and drain terminals are directly connected to each other and thus short-circuited, making MOSFET M N01 It operates in diode-connected transistor mode. Similarly, MOSFET M N02 The gate and drain terminals are also directly connected to each other and thus short-circuited, causing MOSFET M N02 Operates in diode-connected transistor mode.

[0076] The second stage 34 also includes an output component 34c, specifically a first output sub-component 34c' and a second output sub-component 34c'', which are connected in parallel to each other on the first track V. DD Between the second track GND.

[0077] The output component 34c is fabricated using CMOS technology. Specifically, the first output sub-component 34c' includes complementary P-type MOSFETs (or first-rail P-MOSFETs) M. P03 And N-type MOSFET (or first-rail N-MOSFET) M N03 The second output sub-component 34c'' includes complementary P-type MOSFETs (or second-rail P-MOSFETs) M. P04 And N-type MOSFET (or second-rail N-MOSFET) M N04 .

[0078] MOSFET M N03 The gate terminal is directly connected to the second negative common node C. 02n , and MOSFET M N04 The gate terminal is directly connected to the second positive common node C. 02p Therefore, the second positive common node C 02p Second negative common node C 02n The voltages at these points are used to control MOSFET MN04 and MOSFET M, respectively. N03 The operation.

[0079] In addition, MOSFET M P03 and MOSFET M P04 The gate terminals are directly connected to each other.

[0080] MOSFET M P03 and MOSFET M P04 The source extremes are connected in parallel to each other and directly connected to the first orbital V. DD , while MOSFETM N03 and MOSFET M N04 The source extrema are connected in parallel to each other and directly connected to the second track GND.

[0081] MOSFET MP03 and MOSFET M N03 The leaky extreme node is at the third positive (or in-phase) common node C. 03p (Also known as the orthogonal public node C) 03p They are directly connected to each other at points M, thus short-circuiting each other. Similarly, MOSFET M P04 and MOSFETM N04 The leaky extremes are at the third negative (or opposite) common node C. 03n (Also known as the orbital negative common node C) 03n They are directly connected to each other, thus short-circuiting each other.

[0082] Third positive public node C 03p Directly connected to the positive (or non-inverting) output of OTA 30, while the third negative common node C 03n Connect directly to the negative (or inverted) output of the OTA 30.

[0083] In summary, the second stage 34 clearly includes the differential pair 36a (composed of MOSFET M). P01 and M P02 Formation), first current mirror 36b (or positive current mirror, formed by MOSFET M) N01 and MOSFET M N03 (Formed), second current mirror 36c (or negative current mirror, formed by MOSFET M) N02 and MOSFET M N04 Formation), first rail-to-rail assembly 36d (or positive rail-to-rail assembly, composed of MOSFET M) P03 and MOSFET M N03 Forming) and the second rail-to-rail assembly 36e (or negative rail-to-rail assembly, composed of MOSFET M) P04 and MOSFET M N04 form).

[0084] MOSFET M of differential pair 36a P01 and MOSFET M P02 Receive the first positive common node C 01p and the first negative common node C 01n The voltage at the point is converted into a corresponding current, which flows to the MOSFET M. N01 and MOSFET M N02 The first branch of the corresponding current mirror 36b and the first branch of the current mirror 36c are defined. In other words, current mirrors 36b and 36c operate as the electronic load of the differential pair 36a. The current in the first branch of current mirrors 36b and 36c is then mirrored to the current through MOSFET M. N03 and MOSFET MN04 In the corresponding second branch, these currents flow into the corresponding rail-to-rail components 36d and 36e, respectively, at the positive output OUT. p and negative output OUT n The output voltage is generated at that point.

[0085] Specifically, using current mirrors 36b and 36c, the information content of the input signal can be transferred from the differential pair 36a (due to the presence of the second current generator I). tail2 (It cannot provide rail-to-rail output on its own) Transmission to rail-to-rail components 36d and 36e (which have corresponding OUT outputs). p / OUT n They are symmetrically located between orbits V DD And GND and only through MOSFET M P03 M N03 and M P04 and M N04 Track V DD Separated from GND, thus enabling rail-to-rail functionality.

[0086] Furthermore, the second stage 34 includes a second feedback component 34'. The second feedback component 34', together with the other components of the second stage 34, forms a second feedback loop, specifically a common-mode feedback loop.

[0087] The first feedback component 32' and the second feedback component 34' are independent of each other. More specifically, the first feedback component 32' is part of a first feedback loop that forms a feedback loop for common mode operation of the first stage 32, and this feedback loop is independent of the second feedback loop to which the second feedback component 34' belongs. In other words, the first stage 32 and the second stage 34 are connected by a first common node C. 01p and C 01n Connected to MOSFET M respectively P01 and MOSFET M P02 The electrical connections are interconnected. However, this electrical connection is ineffective for common mode; that is, the common mode output of the first stage 32 will not affect the common mode output of the second stage 34 because it is controlled by MOSFET M. P01 and MOSFET M P02 The differential pair suppression is defined. Therefore, in terms of common mode, the operation of the first stage 32 is not affected by the second stage 34, and the operation of the second stage 34 is not affected by the first stage 32. In other words, the first feedback loop and the second feedback loop are separate and independent of each other.

[0088] Specifically, the second feedback component 34' includes a second adder (summation) circuit element S2, a second gain circuit element G2, and a second subtractor (differential) circuit element C2.

[0089] The second adder element S2 is connected to the third positive common node C. 03p and the third negative common node C 03n Specifically, the third positive common node C 03p and the third negative common node C 03n The corresponding inputs are directly connected to the second adder element S2 so that the corresponding voltages are added through the second adder element S2. For example, the second adder element S2 is an analog adder, especially a two-input adder.

[0090] The second adder element S2 is then connected to the second gain element G2. Specifically, the output of the second adder element S2 is directly connected to the input of the second gain element G2, which has a gain of 0.5. For example, the second gain element G2 is an amplifier with a gain of 0.5.

[0091] Therefore, the second adder element S2 and the second gain element G2 allow the computation of the third positive common node C. 03p and the third negative common node C 03n The common-mode (or half-mode) voltage at the location.

[0092] The output of the second gain element G2 and the second common-mode reference voltage V ref,cm2 (For example, equal to the maximum power supply voltage V) DD The difference is calculated by comparing the average value between the minimum supply voltage GND and the minimum supply voltage GND (which is, for example, approximately 1V here). Specifically, the output of the second gain element G2 is directly connected to the positive (or non-inverting) input of the second subtractor element C2, while the second common-mode reference voltage V... ref,cm2 Then the negative (or inverted) input is applied to the second subtractor element C2.

[0093] For example, the second subtractor element C2 is an analog subtractor (e.g., a differential amplifier).

[0094] Furthermore, the second subtractor element C2 also has a second gain A2 (e.g., approximately 10). Therefore, the output of the second subtractor element C2 is equal to the output voltage of the second gain element G2 plus the second common-mode reference voltage V. ref,cm2 The difference between them is multiplied by the second gain A2.

[0095] The output of the second subtractor element C2 is directly connected to MOSFET M. P03 and MOSFET M P04 The gate terminal.

[0096] Thus, the output voltage of the second subtractor element C2 (according to the third common node C) 03p and C 03n The common-mode voltage and the second common-mode reference voltage V ref,cm2(The comparison between them is determined) is used to control MOSFET M P03 and MOSFET M P04 The operations (therefore, generally the second level 34 operations, especially common mode operations).

[0097] Figure 4 schematically shown Figure 3 OTA 30 system-level modeling.

[0098] Specifically, from Figure 4 It can be clearly seen that the first and second feedback components 32' and 34' are independent of each other and unrelated to each other, so there is no feedback that joins the first level 32 and the second level 34.

[0099] Figure 5 Another embodiment of the OTA 30 is shown.

[0100] Figure 5 OTA 30 and Figure 3 The OTA 30 is basically similar, so in addition to emphasizing its similarity to... Figure 3 Aside from the structural differences, this article will not describe them further.

[0101] Specifically, in Figure 5 In the first stage 32, there are also a first cascode component (or positive cascode component) 38a and a second cascode component (or negative cascode component) 38b.

[0102] Specifically, the positive common-source cascode component 38a includes a MOSFET (or a first common-source cascode P-MOSFET) M. P12 and MOSFET (or second common-source cascode P-MOSFET) M P13 Both are P-type, and the negative cascode component 38b includes a MOSFET (or a first cascode N-MOSFET) M. N12 and MOSFET (or second common-source cascode N-MOSFET) M N13 Both are of type N.

[0103] MOSFET M P12 Compared to MOSFET M P10 Cascode MOSFET M P13 Compared to MOSFET M P11 Cascode MOSFET M N12 Compared to MOSFET M N10 Cascode MOSFET M N13 Compared to MOSFET M N11 Common source and common gate.

[0104] MOSFET M P12 and MOSFET M P13 The gate terminals are directly connected to each other and are configured to receive a common-source cascode voltage (or a first common-source cascode voltage) V. cascp Similarly, MOSFET M N12 and MOSFET M N13 The gate terminals are directly connected to each other and are configured to receive a common-source cascode voltage (or a second common-source cascode voltage) V. cascn .

[0105] Common gate voltage V cascp and V cascn Obtained in a manner known per se, its value should enable the cascode components 38a and 38b to operate normally in cascode mode. For example, the cascode voltage V cascn Another current generator (not shown in the figure) can be used, directly connected to the first power rail V. DD With MOSFET M N12 and MOSFET M N13 Between the connection points between the gate terminals) and another diode-connected transistor-mode MOSFET (not shown in the figure, N-type, whose source terminal is directly connected to the first current generator I) and a transistor mode MOSFET (not shown in the figure, its source terminal is directly connected to the first current generator I). tail1 Its drain terminal is directly connected to MOSFET M N12 and MOSFET M N13 The common-source cascode voltage V can be obtained by connecting the gate terminals; a similar structure can also be used to obtain the common-source cascode voltage V. cascp .

[0106] More specifically, MOSFET M P12 and MOSFET M P13 The source terminal is directly connected to the corresponding MOSFET M. P10 and M P11 The drain terminal of MOSFET M N12 and M N13 The source terminal is directly connected to the corresponding MOSFET M. N10 and M N11 The drain terminal of MOSFET M P12 and M N12 The leaky extreme element is in the first negative common node C 01n They are directly connected to each other, and MOSFETM P13 and M N13 The leaky extreme element is in the first positive common node C. 01p They are directly connected to each other.

[0107] The presence of cascode modules 38a and 38b, plus the first common-mode reference voltage V ref,cm1 Set as voltage V DD The approximate midpoint between GND and OTA 30 can further increase the gain of the first stage 32, thereby improving the accuracy of OTA 30.

[0108] Figure 6 Another embodiment of the OTA 30 is shown.

[0109] In detail, Figure 6 In this embodiment, OTA 30 is a single-ended type, and its output is referred to as OUT in the following text.

[0110] Figure 6 OTA 30 and Figure 3 The OTA 30 is basically similar, so in addition to emphasizing its similarity to... Figure 3 Aside from the structural differences, this article will not describe them further.

[0111] Specifically, in Figure 6 In the middle, the second level 34 does not have a second feedback component 34'.

[0112] Furthermore, the second level 34 has only one output OUT, which is exemplarily placed here in the third negative common node C. 03n However, it is also possible to connect the diode from the MOSFET M. P03 Moved to MOSFET M P04 Place the output OUT in the third positive common node C. 03p Place.

[0113] Specifically, in this embodiment, the output OUT is located at the third negative common node C. 03n At, MOSFET M P03 It is in diode-connected transistor mode (i.e., its gate and drain are directly connected and therefore short-circuited). This means that MOSFET M P03 and MOSFET M P04 Form another current mirror 40, which will connect the first branch (here by MOSFET M) P03 The current in the limited section is mirrored to the second branch (here, MOSFET M). P04 (within the constraints), thus allowing the use of a single output OUT.

[0114] In other words, in Figure 6 In the second stage 34, there is a structure commonly referred to as a symmetric OTA.

[0115] The advantages offered by the invention made according to this disclosure are apparent upon examination of its features.

[0116] Specifically, the common-mode output of the first stage 32 can be set independently of the second stage 34, so the first stage 32 can be biased to its maximum gain point without being affected by the second stage 34.

[0117] Furthermore, the second stage 34 is not sensitive to the common-mode output of the first stage 32, therefore there is no need to use a stage with a high threshold voltage V. t The MOSFETs. This makes the manufacturing process of OTA 30 simpler and cheaper, especially since any tolerance and process variation will affect all existing MOSFETs equally, thus making OTA 30 more reliable and thus its operation more homogeneous.

[0118] Because the first-stage amplifier 32 has high gain (which could be even higher if the first-stage amplifier 32 includes cascaded components 38a and 38b), the OTA 30 has high accuracy.

[0119] Furthermore, the second-level 34 is actually a rail-to-rail type.

[0120] Furthermore, since the first feedback loop sets the common-mode output of the first stage 32 to the first common-mode reference voltage V... ref,cm1 Therefore, the output common-mode voltage is insensitive to PVT variations. Thus, the first common-mode reference voltage V can be selected. ref,cm1 To maximize the gain of the first stage 32.

[0121] Finally, the cascading of the first stage 32 and the second stage 34 makes (especially for) Figure 3 and Figure 5 As shown in the fully differential OTA, it is possible to input IN p and IN n With output OUT p and OUT n This achieves high common-mode rejection, thereby reducing positive common-mode feedback. Therefore, OTA 30 significantly reduces the risk of latching problems.

[0122] Finally, it is obvious that modifications and variations can be made to the invention described and illustrated herein without departing from the scope of this disclosure as defined by the appended claims.

[0123] For example, the different embodiments described can be combined with each other to provide further solutions (e.g., Figure 5 The common source cascode components 38a and 38b can also be similarly used for Figure 6 (as in the embodiments).

[0124] Furthermore, referring to Level 2, Section 34, although only so far only describes... Figure 3 , Figure 5 and Figure 6The structure described herein is for illustrative and non-restrictive purposes only, and other rail-to-rail structures can be similarly considered in place of the structure described herein.

[0125] Although what is described now is a P-type control MOSFET M GT1,p However, the situation can obviously be similarly considered for an N-type control MOSFET. In this case, the drain terminal of the N-type control MOSFET is connected to MOSFET M. N10 and MOSFET M N11 The source terminal of the first subtractor element C1 is connected to the second power rail GND, and its gate terminal is connected to the output of the first subtractor element C1; alternatively, the first tail current generator is connected to the first power rail V. DD and MOSFET M P10 source terminals and MOSFET M P11 Between the source extremes.

[0126] In addition, the minimum power supply voltage can be voltage V. ss Instead of ground voltage GND; for example, voltage V ss It could be a negative voltage.

[0127] Furthermore, the structure defined by the adder element and the gain element can efficiently calculate the half-sum of the input voltages of the adder element. Therefore, it is clear that other circuit embodiments with similar operation can be considered as alternatives to the examples presented herein. For instance, this common-mode calculation function can be performed using a simpler circuit (e.g., two resistors or two MOSFETs properly connected in a known manner).

Claims

1. An operational amplifier, comprising: A current-reused first stage, wherein the first stage includes a first feedback component configured to define a first common-mode feedback loop; as well as A second stage of a rail-to-rail type, cascaded with the first stage, wherein the second stage includes a second feedback component configured to define a second common-mode feedback loop; The first common-mode feedback loop of the first stage and the second common-mode feedback loop of the second stage are independent of each other.

2. The operational amplifier according to claim 1, wherein the operational amplifier is a transconductance operational amplifier.

3. The operational amplifier according to claim 1: The first feedback component has a first input, a second input, and an output; and The first feedback component is configured to perform a half-sum on the corresponding voltages at the first input and the second input, and to perform a difference calculation between the half-sum and the first common-mode reference voltage at the output.

4. The operational amplifier according to claim 3, wherein the first feedback component comprises: A first adder element has a first input defining a first input of the first feedback component, a second input defining a second input of the first feedback component, and an output, the first adder element being configured to sum the corresponding voltages at the first input and the second input; A first gain element has an input and an output connected to the output of the first adder element, and the first gain element is configured to halve the sum of the voltages at the first input and the second input of the first adder element. as well as A first subtractor element having a non-inverting first input connected to the output of the first gain element, an inverting second input configured to receive the first common-mode reference voltage, and an output defining the output of the first feedback component, the first subtractor element being configured to calculate the difference between half of the sum and the first common-mode reference voltage.

5. The operational amplifier according to claim 3, further comprising: The first power rail is configured to be set to the maximum power supply voltage; The second power rail is configured to be set to the minimum power supply voltage.

6. The operational amplifier according to claim 5, having a positive input and a negative input: The first stage includes a P-type control MOSFET, the source terminal of which is connected to the first power rail; The first stage further includes a first inverter and a second inverter, which are connected in parallel between the control MOSFET and the second power rail. The first inverter includes a P-type first P-MOSFET and an N-type first N-MOSFET, and the second inverter includes a P-type second P-MOSFET and an N-type second N-MOSFET; The gate terminals of the first P-MOSFET and the first N-MOSFET are coupled to the positive input, and the gate terminals of the second P-MOSFET and the second N-MOSFET are coupled to the negative input. The source terminals of the first P-MOSFET and the second P-MOSFET are connected in parallel to each other to the drain terminal of the control MOSFET; The drain terminals of the first P-MOSFET and the first N-MOSFET are connected to each other at the first negative common node, and the drain terminals of the second P-MOSFET and the second N-MOSFET are connected to each other at the first positive common node; and The first input and the second input of the first feedback component are respectively connected to the first positive common node and the first negative common node, and the output of the first feedback component is connected to the gate terminal of the control MOSFET.

7. The operational amplifier according to claim 6: The first inverter further includes a P-type first common-source cascode P-MOSFET and an N-type first common-source cascode N-MOSFET, and the second inverter further includes a P-type second common-source cascode P-MOSFET and an N-type second common-source cascode N-MOSFET; and Wherein, the first common-source cascode P-MOSFET is common to the first P-MOSFET, the first common-source cascode N-MOSFET is common to the first N-MOSFET, the second common-source cascode P-MOSFET is common to the second P-MOSFET, and the second common-source cascode N-MOSFET is common to the second N-MOSFET.

8. The operational amplifier according to claim 5, having a positive input and a negative input: The first stage includes an N-type control MOSFET, the source terminal of which is connected to the second power rail; The first stage further includes a first inverter and a second inverter, which are connected in parallel between the first power rail and the control MOSFET. The first inverter includes a P-type first P-MOSFET and an N-type first N-MOSFET, and the second inverter includes a P-type second P-MOSFET and an N-type second N-MOSFET; The gate terminals of the first P-MOSFET and the first N-MOSFET are coupled to the positive input, and the gate terminals of the second P-MOSFET and the second N-MOSFET are coupled to the negative input. The source terminal of the first P-MOSFET and the source terminal of the second P-MOSFET are connected in parallel to each other to the first power rail; The drain terminals of the first P-MOSFET and the first N-MOSFET are connected to each other at the first negative common node, and the drain terminals of the second P-MOSFET and the second N-MOSFET are connected to each other at the first positive common node; and The first input and the second input of the first feedback component are respectively connected to the first positive common node and the first negative common node, and the output of the first feedback component is connected to the gate terminal of the control MOSFET.

9. The operational amplifier according to claim 8: The first inverter further includes a P-type first common-source cascode P-MOSFET and an N-type first common-source cascode N-MOSFET, and the second inverter further includes a P-type second common-source cascode P-MOSFET and an N-type second common-source cascode N-MOSFET; and Wherein, the first common-source cascode P-MOSFET is common to the first P-MOSFET, the first common-source cascode N-MOSFET is common to the first N-MOSFET, the second common-source cascode P-MOSFET is common to the second P-MOSFET, and the second common-source cascode N-MOSFET is common to the second N-MOSFET.

10. The operational amplifier of claim 1, wherein the operational amplifier is a fully differential operational amplifier having positive and negative outputs.

11. The operational amplifier according to claim 10: The second feedback component has a first input, a second input, and an output; and The second feedback component is configured to perform a half-sum on the corresponding voltages at the first input and the second input, and to perform a difference calculation between the half-sum and the second common-mode reference voltage at the output.

12. The operational amplifier of claim 11, wherein the second feedback component comprises: The second adder element has a first input defining the first input of the second feedback component, a second input defining the second input of the second feedback component, and an output, and the second adder element is configured to sum the corresponding voltages at the first input and the second input; A second gain element has an input and an output connected to the output of the second adder element, and the second gain element is configured to halve the sum of the voltages at the first input and the second input of the second adder element; as well as The second subtractor element has a non-inverting first input connected to the output of the second gain element, an inverting second input configured to receive the second common-mode reference voltage, and an output defining the output of the second feedback component. The second subtractor element is configured to perform the difference between half of the sum and the second common-mode reference voltage.

13. The operational amplifier of claim 11, wherein the second stage further comprises: The first rail-to-rail assembly includes a P-type first rail P-MOSFET and an N-type first rail N-MOSFET, the first rail P-MOSFET and the first rail N-MOSFET being complementary to each other, extending directly between a first power rail and a second power rail, and coupled to each other at a third positive common node; and The second rail-to-rail assembly includes a P-type second rail P-MOSFET and an N-type second rail N-MOSFET, which are complementary to each other, extend directly between the first power rail and the second power rail, are connected in parallel with the first rail-to-rail assembly, and are coupled to each other at a third negative common node. The third positive common node defines the positive output of the operational amplifier, and the third negative common node defines the negative output of the operational amplifier; and The third positive common node further defines the first input of the second feedback component, the third negative common node further defines the second input of the second feedback component, and the output of the second feedback component is connected to the respective gate terminals of the first rail P-MOSFET and the second rail P-MOSFET.

14. The operational amplifier of claim 13, wherein the second stage further comprises: The differential pair includes a first pair of P-type MOSFETs and a second pair of P-type MOSFETs, wherein the gate terminals of the first pair of MOSFETs are connected to the first positive common node, and the gate terminals of the second pair of MOSFETs are connected to the first negative common node; The first current mirror includes an N-type first mirror MOSFET and a first rail N-MOSFET, wherein the first mirror MOSFET is coupled to the first pair of MOSFETs, and the first current mirror is configured to mirror the current flowing through the first mirror MOSFET in the first rail-to-rail assembly. as well as The second current mirror includes an N-type second mirror MOSFET and a second rail N-MOSFET, wherein the second mirror MOSFET is coupled to the second pair of MOSFETs, and the second current mirror is configured to mirror the current flowing through the second mirror MOSFET in the second rail-to-rail assembly.

15. An operational amplifier, comprising: The first stage of the current-multiplexed type has a first output, a second output, and a first common-mode control transistor; The first stage includes a first feedback component configured to define a first common-mode feedback loop, the first common-mode feedback loop having an input coupled to the first output and the second output and an output coupled to a control terminal of the first common-mode control transistor; as well as The second stage of the rail-to-rail type, cascaded with the first stage, has a third output and a fourth output as well as a second common-mode control transistor; The second stage includes a second feedback component configured to define a second common-mode feedback loop, the second common-mode feedback loop having an input coupled to the third output and the fourth output and an output coupled to a control terminal of the second common-mode control transistor; The first common-mode feedback loop of the first stage and the second common-mode feedback loop of the second stage are independent of each other.

16. The operational amplifier according to claim 15: The first feedback component is configured to perform a half-sum on the corresponding voltages at the first input and the second input, and to perform a difference operation between the half-sum and a first common-mode reference voltage to generate a first common-mode control signal coupled to the control terminal of the first common-mode control transistor; and The second feedback component is configured to perform a half-sum on the corresponding voltages at the third and fourth inputs, and to perform a difference operation between the half-sum and the second common-mode reference voltage to generate a second common-mode control signal coupled to the control terminal of the first common-mode control transistor.

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