LTCC (Low Temperature Co-Fired Ceramic) multilayer duplexer equivalent circuit and duplexer

Abstract

According to the LTCC multilayer duplexer equivalent circuit and the duplexer provided by the invention, lumped parameter model design is adopted to realize the special electrical performance requirements of a novel miniaturized broadband low-insertion-loss LTCC duplexer, a low-frequency path is formed by adopting a second-order low-pass filter, and the low-frequency path is formed by adopting a second-order low-pass filter. The high frequency band forms a transmission zero point at the passband low frequency band by introducing a bridging capacitor, so that the suppression capability of the high frequency passband at the low frequency is enhanced, and in addition, the passband range of the high frequency band is simply and effectively widened by adopting a high-order form. According to the invention, the frequency division of low-frequency signals and high-frequency signals is effectively realized, the high-frequency passband bandwidth is effectively expanded, and the high-frequency band-pass filter has the advantages of miniaturization, low loss, high suppression, high isolation, high reliability, low cost, excellent consistency, suitability for large-scale production and the like, and is also suitable for the development trend of integration and miniaturization of new electronic components.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of duplexers, and in particular to an LTCC multilayer duplexer equivalent circuit and a duplexer. BACKGROUND

[0002] Low Temperature Co-fired Ceramic (LTCC) technology is a new co-firing technology developed by Hughes Corporation of the United States in 1982 based on High Temperature Co-fired Ceramic (HTCC). It is to make low-temperature sintering ceramic powder into a green ceramic tape with accurate thickness and density as a circuit substrate material, then use laser drilling, micro-hole grouting, precision conductor paste printing and other processes to make the required circuit pattern on the green ceramic tape, and bury multiple passive components therein, then stack together, sinter at 900 DEG C, to make a three-dimensional circuit network of passive integrated components, which can also be made into a three-dimensional circuit substrate with built-in passive components, and IC and active devices can be attached on the surface, and finally a passive / active integrated functional module is made.

[0003] With the continuous development of smart phones, mobile terminals and other devices towards miniaturization, multi-band and other directions, higher requirements are put forward for duplexers. On the one hand, the miniaturization trend of devices requires duplexers to have smaller size so as to be better integrated in limited circuit board space. For example, the internal space of a mobile phone, if the duplexer is too large in size, it will occupy too much space, which is not conducive to the layout of other components and the overall lightweight design of the mobile phone.

[0004] On the other hand, the development of multi-band requires duplexers to have excellent performance in terms of performance, to accurately process signals of different frequency bands, to achieve effective isolation and filtering of transmitted and received signals, to ensure that the signals of each frequency band do not interfere with each other, and to have low insertion loss to maintain signal strength and accuracy. Therefore, the above problems need to be solved. SUMMARY

[0005] In view of the above problems, the present application provides a miniaturized, wideband, low-insertion-loss LTCC multilayer duplexer equivalent circuit and a duplexer.

[0006] The present application achieves the above-mentioned purpose by the following technical solution: an LTCC multilayer duplexer equivalent circuit, comprising a common port, a low-frequency port and a high-frequency port, an inductor L1 and an inductor L2 are connected in series between the common port and the low-frequency port, a ground capacitor C1 is connected between the inductor L1 and the inductor L2, a ground capacitor C2 is connected between the inductor L2 and the low-frequency port. The common port and the high-frequency port are sequentially connected in series with a capacitor C3, a capacitor C4, an inductor L4 and a capacitor C8, a ground inductor L3 is connected between the capacitor C3 and the capacitor C4, a ground capacitor C6 is connected between the capacitor C4 and the inductor L4, a ground capacitor C7 is connected between the inductor L4 and the capacitor C8, a ground inductor L5 is connected between the capacitor C8 and the high-frequency port, a cross capacitor C5 is connected between the capacitor C4 and the inductor L4, and the other end of the cross capacitor C5 is connected between the common port and the capacitor C3.

[0007] The application also protects a duplex filter realizing an equivalent circuit of the LCTT multi-layer duplex filter, comprising a ceramic base, a connection port arranged on the bottom surface of the ceramic base and a circuit structure layer arranged inside the ceramic base, the circuit structure layer comprising: The first layer, the first layer, the second layer, the third layer, the fourth layer, the fifth layer and the sixth layer are printed on the ceramic medium substrate and are insulated from each other; The second layer, the first layer, the second layer and the third layer are printed on the ceramic medium substrate and are insulated from each other, the first layer is connected with the fifth layer of the first layer through a first conductive column, the first layer is connected with the first layer of the first layer through a second conductive column, and the second layer is connected with the second layer of the first layer through a third conductive column; The third layer, the first layer, the second layer, the third layer and the fourth layer are printed on the ceramic medium substrate and are insulated from each other, the third layer is connected with the third layer of the first layer through a fourth conductive column, and the fourth layer is connected with the third layer of the second layer through a fifth conductive column; The fourth layer, the first layer, the second layer and the third layer are printed on the ceramic medium substrate and are insulated from each other, the third layer is connected with the sixth layer of the first layer through a sixth conductive column, and the second layer is connected with the second layer of the third layer through a seventh conductive column; The fifth layer, the first layer, the second layer and the third layer are printed on the ceramic medium substrate and are insulated from each other, the third layer is connected with the first layer of the second layer through an eighth conductive column, the first layer is connected with the fourth layer of the first layer through a ninth conductive column, and the second layer is connected with the fourth layer of the third layer through a tenth conductive column; The sixth layer, the layer six first metal plane and the layer six second metal plane are printed on the ceramic dielectric substrate and are insulated from each other, the layer six first metal plane is connected with the layer four first metal plane through the eleventh conductive column, and the layer six second metal plane is connected with the layer four third metal plane through the twelfth conductive column; The seventh layer, the layer seven first metal coil, the layer seven second metal coil and the layer seven third metal coil are printed on the ceramic dielectric substrate and are insulated from each other, one end of the layer seven third metal coil is connected with the layer five second metal plane through the thirteenth conductive column, one end of the layer seven second metal coil is connected with the layer five first metal plane through the fourteenth conductive column, and one end of the layer seven first metal coil is connected with the layer six second metal plane through the fifteenth conductive column; The eighth layer, the layer eight first metal coil and the layer eight second metal coil are printed on the ceramic dielectric substrate and are insulated from each other, one end of the layer eight first metal coil is connected with the other end of the layer seven first metal coil through the sixteenth conductive column, and one end of the layer eight second metal coil is connected with the other end of the layer seven second metal coil through the seventeenth conductive column; The ninth layer, the layer nine first metal coil and the layer nine second metal coil are printed on the ceramic dielectric substrate and are insulated from each other, one end of the layer nine first metal coil is connected with the other end of the layer eight first metal coil through the eighteenth conductive column, and one end of the layer nine second metal coil is connected with the other end of the layer eight second metal coil through the nineteenth conductive column; The tenth layer, the layer ten first metal coil and the layer ten second metal coil are printed on the ceramic dielectric substrate and are insulated from each other, one end of the layer ten first metal coil is connected with the layer three first metal plane through the twentieth conductive column, one end of the layer ten second metal coil is connected with the layer three third metal plane through the twenty-first conductive column, the other end of the layer ten first metal coil is connected with the other end of the layer nine first metal coil through the twenty-second conductive column, and the other end of the layer ten second metal coil is connected with the other end of the layer nine second metal coil through the twenty-third conductive column; The eleventh layer, the layer eleven first metal coil is printed on the ceramic dielectric substrate, and one end of the layer eleven first metal coil is connected with one end of the layer ten first metal coil through the twenty-fourth conductive column; The twelfth layer, the twelfth layer first metal coil, the twelfth layer second metal coil and the twelfth layer third metal coil are printed on the ceramic dielectric substrate and are insulated from each other, one end of the twelfth layer second metal coil is connected with the layer four second metal plane through the twenty-fifth conductive column, one end of the twelfth layer third metal coil is connected with the other end of the layer seven third metal coil through the twenty-sixth conductive column, one end of the twelfth layer first metal coil is connected with the other end of the layer eleven first metal coil through the twenty-seventh conductive column; The thirteenth layer, the thirteenth layer first metal coil, the thirteenth layer second metal coil and the thirteenth layer third metal coil are printed on the ceramic dielectric substrate and are insulated from each other, one end of the thirteenth layer first metal coil is connected with the other end of the twelfth layer first metal coil through the twenty-eighth conductive column, one end of the thirteenth layer second metal coil is connected with one end of the twelfth layer second metal coil through the twenty-ninth conductive column, one end of the thirteenth layer third metal coil is connected with the other end of the twelfth layer third metal coil through the thirtieth conductive column; The fourteenth layer, the fourteenth layer first metal coil, the fourteenth layer second metal coil and the fourteenth layer third metal coil are printed on the ceramic dielectric substrate and are insulated from each other, one end of the fourteenth layer first metal coil is connected with the layer two second metal plane through the thirty-first conductive column, one end of the fourteenth layer second metal coil is connected with one end of the layer ten second metal coil through the thirty-second conductive column, one end of the fourteenth layer third metal coil is connected with the layer six first metal plane through the thirty-third conductive column, the other end of the fourteenth layer first metal coil is connected with the other end of the thirteenth layer first metal coil through the thirty-fourth conductive column, the other end of the fourteenth layer second metal coil is connected with the other end of the thirteenth layer second metal coil through the thirty-fifth conductive column, the other end of the fourteenth layer third metal coil is connected with the other end of the thirteenth layer third metal coil through the thirty-sixth conductive column.

[0008] Further, the connection port includes a first port, a second port, a third port, a fourth port, a fifth port and a sixth port.

[0009] Further, the first port, the third port and the fifth port are ground ports, the second port is the open port, the sixth port is the low frequency port, and the fourth port is the high frequency port.

[0010] Further, a first metal plane of the layer one is connected with the first port, a second metal plane of the layer one is connected with the second port, a third metal plane of the layer one is connected with the third port, a fourth metal plane of the layer one is connected with the fourth port, a fifth metal plane of the layer one is connected with the fifth port, and a sixth metal plane of the layer one is connected with the sixth port.

[0011] Further, a direction mark pattern is printed on the top surface of the ceramic substrate.

[0012] Further, the metal planes in the second layer to the sixth layer are all capacitive substrates.

[0013] Compared with the prior art, the present application has the advantages that: the present application is based on the LTCC technology, and adopts the lumped parameter model design to realize the special electrical performance requirements of the novel miniaturized, wideband and low insertion loss LTCC duplexer, the low frequency path adopts the 2-order low pass filter to constitute, the high frequency band forms the transmission zero point in the low frequency band by introducing the cross connection capacitor to enhance the suppression ability of the high frequency passband in the low frequency, and the high-order form is simple and effective to widen the passband range of the high frequency band. The present application not only effectively realizes the frequency division of the low frequency signal and the high frequency signal, but also effectively widens the high frequency passband bandwidth, has the advantages of miniaturization, low loss, high suppression, high isolation, high reliability, low cost, excellent consistency and suitability for large-scale production, and in addition, it also adapts to the development trend of the new electronic element integration and miniaturization. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 It is the equivalent circuit schematic diagram of the LTCC multilayer duplexer of the present application; Figure 2 It is the perspective schematic diagram of the duplexer of the present application; Figure 3 It is the internal structure schematic diagram of the duplexer of the present application; Figure 4 It is the electrical characteristic curve diagram of the duplexer of the present application; Figure 5 It is the first layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 6 It is the second layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 7 It is the third layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 8 It is the fourth layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 9 It is the fifth layer circuit plane structure schematic diagram of the duplexer of the present application Figure 10 It is the sixth layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 11 The seventh layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 12 The eighth layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 13 The ninth layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 14 The tenth layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 15 The eleventh layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 16 The twelfth layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 17 The thirteenth layer circuit plane structure schematic diagram of the duplexer of the present application; Figure 18 The fourteenth layer circuit plane structure schematic diagram of the duplexer of the present application. DETAILED DESCRIPTION

[0015] In order to facilitate the understanding of the present application, the present application will be described in more detail below in conjunction with the drawings and specific embodiments. It should be noted that when an element is described as "fixed to" another element, it can be directly on the other element or one or more intervening elements can be present therebetween. When an element is described as "connected to" another element, it can be directly connected to the other element or one or more intervening elements can be present therebetween. The terms "upper", "lower", "left", "right", "inner", "outer" and similar expressions used in the present specification are for the purpose of illustration only.

[0016] Unless otherwise defined, all technical and scientific terms used in the present specification are the same as those commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used in the present specification includes any and all combinations of one or more related listed items.

[0017] As shown in Figure 1 The present application protects a LTCC multilayer duplexer equivalent circuit, which comprises a common port 1, a low-frequency port 2 and a high-frequency port 3, in which the inductor L1 and the inductor L2 are connected in series between the common port 1 and the low-frequency port 2, the ground capacitor C1 is connected between the inductor L1 and the inductor L2, and the ground capacitor C2 is connected between the inductor L2 and the low-frequency port 2. The common port 1 and the high-frequency port 3 are connected in series with a capacitor C3, a capacitor C4, an inductor L4 and a capacitor C8, the capacitor C3 and the capacitor C4 are connected with a ground inductor L3, the capacitor C4 and the inductor L4 are connected with a ground capacitor C6, the inductor L4 and the capacitor C8 are connected with a ground capacitor C7, the capacitor C8 and the high-frequency port 3 are connected with a ground inductor L5, the capacitor C4 and the inductor L4 are connected with a cross capacitor C5, and the other end of the cross capacitor C5 is connected between the common port 1 and the capacitor C3.

[0018] Specifically, the equivalent circuit is combined by a low-frequency channel and a high-frequency channel, the low-frequency channel is a circuit connected in series between the common port 1 and the low-frequency port 2, and the low-frequency channel can provide a 617MHz-960MHz signal channel; the high-frequency channel is a circuit connected in series between the common port 1 and the high-frequency port 3, and the high-frequency channel can provide a 1427MHz-2690MHz signal channel. The ground capacitor C1 and the ground capacitor C2 form a zero point in the low-pass stop band, which enhances the out-of-band rejection of the low-pass filter, wherein the cross capacitor C5, the ground inductor L3 and the ground inductor L5 form a transmission zero point in the low-end stop band of the high-frequency channel, the ground capacitor C6 and the ground capacitor C7 form a transmission zero point in the high-end stop band of the high-frequency channel, which effectively improves the stop band attenuation of the high-frequency channel, and in addition, the high-order mode can effectively widen the high-frequency band bandwidth. The low-frequency port 2 is a port for input / output of the low-frequency band, and the high-frequency port 3 is a port for input / output of the high-frequency band.

[0019] As shown in Figures 2 to 18 The application also protects a duplex filter for realizing the equivalent circuit of the LCTT multi-layer duplex filter, which comprises a ceramic base, a connection port arranged on the bottom surface of the ceramic base and a circuit structure layer arranged inside the ceramic base, and the circuit structure layer comprises: A first layer, a first layer first metal plane 1-1, a first layer second metal plane 1-2, a first layer third metal plane 1-3, a first layer fourth metal plane 1-4, a first layer fifth metal plane 1-5 and a first layer sixth metal plane 1-6 are printed on the ceramic dielectric substrate and are insulated from each other; A second layer, a second layer first metal plane 2-1, a second layer second metal plane 2-2 and a second layer third metal plane 2-3 are printed on the ceramic dielectric substrate and are insulated from each other, the second layer first metal plane 2-1 is connected with the first layer fifth metal plane 1-5 through a first conductive column 4, the second layer first metal plane 2-1 is connected with the first layer first metal plane 1-1 through a second conductive column 5, and the second layer second metal plane 2-2 is connected with the first layer second metal plane 1-2 through a third conductive column 6; The third layer, the ceramic dielectric substrate is printed with mutually insulated layer three first metal plane 3-1, layer three second metal plane 3-2, layer three third metal plane 3-3 and layer three fourth metal plane 3-4, layer three third metal plane 3-3 and layer one third metal plane 1-3 are connected by the fourth conductive column 7, layer three fourth metal plane 3-4 and layer two third metal plane 2-3 are connected by the fifth conductive column 8;Wherein layer two first metal plane 2-1 and layer three first metal plane 3-1 form ground capacitor C1;Layer two second metal plane 2-2 and layer three second metal plane 3-2 form capacitor C3;Layer two third metal plane 2-3 and layer three third metal plane 3-3 form ground capacitor C6;Layer two second metal plane 2-2 and layer three fourth metal plane 3-4 form cross capacitor C5; The fourth layer, the ceramic dielectric substrate is printed with mutually insulated layer four first metal plane 4-1, layer four second metal plane 4-2 and layer four third metal plane 4-3, layer four third metal plane 4-3 and layer one sixth metal plane 1-6 are connected by the sixth conductive column 9, layer four second metal plane 4-2 and layer three second metal plane 3-2 are connected by the seventh conductive column 10;Wherein layer four first metal plane 4-1 and layer three third metal plane 3-3 form ground capacitor C7;Layer four second metal plane 4-2, layer three fourth metal plane 3-4 and layer five second metal plane 5-2 together form capacitor C4; The fifth layer, the ceramic dielectric substrate is printed with mutually insulated layer five first metal plane 5-1, layer five second metal plane 5-2 and layer five third metal plane 5-3, layer five third metal plane 5-3 and layer two first metal plane 2-1 are connected by the eighth conductive column 11, layer five first metal plane 5-1 and layer one fourth metal plane 1-4 are connected by the ninth conductive column 12, layer five second metal plane 5-2 layer three fourth metal plane 3-4 are connected by the tenth conductive column 13;Wherein layer five first metal plane 5-1, layer four first metal plane 4-1 and layer six first metal plane 6-1 together form capacitor C8;Layer five third metal plane 5-3, layer four third metal plane 4-3, layer two first metal plane 2-1 and layer six second metal plane 6-2 together form ground capacitor C2; The sixth layer, the ceramic dielectric substrate is printed with mutually insulated layer six first metal plane 6-1 and layer six second metal plane 6-2, layer six first metal plane 6-1 and layer four first metal plane 4-1 are connected by the eleventh conductive column 14, layer six second metal plane 6-2 and layer four third metal plane 4-3 are connected by the twelfth conductive column 15; The seventh layer, the ceramic dielectric substrate is printed with mutually insulated layer seven first metal coil 7-1, layer seven second metal coil 7-2 and layer seven third metal coil 7-3, one end (7-3b) of layer seven third metal coil 7-3 is connected with layer five second metal plane 5-2 through the thirteenth conductive column 16, one end (7-2a) of layer seven second metal coil 7-2 is connected with layer five first metal plane 5-1 through the fourteenth conductive column 17, one end (7-1b) of layer seven first metal coil 7-1 is connected with layer six second metal plane 6-2 through the fifteenth conductive column 18; The eighth layer, the ceramic dielectric substrate is printed with mutually insulated layer eight first metal coil 8-1 and layer eight second metal coil 8-2, one end (8-1b) of layer eight first metal coil 8-1 is connected with the other end (7-1a) of layer seven first metal coil 7-1 through the sixteenth conductive column 19, one end (8-2a) of layer eight second metal coil 8-2 is connected with the other end (7-2b) of layer seven second metal coil 7-2 through the seventeenth conductive column 20; The ninth layer, the ceramic dielectric substrate is printed with mutually insulated layer nine first metal coil 9-1 and layer nine second metal coil 9-2, one end (9-1b) of layer nine first metal coil 9-1 is connected with the other end (8-1a) of layer eight first metal coil 8-1 through the eighteenth conductive column 21, one end (9-2a) of layer nine second metal coil 9-2 is connected with the other end (8-2b) of layer eight second metal coil 8-2 through the nineteenth conductive column 22; The tenth layer, the ceramic dielectric substrate is printed with mutually insulated layer ten first metal coil 10-1 and layer ten second metal coil 10-2, one end (10-1a) of layer ten first metal coil 10-1 is connected with layer three first metal plane 3-1 through the twentieth conductive column 23, one end (10-2a) of layer ten second metal coil 10-2 is connected with layer three third metal plane 3-3 through the twenty first conductive column 24, the other end (10-1b) of layer ten first metal coil 10-1 is connected with the other end (9-1a) of layer nine first metal coil 9-1 through the twenty second conductive column 25, the other end (10-2b) of layer ten second metal coil 10-2 is connected with the other end (9-2b) of layer nine second metal coil 9-2 through the twenty third conductive column 26;Wherein layer seven first metal coil 7-1, layer eight first metal coil 8-1, layer nine first metal coil 9-1 and layer ten first metal coil 10-1 are combined into inductance L2;Layer seven second metal coil 7-2, layer eight second metal coil 8-2, layer nine second metal coil 9-2 and layer ten second metal coil 10-2 are combined into ground inductance L5; The eleventh layer, the first metal coil 11-1 is printed on the ceramic dielectric substrate, one end (marked as 11-1a) of the first metal coil 11-1 is connected with one end (marked as 10-1a) of the first metal coil 10-1 through the twenty-fourth conductive column 27; The twelfth layer, the first metal coil 12-1, the second metal coil 12-2 and the third metal coil 12-3 are printed on the ceramic dielectric substrate and insulated from each other, one end (marked as 12-2a) of the second metal coil 12-2 is connected with the second metal plane 4-2 through the twenty-fifth conductive column 28, one end (marked as 12-3b) of the third metal coil 12-3 is connected with the other end (marked as 7-3a) of the third metal coil 7-3 through the twenty-sixth conductive column 29, one end (marked as 12-1a) of the first metal coil 12-1 is connected with the other end (marked as 11-1b) of the first metal coil 11-1 through the twenty-seventh conductive column 30; The thirteenth layer, the first metal coil 13-1, the second metal coil 13-2 and the third metal coil 13-3 are printed on the ceramic dielectric substrate and insulated from each other, one end (marked as 13-1a) of the first metal coil 13-1 is connected with the other end (marked as 12-1b) of the first metal coil 12-1 through the twenty-eighth conductive column 31, one end (marked as 13-2a) of the second metal coil 13-2 is connected with one end (marked as 12-2b) of the second metal coil 12-2 through the twenty-ninth conductive column 32, one end (marked as 13-3b) of the third metal coil 13-3 is connected with the other end (marked as 12-3a) of the third metal coil 12-3 through the thirtieth conductive column 33; The fourteenth layer, the ceramic dielectric substrate is printed with the mutually insulated fourteenth layer first metal coil 14-1, the fourteenth layer second metal coil 14-2 and the fourteenth layer third metal coil 14-3, one end (marked as 14-1a) of the fourteenth layer first metal coil 14-1 is connected with the second layer second metal plane 2-2 through the thirty-first conductive column 34, one end (marked as 14-2a) of the fourteenth layer second metal coil 14-2 is connected with one end (marked as 10-2a) of the tenth layer second metal coil 10-2 through the thirty-second conductive column 35, one end (marked as 14-3b) of the fourteenth layer third metal coil 14-3 is connected with the sixth layer first metal plane 6-1 through the thirty-third conductive column 36, the other end (marked as 14-1b) of the fourteenth layer first metal coil 14-1 is connected with the other end (marked as 13-1b) of the thirteenth layer first metal coil 13-1 through the thirty-fourth conductive column 37, the other end (marked as 14-2b) of the fourteenth layer second metal coil 14-2 is connected with the other end (marked as 13-2b) of the thirteenth layer second metal coil 13-2 through the thirty-fifth conductive column 38, the other end (marked as 14-3a) of the fourteenth layer third metal coil 14-3 is connected with the other end (marked as 13-3a) of the thirteenth layer third metal coil 13-3 through the thirty-sixth conductive column 39. The eleventh layer first metal coil 11-1, the twelfth layer first metal coil 12-1, the thirteenth layer first metal coil 13-1 and the fourteenth layer first metal coil 14-1 are combined into an inductor L1; the twelfth layer second metal coil 12-2, the thirteenth layer second metal coil 13-2 and the fourteenth layer second metal coil 14-2 are combined into a ground inductor L3; and the seventh layer third metal coil 7-3, the twelfth layer third metal coil 12-3, the thirteenth layer third metal coil 13-3 and the fourteenth layer third metal coil 14-3 are combined into an inductor L4.

[0020] The connection ports include a first port P1, a second port P2, a third port P3, a fourth port P4, a fifth port P5 and a sixth port P6. The first port P1, the third port P3 and the fifth port P5 are ground ports, the second port P2 is an open port 1, the sixth port P6 is a low-frequency port 2, and the fourth port P4 is a high-frequency port 3. The first layer first metal plane 1-1 is connected with the first port P1, the first layer second metal plane 1-2 is connected with the second port P2, the first layer third metal plane 1-3 is connected with the third port P3, the first layer fourth metal plane 1-4 is connected with the fourth port P4, the first layer fifth metal plane 1-5 is connected with the fifth port P5, and the first layer sixth metal plane 1-6 is connected with the sixth port P6. The top surface of the ceramic substrate is printed with a direction identification pattern mark. It should be noted that the metal planes in the second layer to the sixth layer are all capacitor substrates.

[0021] Reference Figure 4As shown, in the brackets of each curve name, 1 is a common port, 2 is a high-frequency port output, and 3 is a low-frequency port output. Figures 5 to 18 In the figure, each circle represents the cross section of the corresponding conductive column, which is not labeled, and those skilled in the art can infer from the figure and without doubt obtain the corresponding figure number of the conductive column, and the corresponding figure number can be clearly understood, and here is not repeated. Figure 3 In the figure, each circle represents the cross section of the corresponding conductive column, which is not labeled, and those skilled in the art can infer from the figure and without doubt obtain the corresponding figure number of the conductive column, and the corresponding figure number can be clearly understood, and here is not repeated.

[0022] The present application is based on LTCC technology, and adopts a lumped parameter model to design and realize the special electrical performance requirements of a novel small-sized, wide-band and low-insertion-loss LTCC duplexer. A 2-order low-pass filter is used for a low-frequency path, a cross-over capacitor is introduced to form a transmission zero point in a low-frequency band of a high-frequency path to enhance the suppression ability of the high-frequency passband at low frequencies, and a high-order form is used to simply and effectively widen the passband range of the high-frequency band. The present application not only effectively realizes the frequency division of low-frequency signals and high-frequency signals, and effectively widens the high-frequency passband bandwidth, but also has the advantages of small size, low loss, high suppression, high isolation, high reliability, low cost, excellent consistency, and suitability for large-scale production, and the like. In addition, the present application also adapts to the development trend of new electronic component integration and miniaturization.

[0023] In summary, the technical scheme of the present application can effectively achieve the above-mentioned purposes, and the structure and functional principle of the present application have been fully verified in the embodiments, and the expected effects and purposes can be achieved. Without departing from the principles and essence of the present application, various changes or modifications can be made to the embodiments of the present application. Therefore, the present application includes all alternatives within the scope of the patent application, and any equivalent changes made within the scope of the patent application are within the scope of the present application.

Claims

1. An equivalent circuit for an LTCC multilayer duplexer, comprising a common port (1), a low-frequency port (2), and a high-frequency port (3), characterized in that: An inductor L1 and an inductor L2 are connected in series between the common port (1) and the low-frequency port (2). A grounding capacitor C1 is connected between the inductor L1 and the inductor L2. A grounding capacitor C2 is connected between the inductor L2 and the low-frequency port (2). A capacitor C3, a capacitor C4, an inductor L4, and a capacitor C8 are connected in series between the common port (1) and the high-frequency port (3). A grounding inductor L3 is connected between the capacitor C3 and the capacitor C4. A grounding capacitor C6 is connected between the capacitor C4 and the inductor L4. A grounding capacitor C7 is connected between the inductor L4 and the capacitor C8. A grounding inductor L5 is connected between the capacitor C8 and the high-frequency port (3). A bridging capacitor C5 is connected between the capacitor C4 and the inductor L4. The other end of the bridging capacitor C5 is connected between the common port (1) and the capacitor C3.

2. A duplexer that implements the equivalent circuit of the LCTT multilayer duplexer as described in claim 1, characterized in that, It includes a ceramic substrate, a connection port disposed on the bottom surface of the ceramic substrate, and a circuit structure layer disposed inside the ceramic substrate, wherein the circuit structure layer includes: The first layer consists of a first metal plane (1-1), a second metal plane (1-2), a third metal plane (1-3), a fourth metal plane (1-4), a fifth metal plane (1-5), and a sixth metal plane (1-6) that are mutually insulated on a ceramic dielectric substrate. The second layer consists of a first metal plane (2-1), a second metal plane (2-2), and a third metal plane (2-3) that are mutually insulated on a ceramic dielectric substrate. The first metal plane (2-1) of the second layer is connected to the fifth metal plane (1-5) of the first layer through a first conductive post (4). The first metal plane (2-1) of the second layer is connected to the first metal plane (1-1) of the first layer through a second conductive post (5). The second metal plane (2-2) of the second layer is connected to the second metal plane (1-2) of the first layer through a third conductive post (6). The third layer consists of three mutually insulated metal planes: a first metal plane (3-1), a second metal plane (3-2), a third metal plane (3-3), and a fourth metal plane (3-4). The third metal plane (3-3) is connected to the third metal plane (1-3) of the first layer via a fourth conductive post (7), and the fourth metal plane (3-4) is connected to the third metal plane (2-3) of the second layer via a fifth conductive post (8). The fourth layer consists of a first metal plane (4-1), a second metal plane (4-2), and a third metal plane (4-3) that are mutually insulated on a ceramic dielectric substrate. The third metal plane (4-3) is connected to the sixth metal plane (1-6) of the first layer by a sixth conductive post (9), and the second metal plane (4-2) of the fourth layer is connected to the second metal plane (3-2) of the third layer by a seventh conductive post (10). The fifth layer consists of three mutually insulated metal planes: a first metal plane (5-1), a second metal plane (5-2), and a third metal plane (5-3). The third metal plane (5-3) is connected to the first metal plane (2-1) via an eighth conductive post (11). The first metal plane (5-1) is connected to the fourth metal plane (1-4) via a ninth conductive post (12). The second metal plane (5-2) and the fourth metal plane (3-4) are connected via a tenth conductive post (13). The sixth layer has a first metal plane (6-1) and a second metal plane (6-2) of the sixth layer printed on a ceramic dielectric substrate. The first metal plane (6-1) of the sixth layer is connected to the first metal plane (4-1) of the fourth layer through an eleventh conductive post (14), and the second metal plane (6-2) of the sixth layer is connected to the third metal plane (4-3) of the fourth layer through a twelfth conductive post (15). The seventh layer has a first metal coil (7-1), a second metal coil (7-2), and a third metal coil (7-3) printed on a ceramic dielectric substrate. One end of the third metal coil (7-3) is connected to the second metal plane (5-2) of the fifth layer through a thirteenth conductive post (16). One end of the second metal coil (7-2) is connected to the first metal plane (5-1) of the fifth layer through a fourteenth conductive post (17). One end of the first metal coil (7-1) is connected to the second metal plane (6-2) of the sixth layer through a fifteenth conductive post (18). The eighth layer has a first metal coil (8-1) and a second metal coil (8-2) printed on a ceramic dielectric substrate, which are insulated from each other. One end of the first metal coil (8-1) is connected to the other end of the first metal coil (7-1) of the seventh layer through a sixteenth conductive post (19), and one end of the second metal coil (8-2) of the eighth layer is connected to the other end of the second metal coil (7-2) of the seventh layer through a seventeenth conductive post (20). The ninth layer has a first metal coil (9-1) and a second metal coil (9-2) printed on a ceramic dielectric substrate, which are insulated from each other. One end of the first metal coil (9-1) is connected to the other end of the first metal coil (8-1) of the eighth layer through an eighteenth conductive post (21), and one end of the second metal coil (9-2) of the ninth layer is connected to the other end of the second metal coil (8-2) of the eighth layer through a nineteenth conductive post (22). The tenth layer has a first metal coil (10-1) and a second metal coil (10-2) printed on a ceramic dielectric substrate, which are insulated from each other. One end of the first metal coil (10-1) is connected to the first metal plane (3-1) of the third layer through the twentieth conductive post (23). One end of the second metal coil (10-2) is connected to the third metal plane (3-3) of the third layer through the twentieth conductive post (24). The other end of the first metal coil (10-1) is connected to the other end of the first metal coil (9-1) of the ninth layer through the twentieth conductive post (25). The other end of the second metal coil (10-2) is connected to the other end of the second metal coil (9-2) of the ninth layer through the twentieth conductive post (26). The eleventh layer has a first metal coil (11-1) printed on a ceramic dielectric substrate. One end of the first metal coil (11-1) of the eleventh layer is connected to one end of the first metal coil (10-1) of the tenth layer through a twenty-fourth conductive post (27). The twelfth layer has a first metal coil (12-1), a second metal coil (12-2), and a third metal coil (12-3) printed on a ceramic dielectric substrate. One end of the second metal coil (12-2) is connected to the second metal plane (4-2) of the fourth layer through a twenty-fifth conductive post (28). One end of the third metal coil (12-3) is connected to the other end of the third metal coil (7-3) of the seventh layer through a twenty-sixth conductive post (29). One end of the first metal coil (12-1) is connected to the other end of the first metal coil (11-1) of the eleventh layer through a twenty-seventh conductive post (30). The thirteenth layer has three mutually insulated metal coils: a first metal coil (13-1), a second metal coil (13-2), and a third metal coil (13-3). One end of the first metal coil (13-1) is connected to the other end of the first metal coil (12-1) of the twelfth layer through a twenty-eighth conductive post (31). One end of the second metal coil (13-2) is connected to the other end of the second metal coil (12-2) of the twelfth layer through a twenty-ninth conductive post (32). One end of the third metal coil (13-3) is connected to the other end of the third metal coil (12-3) of the twelfth layer through a thirtieth conductive post (33). The fourteenth layer comprises three mutually insulated metal coils: a first metal coil (14-1), a second metal coil (14-2), and a third metal coil (14-3). One end of the first metal coil (14-1) is connected to the second metal plane (2-2) of the second layer via thirty-one conductive posts (34). One end of the second metal coil (14-2) is connected to one end of the second metal coil (10-2) of the tenth layer via thirty-two conductive posts (35). One end of the third metal coil (14-3) is connected to the first metal plane (2-2) of the sixth layer via thirty-two conductive posts (35). The metal planes (6-1) are connected by thirty-three conductive posts (36), the other end of the first metal coil (14-1) of layer fourteen is connected to the other end of the first metal coil (13-1) of layer thirteen by thirty-four conductive posts (37), the other end of the second metal coil (14-2) of layer fourteen is connected to the other end of the second metal coil (13-2) of layer thirteen by thirty-five conductive posts (38), and the other end of the third metal coil (14-3) of layer fourteen is connected to the other end of the third metal coil (13-3) of layer thirteen by thirty-six conductive posts (39).

3. The duplexer according to claim 2, characterized in that: The connection ports include a first port (P1), a second port (P2), a third port (P3), a fourth port (P4), a fifth port (P5), and a sixth port (P6).

4. The duplexer according to claim 3, characterized in that: The first port (P1), the third port (P3) and the fifth port (P5) are all grounded ports, the second port (P2) is the public port (1), the sixth port (P6) is the low-frequency port (2), and the fourth port (P4) is the high-frequency port (3).

5. The duplexer according to claim 4, characterized in that: The first metal plane (1-1) of layer one is connected to the first port (P1), the second metal plane (1-2) of layer one is connected to the second port (P2), the third metal plane (1-3) of layer one is connected to the third port (P3), the fourth metal plane (1-4) of layer one is connected to the fourth port (P4), the fifth metal plane (1-5) of layer one is connected to the fifth port (P5), and the sixth metal plane (1-6) of layer one is connected to the sixth port (P6).

6. The duplexer according to claim 2, characterized in that: The top surface of the ceramic substrate is printed with a directional marking pattern.

7. The duplexer according to claim 2, characterized in that: The metal planes in the second to sixth layers are all capacitor substrates.

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