Flit decoder, communication device, and method of operating flit decoder

Abstract

A flit decoder, a communication device, and a method of operating the flit decoder are provided. The flit decoder includes: an error correction code (ECC) decoder that generates an ECC decoded packet segment based on the packet segment; an interleaver circuit generating an interleaved data packet based on the ECC decoded data packet segments; a cyclic redundancy check (CRC) decoder generating an enable signal in response to a CRC decoding operation failure of the interleaved data packet; a reliability calculator that generates bitstream information for identifying first to Nth estimated error symbols of the packet segment; and a post decoder.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0130139, filed on September 25, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to packet decoding, and more specifically, to a flit (flow control unit) decoder that generates decoded packet fragments, a communication device including the flit decoder, and a method for operating the flit decoder. Background Technology

[0003] Electronic systems manage data packets representing various types of information. Electronic systems may include various components (such as processors, memory, etc.). Components can transmit data packets via communication interface circuits. Communication devices can provide encoded data packets to other communication devices to ensure the reliability of the data packets, and can decode data packets received from other communication devices. Communication devices can correct erroneous bits in data packets by performing data packet decoding operations.

[0004] Communication devices may have error correction capabilities. When the error level of a data packet (e.g., the number of erroneous bits in the data packet) does not exceed the error correction capability, the communication device can correct the erroneous bits of the data packet. When the error level of a data packet exceeds the error correction capability, the communication device can request the retransmission of the data packet from another communication device. Retransmission of data packets can reduce the communication speed between communication devices within the transmission system. Summary of the Invention

[0005] One aspect is to provide a flit decoder for generating decoded data packet fragments, a communication device including the flit decoder, and a method for operating the flit decoder.

[0006] According to one aspect of one or more embodiments, a flit decoder is provided, the flit decoder comprising: an error correction code (ECC) decoder configured to: generate a first ECC-decoded data packet fragment based on a first data packet fragment; an interleaver circuit configured to: generate a first interleaved data packet based on the first ECC-decoded data packet fragment; a cyclic redundancy check (CRC) decoder configured to: generate an enable signal based on a first CRC decoding operation failure of the first interleaved data packet; a reliability calculator configured to: generate bitstream information for identifying a first estimated error symbol to an Nth estimated error symbol among a plurality of symbols of the first data packet fragment; and a post-decoder. The post-decoder is configured to: in response to an enable signal, generate first index values ​​to Nth index values ​​corresponding to the first estimated error symbols to the Nth estimated error symbols, respectively, based on bitstream information; generate first candidate information to Mth candidate information, the first candidate information to Mth candidate information indicating two of the first index values ​​to Nth index values ​​that are combined without repetition and without regard to order; generate first erasure decoding data packet fragments to Mth erasure decoding data packet fragments based on the first data packet fragment and the first candidate information to the Mth candidate information; and provide one of the selected first erasure decoding data packet fragments to the Mth erasure decoding data packet fragments to the interleaver circuit. "N" is a natural number less than the number of the plurality of symbols, and "M" is... N C2.

[0007] According to another aspect of one or more embodiments, a communication apparatus is provided, the communication apparatus comprising: input / output (I / O) circuitry including a plurality of transmitters and a plurality of receivers; a flit encoder configured to provide a first data packet to the plurality of transmitters; and a flit decoder configured to receive a second data packet from the plurality of receivers. The flit decoder includes: an error correction code (ECC) decoder configured to generate ECC-decoded data packet fragments based on data packet fragments of the second data packet; an interleaver circuit configured to generate interleaved data packets based on the ECC-decoded data packet fragments; a cyclic redundancy check (CRC) decoder configured to generate an enable signal based on a failure of a CRC decoding operation on the interleaved data packets; a reliability calculator configured to generate bitstream information for identifying a first estimated error symbol to an Nth estimated error symbol among a plurality of symbols of the data packet fragments; and a post-decoder. The post-decoder is configured to: in response to an enable signal, generate first index values ​​to Nth index values ​​corresponding to the first estimated error symbols to the Nth estimated error symbols, respectively, based on bitstream information; generate first candidate information to Mth candidate information, the first candidate information to Mth candidate information indicating two of the first index values ​​to Nth index values ​​that are combined without repetition and without regard to order; generate first erasure decoding data packet fragments to Mth erasure decoding data packet fragments based on the first data packet and the first candidate information to the Mth candidate information; and provide one of the selected first erasure decoding data packet fragments to the Mth erasure decoding data packet fragments to the interleaver circuit. "N" is a natural number less than the number of the plurality of symbols, and "M" is... N C2.

[0008] According to another aspect of one or more embodiments, a method for operating a flit decoder is provided, the method comprising: receiving a data packet including a first data packet fragment, a second data packet fragment, and a third data packet fragment; generating a first error correction code (ECC) decoded data packet fragment, a second ECC decoded data packet fragment, and a third ECC decoded data packet fragment based on the first data packet fragment, the second data packet fragment, and the third data packet fragment; generating a first interleaved data packet based on the first ECC decoded data packet fragment, the second ECC decoded data packet fragment, and the third ECC decoded data packet fragment; generating an enable signal based on a failure of a first cyclic redundancy check (CRC) decoding operation on the first interleaved data packet; generating bitstream information for identifying a first estimated error symbol to an Nth estimated error symbol among a plurality of symbols of the first data packet fragment, where "N" is a natural number less than the number of the plurality of symbols; generating first index values ​​to Nth index values ​​respectively corresponding to the first estimated error symbols to the Nth estimated error symbols according to the enable signal and the bitstream information; generating first candidate information to Mth candidate information, the first candidate information to the Mth candidate information indicating two of the first index values ​​to the Nth index values ​​that are combined without repetition and without regard to order, where "M" is... N C2; Based on the first data packet fragment and the first candidate information to the Mth candidate information, generate the first erasure decoding data packet fragment to the Mth erasure decoding data packet fragment; select one of the first erasure decoding data packet fragment to the Mth erasure decoding data packet fragment as the post-decoded data packet fragment; and based on the post-decoded data packet fragment, the second ECC decoded data packet fragment, and the third ECC decoded data packet fragment, generate the second interleaved data packet. Attached Figure Description

[0009] The above and other aspects will become clear from the detailed description of embodiments of this disclosure with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating an electronic system according to an embodiment.

[0011] Figure 2 This illustrates some embodiments. Figure 1 A block diagram of the communication device of an electronic system.

[0012] Figure 3 This illustrates some embodiments. Figure 2 A block diagram of the flit decoder for a communication device.

[0013] Figure 4 This is a graph showing the voltage levels of data packets according to some embodiments.

[0014] Figure 5This is a table showing data packets in flit mode according to some embodiments.

[0015] Figure 6 This is a diagram illustrating a packet fragment in flit mode according to some embodiments.

[0016] Figure 7 This is a diagram illustrating interleaved data packets according to some embodiments.

[0017] Figure 8 This is a flowchart illustrating how the flit decoder operates.

[0018] Figure 9 This is a flowchart illustrating a method for operating a flit decoder according to some embodiments.

[0019] Figure 10 This is a diagram illustrating a method of operating a flit decoder according to some embodiments.

[0020] Figure 11 This illustrates some embodiments. Figure 10 A diagram illustrating the bitstream information of the flit decoder.

[0021] Figure 12 This illustrates some embodiments. Figure 10 A diagram illustrating the data packet fragments decoded by the flit decoder.

[0022] Figure 13 This illustrates some embodiments. Figure 10 A diagram of the post-decoder of the flit decoder.

[0023] Figure 14 This illustrates some embodiments. Figure 13 A diagram of the erase position calculator for the post-decoder.

[0024] Figure 15 This is a flowchart illustrating a method for operating a flit decoder according to some embodiments. Detailed Implementation

[0025] In the following description, various embodiments will be clearly and in detail so that those skilled in the art can readily implement them.

[0026] Figure 1 This is a block diagram illustrating an electronic system according to an embodiment. (Refer to...) Figure 1The electronic system 10 can manage various types of information or data. For example, the electronic system 10 can be implemented as a computing system configured to process various types of information (such as a personal computer (PC), laptop computer, computer, server, workstation, tablet PC, smartphone, digital camera, and / or black box). In some embodiments, the electronic system 10 can be implemented as a storage system, server system, database server, etc., for managing large amounts of user data.

[0027] The electronic system 10 may include multiple components for managing various types of information or data. For example, these components may be implemented as a processor, a volatile memory device, a non-volatile memory device, a network interface card (NIC), a graphics card, etc. The components may be used as means for transmitting data packets (e.g., the first communication device 100 and the second communication device 200). The data packets may represent various types of information or data.

[0028] The electronic system 10 may include a communication interface circuit 11, a first communication device 100, and a second communication device 200. The first communication device 100 and the second communication device 200 may also be referred to as the first component and the second component of the electronic system 10, respectively. The first communication device 100 and the second communication device 200 can transmit data packets through the communication interface circuit 11.

[0029] The communication interface circuit 11 provides an interface between the first communication device 100 and the second communication device 200. For example, in one embodiment, the communication interface circuit 11 may be implemented as a Peripheral Component Interconnect Fast (PCIe) communication interface circuit. The communication interface circuit 11 may support a PCIe link between the first communication device 100 and the second communication device 200.

[0030] The first communication device 100 may include a transaction layer TL1, a data link layer DL1, and a physical layer PL1. The transaction layer TL1, the data link layer DL1, and the physical layer PL1 may also be referred to as the top layer, the middle layer, and the bottom layer, respectively.

[0031] The Transaction Layer 1 (TL1) is responsible for decomposing and assembling Transaction Layer Protocol (TLP) packets. TLPs are used to transmit transactions such as reads and writes, as well as specific types of events. TL1 manages credit-based flow control regarding TLPs. All request packets requiring a response packet are implemented as split transactions. Each packet includes a unique identifier that ensures the response packet is delivered to the correct originator. The packet format supports different address types depending on the transaction type (e.g., memory, I / O, configuration, message, etc.). The Transaction Layer supports four address spaces: three PCI address spaces (e.g., memory, I / O, and configuration) and a message space.

[0032] The Data Link Layer (DL1) acts as an intermediate layer between the Transaction Layer (TL1) and the Physical Layer (PL1). DL1 is responsible for link management and data integrity, including error detection and correction. The sending side of DL1 receives the Data Protection Token (TLP) assembled by TL1, calculates and applies the Data Protection Code and TLP sequence number, and submits them to PL1 for transmission via communication interface circuit 11. The receiving side of DL1 checks the integrity of the received TLPs and submits them to TL1 for further processing. When one or more TLP errors are detected, DL1 requests a retransmission of the TLP until the information is correctly received or the PCIe link is determined to have failed. DL1 generates and consumes packets for PCIe link management functions. To distinguish these packets from the TLPs used by TL1, packets generated and consumed by DL1 are referred to as Data Link Layer Packets (DLPs).

[0033] The physical layer PL1 may include circuitry for interface operation, such as drivers, input buffer circuitry, parallel-to-serial (PS) conversion circuitry, serial-to-parallel (SP) conversion circuitry, phase-locked loop (PLL) circuitry, and / or impedance matching circuitry. The physical layer PL1 performs logic functions related to interface initialization and maintenance. The physical layer PL1 can exchange information in a specific format with the data link layer DL1. The physical layer PL1 can convert information received from the data link layer DL1 into an appropriate serialization format and can transmit the converted information through the communication interface circuitry 11 at a frequency and bandwidth compatible with other components, such as the second communication device 200.

[0034] The physical layer PL1 may include a transmitter Tx, a receiver Rx, logic subblocks, and electrical subblocks. The transmitter Tx can send data packets to the receiver Rx of the second communication device 200 via the communication interface circuit 11. The receiver Rx can receive data packets from the transmitter Tx of the second communication device 200 via the communication interface circuit 11.

[0035] The logic subblock may include a transmitting section and a receiving section. The transmitting section prepares information received from the data link layer DL1 for transmission via the electrical subblock, and the receiving section identifies and prepares information received via the communication interface circuit 11 to be transmitted to the data link layer DL1. The logic subblock directs the control and management of the physical layer PL1's functions. The logic subblock can support two data flow modes. These two data flow modes may include a flit mode and a non-flit mode.

[0036] Flit mode is supported in PCIe 6.0 or next-generation PCIe (e.g., PCIe 7.0). Packets in flit mode can include TLP symbols, DLP symbols, Cyclic Redundancy Check (CRC) symbols, Error Correction Code (ECC) symbols, etc. See below for further details. Figure 5 This provides a more detailed description of packets in flit mode. Non-flit mode indicates a situation where flit mode is not applied.

[0037] The electrical subblock supports non-return-to-zero (NRZ) signaling, pulse amplitude modulation (PAM)-4 signaling, reference clock architecture, spread spectrum clock, reduced swing mode for low-power link operation, in-band receiver detection and electrical idle detection, channel compatibility methods, adaptive transmitter equalization and reference receiver equalization, data channel merging, and AC coupling channels. For example, the electrical subblock can perform analog-to-digital conversion (ADC) operations and equalization on electrical signals received through communication interface circuit 11, and can provide the converted signals to the logic subblock.

[0038] The second communication device 200 may include a transaction layer TL2, a data link layer DL2, and a physical layer PL2. Similar to the physical layer PL1 of the first communication device 100, the physical layer PL2 may include a transmitter Tx, a receiver Rx, logic subblocks, and electrical subblocks. The characteristics of the transaction layer TL2, data link layer DL2, and physical layer PL2 of the second communication device 200 are similar to those of the transaction layer TL1, data link layer DL1, and physical layer PL1 of the first communication device 100. Therefore, additional descriptions of the characteristics of the transaction layer TL2, data link layer DL2, and physical layer PL2 of the second communication device 200 are omitted to avoid redundancy.

[0039] Figure 2 This illustrates some embodiments. Figure 1 A block diagram of the communication device. (Refer to...) Figure 1 and Figure 2 The first communication device 100 may include a flit encoder 110, a flit decoder 120, and an I / O circuit 130.

[0040] The flit encoder 110 may correspond to the data link layer DL1 and the physical layer PL1. For example, the flit encoder 110 may be implemented as part of the data link layer DL1, part of the physical layer PL1, or a combination thereof.

[0041] The flit encoder 110 supports the flit mode of the PCIe standard. The flit encoder 110 can encode packets conforming to the flit mode format. In flit mode, packets can include symbols based on Reed Solomon (RS) codes. RS-based symbols can be 1 byte in size and can correspond to four PAM-4 symbols, each PAM-4 symbol being 2 bits in size.

[0042] More specifically, the flit encoder 110 may receive TLPs from the transaction layer TL1 or the data link layer DL1. A TLP may be a set of TLP symbols, and a TLP symbol may have a size of 1 byte (i.e., 8 bits). The flit encoder 110 may receive DLPs from the data link layer DL1. A DLP may be a set of DLP symbols, and a DLP symbol may have a size of 1 byte.

[0043] The flit encoder 110 may include a CRC encoder 111 and an ECC encoder 112. The CRC encoder 111 generates CRC parity symbols based on CRC encoding operations. A CRC parity symbol may be 1 byte in size. The CRC parity symbol is used to determine whether error correction performed using the CRC parity symbol passes or fails. A pass indicates that the integrity of the corrected symbol has been verified. A failure indicates that the integrity of the corrected symbol has not been verified.

[0044] The ECC encoder 112 can generate ECC parity symbols based on ECC encoding operations. An ECC parity symbol can be 1 byte in size. ECC parity symbols can be used to correct erroneous symbols among symbols encoded together by ECC encoding operations. When the position of an erroneous symbol is specified, more erroneous symbols can be corrected using the same ECC parity symbol.

[0045] The flit encoder 110 can generate flit-mode data packets based on TLP symbols, DLP symbols, CRC parity symbols, and ECC parity symbols. The flit encoder 110 can provide flit-mode data packets to the first transmitter Tx1 to the Pth transmitter TxP of the I / O circuit 130. The data packets can be provided to the second communication device 200 through the I / O circuit 130.

[0046] The flit decoder 120 may correspond to the data link layer DL1 and the physical layer PL1. For example, the flit decoder 120 may be implemented as a part of the data link layer DL1, a part of the physical layer PL1, or a combination thereof.

[0047] The flit decoder 120 supports the flit mode of the PCIe standard. The flit decoder 120 can decode data packets conforming to the flit mode format. More specifically, the flit decoder 120 can receive flit mode data packets from multiple receivers Rx1 to RxP of the I / O circuit 130. The data packets can be data packets received from the second communication device 200 via the I / O circuit 130. Data packets in flit mode may include TLP symbols, DLP symbols, CRC parity symbols, and ECC parity symbols.

[0048] The flit decoder 120 may include a CRC decoder 121 and an ECC decoder 122. The ECC decoder 122 can perform ECC decoding based on packets in flit mode. The CRC decoder 121 can perform CRC decoding based on ECC-decoded packets. When the CRC decoding operation fails, the CRC decoder 121 may request a subsequent decoding operation, or it may request that the packet be retransmitted to the second communication device 200. See below for further details. Figure 3 To describe the decoding operation in more detail. When the CRC decoding operation is successful, the CRC decoder 121 can provide the TLP to the transaction layer TL1 or the data link layer DL1, and can also provide the DLP to the data link layer DL1.

[0049] I / O circuitry 130 may correspond to physical layer PL1. For example, I / O circuitry 130 may be implemented as part of physical layer PL1.

[0050] I / O circuitry 130 can be connected to data channels P through P. For example, "P" can be 1, 2, 4, 8, or 16, but embodiments are not limited thereto, and the number of data channels "P" can be varied. A data channel can represent a PCIe channel of communication interface circuitry 11. Data channels can correspond to a transmitter and a receiver. The transmitter can output data packets in a differential signal format to the data channel. The receiver can receive data packets in a differential signal format from the data channel.

[0051] I / O circuitry 130 may include first transmitters Tx1 to P-th transmitters TxP and first receivers Rx1 to P-th receivers RxP. The first transmitter Tx1 and the first receiver Rx1 may be connected to a first data channel. A second transmitter Tx2 and a second receiver Rx2 may be connected to a second data channel. As described above, the P-th transmitter TxP and the P-th receiver RxP may be connected to a P-th data channel.

[0052] The first transmitter Tx1 to the Pth transmitter TxP can receive data packets in the flit mode from the flit encoder 110, and can provide the data packets in the flit mode to the second communication device 200 through the first data channel to the Pth data channel.

[0053] The first receiver Rx1 to the Pth receiver RxP can receive data packets in flit mode from the second communication device 200 through the first data channel to the Pth data channel, and can provide the data packets in flit mode to the flit decoder 120.

[0054] Figure 3 This illustrates some embodiments. Figure 2 A block diagram of the flit decoder. (Refer to...) Figure 2 and Figure 3 The flit decoder 120 may include a CRC decoder 121, an ECC decoder 122, an interleaver circuit 123, a reliability calculator 124, a post-decoder 125, and a packet interface circuit 126.

[0055] ECC decoder 122 can receive data packets in flit mode. The data packets can be 256 bytes in size. The data packets may include a first data packet fragment PF1, a second data packet fragment PF2, and a third data packet fragment PF3. ECC decoder 122 can generate the first data packet fragment PF1 to the third data packet fragment PF3 based on data packet allocation operations, and can generate the first ECC-decoded data packet fragment PFDe1, the second ECC-decoded data packet fragment PFDe2, and the third ECC-decoded data packet fragment PFDe3 based on the ECC decoding operations of the first data packet fragment PF1 to the third data packet fragment PF3.

[0056] ECC decoder 122 may include packet distributor 122d, first ECC sub-decoder 122e1, second ECC sub-decoder 122e2 and third ECC sub-decoder 122e3.

[0057] The packet distributor 122d can generate a first packet fragment PF1, a second packet fragment PF2, and a third packet fragment PF3 based on packet distribution operations. The first packet fragment PF1 can be 86 bytes in size. The second packet fragment PF2 can be 85 bytes in size. The third packet fragment PF3 can be 85 bytes in size.

[0058] Packet distributor 122d can provide a first packet fragment PF1 to a first ECC sub-decoder 122e1. Packet distributor 122d can provide a second packet fragment PF2 to a second ECC sub-decoder 122e2. Packet distributor 122d can provide a third packet fragment PF3 to a third ECC sub-decoder 122e3. Packet distributor 122d can provide the first packet fragment PF1 to the third packet fragment PF3 to a reliability calculator 124. Packet distributor 122d can provide the first packet fragment PF1 to the third packet fragment PF3 to a post-decoder 125.

[0059] The first ECC sub-decoder 122e1 can generate a first ECC-decoded data packet fragment PFDe1 based on the ECC decoding operation of the first data packet fragment PF1. The first ECC-decoded data packet fragment PFDe1 can have a size of 84 bytes. For example, the first data packet fragment PF1 may include two ECC parity symbols. The first ECC sub-decoder 122e1 can perform ECC decoding operations on the remaining 84 symbols of the first data packet fragment PF1 based on the two ECC parity symbols to generate the first ECC-decoded data packet fragment PFDe1.

[0060] The first ECC sub-decoder 122e1 can correct one erroneous symbol among the symbols of the first data packet fragment PF1. The first ECC sub-decoder 122e1 can perform ECC decoding regardless of the position of the erroneous symbol (e.g., which symbol is the erroneous symbol among the 86 symbols corresponding to the first data packet fragment PF1). When the first data packet fragment PF1 contains two or more erroneous symbols, the ECC decoding operation of the first ECC sub-decoder 122e1 may fail. Subsequently, the CRC decoder 121 may cause the CRC decoding operation to fail.

[0061] As described above, the second ECC sub-decoder 122e2 can generate a second ECC-decoded data packet fragment PFDe2 based on the ECC decoding operation of the second data packet fragment PF2. The second ECC-decoded data packet fragment PFDe2 can have a size of 83 bytes. The second data packet fragment PF2 may include two ECC parity symbols. The third ECC sub-decoder 122e3 can generate a third ECC-decoded data packet fragment PFDe3 based on the ECC decoding operation of the third data packet fragment PF3. The third ECC-decoded data packet fragment PFDe3 can have a size of 83 bytes. The third data packet fragment PF3 may include two ECC parity symbols.

[0062] The interleaver circuit 123 can receive first-decoded data packet fragments PFDe1 to third-decoded data packet fragments PFDe3 from the first ECC sub-decoder 122e1 to the third ECC sub-decoder 122e3, respectively. The interleaver circuit 123 can buffer the first-decoded data packet fragments PFDe1 to the third-decoded data packet fragments PFDe3. Based on the interleaving operation of the first-decoded data packet fragments PFDe1 to the third-decoded data packet fragments PFDe3, the interleaver circuit 123 can generate interleaved packets (PI). The interleaved packets PI can have a size of 250 bytes.

[0063] Interleaving can be a process of sequentially mixing packet fragments PFDe1 (decoded by the first ECC) to PFDe3 (decoded by the third ECC). See below for further details. Figure 7 To describe the interleaving operation in more detail.

[0064] CRC decoder 121 can receive interleaved data packet PI from interleaver circuit 123. CRC decoder 121 can perform a CRC decoding operation on the interleaved data packet PI. When the CRC decoding operation is successful, CRC decoder 121 can provide the CRC-decoded data packet PDc to data packet interface circuit 126. The CRC-decoded data packet PDc can have a size of 242 bytes. For example, the interleaved data packet PI can include 8 CRC parity check symbols. CRC decoder 121 can determine whether the CRC decoding operation on the remaining 242 symbols of the interleaved data packet PI has passed or failed based on the 8 CRC parity check symbols, and when the CRC decoding operation is successful, CRC decoder 121 can generate the CRC-decoded data packet PDc.

[0065] The packet interface circuit 126 can receive CRC-decoded data packets PDc from the CRC decoder 121. The CRC-decoded data packet PDc may include a TLP and a DLP. The TLP may be 236 bytes in size and may include 236 TLP symbols. The DLP may be 6 bytes in size and may include 6 DLP symbols. The packet interface circuit 126 can provide the TLP to... Figure 1 The transaction layer TL1 or data link layer DL1. The packet interface circuit 126 can provide DLP to... Figure 1 Data link layer DL1.

[0066] Referring back to CRC decoder 121, when the CRC decoding operation fails, CRC decoder 121 can provide an enable signal EN to the post-decoder 125. The enable signal EN can activate the post-decoding operation of post-decoder 125.

[0067] The reliability calculator 124 can receive first data packet fragments PF1 to third data packet fragments PF3 from the data packet distributor 122d. The reliability calculator 124 can generate first bit stream information bs1, second bit stream information bs2, and third bit stream information bs3 based on the first data packet fragments PF1 to the third data packet fragments PF3.

[0068] For example, the first data packet fragment PF1 may include 86 symbols, and each symbol may correspond to four PAM-4 symbols. When a PAM-4 symbol with an unreliable voltage level is detected among the four PAM-4 symbols corresponding to a symbol, the reliability calculator 124 may assign a first bit value (e.g., "1") to the corresponding symbol. Conversely, when all four PAM-4 symbols corresponding to a symbol are detected to have a reliable voltage level, the reliability calculator 124 may assign a second bit value (e.g., "0") to the corresponding symbol.

[0069] The first bitstream information bs1 identifies the positions of symbols in the first data packet segment PF1 that are estimated to be erroneous. The first bitstream information bs1 may be 86 bits in size. The second bitstream information bs2 identifies the positions of symbols in the second data packet segment PF2 that are estimated to be erroneous. The second bitstream information bs2 may be 85 bits in size. The third bitstream information bs3 identifies the positions of symbols in the third data packet segment PF3 that are estimated to be erroneous. The third bitstream information bs3 may be 85 bits in size.

[0070] The post-decoder 125 can receive an enable signal EN from the CRC decoder 121, receive first data packet fragments PF1 to third data packet fragments PF3 from the data packet distributor 122d, and receive first bitstream information bs1 to third bitstream information bs3 from the reliability calculator 124. In response to the enable signal EN, the post-decoder 125 can perform a post-decoding operation on at least one of the first data packet fragments PF1 to third data packet fragments PF3 based on the first bitstream information bs1 to third bitstream information bs3, thereby generating at least one post-decoded data packet fragment PFDp. The post-decoded data packet fragment PFDp can have a size of 84 bytes or 83 bytes.

[0071] The post-decoder 125 can replace at least one of the first ECC-decoded data packet segments PFDe1 to the third ECC-decoded data packet segments PFDe3 buffered by the interleaver circuit 123 with at least one post-decoded data packet segment PFDp. The interleaver circuit 123 can also perform an interleaving operation based on the replaced at least one post-decoded data packet segment PFDp to generate another interleaved data packet PI. The CRC decoder 121 can perform a CRC decoding operation on the other interleaved data packet PI. When the CRC decoding operation on the other interleaved data packet PI fails, the CRC decoder 121 can generate a request signal RQ for retransmitting the data packet in flit mode, and can be used to... Figure 2 The I / O circuit 130 provides the request signal RQ to Figure 1 The second communication device 200.

[0072] The post-decoded data packet segment PFDp can correspond to one of the data packet segments PFDe1 (decoded by the first ECC) to PFDe3 (decoded by the third ECC). When two or more bits with a first bit value (e.g., "1") exist in the corresponding bitstream, the post-decoder 125 can perform the post-decoding operation of the corresponding data packet segment. There can be one, two, or three post-decoded data packet segments PFDp.

[0073] The post-decoding operation may include: performing erasure decoding (also known as erasure decoding) on ​​the estimated combination of erroneous symbols based on the corresponding bitstream, and selecting one of the erasure-decoded packet fragments as the post-decoded packet fragment PFDp. Erasure decoding can be the correction of two erroneous symbols with specified positions.

[0074] Through the post-decoding operation, the two erroneous symbols at specified positions within the symbols of the first data packet fragment PF1 can be corrected. Afterwards, the CRC decoder 121 can allow the CRC decoding operation to proceed. Conversely, if the first data packet fragment PF1 contains three or more erroneous symbols, the post-decoding operation may fail. Afterwards, the CRC decoder 121 can allow the CRC decoding operation to fail. As described above, through the post-decoding operation, the two erroneous symbols at specified positions within the symbols of the second data packet fragment PF2 can be corrected. Through the post-decoding operation, the two erroneous symbols at specified positions within the symbols of the third data packet fragment PF3 can be corrected.

[0075] Figure 4 This is a graph showing the voltage levels of data packets according to some embodiments. (Refer to...) Figure 3 and Figure 4 The data packet may include 256 symbols. Each symbol may include four PAM-4 symbols. A PAM-4 symbol may correspond to two bits. A PAM-4 symbol may have a voltage level corresponding to its PAM-4 symbol value. Referring to the graph, the eye diagram of a PAM-4 symbol is shown. Figure 1 The voltage level measured at receiver Rx of the physical layer PL1 of the first communication device 100. The horizontal axis represents time. The vertical axis represents voltage.

[0076] A PAM-4 symbol can correspond to one of the PAM-4 symbol values ​​“00”, “10”, “11”, and “01”. A PAM-4 symbol can have one of the first to third unreliable voltage levels. In the graph, the first to third unreliable voltage levels are shown as shaded areas. The first to third unreliable voltage levels can be collectively referred to as the unreliable voltage levels of the PAM-4 symbol.

[0077] The first voltage level VR1 represents the intermediate value of the voltage level corresponding to the PAM-4 symbol values ​​"01" and "11". The voltage within the reference voltage level Vref centered on the first voltage level VR1 can be called the first unreliable voltage level. The second voltage level VR2 represents the intermediate value of the voltage level corresponding to the PAM-4 symbol values ​​"11" and "10". The voltage within the reference voltage level Vref centered on the second voltage level VR2 can be called the second unreliable voltage level. The third voltage level VR3 represents the intermediate value of the voltage level corresponding to the PAM-4 symbol values ​​"10" and "00". The voltage within the reference voltage level Vref centered on the third voltage level VR3 can be called the third unreliable voltage level.

[0078] The reliability calculator 124 can generate first bit stream information bs1 to third bit stream information bs3 based on whether the PAM-4 symbols corresponding to the symbols of the first data packet fragment PF1 to the third data packet fragment PF3 have unreliable voltage levels.

[0079] For example, the reliability calculator 124 may receive a first data packet fragment PF1. The first data packet fragment PF1 may include symbols from the first symbol to the Kth symbol. "K" may represent the number of symbols in the first data packet fragment PF1. "K" may be 86. Each of the first symbol to the Kth symbol may include four PAM-4 symbols. The Jth symbol may represent one of the first symbol to the Kth symbol. "J" is a positive integer less than or equal to "K".

[0080] The reliability calculator 124 can determine whether at least one of the four PAM-4 symbols corresponding to the Jth symbol (from the first to the Kth symbols) has an unreliable voltage level. In response to determining that at least one of the four PAM-4 symbols corresponding to the Jth symbol has an unreliable voltage level, the reliability calculator 124 can set the bit corresponding to the Jth symbol among the "K" bits of the first bitstream information bs1 to a first bit value (e.g., "1"). In response to determining that none of the four PAM-4 symbols corresponding to the Jth symbol has an unreliable voltage level, the reliability calculator 124 can set the bit corresponding to the Jth symbol among the "K" bits of the first bitstream information bs1 to a second bit value (e.g., "0").

[0081] As described above, the reliability calculator 124 can generate second bitstream information bs2 based on the voltage level of the PAM-4 symbol corresponding to the symbol of the second data packet segment PF2. The reliability calculator 124 can generate third bitstream information bs3 based on the voltage level of the PAM-4 symbol corresponding to the symbol of the third data packet segment PF3.

[0082] Figure 5 This is a table illustrating data packets in the flit mode according to some embodiments. See also... Figure 5 A data packet in flit mode can include 256 symbols. These 256 symbols can be transmitted through 16 data channels. For example, in... Figure 2 In this context, "P" can be 16, and the first communication device 100 can receive 256 symbols through the first data channel to the sixteenth data channel.

[0083] Referring to this table, the symbols transmitted for each data channel are described. Items in the row direction represent byte index values. Byte index values ​​“0:255” uniquely represent one of the 256 symbols in the data packet. Items in the column direction represent data channel index values. Data channel index values ​​“1:16” uniquely represent one of the data channels transmitting the data packet, from the first to the sixteenth.

[0084] A packet in flit mode has 256 symbols that can represent 236 TLP symbols "TLP0:TLP235", 6 DLP symbols "DLP0:DLP5", 8 CRC parity check symbols "CRC0:CRC7", and 6 ECC parity check symbols "ECC1a, ECC1b, ECC2a, ECC2b, ECC3a, and ECC3b". Each of the 256 symbols can be associated with... Figure 3 It corresponds to one of the first data packet fragment PF1, the second data packet fragment PF2, and the third data packet fragment PF3. Depending on the type of the data packet fragment corresponding to each symbol, the symbol is depicted as a different type (e.g., dark shadow, light shadow, or no shadow).

[0085] To aid in understanding this disclosure, 256 symbols are described based on 16 data channels; however, the scope of this disclosure is not limited thereto, nor are the embodiments limited thereto. In some embodiments, the number of data channels may be varied to more or less than 16.

[0086] Figure 6 This is a diagram illustrating a packet fragment of a packet in flit mode according to some embodiments. (Refer to...) Figure 5 and Figure 6 A data packet in flit mode may include a first data packet fragment PF1, a second data packet fragment PF2, and a third data packet fragment PF3. The symbol corresponding to the first data packet fragment PF1 is shown in dark shading. The symbol corresponding to the second data packet fragment PF2 is shown without shading. The symbol corresponding to the third data packet fragment PF3 is shown in light shading.

[0087] The first data packet fragment PF1 may be 86 bytes in size. The first data packet fragment PF1 may include a data portion of 81 bytes, a CRC parity check portion of 3 bytes, and an ECC parity check portion of 2 bytes.

[0088] The first data packet fragment PF1 may include 86 symbols. The 86 symbols of the first data packet fragment PF1 may include 79 TLP symbols “TLP0, ..., TLP231 and TLP234”, two DLP symbols “DLP1 and DLP4”, three CRC parity check symbols “CRC1, CRC4 and CRC7”, and two ECC parity check symbols “ECC1a and ECC1b”.

[0089] The 79 TLP symbols “TLP0, ..., TLP231 and TLP234” and the two DLP symbols “DLP1 and DLP4” correspond to the data portion. The three CRC parity symbols “CRC1, CRC4 and CRC7” correspond to the CRC parity portion. The two ECC parity symbols “ECC1a and ECC1b” correspond to the ECC parity portion.

[0090] The second data packet fragment PF2 may be 85 bytes in size. The second data packet fragment PF2 may include a data portion of 81 bytes, a CRC parity check portion of 2 bytes, and an ECC parity check portion of 2 bytes.

[0091] The second data packet fragment PF2 may include 85 symbols. The 85 symbols of the second data packet fragment PF2 may represent 79 TLP symbols “TLP1, ..., TLP232 and TLP235”, two DLP symbols “DLP2 and DLP5”, two CRC parity check symbols “CRC2 and CRC5”, and two ECC parity check symbols “ECC2a and ECC2b”.

[0092] The 79 TLP symbols “TLP1, ..., TLP232 and TLP235” and the two DLP symbols “DLP2 and DLP5” correspond to the data portion. The two CRC parity symbols “CRC2 and CRC5” correspond to the CRC parity portion. The two ECC parity symbols “ECC2a and ECC2b” correspond to the ECC parity portion.

[0093] The third data packet fragment PF3 can be 85 bytes in size. PF3 may include an 80-byte data portion, a 3-byte CRC parity check portion, and a 2-byte ECC parity check portion.

[0094] The third data packet fragment PF3 may include 85 symbols. The 85 symbols of the third data packet fragment PF3 may represent 78 TLP symbols “TLP2, ..., and TLP233”, two DLP symbols “DLP0 and DLP3”, three CRC parity check symbols “CRC0, CRC3 and CRC6”, and two ECC parity check symbols “ECC3a and ECC3b”.

[0095] The 78 TLP symbols “TLP2, ..., and TLP233” and the two DLP symbols “DLP0 and DLP3” correspond to the data portion. The three CRC parity symbols “CRC0, CRC3, and CRC6” correspond to the CRC parity portion. The two ECC parity symbols “ECC3a and ECC3b” correspond to the ECC parity portion.

[0096] Figure 7 This is a diagram illustrating interleaved data packets according to some embodiments. (Refer to...) Figure 3 and Figure 7 The interleaved data packet PI can include 250 symbols. The interleaver circuit 123 can send the interleaved data packet PI to the CRC decoder 121 through the first interleaver channel to the fourth interleaver channel.

[0097] Referring to this table, the symbols transmitted for each interleaver channel are described. Items in the row direction represent byte index values. Byte index values ​​“0:249” uniquely represent one of the 250 symbols in the interleaved data packet PI. Items in the column direction represent interleaver channel index values. Interleaver channel index values ​​“1:4” uniquely represent one of the first to fourth interleaver channels transmitting the interleaved data packet PI.

[0098] The 250 symbols of the interleaved data packet PI can include 236 TLP symbols “TLP0:TLP235”, 6 DLP symbols “DLP0:DLP5”, and 8 CRC parity symbols “CRC0:CRC7”. Depending on the type of data packet segment corresponding to each symbol, the symbols are depicted as different types (e.g., dark shading, light shading, or no shading).

[0099] To aid in understanding this disclosure, the interleaved data packet PI is described based on four interleaver channels; however, the scope of this disclosure is not limited thereto, nor are the embodiments limited thereto. In some embodiments, the number of interleaver channels may be varied to more or fewer than four.

[0100] Figure 8 This is a flowchart illustrating how the flit decoder operates. (See reference...) Figure 8The communication device can communicate with other communication devices via a communication interface circuit. The communication device may include a universal flit decoder. Although a universal flit decoder is described to aid understanding of this disclosure, it may include technical features not disclosed in existing literature. The universal flit decoder is not intended to limit the scope of this disclosure.

[0101] In operation S11, the general-purpose flit decoder can receive data packets from another communication device. The data packets may conform to the format of the PCIe standard's flit mode. The data packets may include multiple packet fragments.

[0102] In operation S12, the general-purpose flit decoder can perform ECC decoding operations on data packets. For example, the general-purpose flit decoder can generate multiple ECC-decoded data packet fragments based on multiple data packet fragments, and can generate interleaved data packet fragments based on multiple ECC-decoded data packet fragments.

[0103] In operation S13, the general-purpose flit decoder can perform CRC decoding operations based on interleaved data packet fragments.

[0104] In operation S14, the general-purpose flit decoder determines whether the CRC decoding operation passed or failed. When the CRC decoding operation passed (S14, Yes), the general-purpose flit decoder executes operation S15.

[0105] In operation S15, the general-purpose flit decoder can provide the CRC-decoded data packet to the upper layer. The CRC-decoded data packet may include TLP and DLP. The upper layer can represent... Figure 1 The transaction layer TL1 and the data link layer DL1.

[0106] On the other hand, when the CRC decoding operation fails (S14, No), the general-purpose flit decoder can perform operation S16.

[0107] In operation S16, the general-purpose flit decoder can generate a request signal RQ for retransmission of data packets and can provide the request signal RQ to other communication devices. Retransmission of data packets can reduce the communication speed of electronic systems including communication devices. Techniques for reducing the retransmission rate of data packets can be used.

[0108] Figure 9 This is a flowchart illustrating a method for operating a flit decoder according to some embodiments. (Refer to...) Figure 9 The communication device can communicate with other communication devices via a communication interface circuit. The communication device may include a flit decoder. For example, in one embodiment, the flit decoder may be a reference... Figures 1 to 7 The described flit decoder 120.

[0109] In operation S110, the flit decoder can receive data packets from another communication device. The data packets can conform to the format of the PCIe standard's flit mode. The data packets may include multiple packet fragments.

[0110] In operation S120, the flit decoder can perform ECC decoding on the data packets. For example, the flit decoder can generate multiple ECC-decoded data packet fragments based on multiple data packet fragments, and can generate a first interleaved data packet fragment based on the multiple ECC-decoded data packet fragments.

[0111] In operation S130, the flit decoder can perform a first CRC decoding operation based on the first interleaved data packet fragment.

[0112] In operation S140, the flit decoder can determine whether the first CRC decoding operation passed or failed. When the first CRC decoding operation passed (S140, yes), the flit decoder can execute operation S150.

[0113] In operation S150, the flit decoder can provide the CRC-decoded data packet to the upper layer. The CRC-decoded data packet may include TLP and DLP. The upper layer can represent... Figure 1 The transaction layer TL1 and the data link layer DL1.

[0114] On the other hand, when the first CRC decoding operation fails (S140, no), the flit decoder can perform operation S161.

[0115] In operation S161, the flit decoder can perform a post-decoding operation. The post-decoding operation can represent performing erasure decoding on the estimated combination of erroneous symbols and selecting one of the erasure-decoded data packet fragments obtained through the erasure decoding operation as the post-decoded data packet fragment. The error correction capability of the erasure decoding operation can be greater than that of the ECC decoding operation.

[0116] The post-decoded data packet fragment can replace one of the ECC-decoded data packet fragments obtained through the ECC decoding operation of S120. For example, the flit decoder can generate a second interleaved data packet based on the post-decoded data packet fragment instead of the ECC-decoded data packet fragment.

[0117] In operation S162, the flit decoder can perform a second CRC operation based on the second interleaved data packet. The flit decoder can determine whether the second CRC decoding operation passes or fails. When the second CRC decoding operation passes (S162, Yes), the flit decoder can perform operation S150 based on the CRC-decoded data packet obtained through the second CRC decoding operation.

[0118] On the other hand, when the second CRC decoding operation fails (S162, no), the flit decoder can perform operation S163.

[0119] In operation S163, the flit decoder can generate a request signal RQ for retransmission of data packets and can provide the request signal RQ to another communication device. In other words, when the first CRC decoding operation fails, the flit decoder can perform a post-decoding operation instead of requesting retransmission of the data packet. Since the error correction capability of the post-decoding operation is greater than that of the ECC decoding operation, the retransmission rate of the data packet can be reduced through the post-decoding operation.

[0120] More specifically, the post-decoding operation may include erasure decoding for combinations of estimated erroneous symbols. The error correction capability of erasure decoding can be greater than that of ECC decoding. By performing erasure decoding, the error correction capability of the flit decoder can be improved, and the packet retransmission rate can be reduced.

[0121] Figure 10 This is a diagram illustrating a method of operating a flit decoder according to some embodiments. (Refer to...) Figure 10 The flit decoder 120 may include a CRC decoder 121, an ECC decoder 122, an interleaver circuit 123, a reliability calculator 124, a post-decoder 125, and a packet interface circuit 126. The ECC decoder 122 may include a packet distributor 122d, a first ECC sub-decoder 122e1, a second ECC sub-decoder 122e2, and a third ECC sub-decoder 122e3.

[0122] In operation S210, the ECC decoder 122 can receive data packets. The data packets may conform to the format of the PCIe standard's flit mode. The data packets may include first data packet fragments PF1 through third data packet fragments PF3.

[0123] In operation S220, ECC decoder 122 can perform ECC decoding operations on data packets. For example, data packet distributor 122d can generate first data packet fragments PF1 to third data packet fragments PF3 based on data packet distribution operations. First ECC sub-decoders 122e1 to third ECC sub-decoders 122e3 can generate first ECC decoded data packet fragments PFDe1 to third ECC decoded data packet fragments PFDe3 based on the first data packet fragments PF1 to PF3, respectively.

[0124] ECC decoder 122 can provide first data packet fragments PF1 to third data packet fragments PF3 to reliability calculator 124 and post-decoder 125. Reliability calculator 124 can provide first bitstream information bs1 to third bitstream information bs3 to post-decoder 125 based on first data packet fragments PF1 to third data packet fragments PF3.

[0125] ECC decoder 122 can provide data packet segments PFDe1 to PFDe3, decoded by the first ECC, to interleaver circuit 123. Interleaver circuit 123 can generate a first interleaved data packet PI1 based on the interleaving operation of the data packet segments PFDe1 to PFDe3. Interleaver circuit 123 can provide the first interleaved data packet PI1 to CRC decoder 121.

[0126] In operation S230, CRC decoder 121 can perform a first CRC decoding operation on the first interleaved data packet PI1. CRC decoder 121 can determine whether the first CRC decoding operation succeeds or fails.

[0127] In response to the successful completion of the first CRC decoding operation, the CRC decoder 121 can provide the CRC-decoded data packet PDc generated by the first CRC decoding operation to the data packet interface circuit 126. The data packet interface circuit 126 can generate a TLP and a DLP based on the CRC-decoded data packet PDc, and can provide the TLP to... Figure 1 The transaction layer TL1, and can provide DLP to Figure 1 Data link layer DL1.

[0128] In response to the failure of the first CRC decoding operation, the CRC decoder 121 can provide the enable signal EN to the post-decoder 125.

[0129] In operation S261, the post-decoder 125, in response to the enable signal EN, performs a post-decoding operation based on the first bitstream information bs1 to the third bitstream information bs3 and the first data packet fragment PF1 to the third data packet fragment PF3. Based on the post-decoding operation, it can generate at least one post-decoded data packet fragment PFDp and provide it to the interleaver circuit 123. The at least one post-decoded data packet fragment PFDp can replace at least one of the first ECC-decoded data packet fragments PFDe1 to the third ECC-decoded data packet fragments PFDe3 in the interleaver circuit 123.

[0130] The interleaver circuit 123 can generate a second interleaved data packet PI2 based on the unreplaced portions of at least one post-decoded data packet segment PFDp and data packet segments PFDe1 to PFDe3 decoded by the first ECC. The interleaver circuit 123 can provide the second interleaved data packet PI2 to the CRC decoder 121.

[0131] In operation S262, CRC decoder 121 can perform a second CRC decoding operation on the second interleaved data packet PI2. CRC decoder 121 can determine whether the second CRC decoding operation succeeds or fails.

[0132] In response to the successful completion of the second CRC decoding operation, the CRC decoder 121 can provide the CRC-decoded data packet PDc generated by the second CRC decoding operation to the data packet interface circuit 126. The data packet interface circuit 126 can generate a TLP and a DLP based on the CRC-decoded data packet PDc, and can provide the TLP to... Figure 1 The transaction layer TL1, and can provide DLP to Figure 1 Data link layer DL1.

[0133] In response to a failure of the second CRC decoding operation, CRC decoder 121 may generate a request signal RQ for retransmission of the data packet used in operation S210. CRC decoder 121 may provide the request signal RQ to... Figure 1 The second communication device 200.

[0134] Figure 11 This illustrates some embodiments. Figure 10 A diagram illustrating the bitstream information. (Refer to...) Figures 10 to 11 The reliability calculator 124 can generate the first bit stream information bs1 based on the first data packet fragment PF1.

[0135] The first data packet fragment PF1 may be 86 bytes in size. The first data packet fragment PF1 may include the first symbol SY1 through the eighty-sixth symbol SY86. The first symbol SY1 through the eighty-sixth symbol SY86 may each correspond to four PAM-4 symbols.

[0136] The first data packet fragment PF1 may include “N” estimated error symbols. “N” is a positive integer less than the number of symbols in the first data packet fragment PF1 (i.e., 86). For example, among the first symbols SY1 to the eighty-sixth symbol SY86 of the first data packet fragment PF1, the first symbol SY1, the fourth symbol SY4, and the eighth symbol SY8 may be estimated error symbols. The first symbol SY1, the fourth symbol SY4, and the eighth symbol SY8 may be referred to as the first estimated error symbol eSY1, the second estimated error symbol eSY2, and the third estimated error symbol eSY3, respectively. In this case, “N” can be “3”.

[0137] The first symbol SY1 may include the first PAM-4 symbol SY1-p1 through the fourth PAM-4 symbol SY1-p4. The first PAM-4 symbol SY1-p1 may have an unreliable voltage level. Errors may occur in the first PAM-4 symbol SY1-p1. Symbols that are estimated to have encountered an error and have actually encountered an error are shown in dark shading. Symbols that are estimated not to have encountered an error are shown without shading. The first PAM-4 symbol SY1-p1 may also be referred to as the low-reliability symbol LR. The second PAM-4 symbols SY1-p2 through the fourth PAM-4 symbols SY1-p4 may not have an unreliable voltage level.

[0138] When at least one of the first PAM-4 symbols SY1-p1 to the fourth PAM-4 symbols SY1-p4 of the first symbol SY1 is a low reliability symbol LR, the reliability calculator 124 may set the bit corresponding to the first symbol SY1 to a first bit value (e.g., "1"). For example, in the 86 bits of the first bit stream information bs1, the first bit corresponding to the first symbol SY1 may be set to "1".

[0139] The fourth symbol SY4 may include the first PAM-4 symbol SY4-p1 through the fourth PAM-4 symbol SY4-p4. The first PAM-4 symbol SY4-p1 may have an unreliable voltage level. No error may occur in the first PAM-4 symbol SY4-p1. Symbols that are estimated to have an error but did not are shown in light shading. The first PAM-4 symbol SY4-p1 may also be referred to as the low-reliability symbol LR. An error may occur in the third PAM-4 symbol SY4-p3. The third PAM-4 symbol SY4-p3 may also be referred to as the low-reliability symbol LR. The second PAM-4 symbol SY4-p2 and the fourth PAM-4 symbol SY4-p4 may not have an unreliable voltage level.

[0140] When at least one of the first PAM-4 symbols SY4-p1 to the fourth PAM-4 symbol SY4-p4 of the fourth symbol SY4 is a low reliability symbol LR, the reliability calculator 124 may set the bit corresponding to the fourth symbol SY4 to a first bit value (e.g., "1"). For example, in the 86 bits of the first bit stream information bs1, the fourth bit corresponding to the fourth symbol SY4 may be set to "1".

[0141] The eighth symbol SY8 may include the first PAM-4 symbol SY8-p1 through the fourth PAM-4 symbol SY8-p4. The fourth PAM-4 symbol SY8-p4 may have an unreliable voltage level. No error may occur in the fourth PAM-4 symbol SY8-p4. The fourth PAM-4 symbol SY8-p4 may also be referred to as the low-reliability symbol LR. The first PAM-4 symbol SY8-p1, the second PAM-4 symbol SY8-p2, and the third PAM-4 symbol SY8-p3 may not have an unreliable voltage level.

[0142] When at least one of the first PAM-4 symbols SY8-p1 to the fourth PAM-4 symbol SY8-p4 of the eighth symbol SY8 is a low reliability symbol LR, the reliability calculator 124 may set the bit corresponding to the eighth symbol SY8 to a first bit value (e.g., "1"). For example, in the 86 bits of the first bit stream information bs1, the eighth bit corresponding to the eighth symbol SY8 may be set to "1".

[0143] The reliability calculator 124 can set each of the bits corresponding to the symbols that do not have a low reliability symbol LR among the first symbols SY1 to the eighty-sixth symbol SY86 of the first data packet segment PF1 to a second bit value (e.g., "0"). For example, among the 86 bits of the first bit stream information bs1, the bits corresponding to the second symbols SY2, the third symbols SY3, the fifth symbols SY5 to the seventh symbols SY7, and the ninth symbols SY9 to the eighty-sixth symbols SY86 can be set to "0".

[0144] To avoid complexity in the description, the reliability calculator 124 is described as generating first bitstream information bs1 based on the first data packet fragment PF1. However, the reliability calculator 124 can generate second bitstream information bs2 and third bitstream information bs3 based on the second data packet fragment PF2 and the third data packet fragment PF3 in a similar manner as described above. Therefore, for the sake of brevity, the repeated description of the reliability calculator 124 is omitted.

[0145] Figure 12 This illustrates some embodiments. Figure 10 A diagram illustrating the decoded data packet fragments. (Refer to...) Figure 10 and Figure 12The first ECC sub-decoder 122e1 can generate the first ECC-decoded data packet fragment PFDe1 based on the ECC decoding operation of the first data packet fragment PF1. The post-decoder 125 can generate the post-decoded data packet fragment PFDp based on the first data packet fragment PF1 and the first bit stream information bs1.

[0146] The first data packet fragment PF1 may be 86 bytes in size. The first data packet fragment PF1 may include symbols SY1 through SY86. Symbols SY1, SY4, and SY8 may be referred to as the first estimated error symbol eSY1, the second estimated error symbol eSY2, and the third estimated error symbol eSY3, respectively. Errors may have actually occurred in symbols SY1 and SY4. Symbols SY1 and SY4 may also be referred to as error symbols. An error may not have occurred in symbol SY8. Symbols that are estimated to have occurred and have actually occurred are shown in dark shading. Symbols that are estimated to have occurred but have not yet occurred are shown in light shading. Symbols that are estimated not to have occurred are shown without shading.

[0147] The first bitstream information bs1 may include the first to the eighty-sixth bits corresponding to the first symbols SY1 to SY86 of the first data packet fragment PF1. Among the first to the eighty-sixth bits, the first, fourth, and eighth bits may have a first bit value (e.g., "1"), and the remaining bits may have a second bit value (e.g., "0").

[0148] The error correction capability of the first ECC sub-decoder 122e1 can correspond to one symbol per data packet segment (i.e., 1SY / PF). For example, the first ECC sub-decoder 122e1 can correct one erroneous symbol among the first symbol SY1 to the eighty-sixth symbol SY86 of the first data packet segment PF1. Since the first data packet segment PF1 includes two erroneous symbols (i.e., the first symbol SY1 and the fourth symbol SY4), the error level of the first data packet segment PF1 can exceed the error correction capability of the first ECC sub-decoder 122e1. The CRC decoder 121 can cause the CRC decoding operation to fail based on the data packet segment PFDe1 decoded by the first ECC.

[0149] The error correction capability of the post-decoder 125 can correspond to two symbols per data packet segment (i.e., 2SY / PF). The post-decoder 125 can request position estimates for the two erroneous symbols. For example, the post-decoder 125 can correct two erroneous symbols whose positions are estimated among the first symbols SY1 to the eighty-sixth symbol SY86 of the first data packet segment PF1. The post-decoder 125 can estimate the positions of the two erroneous symbols based on the first bitstream information bs1. The first data packet segment PF1 may include two erroneous symbols (i.e., the first symbol SY1 and the fourth symbol SY4). The error level of the first data packet segment PF1 may not exceed the error correction capability of the post-decoder 125. The CRC decoder 121 can pass the CRC decoding operation based on the post-decoded data packet segment PFDp that replaces the first ECC-decoded data packet segment PFDe1.

[0150] To avoid complexity, the ECC decoding and post-decoding operations are described for the first data packet segment PF1. However, the ECC decoding and post-decoding operations can be performed in a similar manner for the second data packet segment PF2 and the third data packet segment PF3. Therefore, for the sake of brevity, the repeated descriptions of the ECC decoding and post-decoding operations are omitted.

[0151] Figure 13 This illustrates some embodiments. Figure 10 A diagram of the post-decoder. (Refer to...) Figure 10 and Figure 13 The post-decoder 125 can generate a post-decoded data packet fragment PFDp based on the enable signal EN, the first bitstream information bs1, and the first data packet fragment PF1. The first bitstream information bs1 can identify "N" estimated erroneous symbols from the first symbol to the eighty-sixth symbol of the first data packet fragment PF1. For example, the first symbol, the fourth symbol, and the eighth symbol from the first symbol to the eighty-sixth symbol can be referred to as the first estimated erroneous symbol to the third estimated erroneous symbol, respectively. "N" can be 3. The first symbol and the fourth symbol can be the symbols that actually caused the error. The eighth symbol can be the symbol that was estimated to have caused an error but did not actually cause an error.

[0152] The post-decoder 125 may include an erasure position calculator 125c, an erasure decoder 125e, and a selection circuit 125s. The erasure decoder 125e may include a first erasure sub-decoder 125e1, a second erasure sub-decoder 125e2, and a third erasure decoder 125e3.

[0153] The erase position calculator 125c can be activated in response to the enable signal EN, and can generate first candidate information to M candidate information based on the first bitstream information bs1 used to identify the first estimated error symbol to the Nth estimated error symbol. "M" can be... The result of a combinational arithmetic operation (representing an arithmetic operation that selects two elements from N elements without repetition or regard to order).

[0154] For example, the first estimated error symbols to the Nth estimated error symbols can be the first symbol, the fourth symbol, and the eighth symbol of the first data packet segment PF1. "N" can be 3. "M" can be 3. The first candidate information to the Mth candidate information can be the first candidate information ci1, the second candidate information ci2, and the third candidate information ci3. The first candidate information ci1 can represent the first symbol and the fourth symbol. The second candidate information ci2 can represent the first symbol and the eighth symbol. The third candidate information ci3 can represent the fourth symbol and the eighth symbol.

[0155] The erasure decoder 125e can generate first erasure decoded data packet fragments to Mth erasure decoded data packet fragments based on the first data packet fragment PF1 and the first to Mth candidate information. For example, the first to Mth candidate information can be first candidate information ci1 to third candidate information ci3 representing two combined ones of the first symbol, the fourth symbol, and the eighth symbol.

[0156] More specifically, the first erasure sub-decoder 125e1 can perform erasure decoding on the first data packet fragment PF1 based on the first candidate information ci1 representing the first symbol and the fourth symbol, generating a first erasure decoded data packet fragment PFDer1. Erasure decoding can be performed by correcting two erroneous symbols whose positions are specified based on the candidate information.

[0157] The first and fourth symbols can be the symbols in which the error actually occurred. The first erasure decoding packet fragment PFDer1 can include the symbols in which the error was corrected. Specifically, the first erasure decoding packet fragment PFDer1 may not include the erroneous symbols.

[0158] As described above, the second erasure sub-decoder 125e2 can perform erasure decoding on the first data packet fragment PF1 based on the second candidate information ci2 representing the first symbol and the eighth symbol, generating the second erasure decoded data packet fragment PFDer2. The third erasure sub-decoder 125e3 can perform erasure decoding on the first data packet fragment PF1 based on the third candidate information ci3 representing the fourth symbol and the eighth symbol, generating the third erasure decoded data packet fragment PFDer3.

[0159] The eighth symbol can be any symbol that did not have an error. Because erasure decoding is performed based on incorrectly estimated symbols (i.e., the eighth symbol), the packet fragments PFDer2 and PFDer3 of the second and third erasure decoding can contain many erroneous symbols.

[0160] Erasure decoder 125e is described as including first erasure sub-decoders 125e1 to third erasure sub-decoders 125e3, but embodiments are not limited thereto. In some embodiments, the number of erasure sub-decoders included in erasure decoder 125e may be fewer or more than three. In one embodiment, the erasure sub-decoders may perform erasure decoding operations based on two or more candidate information corresponding to the same bitstream information. In some embodiments, when the number of candidate information is small, some erasure sub-decoders may not perform erasure decoding operations.

[0161] The selection circuit 125s can select one of the first erasure decoding data packet fragments to the Mth erasure decoding data packet fragments as the post-decoded data packet fragment PFDp, and can provide the post-decoded data packet fragment PFDp to the interleaver circuit 123.

[0162] For example, the selection circuit 125s can calculate a first difference, a second difference, and a third difference based on a comparison operation between each of the first erasure decoding data packet fragments PFDer1 to the third erasure decoding data packet fragments PFDer3 and the first data packet fragment PF1. The difference can represent the number of different bits between the data packet fragment and the erasure decoding data packet fragment. Since the first erasure decoding data packet fragment PFDer1 is similar to the first data packet fragment PF1 except for the first and fourth symbols, the first difference can be relatively small. Because the second and third erasure decoding data packet fragments PFDer2 and PFDer3 include many erroneous symbols due to erasure decoding based on incorrectly estimated symbols (i.e., the eighth symbol), the second and third differences can be relatively large.

[0163] The selection circuit 125s can select the first difference as the smallest difference among the first difference to the third difference, and can select the first erasure decoding data packet segment PFDer1 corresponding to the first difference as the later decoded data packet segment PFDp. The later decoded data packet segment PFDp can replace the first ECC decoded data packet segment PFDe1 buffered by the interleaver circuit 123.

[0164] To avoid the complexity of the description, the post-decoder 125 is described as generating a post-decoded data packet fragment PFDp corresponding to the first data packet fragment PF1. However, the post-decoder 125 may also generate a post-decoded data packet fragment PFDp based on the second data packet fragment PF2 or the third data packet fragment PF3.

[0165] Figure 14 This illustrates some embodiments. Figure 13 An illustration of the erase position calculator. (Refer to...) Figure 13 and Figure 14 The erase position calculator 125c can be activated in response to the enable signal EN. The erase position calculator 125c can generate first candidate information to Mth candidate information based on the first bit stream information bs1. For example, "M" can be 3. The erase position calculator 125c may include a divider 125c1, an index value generator 125c2, a counter 125c3, and a combiner 125c4.

[0166] The segmenter 125c1 can receive first bitstream information bs1 for identifying first estimated error symbols to Nth estimated error symbols. The segmenter 125c1 can generate first segment values ​​to Nth segment values, each having a bit string type, based on one-hot encoding operations of the first bitstream information bs1.

[0167] For example, "N" can be 3. The first estimated error symbols to the third estimated error symbols can represent the first symbol, the fourth symbol, and the eighth symbol of the first data packet segment PF1, respectively. The segmenter 125c1 can generate a first segment value sv1, a second segment value sv2, and a third segment value sv3 based on the one-hot encoding operation of the first bit stream information bs1. Each of the first segment value sv1, the second segment value sv2, and the third segment value sv3 has a bit string type.

[0168] The first segment sv1 can be a bit string in which the first bit has a first bit value and the remaining bits have a second bit value. The second segment sv2 can be a bit string in which the fourth bit has a first bit value and the remaining bits have a second bit value. The third segment sv3 can be a bit string in which the eighth bit has a first bit value and the remaining bits have a second bit value. The length (e.g., the number of bits) of each of the first segment sv1 to the third segment sv3 can be the same as the length of the first bit stream information bs1.

[0169] The index value generator 125c2 can generate first to Nth index values, each having an integer type, based on type conversion operations from the first segment value to the Nth segment value. The first to Nth index values ​​can correspond to the first to Nth estimated error symbols identified by the first bitstream information bs1, respectively.

[0170] For example, the index value generator 125c2 can generate a first index value iv1, a second index value iv2, and a third index value iv3, each having an integer type, based on a type conversion operation from the first segment value sv1 to the third segment value sv3. The first index value iv1 can represent the integer value "1". The second index value iv2 can represent the integer value "4". The third index value iv3 can represent the integer value "8".

[0171] Counter 125c3 can generate a count value "cv" indicating "N" based on the counting operation of the first bit stream information bs1. "N" can be the number of bits in the first bit stream information bs1 that have a first bit value. For example, the first bit stream information bs1 may include bits 1 through 86. The first bit, fourth bit, and eighth bit may have a first bit value, and the remaining bits may have a second bit value. Counter 125c3 can also generate a count value cv indicating "3" based on the counting operation of the first bit stream information bs1.

[0172] Combiner 125c4 can generate first candidate information to Mth candidate information, which indicate two of the first to Nth index values ​​that are combined without repetition and without regard to order. "N" can be the estimated number of erroneous symbols identified by the first bitstream information bs1. "M" can be... .

[0173] For example, combiner 125c4 can receive first index values ​​iv1 to third index values ​​iv3, indicating integer values ​​"1", "4", and "8", respectively. Combiner 125c4 can also receive a count value cv, indicating "3". Combiner 125c4 can perform operations based on the first index values ​​iv1 to third index values ​​iv3 and the count value cv. Combining arithmetic operations, first candidate information ci1 to third candidate information ci3 are generated. First candidate information ci1 can represent the first and fourth symbols of the first data packet segment PF1. Second candidate information ci2 can represent the first and eighth symbols of the first data packet segment PF1. Third candidate information ci3 can represent the fourth and eighth symbols of the first data packet segment PF1.

[0174] To avoid complexity in the description, the erase position calculator 125c is described as generating first candidate information ci1 to third candidate information ci3 corresponding to the first bitstream information bs1. However, in some embodiments, the erase position calculator 125c may generate more or fewer than three candidate information based on the first bitstream information bs1. In some embodiments, the erase position calculator 125c may generate other candidate information based on the second bitstream information bs2 and the third bitstream information bs3.

[0175] Figure 15This is a flowchart illustrating a method for operating a flit decoder according to some embodiments. (Refer to...) Figure 15 The communication device can communicate with other communication devices via a communication interface circuit. The communication device may include a flit decoder. The flit decoder can be... Figure 10 The flit decoder 120 is shown in the image.

[0176] In operation S310, the flit decoder can receive data packets including a first data packet fragment PF1, a second data packet fragment PF2, and a third data packet fragment PF3.

[0177] In operation S320, the flit decoder can generate a first decoded data packet PFDe1, a second decoded data packet PFDe2, and a third ECC decoded data packet PFDe3 based on the first data packet fragment PF1, the second data packet fragment PF2, and the third data packet fragment PF3.

[0178] In operation S330, the flit decoder can generate a first interleaved data packet PI1 based on the data packet fragment PFDe1 decoded by the first ECC, the data packet fragment PFDe2 decoded by the second ECC, and the data packet fragment PFDe3 decoded by the third ECC.

[0179] In operation S340, the flit decoder may perform a first CRC decoding operation on the first interleaved data packet PI1. The flit decoder may generate an enable signal EN in response to the failure of the first CRC decoding operation. For example, the first data packet fragment PF1 may include a first symbol to a Kth symbol. The first symbol to the Kth symbol may include a first estimated erroneous symbol to an Nth estimated erroneous symbol. Two of the first estimated erroneous symbols to the Nth estimated erroneous symbol may be erroneous symbols. The first CRC decoding operation may fail based on the two erroneous symbols of the first data packet fragment PF1. "K" may represent the number of symbols in the first data packet fragment PF1. "N" may represent the number of estimated erroneous symbols and may be less than "K".

[0180] In operation S350, the flit decoder can generate first bitstream information bs1, which is used to identify the first estimated error symbol to the Nth estimated error symbol among the first symbol to the Kth symbol of the first data packet fragment PF1.

[0181] In operation S360, the flit decoder may perform post-decoding operations based on the enable signal EN, the first bitstream information bs1, and the first data packet fragment PF1. Operation S360 may include operations S361 to S364.

[0182] In operation S361, the flit decoder can generate first index values ​​iv1 to Nth index values ​​ivN, respectively, corresponding to the first estimated error symbols to the Nth estimated error symbols, based on the enable signal EN and the first bit stream information bs1.

[0183] For example, the flit decoder can generate first to Nth segment values, each with a bit string type, based on the one-hot encoding operation of the first bit stream information bs1. The flit decoder can also generate first to Nth index values, each with an integer type, based on the type conversion operation of the first to Nth segment values.

[0184] In operation S362, the flit decoder can generate first candidate information ci1 to Mth candidate information ciM, where the first candidate information ci1 to Mth candidate information ciM indicate two of the first index values ​​iv1 to Nth index values ​​ivN that are combined without repetition and without regard to order. "M" can be... .

[0185] For example, the flit decoder can generate a count value corresponding to "N" based on the counting operation of the first bitstream information bs1. The flit decoder can perform operations based on the first index value iv1 to the Nth index value ivN and the count value. Combine arithmetic operations to generate candidate information ci1 to candidate information ciM.

[0186] In operation S363, the flit decoder can generate first erasure decoding data packet fragments PFDer1 to Mth erasure decoding data packet fragments PFDerM based on the first data packet fragment PF1 and the first candidate information ci1 to the Mth candidate information ciM.

[0187] During operation S364, the flit decoder can select one of the first erasure decoding packet fragments PFDer1 to the Mth erasure decoding packet fragments PFDerM as the subsequent decoded packet fragment PFDp. The subsequent decoded packet fragment PFDp can be used to replace the first ECC decoded packet fragment PFDe1.

[0188] During operation S370, the flit decoder can generate a second interleaved data packet PI2 based on the post-decoded data packet fragment PFDp, the second ECC-decoded data packet fragment PFDe2, and the third ECC-decoded data packet fragment PFDe3.

[0189] Subsequently, the flit decoder can perform a second CRC decoding operation based on the second interleaved data packet PI2. In response to a successful second CRC decoding operation, the flit decoder can obtain the TLP and DLP from the CRC-decoded data packet and provide them to the upper layer. In response to a failed second CRC decoding operation, the flit decoder can generate a request signal for retransmission of the data packet.

[0190] According to various embodiments, a flit decoder for generating decoded data packet fragments, a communication device including the flit decoder, and a method for operating the flit decoder are provided.

[0191] According to various embodiments, a flit decoder, a communication device including the flit decoder, and a method for operating the flit decoder are provided, wherein error correction capability is improved and packet retransmission rate is reduced by performing erasure decoding operations on combinations of estimated erroneous symbols.

[0192] The above description describes detailed embodiments for carrying out this disclosure. Embodiments in which the design is simply modified or easily altered may be included in this disclosure and the various embodiments described above. Furthermore, techniques that can be easily modified and implemented using the above embodiments may be included in this disclosure. Therefore, the scope of this disclosure should not be limited to the above embodiments and should be defined not only by the claims but also by those equivalent to the claims of this disclosure.

Claims

1. A flit decoder, comprising: an error correction code decoder configured to generate a first error correction code decoded flit based on a first flit; an interleaver circuit configured to generate a first interleaved flit based on the first error correction code decoded flit; a cyclic redundancy check decoder configured to generate an enable signal based on a first cyclic redundancy check decoding operation of the first interleaved flit failing; a reliability calculator configured to generate bitstream information identifying a first estimated error symbol to an Nth estimated error symbol among a plurality of symbols of the first flit; and a post-decoder configured to: generate, in response to the enable signal, a first index value to an Nth index value corresponding to the first estimated error symbol to the Nth estimated error symbol based on the bitstream information; generate a first candidate information to an Mth candidate information indicating two of the first index value to the Nth index value combined without repetition and without considering order; generate a first erasure decoding decoded flit to an Mth erasure decoding decoded flit based on the first flit and the first candidate information to the Mth candidate information; and provide a selected one of the first erasure decoding decoded flit to the Mth erasure decoding decoded flit to the interleaver circuit, where "N" is a positive integer less than a number of the plurality of symbols, and wherein "M" is .

2. The flit decoder of claim 1, wherein, the post-decoder comprises: an erasure position calculator configured to be activated based on the enable signal and to generate the first candidate information to the Mth candidate information based on the bitstream information; an erasure decoder configured to generate the first erasure decoding decoded flit to the Mth erasure decoding decoded flit by performing an erasure decoding operation on the first flit based on the first candidate information to the Mth candidate information; and a selection circuit configured to select one of the first erasure decoding decoded flit to the Mth erasure decoding decoded flit having a smallest difference value as a post-decoded flit based on a comparison operation of each of the first erasure decoding decoded flit to the Mth erasure decoding decoded flit with the first flit, and replace the first error correction code decoded flit buffered by the interleaver circuit with the post-decoded flit.

3. The flit decoder of claim 2, wherein, the erasure position calculator comprises: a splitter configured to generate a first split value to an Nth split value each having a bit string type based on a one-hot encoding operation of the bitstream information; an index value generator configured to generate a first index value to an Nth index value each having an integer type based on a type conversion operation of the first split value to the Nth split value; a counter configured to generate a count value corresponding to "N" based on a counting operation of the bitstream information; and The combiner is configured to generate the first candidate information to the Mth candidate information by performing an arithmetic operation based on the first index value to the Nth index value and the count value. The combiner is configured to generate the first candidate information to the Mth candidate information by performing an arithmetic operation based on the first index value to the Nth index value and the count value.

4. The flit decoder of claim 1, wherein, the plurality of symbols of the first flit comprises a first symbol to a Kth symbol, where each of the first symbol to the Kth symbol comprises four pulse amplitude modulation (PAM-4) symbols, where the reliability calculator is configured to: determine whether at least one of the four PAM-4 symbols corresponding to a Jth symbol among the first symbol to the Kth symbol has an unreliable voltage level; in response to determining that at least one of the four PAM-4 symbols has an unreliable voltage level, setting a bit of the bitstream information corresponding to the Jth symbol to a first bit value; and in response to determining that none of the four PAM-4 symbols has an unreliable voltage level, setting the bit of the bitstream information corresponding to the Jth symbol to a second bit value, wherein "K” is a number of the plurality of symbols of the first data packet segment, and wherein "J” is a positive integer less than or equal to "K”.

5. The flit decoder of claim 1, wherein, The interleaver circuit is further configured to receive the selected one of the first through Mth erasure-decoded data packet segments from the post-decoder and generate a second interleaved data packet based on the selected one instead of the first error correction code-decoded data packet segment, and wherein the cyclic redundancy check decoder is further configured to perform a second cyclic redundancy check decoding operation on the second interleaved data packet.

6. The flit decoder of claim 5, wherein, The cyclic redundancy check decoder is further configured to generate a cyclic redundancy check-decoded data packet based on a pass of the second cyclic redundancy check decoding operation, and wherein the flit decoder further comprises: a data packet interface circuit configured to generate a transaction layer data packet and a data link layer data packet based on the cyclic redundancy check-decoded data packet, provide the transaction layer data packet to the transaction layer, and provide the data link layer data packet to the data link layer.

7. The flit decoder of claim 5, wherein, The cyclic redundancy check decoder is further configured to generate a request signal for retransmission of the data packet including the first data packet segment based on a failure of the second cyclic redundancy check decoding operation.

8. The flit decoder of any of claims 1 to 7, wherein, The error correction code decoder has an error correction capability corresponding to one symbol per data packet segment, and wherein the post-decoder has an error correction capability corresponding to two symbols per data packet segment, the positions of the two symbols being estimated.

9. The flit decoder of any of claims 1 to 7, wherein, The first data packet segment has a size of 86 bytes, and wherein the first data packet segment includes 79 transaction layer data packet symbols, 2 data link layer data packet symbols, 3 cyclic redundancy check parity symbols, and 2 error correction code parity symbols.

10. The flit decoder of any of claims 1 to 7, wherein, The first data packet segment has a size of 85 bytes, and wherein the first data packet segment includes 79 transaction layer data packet symbols, 2 data link layer data packet symbols, 2 cyclic redundancy check parity symbols, and 2 error correction code parity symbols.

11. The flit decoder of any of claims 1 to 7, wherein, The first data packet segment has a size of 85 bytes, and wherein the first data packet segment includes 78 transaction layer data packet symbols, 2 data link layer data packet symbols, 3 cyclic redundancy check parity symbols, and 2 error correction code parity symbols.

12. The flit decoder of claim 1, wherein, The error correction code decoder is further configured to: receive a data packet including a first data packet segment, a second data packet segment, and a third data packet segment, generate a second error correction code-decoded data packet segment based on the second data packet segment, and generate a third error correction code-decoded data packet segment based on the third data packet segment, and wherein the interleaver circuit is further configured to generate a first interleaved data packet based on an interleaving operation of the first error correction code-decoded data packet segment, the second error correction code-decoded data packet segment, and the third error correction code-decoded data packet segment.

13. The flit decoder of claim 12, wherein, The error correction code decoder includes: a data packet distributor configured to generate a first data packet segment, a second data packet segment, and a third data packet segment based on a distribution operation of a data packet; a first error correction code sub-decoder configured to generate a first error correction code decoded data packet segment based on a first error correction code decoding operation of the first data packet segment; a second error correction code sub-decoder configured to generate a second error correction code decoded data packet segment based on a second error correction code decoding operation of the second data packet segment; and a third error correction code sub-decoder configured to generate a third error correction code decoded data packet segment based on a third error correction code decoding operation of the third data packet segment.

14. The flit decoder of claim 1, wherein, The flit decoder supports a flit mode of a Peripheral Component Interconnect Express standard, and wherein the data packet including the first data packet segment conforms to a format of the flit mode.

15. A communication apparatus comprising: input / output circuitry comprising a plurality of transmitters and a plurality of receivers; a flit encoder configured to provide a first data packet to the plurality of transmitters; and a flit decoder configured to receive a second data packet from the plurality of receivers, wherein the flit decoder comprises: an error correction code decoder configured to generate error correction code decoded data packet segments based on data packet segments of the second data packet; interleaver circuitry configured to generate interleaved data packets based on the error correction code decoded data packet segments; a cyclic redundancy check decoder configured to generate an enable signal based on a failure of a cyclic redundancy check decoding operation of the interleaved data packets; a reliability calculator configured to generate bitstream information identifying a first estimated error symbol to an Nth estimated error symbol among a plurality of symbols of the data packet segments of the second data packet; and a post-decoder configured to: generate, in response to the enable signal, a first index value to an Nth index value corresponding to the first estimated error symbol to the Nth estimated error symbol based on the bitstream information; generate first candidate information to Mth candidate information indicating two of the first index value to the Nth index value combined without repetition and without considering order; generate first erasure decoding data packet segments to Mth erasure decoding data packet segments based on the data packet segments of the second data packet and the first candidate information to the Mth candidate information; and provide a selected one of the first erasure decoding data packet segments to the Mth erasure decoding data packet segments to the interleaver circuitry, wherein "N" is a positive integer less than a number of the plurality of symbols, and the post-decoder comprises: wherein "M" is .

16. The communication apparatus of claim 15, wherein, an erasure position calculator configured to be activated based on the enable signal and to generate the first candidate information to the Mth candidate information based on the bitstream information; an erasure decoder configured to generate the first erasure decoding data packet segments to the Mth erasure decoding data packet segments by performing an erasure decoding operation on the data packet segments of the second data packet based on the first candidate information to the Mth candidate information; and ​ The selection circuit is configured to select one of the first erasure-decoded data packet segment to the Mth erasure-decoded data packet segment as a post-decoded data packet segment based on a comparison operation of each of the first erasure-decoded data packet segment to the Mth erasure-decoded data packet segment with the data packet segment of the second data packet, and replace the error correction code-decoded data packet segment buffered by the interleaver circuit with the post-decoded data packet segment.

17. The communication apparatus of claim 16, wherein, The erasure position calculator includes: The splitter is configured to generate the first split value to the Nth split value each having a bit string type based on a one-hot encoding operation of the bit stream information; The index value generator is configured to generate the first index value to the Nth index value each having an integer type based on a type conversion operation of the first split value to the Nth split value; The counter is configured to generate a count value corresponding to "N" based on a counting operation of the bit stream information; and The combiner is configured to generate the first candidate information to the Mth candidate information by performing an arithmetic operation based on the first index value to the Nth index value and the count value. The combiner is configured to generate the first candidate information to the Mth candidate information by performing an arithmetic operation based on the first index value to the Nth index value and the count value. 18.A method of operating a flit decoder, the method comprising: receiving a data packet including a first data packet segment, a second data packet segment, and a third data packet segment; generating a first error correction code-decoded data packet segment, a second error correction code-decoded data packet segment, and a third error correction code-decoded data packet segment based on the first data packet segment, the second data packet segment, and the third data packet segment; generating a first interleaved data packet based on the first error correction code-decoded data packet segment, the second error correction code-decoded data packet segment, and the third error correction code-decoded data packet segment; generating an enable signal based on a failure of a first cyclic redundancy check decoding operation of the first interleaved data packet; generating bit stream information for identifying a first estimated error symbol to an Nth estimated error symbol among a plurality of symbols of the first data packet segment, "N" being a positive integer smaller than a number of the plurality of symbols; generating a first index value to an Nth index value corresponding to the first estimated error symbol to the Nth estimated error symbol, respectively, based on the enable signal and the bit stream information; generating first candidate information to Mth candidate information, the first candidate information to the Mth candidate information indicating two of the first index value to the Nth index value combined without repetition and regardless of order, "M" being ; generating a first erasure-decoded data packet segment to an Mth erasure-decoded data packet segment based on the first data packet segment and a first candidate information to an Mth candidate information; selecting one of the first erasure-decoded data packet segment to the Mth erasure-decoded data packet segment as a post-decoded data packet segment; and generating a second interleaved data packet based on the post-decoded data packet segment, the second error correction code-decoded data packet segment, and the third error correction code-decoded data packet segment.

19. The method of claim 18, wherein, The step of generating the first index value to the Nth index value includes: generating the first split value to the Nth split value each having a bit string type based on a one-hot encoding operation of the bit stream information; and generating the first index value to the Nth index value each having an integer type based on a type conversion operation of the first split value to the Nth split value; wherein the step of generating the first candidate information to the Mth candidate information includes: generating a count value corresponding to "N" based on a counting operation of the bit stream information; and The first candidate information to the Mth candidate information are generated by performing a combination arithmetic operation based on the first index value to the Nth index value and the count value. The first candidate information to the Mth candidate information are generated by performing a combination arithmetic operation based on the first index value to the Nth index value and the count value. 20.The method of claim 18, further comprising: performing a second cyclic redundancy check decoding operation on the second interleaved data packet; and A request signal for retransmission of the data packet is generated based on a failure of a second cyclic redundancy check decoding operation.

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