A method for implementing a ZUC algorithm linear sub-component suitable for multiple scenarios

Abstract

The application relates to a kind of implementation methods of ZUC algorithm linear subcomponent applicable to multiple scenarios.The method comprises the following steps: according to the definition of linear subcomponent in ZUC algorithm, the linear transformation matrix expression of linear subcomponent input bit sequence to output bit sequence is constructed; the linear transformation matrix expression is divided in structure, and the original large-scale matrix operation is decomposed into at least two independent small-scale matrix operations; according to each small-scale matrix, a logic gate level implementation scheme based on in-place XOR operation is designed, and a bit operation sequence is generated; according to the data dependency relationship between each bit operation sequence, the logic gate level implementation scheme is mapped to a plurality of physical circuit modules with hierarchical connection relationship, so that all physical circuit modules jointly constitute a component structure applicable to multiple scenarios.Using the method can enhance the reliability and applicability of the communication system or equipment in executing ZUC algorithm.

Description

Technical Field

[0001] This application relates to the field of information security technology, and in particular to an implementation method of the linear sub-component of the ZUC algorithm applicable to multiple scenarios. Background Technology

[0002] Symmetric cryptography algorithms are widely used in various scenarios, playing a crucial role in protecting data privacy and security. In file encryption, VPNs, wireless communication, and storage encryption, symmetric cryptography is favored due to its fast processing speed and low resource overhead. Therefore, optimizing the implementation of symmetric cryptography algorithms in classical application scenarios has become a research hotspot. Furthermore, the development of quantum technology has brought certain security challenges to cryptographic algorithms. The quantum implementation of cryptographic algorithms is indispensable for launching quantum attacks. Therefore, the quantum-optimized implementation of symmetric cryptographic algorithms is also of great interest. The ZUC algorithm is an important component of my country's commercial cryptographic algorithm system and has become an international standard. The design and application of the ZUC algorithm reflect the dual focus on efficiency and security in modern cryptography, demonstrating strong performance and reliability in practical applications, and is therefore widely used to ensure the security of mobile communication data.

[0003] For symmetric cryptography algorithms, the linear layer is a crucial component. The main purpose of the linear layer is to break the inherent relationships between data, making the relationship between the input and output of the linear layer more complex, increasing the difficulty for attackers to crack the algorithm, thereby increasing the algorithm's complexity and improving its security. For the ZUC algorithm, It is an important component of its linear layer.

[0004] The implementation of linear layers is typically based on linear transformations, most commonly matrix multiplication. Research indicates that the implementation of the matrix corresponding to the linear layer in a cryptographic algorithm significantly impacts the algorithm's security and efficiency. Finding the optimal implementation of the matrix is ​​an NP-hard problem, limiting existing methods to designing only relatively superior implementations. Furthermore, matrix dimension and density significantly affect the efficiency of current matrix implementation search methods. For example, as the matrix size increases, existing methods take longer to develop a suitable implementation, resulting in less than satisfactory performance. Whether for classical or quantum applications, the optimized implementation of linear layers remains a hot research topic in symmetric cryptography. Summary of the Invention

[0005] Therefore, it is necessary to address the aforementioned technical problems by providing a method for implementing the ZUC algorithm linear sub-component in multiple scenarios that can ensure the security of communication data, improve the reliability and applicability of cryptographic algorithms during communication, and effectively reduce the area required for classical circuit implementation and the cost of quantum implementation of the ZUC algorithm.

[0006] A method for implementing a linear subcomponent of the ZUC algorithm applicable to multiple scenarios, used to optimize the linear transformation hardware circuit and quantum circuit of the ZUC cryptographic algorithm, the method comprising:

[0007] Based on the definition of the linear sub-component in the ZUC algorithm, construct the linear transformation matrix expression from the input bit sequence to the output bit sequence of the linear sub-component.

[0008] The linear transformation matrix expression is structurally partitioned, decomposing the original large-scale matrix operation into at least two independent small-scale matrix operations.

[0009] For each small-scale matrix, design a logic gate-level implementation scheme based on in-situ XOR operation to generate a bit operation sequence.

[0010] Based on the data dependencies between each operation sequence, the logic gate-level implementation scheme is mapped to multiple physical circuit modules with hierarchical connections, so that all physical circuit modules together constitute a component structure suitable for multiple scenarios.

[0011] The aforementioned method for implementing the linear subcomponent of the ZUC algorithm in multiple scenarios firstly involves directly searching for implementation schemes on a large-scale binary matrix. However, as the scale increases, the search space expands exponentially, leading to a dramatic increase in time consumption and often suboptimal results. To address this, the linear transformation matrix expression is structurally partitioned. By deeply analyzing the variable dependencies of the output bit expression, its inherent parity-separability is discovered and utilized, decomposing a single large-scale matrix operation into two independent small-scale matrix operations. This reduces the complexity and time of the optimization search, making deep and refined optimization of each submatrix possible and efficient. Secondly, at the implementation level, multi-scenario adaptability is achieved. Based on the decomposed small-scale matrices, a unified logic gate-level implementation scheme based on in-situ XOR operations is designed, generating an optimized bit operation sequence. This sequence possesses a crucial dual-mapping characteristic: in classical CMOS circuits, it directly corresponds to S-XOR logic gate operations; in quantum circuits, it is equivalent to CNOT gate operations. This "one design, two implementations" architecture allows the same highly optimized core algorithm to be seamlessly applied to both classical information security chips and quantum cryptographic coprocessors, greatly expanding the applicability of the technology. Ultimately, by mapping the optimized bit operation sequence to multiple physical circuit modules with clear hierarchical connections based on data dependencies, not only is extreme optimization of hardware resources (number of logic gates / qubit gates) achieved, but also a highly efficient, reliable, and integrable hardware entity is constructed. The reduction in the number of gates directly translates to a reduction in circuit area and power consumption, and a potential increase in operating speed, which is crucial in resource-constrained embedded security devices and quantum computing where fault tolerance costs are extremely high. Smaller, faster, and more energy-efficient hardware implementations directly enhance the reliability and real-time performance of communication devices or systems integrating this component when executing the ZUC algorithm. Simultaneously, its adaptability to both classical and quantum scenarios provides a unified and forward-looking cryptographic hardware solution for addressing security challenges in both current classical computing environments and future quantum computing environments, fundamentally strengthening the protection of information data throughout its entire lifecycle and effectively reducing the area and implementation cost of the ZUC algorithm for classical circuits. Attached Figure Description

[0012] Figure 1 Here is a flowchart of a ZUC algorithm in one embodiment;

[0013] Figure 2 This is a flowchart illustrating an implementation method of a linear sub-component of the ZUC algorithm applicable to multiple scenarios in one embodiment;

[0014] Figure 3 For one embodiment The flowchart for further partitioning the expressions of the 32 output variables;

[0015] Figure 4 ZUC algorithm subcomponent in one embodiment Optimized implementation modules suitable for various application scenarios;

[0016] Figure 5 ZUC algorithm subcomponent in one embodiment A flowchart outlining the optimization steps applicable to various application scenarios. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0018] This application provides a method for implementing the linear sub-component of the ZUC algorithm in multiple scenarios, used to optimize the implementation of the linear sub-component for various scenarios. Figure 1 The linear transformation of the ZUC algorithm shown Partial. Recovery sub-component The output expression for The output expression is further partitioned to reduce the problem size, and an optimized implementation scheme for small-scale matrices is designed, employing modular design. Implementation methods applicable to various application scenarios.

[0019] In one embodiment, such as Figure 2 As shown, a method for implementing the linear sub-component of the ZUC algorithm applicable to multiple scenarios is provided, which is used to optimize the linear transformation hardware circuit of the ZUC cryptographic algorithm, including the following steps:

[0020] Step 202: Based on the definition of the linear sub-component in the ZUC algorithm, construct the linear transformation matrix expression from the input bit sequence to the output bit sequence of the linear sub-component.

[0021] Specifically, linear sub-components are recovered based on the definition of ZUC algorithm components. The output variable expression, ZUC algorithm subcomponent Both the input and output are 32 bits. The inputs and outputs are respectively and ,have:

[0022] ;

[0023] As can be seen from the design principle of the ZUC algorithm, sub-components The definition is as follows:

[0024] ;

[0025] in and They are respectively Inputs and outputs, " indicates a circular left shift operation.

[0026] Furthermore, for a vector, the state obtained by XORing its state with its own state after a circular left shift can be represented as an expression about its own components. For example, suppose... ,but .remember The output is .but Each component , , This can be specifically expressed as follows regarding vectors Each component , , The expression:

[0027] ;

[0028] ;

[0029] ;

[0030] Therefore, the ZUC algorithm sub-component The 32 output variables can also be represented as expressions about their input variables. Let... The inputs and outputs are respectively and Output variables Specifically, it can be represented as follows:

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[0063] Step 204: Perform structural partitioning on the linear transformation matrix expression, decomposing the original large-scale matrix operation into at least two independent small-scale matrix operations.

[0064] Specifically, for The expression for the output variable is further divided to reduce the problem's solution scale; linear transformations can be represented as matrix multiplication operations. Therefore, the ZUC algorithm sub-components are optimized. This can be achieved by improving the implementation of its corresponding matrix. However, this binary matrix is ​​quite large, with dimensions of 1 / 2. Searching for its implementation using existing methods is very time-consuming, and the resulting implementation is not satisfactory.

[0065] Further observation From the expressions of the 32 output variables, it can be seen that each output variable expression is linearly related to only 5 input variables. This means that once from... Selecting a number of expressions from the 32 output expressions such that the selected expressions are linear expressions with fewer than 32 input variables, and the remaining expressions are also linear expressions with fewer than 32 input variables, allows us to achieve [the desired result]. The problem starts from implementation The binary matrix is ​​transformed into a smaller matrix, thus reducing the solution size of the problem. Note that reducing the solution size helps in designing better implementations of large-scale matrices for specific metrics (such as the number of logic gates). For example, transforming a... The implementation of a binary matrix is ​​transformed into several When implementing a binary matrix ( (The marker indicates the matrix number). Once the sum of the costs of implementing the above matrices is less than the cost of directly implementing the original... The cost of a binary matrix, i.e., finding a... A better implementation method for binary matrices.

[0066] Step 206: Design a logic gate-level implementation scheme based on in-situ XOR operation for each small-scale matrix, and generate a bit operation sequence.

[0067] Specifically, for Two output expressions and In other words, if they are about Given expressions with different input variables, then... and from Selecting from the 32 output expressions does not significantly reduce the solution size (matrix size). However, if... and If the variables involved in the expression have overlap, the solution size (matrix size) of the problem may be reduced. Taking the output expression as an example, , and All are linearly correlated with the five input variables, as shown in the following expressions:

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[0071] If and from The 32 output expressions were selected and categorized into one class. and The calculation involves 10 input variables, namely... , , , , , , , , , This means and The implementation actually corresponds to a The implementation of a binary matrix, namely:

[0072] ;

[0073] If and from The 32 output expressions were selected and categorized into one class. and The calculation depends on nine input variables. This is because in and Simultaneously appearing and In the expression. Therefore, and The implementation actually corresponds to a The implementation of a binary matrix. From a matrix perspective, The matrix has a relatively large dimension The matrix dimension is large, and its implementation process requires consideration of many more factors. Therefore, compared to selecting... and , choose to and Categorizing them into one category is more beneficial for design. Optimized implementation.

[0074] Furthermore, such as Figure 3 As shown, in order to The expressions for the 32 output variables are further divided, and the following steps are performed:

[0075] Step 1: Define variables and and initialize Proceed to step 2;

[0076] Step 2: Define an empty set For storage The output variable, and deposit ,Right now Proceed to step 3;

[0077] Step 3: Order ,like Less than 32 means that for The repartitioning of the expression for the 32 output variables is not yet complete; proceed to step 4. Otherwise, proceed to... The repartitioning of the expressions for the 32 output variables has been completed, so proceeding to step 5 yields the results. A complete reclassification method for expressions with 32 output variables;

[0078] Step 4: For the current items to be classified Judge its expression in turn. , , , Do the expressions for the variables in the expression have the same variable? If so (assuming they are the same as...) If the expressions containing variables have the same variable, then... deposit the corresponding Among them Proceed to step 3; otherwise, if , , , If none of the expressions for the variables in the middle have common variables, then let Then proceed to step 2;

[0079] Step 5: Obtain the correct answer The repartitioning of the expression for the 32 output variables, i.e. , , .

[0080] Furthermore, by using the above steps, it is possible to The 32 output expressions were re-divided into two parts. and Therefore, to achieve Transformed into utilization , , , Compute set Elements in, and computed sets The elements in.

[0081] Specifically, sets The expressions involved are as follows:

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[0098] gather The expressions involved are as follows:

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[0115] Furthermore, further observation of the two sets mentioned above and the expressions containing the output variables reveals that, for the set... In other words, it includes The 16 output expressions, and these expressions can be based on The calculation of the 16 input variables, i.e. , , , This means achieving In reality, it is to achieve a A binary matrix. Similarly, for the set... In other words, it also includes The 16 output expressions, and these expressions can be based on The calculation of the 16 input variables, i.e. , , , This means achieving In reality, it is also to achieve a A binary matrix. Therefore, the sub-components for implementing the ZUC algorithm... This is equivalent to achieving two A binary matrix.

[0116] Step 208: Based on the data dependencies between each operation sequence, the logic gate-level implementation scheme is mapped to multiple physical circuit modules with hierarchical connections, so that all physical circuit modules together constitute a component hardware structure suitable for multiple scenarios.

[0117] Specifically, based on the The design of the output variable expression partitioning scheme is based on an optimized implementation scheme for small-scale matrices, using sets... Taking the output variables included in the example, , , , Both can be expressed as about , , , The linear expression for can therefore be represented by matrix multiplication, i.e.:

[0118] , , , ;

[0119] in As follows A binary matrix: 1000100100010001 1100010010001000 0110001001000100 0011000100100010 0001100010010001 1000110001001000 0100011000100100 0010001100010010 0001000110001001 1000100011000100 0100010001100010 0010001000110001 1001000100011000 0100100010001100 0010010001000110 0001001000100011

[0136] Implement matrix It can be calculated It contains 16 output variables.

[0137] Using matrices Based on the form The implementation scheme of the operation can compute sets for various application scenarios. The output variables included are shown in Table 1 below.

[0138] Table 1 Collection Optimization of the output variables involved

[0139]

[0140] The results in the table above show that in the ZUC algorithm sub-component The 32 output variables are stored in a set The 16 in the middle can be used in 41 forms such as The operation implementation, and Output , , , The value is stored in the input variable , , , Table 2 below lists the correspondence between the subscripts of matrix output variables and matrix input variables. The value is stored in the variable middle.

[0141] Table 2 shows the correspondence between the values ​​of output variables and the values ​​of input variables.

[0142]

[0143] With sets The calculation method for output variables is similar to that of sets. The output variables contained therein can be calculated in the same way. (Set) The specific implementation of the optimized output variables involved is shown in Table 3 below.

[0144] Table 3 Collection Optimization of the output variables involved

[0145]

[0146] As can be seen from the results in Table 3 above, in the ZUC algorithm sub-component The 32 output variables are stored in a set The 16 in the middle can be used in 41 forms such as The operation implementation, and Output , , , The value is stored in the input variable , , , The table below shows the correspondence between the subscripts of matrix output variables and matrix input variables. The value is stored in the variable middle.

[0147] Table 4 shows the correspondence between the values ​​of output variables and the values ​​of input variables.

[0148]

[0149] Furthermore, modular design to meet different needs Circuits suitable for various application scenarios, based on the sets listed in Tables 1 and 3. and The optimized implementation of the output variables allows for the computation of ZUC algorithm sub-components. The 32 outputs. To more intuitively represent the sub-components of the ZUC algorithm. This is implemented by further modularizing the operations listed in Tables 1 and 3. Specifically:

[0150] (1) Module 1

[0151] Module 1 32 input variables , , , As input, 36 operations are executed sequentially to update. , , , , , , , The value of .

[0152] The specific operations for Module 1 are as follows: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , .

[0153] (2) Module 2

[0154] Module 2 12 input variables , , , , , , , , , As input, where , , , , , , , The value is updated in module 1, becoming the output of module 1. Module 2 performs 6 operations to update... , , , , , The value, and generate Output , , , .

[0155] The specific operations for module 2 are as follows: , , , , , ,in, The value is stored in the variable middle, The value is stored in the variable middle, The value is stored in the variable middle, The value is stored in the variable middle.

[0156] (3) Module 3

[0157] Module 3 8 input variables , , , , , , , As input, where , , , , , The value is updated in module 1, becoming the output of module 1. Module 3 performs four operations to update... , , , The value of .

[0158] The specific operations for module 3 are as follows: , , , .

[0159] (4) Module 4

[0160] Module 4 8 input variables , , , , , , , As input, where , The value is updated in module 3, becoming the output of module 3. , , , , , The value is updated in module 1, becoming the output of module 1. Module 4 performs four operations to update... , , , The value, and generate Output , .

[0161] The specific operations for module 4 are as follows: , , , ,in The value is stored in the variable middle, The value is stored in the variable middle.

[0162] (5) Module 5

[0163] Module 5 8 input variables , , , , , , , As input, where , The value is updated in module 4, becoming the output of module 4. , , , The value is updated in module 1, becoming the output of module 1. Module 5 performs four operations to update... , , , The value, and generate Output , .

[0164] The specific operations for module 5 are as follows: , , , ,in The value is stored in the variable middle, The value is stored in the variable middle.

[0165] (6) Module 6

[0166] Module 6 12 input variables , , , , , , , , , As input, where , The value is updated in module 4, becoming the output of module 4. , The value is updated in module 5, becoming the output of module 5. , , , , , The value is updated in module 1, becoming the output of module 1. Module 6 performs 6 operations to update... , , , , , The value, and generate Output , .

[0167] The specific operations for module 6 are as follows: , , , , , ,in The value is stored in the variable middle, The value is stored in the variable middle.

[0168] (7) Module 7

[0169] Module 7 12 input variables , , , , , , , , , , , As input, where , The value is updated in module 2, becoming the output of module 2. , The value is updated in module 3, becoming the output of module 3. , The value is updated in module 6, becoming the output of module 6. , , , , , The value is updated in module 1, becoming the output of module 1. Module 7 performs 6 operations to update... , , , , , The value, and generate Output , , , , .

[0170] The specific operations for module 7 are as follows: , , , , , ,in The value is stored in the variable middle, The value is stored in the variable middle, The value is stored in the variable middle, The value is stored in the variable middle, The value is stored in the variable middle, The value is stored in the variable middle.

[0171] (8) Module 8

[0172] Module 8 4 input variables , , , As input, where , The value is updated in module 3, becoming the output of module 3. , The value is updated in module 1, becoming the output of module 1. Module 8 performs two operations to update... , The value, and generate Output , .

[0173] The specific operations for module 8 are as follows: , ,in The value is stored in the variable middle, The value is stored in the variable middle.

[0174] (9) Module 9

[0175] Module 9 8 input variables , , , , , , , As input, where , The value is updated in module 8, becoming the output of module 8. , The value is updated in module 6, becoming the output of module 6. , The value is updated in module 5, becoming the output of module 5. , The value is updated in module 1, becoming the output of module 1. Module 9 performs four operations to update... , , , The value, and generate Output , , , .

[0176] The specific operation of module 9 is as follows: , , , ,in The value is stored in the variable middle, The value is stored in the variable middle, The value is stored in the variable middle, The value is stored in the variable middle.

[0177] (10) Module 10

[0178] Module 10 4 input variables , , , As input, where , The value is updated in module 6, becoming the output of module 6. , The value is updated in module 1, becoming the output of module 1. Module 10 performs two operations sequentially to update... , The value, and generate Output , .

[0179] The specific operations for module 10 are as follows: , ,in Output Stored in its input variables middle Stored in its input variables middle.

[0180] (11) Module 11

[0181] Module 11 8 input variables , , , , , , , As input, where , The value is updated in module 10, becoming the output of module 10. , The value is updated in module 2, becoming the output of module 2. , , , The value is updated in module 1, becoming the output of module 1. Module 11 performs four operations to update... , , , The value, and generate Output , , , .

[0182] The specific operations of module 11 are as follows: , , , ,in The value is stored in the variable middle The value is stored in the variable middle, The value is stored in the variable middle The value is stored in the variable middle.

[0183] (12) Module 12

[0184] Module 12 4 input variables , , , As input, where , The value is updated in module 2, becoming the output of module 2. , The value is updated in module 1, becoming the output of module 1. Module 12 performs two operations to update... , The value, and generate Output , .

[0185] The specific operations for module 12 are as follows: , ,in The value is stored in the variable middle The value is stored in the variable middle.

[0186] (13) Module 13

[0187] Module 13 4 input variables , , , As input, where , The value is updated in module 2, becoming the output of module 2. , The value is updated in module 1, becoming the output of module 1. Module 13 performs two operations to update... , The value, and generate Output , .

[0188] The specific operations for module 13 are as follows: , ,in The value is stored in the variable middle The value is stored in the variable middle.

[0189] The above implements the ZUC operator component Of the 13 modules, the output of module 1 is the same as... The input is related to the output of the second module. The inputs of module 3 are related to some of the outputs of module 1, and the outputs of module 3 are related to... The partial inputs of module 1 are related to the partial outputs of module 1; the output of module 4 is related to the partial outputs of modules 1 and 3; and the output of module 5 is related to... The output of module 6 is related to the partial inputs of modules 1, 4, and 5; the output of module 7 is related to the partial outputs of modules 1, 2, 3, and 6; the output of module 8 is related to the partial outputs of modules 1 and 3; the output of module 9 is related to the partial outputs of modules 1, 5, 6, and 8; the output of module 10 is related to the partial outputs of modules 1 and 6; the output of module 11 is related to the partial outputs of modules 1, 2, and 10; the output of module 12 is related to the partial outputs of modules 1 and 2; and the output of module 13 is related to the partial outputs of modules 1 and 2. The relationships between the above modules are as follows: Figure 4 As shown, solid lines represent (partial) outputs of this module that will serve as (partial) inputs to the target module, while dashed lines represent outputs of this module that include sub-components of the ZUC algorithm. Partial output.

[0190] In the aforementioned method for implementing the linear subcomponent of the ZUC algorithm applicable to multiple scenarios, firstly, directly searching for implementation schemes for large-scale binary matrices is problematic. As the scale increases, the search space expands exponentially, leading to a dramatic increase in time consumption and often suboptimal results. To address this, the linear transformation matrix expression is structurally partitioned. By deeply analyzing the variable dependencies of the output bit expression, its inherent parity-separability is discovered and utilized, decomposing a single large-scale matrix operation into two independent small-scale matrix operations. This reduces the complexity and time of the optimization search, making deep and refined optimization of each submatrix possible and efficient. Secondly, at the implementation level, multi-scenario adaptability is achieved, achieving two goals at once. Based on the decomposed small-scale matrices, a unified logic gate-level implementation scheme based on in-situ XOR operations is designed, generating an optimized bit operation sequence. This sequence possesses a crucial dual-mapping characteristic: in classical CMOS circuits, it directly corresponds to S-XOR logic gate operations; in quantum circuits, it is equivalent to CNOT gate operations. This "one design, two implementations" architecture allows the same highly optimized core algorithm to be seamlessly applied to both classical information security chips and quantum cryptographic coprocessors, greatly expanding the applicability of the technology. Ultimately, by mapping the optimized bit operation sequence to multiple physical circuit modules with clear hierarchical connections based on data dependencies, not only is extreme optimization of hardware resources (number of logic gates / qubit gates) achieved, but also a highly efficient, reliable, and integrable hardware entity is constructed. The reduction in the number of gates directly translates to a reduction in circuit area and power consumption, and a potential increase in operating speed, which is crucial in resource-constrained embedded security devices and quantum computing where fault tolerance costs are extremely high. Smaller, faster, and more energy-efficient hardware implementations directly enhance the reliability and real-time performance of communication devices or systems integrating this component when executing the ZUC algorithm. Simultaneously, its adaptability to both classical and quantum scenarios provides a unified and forward-looking cryptographic hardware solution for addressing security challenges in both current classical computing environments and future quantum computing environments, fundamentally strengthening the protection of information data throughout its entire lifecycle and effectively reducing the area and implementation cost of the ZUC algorithm for classical circuits.

[0191] In one embodiment, based on the variable dependencies of the output bit expressions of the linear subcomponent, a preset number of output bits are divided into two disjoint sets. The first output set depends on input bits with even indices, and the second output set depends on input bits with odd indices. Based on the first and second output sets, the original large-scale matrix operation is decomposed into a first small-scale matrix operation and a second small-scale matrix operation. The first and second small-scale matrix operations are matrix operations of the same dimension.

[0192] In one embodiment, a specific bit operation sequence consisting of preset bit operations is generated by optimization search based on each of the small-scale matrix operations, wherein the operand of each bit operation corresponds to a specific memory cell of the linear transformation hardware circuit.

[0193] In one embodiment, the bit operation sequence is optimized so that the implementation of the entire linear sub-component requires a total of 82 in-situ XOR operations, which corresponds to 82 S-XOR gates in the classical circuit implementation and 82 CNOT gates in the quantum circuit implementation.

[0194] In one embodiment, a hierarchical circuit topology is constructed, comprising several functional modules. The first module performs a preliminary mixing operation, while the remaining functional modules execute sequentially based on data dependencies. These functional modules are connected via intermediate registers and routing networks, forming a partially pipelined structure with clearly defined data flow directions.

[0195] In one embodiment, at least one of the functional modules has its output port directly connected to the input port of the next-level processing unit of the ZUC algorithm, so as to complete the integration of the linear sub-unit with other components of the ZUC algorithm.

[0196] In one embodiment, such as Figure 5 As shown, a ZUC algorithm sub-component is provided. The optimization implementation steps, applicable to various application scenarios, are as follows:

[0197] Recover the linear sub-component based on the definition of ZUC algorithm components. The output variable expression;

[0198] right The expression for the output variable is further divided to reduce the problem's solution size;

[0199] The process of dividing the work begins;

[0200] Define variables and and initialize ;

[0201] Define an empty set ,initialization ;

[0202] make like Less than 32 means that for The repartitioning of the expression for the 32 output variables is not yet complete; the check for existence is still in progress. belong satisfy The expression and Do the expressions containing variables in the code have the same variable? If so, update... If not, then let ;

[0203] like Not less than 32, for The repartitioning of the expressions for the 32 output variables has been completed, so the output will be executed directly. The division of the expression for the output variable , ;

[0204] The partitioning process is complete;

[0205] Based on The design of the output variable expression partitioning scheme is optimized for small-scale matrices;

[0206] Modular design for different needs Implementation methods applicable to various application scenarios.

[0207] It should be understood that, although Figures 1-3 , Figure 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-3 , Figure 5 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0208] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink, DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0209] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0210] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for implementing the linear sub-component of the ZUC algorithm applicable to multiple scenarios, characterized in that, The method for optimizing linear transformation hardware circuits and quantum circuits in the ZUC cryptographic algorithm includes: Based on the definition of the linear sub-component in the ZUC algorithm, construct the linear transformation matrix expression from the input bit sequence to the output bit sequence of the linear sub-component; The linear transformation matrix expression is structurally divided, and the original large-scale matrix operation is decomposed into at least two independent small-scale matrix operations. The specific steps are as follows: according to the variable dependency relationship of each output bit expression of the linear sub-component, the number of output bits corresponding to the preset value is divided into two non-overlapping sets, wherein the first output set depends on the input bits with even subscripts, and the second output set depends on the input bits with odd subscripts. Based on the first output set and the second output set, the original large-scale matrix operation is decomposed into a first small-scale matrix operation and a second small-scale matrix operation; the first small-scale matrix operation and the second small-scale matrix operation are matrix operations of the same dimension; Design a logic gate-level implementation scheme based on in-situ XOR operation for each small-scale matrix, and generate a bit operation sequence. The specific steps are as follows: generate a specific bit operation sequence composed of preset bit operations by optimizing the operation of each small-scale matrix, wherein the operand of each bit operation corresponds to a specific memory unit of the linear transformation circuit. Based on the data dependencies between the bit operation sequences, the logic gate-level implementation scheme is mapped to multiple physical circuit modules with hierarchical connections, so that all the physical circuit modules together constitute a component structure suitable for multiple scenarios.

2. The method according to claim 1, characterized in that, The bit operation sequence is optimized so that the implementation of the entire linear sub-component requires a total of 82 in-situ XOR operations, which corresponds to 82 S-XOR gates in classical circuit implementation and 82 CNOT gates in quantum circuit implementation.

3. The method according to claim 1, characterized in that, Based on the data dependencies between the bit operation sequences, the logic gate-level implementation scheme is mapped to multiple physical circuit modules with hierarchical connections, including: Construct a hierarchical circuit topology with several functional modules, where the first module performs a preliminary mixing operation, and the remaining functional modules execute sequentially according to data dependencies. The functional modules are connected through intermediate registers and routing networks to form a partially pipelined structure with a clear data flow direction.

4. The method according to claim 3, characterized in that, At least one of the functional modules has its output port directly connected to the input port of the next-level processing unit of the ZUC algorithm, so as to complete the integration of the linear sub-unit with other components of the ZUC algorithm.

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