Method for manufacturing wiring board

Abstract

The invention provides a method for manufacturing a wiring board. The wiring board is provided with a via hole conductor which is accurately formed. A method of manufacturing a wiring board according to an embodiment includes the steps of: preparing a support substrate having a metal film layer (ML2) formed on a surface thereof; forming a plating film layer (122) including an alignment pattern (AP) on the metal film layer (ML2); forming an insulating layer (11) covering the plating film layer (122); forming a through hole penetrating the insulating layer (11) in the thickness direction by irradiating the insulating layer (11) with laser light (LL) by referring to position information obtained from the alignment pattern (AP); and forming a via conductor by filling the through hole with a conductor. The step in which the plating film layer (122) is formed includes a step in which the positive reflectance of light having a predetermined wavelength on the upper surface of the metal film layer (ML2) is made different from the positive reflectance of light having a predetermined wavelength on the upper surface of the plating film layer (122).

Description

Technical Field

[0001] This invention relates to a method for manufacturing a wiring substrate. Background Technology

[0002] Patent Document 1 discloses a method for manufacturing a wiring substrate. In the method disclosed in Patent Document 1, for example, a resist layer with an opening is formed on a support body serving as copper foil, and a first wiring layer is formed within the opening of the resist layer. After forming the first wiring layer, the resist layer is removed, and a first insulating layer is formed on the first wiring layer and on the copper foil exposed from the pattern of the first wiring layer. Vias are formed by laser processing the first insulating layer, and via wiring is formed within the vias.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2012-9606

[0004] In the wiring substrate manufacturing method disclosed in Patent Document 1, it is believed that there are cases where vias are difficult to form precisely relative to the positions where vias should be formed in the first insulating layer. Summary of the Invention

[0005] The method for manufacturing a wiring substrate according to the present invention includes the following steps: preparing a support substrate on which a metal film layer is formed on its surface; forming a plating film layer including an alignment pattern on the metal film layer; forming an insulating layer covering the plating film layer; forming a through-hole penetrating the insulating layer along its thickness direction by irradiating the insulating layer with a laser by referring to position information obtained from the alignment pattern; and forming a via conductor by filling the through-hole with a conductor. The step of forming the plating film layer includes the following step: making the normal reflectivity of light of a predetermined wavelength on the upper surface of the metal film layer different from the normal reflectivity of the upper surface of the plating film layer.

[0006] According to an embodiment of the present invention, the orthoreflectivity of light of a specified wavelength on the upper surface of the metal film layer is different from that on the upper surface of the coated film layer. Therefore, alignment patterns can be identified more accurately, thereby obtaining accurate positional information. A wiring substrate with via conductors formed in more precise locations can be provided. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view showing an example of a wiring substrate manufactured by a manufacturing method according to an embodiment of the present invention.

[0008] Figure 2 This is a cross-sectional view showing another example of a wiring substrate manufactured by a manufacturing method according to one embodiment of the present invention.

[0009] Figure 3A This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0010] Figure 3B This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0011] Figure 3C This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0012] Figure 3D This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0013] Figure 3E This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0014] Figure 3F This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0015] Figure 3G This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0016] Figure 3H This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0017] Figure 3I This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0018] Figure 3J This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0019] Figure 3K This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0020] Figure 3L This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0021] Figure 3M This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0022] Figure 3N This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0023] Figure 3O This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0024] Figure 3PThis is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0025] Figure 3Q This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0026] Figure 3R This is a diagram illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0027] Label Explanation

[0028] 1, 1a: Wiring substrate; 10: First stacked layer; 20: Second stacked layer; 30: Third stacked layer; 11: Insulating layer (first insulating layer); 12: Conductor layer (first conductor layer); 21: Insulating layer (second insulating layer); 22: Conductor layer (second conductor layer); 31: Insulating layer (third insulating layer); 32: Conductor layer (third conductor layer); 13: Via conductor (first via conductor); 23: Via conductor (second via conductor); 33: Via conductor (third via conductor); 121, 221: Metal film layer; 122, 222: Plating film layer; 12p, 32p: Conductor pad; AP: Alignment pattern; C: Central part; P: Peripheral part; FW: Wiring; MA: Product area; SA: Peripheral area; SP1: First support substrate; SP1a: First side; SP1b: Second side; SP2: Second support substrate; GS1: Core material; GS1a: One side; GS1b: The other side. Detailed Implementation

[0029] Hereinafter, the manufacturing method of the wiring substrate of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a cross-sectional view of wiring substrate 1, showing an example of a wiring substrate manufactured by a manufacturing method according to one embodiment. Furthermore, wiring substrate 1 is merely one example of a manufactured wiring substrate. The layer stack structure of the manufactured wiring substrate and the number of conductor layers and insulating layers are not limited to [specific details needed]. Figure 1 The diagram shows the stacked structure of the wiring substrate 1 and the respective numbers of conductor layers and insulating layers included in the wiring substrate 1. Furthermore, the accompanying drawings do not intend to show exact ratios of the structural elements, but rather depict them in a manner that facilitates understanding of the features of the invention.

[0030] The wiring substrate 1 has a laminated structure comprising a multilayer section consisting of alternating conductor layers and insulating layers. The multilayer section constituting the wiring substrate 1 has two surfaces perpendicular to its thickness direction (a first surface 1F and a second surface 1B opposite to the first surface 1F). The surface of the first multilayer section 10 constitutes the first surface 1F. The surface of the third multilayer section 30 constitutes the second surface 1B.

[0031] Figure 1The wiring substrate 1 in the example shown further includes a second stacked portion 20 and a third stacked portion 30 on the second surface 10B side of the first stacked portion 10, which are composed of alternating layers of insulating and conductive layers.

[0032] In addition, Figure 1 In the description of the wiring substrate 1 of this embodiment, the first surface 10F of the first laminate portion 10, i.e., the side of the first surface 1F of the wiring substrate 1, is referred to as "upper" or "upper side," and the second surface 1B of the wiring substrate 1 is referred to as "lower" or "lower side." In addition, among the various structural elements, the surface of the wiring substrate 1 facing the first surface 1F is also referred to as the "upper surface," and the surface of the wiring substrate 1 facing the second surface 1B is also referred to as the "lower surface."

[0033] In the illustrated example, the first stacked section 10, the second stacked section 20, and the third stacked section 30 each include multiple insulating layers and multiple conductor layers. As shown, the first stacked section 10 has alternating layers of insulating layers (first insulating layers) 11 and conductor layers (first conductor layers) 12. The conductor layers, separated by one insulating layer 11, are connected to each other using via conductors (first via conductors) 13. The second stacked section 20 has alternating layers of insulating layers (second insulating layers) 21 and conductor layers (second conductor layers) 22. The conductor layers, separated by one insulating layer 21, are connected to each other using via conductors (second via conductors) 23. The third stacked section 30 has alternating layers of insulating layers (third insulating layers) 31 and conductor layers (third conductor layers) 32. The conductor layers, separated by one insulating layer 31, are connected to each other using via conductors (third via conductors) 33.

[0034] Each conductor layer 12, 22, and 32 is patterned with a predetermined conductor pattern. In the illustrated example, the first conductor layer 12 constituting the first surface 10F is formed as a pattern having a plurality of conductor pads 12p. As shown, a solder resist layer SR1 formed, for example, using a photosensitive polyimide resin or epoxy resin, is formed on the first surface 10F. An opening SR1a is formed in the solder resist layer SR1, and conductor protrusions BP are formed on the conductor pads 12p exposed within the opening SR1a. Figure 1 As shown in the example, the first surface 1F of the wiring substrate 1 is a component mounting surface for mounting electronic components E1 and E2, which are active components such as semiconductor integrated circuit devices and transistors. The conductor pad 12p can be connected to the electronic components E1 and E2 via the conductor protrusion BP. Specifically, the electronic components E1 and E2 can be, for example, integrated circuits such as logic chips assembled with logic circuits, or processing devices such as MPUs (Microprocessor Units) or memory elements such as HBMs (High Bandwidth Memory).

[0035] In the illustrated example, the wiring substrate 1 also has a solder resist layer SR2 formed on a second surface 1B formed by the surfaces of the insulating layer 31 and the conductor layer 32. The solder resist layer SR2 is formed, for example, using a photosensitive polyimide resin or epoxy resin. An opening SR2a is formed in the solder resist layer SR2, through which the conductor pads 32p of the conductor layer 32 of the third stacked portion 30 are exposed. When the wiring substrate 1 itself is mounted on an external element such as an external wiring substrate (e.g., the motherboard of any electrical device), the second surface 1B of the wiring substrate 1, opposite to the component mounting surface of the wiring substrate 1, can be a connection surface connected to the external element. The conductor pads 32p can be connected to any substrate, electrical component, or mechanical component.

[0036] The first insulating layer 11 of the first laminated portion 10 can be formed using an insulating resin such as epoxy resin or phenolic resin. The insulating layer 11 may contain any one of fluoropolymer, liquid crystal polymer (LCP), fluorinated vinyl resin (PTFE), polyester resin (PE), or modified polyimide resin (MPI).

[0037] As conductors constituting the conductor layer 12 and the via conductor 13 of the first stacked portion 10, examples include copper and nickel, with copper being preferred. Figure 1 In this diagram, for ease of observation, conductor layer 12 and via conductor 13 are shown as a single layer, but conductor layer 12 and via conductor 13 can have a multilayer structure. For example, conductor layer 12 and via conductor 13 can have a two-layer structure comprising a metal film layer (e.g., a sputtered film layer or a chemically plated film layer) and a plated film layer (e.g., an electroplated film layer).

[0038] The second insulating layer 21 constituting the second laminate 20 and the third insulating layer 31 constituting the third laminate 30 can be formed using the same insulating resin as the first insulating layer 11. Each insulating layer 11, 21, and 31 may contain the same insulating resin in each laminate, or may contain different insulating resins. Each insulating layer 21 and 31 may also contain a core material (reinforcing material) made of glass fiber or aramid fiber.

[0039] The second conductor layer 22 of the second stacked layer 20 and the third conductor layer 32 of the third stacked layer 30, as well as each via conductor 23, 33, can be formed using any metal such as copper or nickel, similar to the first conductor layer 12 and the first via conductor 13. Each conductor layer 22, 32 is patterned to have a predetermined conductor pattern. The conductor layers 22, 32 and the via conductors 23, 33 can be composed of a multilayer structure, for example, a two-layer structure including a metal film layer and a plating film layer.

[0040] exist Figure 2As another example of a wiring substrate manufactured by the manufacturing method of the embodiment, wiring substrate 1a is shown. Wiring substrate 1a includes a first laminate portion 10 having a first surface 10F and a second surface 10B, a solder resist layer SR1 covering the first surface 10F, and a solder resist layer SR2 covering the second surface 10B. Conductor pads 12p are exposed in the opening SR1a formed in the solder resist layer SR1, and conductor protrusions BP are formed on the conductor pads 12p. The lowermost conductor layer 12 is exposed in the opening SR2a formed in the solder resist layer SR2. Wiring substrates manufactured by the manufacturing method of the embodiment may have the wiring substrate 1a shown in the figure if they do not have laminate portions other than the first laminate portion 10. In addition, the wiring substrates 1 and 1a described above have, for example, a rectangular shape with each side having a dimension of 80 mm or more and less than 240 mm when viewed from above. Here, "viewed from above" means viewing an object with a line of sight parallel to the thickness direction of the wiring substrate 1.

[0041] Next, refer to Figures 3A to 3R To manufacture Figure 1 Taking the example of wiring substrate 1 shown, the manufacturing method of the wiring substrate according to the embodiment will be described. Furthermore, the structural elements formed in the manufacturing method described below can be used in [various applications] unless otherwise specified. Figure 1 The wiring substrate 1 is formed from the material exemplified as the material of the corresponding structural element in the description of the wiring substrate 1. Furthermore, in the following description of the manufacturing method of the wiring substrate 1, the side closest to the core material GS1 of the first support substrate SP1 on which the first stacked portion 10 is formed is referred to as "lower" or "lower side," and the side furthest from the core material GS1 is referred to as "upper" or "upper side." Therefore, the surface of each element constituting the wiring substrate 1 facing the first support substrate SP1 is referred to as the "lower surface," and the surface facing the side opposite to the first support substrate SP1 is also referred to as the "upper surface."

[0042] First, such as Figure 3AAs shown, a first support substrate SP1 is prepared. The first support substrate SP1 has a first surface SP1a and a second surface SP1b opposite to the first surface SP1a as two surfaces perpendicular to its thickness direction. The first support substrate SP1 includes a core material GS1, which has one surface GS1a and another surface GS1b opposite to the first surface GS1a. The core material GS1 can be, for example, a glass substrate, a ceramic substrate, or a silicon substrate. In addition to the core material GS1, the first support substrate SP1 also includes a first metal film layer ML1 stacked on the surface of one surface GS1a of the core material GS1 and a second metal film layer ML2 stacked on the first metal film layer ML1 through an adhesive layer AL1. The first metal film layer ML1 and the second metal film layer ML2 are metal film layers formed, for example, by chemical plating or sputtering. The first metal film layer ML1 and the second metal film layer ML2 are depicted as single layers in the figure, but they may also contain multiple layers. For example, the first metal film layer ML1 and the second metal film layer ML2 sometimes have a two-layer structure composed of a titanium layer and a copper layer, respectively (not shown). In this case, a copper layer is disposed outside the titanium layer in both the first metal film layer ML1 and the second metal film layer ML2. Therefore, in this case, the first surface SP1a of the first support substrate SP1 is formed by the surface of the copper layer constituting the second metal film layer ML2.

[0043] Additionally, the following, in Figure 3A as well as Figures 3B to 3R The example described is one where a first support substrate SP1 has a product area MA on its first surface SP1a, and a wiring substrate is formed in the product area MA. However, sometimes the first support substrate has one or more product areas MA in which a wiring substrate is formed. When the first surface SP1a of the first support substrate SP1 has multiple product areas MA, the wiring substrate is manufactured by dividing a laminate continuously formed over multiple product areas MA into sections for each product area MA. For example, the product areas MA in the first surface SP1a of the first support substrate SP1 have a rectangular shape with each side having a dimension of 80 mm or more and 240 mm or less when viewed from above. Therefore, the laminate (stacked portion) forming the wiring substrate by one or more product areas MA on the first surface SP1a of the first support substrate SP1 can have a rectangular shape with each side having a dimension of 80 mm or more and 240 mm or less when viewed from above. Furthermore, as shown in the figure, the first surface SP1a of the support substrate SP1 has a peripheral area SA located around the product areas MA in addition to the product areas MA. In the peripheral area SA, as shown in the figure... Figures 3B to 3H As will be described later, an alignment pattern is formed as a reference for the positional information used in the manufacturing process of the wiring substrate 1.

[0044] Next, refer to Figures 3B to 3JA first laminate portion 10 is formed on the first support substrate SP1 (see reference). Figure 1 The first laminate portion 10 is formed only on the upper side of the first surface SP1a of the first support substrate SP1.

[0045] like Figure 3B As shown, a resist layer RL with an opening RLa is formed on the surface of the metal film layer ML2 constituting the first surface SP1a of the first support substrate SP1. First, for example, a dry film resist containing a photosensitive epoxy resin is bonded to the upper surface of the metal film layer ML2 to form the resist layer RL. Next, the resist layer RL is exposed. In the process of exposing the resist layer RL, direct imaging exposure with relatively high resolution can be performed. In direct imaging exposure, no photomask is used, and the resist layer RL is directly irradiated with light for exposure. According to the conductor pattern of the first conductor layer 12 to be formed on the metal film layer ML2 (see reference...), ... Figure 3D The corresponding drawing pattern is scanned by the light used for exposure. Next, the resist layer RL is developed using a developer. Through development, a conductor pad 12p is formed within the product area MA, which serves as the conductor pattern of the first conductor layer 12 to be formed on the metal film layer ML1, and an alignment pattern AP (see reference) is formed with the surrounding area SA. Figure 3D The corresponding opening RLa has a resist layer RL.

[0046] Next, as Figure 3C As shown, by electroplating the metal film layer ML2 as a power supply layer, a plating layer 122 constituting the first conductor layer 12 is formed within the opening RLa. A plating layer 122 constituting the formed conductor pad 12p is formed within the opening RLa located in the product region MA, and a plating layer 122 constituting the formed alignment pattern AP is formed within the opening RLa located in the peripheral region SA. The plating layer 122 is formed, for example, with a thickness of 3 μm or more and 6 μm or less (the shortest distance between the upper surface of the metal film layer ML2 and the upper surface of the plating layer 122). The plating layer 122 can be formed from the same material constituting the metal film layer ML2 (e.g., copper).

[0047] Next, the upper surface of the coated film layer 122 is roughened. For example, the upper surface of the coated film layer 122 is roughened by wet etching using a solution such as a manganate solution, or by dry etching using a plasma gas such as oxygen plasma. Specifically, as shown in reference... Figure 3GAs described later, the upper surface of the coated film layer 122 is roughened so that the normal reflectance of light of a specified wavelength, detectable by the device for photographing the alignment pattern AP, on the upper surface of the coated film layer 122 is different from the normal reflectance on the upper surface of the metal film layer ML2. This roughening treatment is performed with the coated film layer 122 filling the opening RLa of the resist layer RL formed on the metal film layer ML2.

[0048] Next, remove the resist layer RL, such as Figure 3D As shown, the upper surface of the metal film ML2 is exposed. Figure 3E It shows Figure 3D The top view shown shows the upper surface of the metal film ML2 and the upper surface of the coated film 122 exposed. Figure 3D Show along Figure 3E The cross-section of the DD line in the diagram. Figure 3D as well as Figure 3E The alignment pattern AP shown has a circular central portion C and an annular peripheral portion P surrounding the central portion C, formed by the coating layer 122 in the peripheral region SA. The upper surface of the metal film layer ML2 is exposed at the gap G between the central portion C and the peripheral portion P. Furthermore, the planar shape of the alignment pattern AP is not limited to the shape described above; for example, it may have a cross-shaped planar shape formed by the coating layer 122.

[0049] Reference and Figure 3E The region e enclosed by a single-dot dash corresponds to Figure 3D An enlarged view of the region E enclosed by a single-dot dashed line. Figure 3F The surface condition of the alignment pattern AP will be described. The upper surface of the coating layer 122 constituting the central portion C and the surrounding portion P was subjected to a reference coating. Figure 3C The roughening treatment described above. Through this roughening treatment, as described above, the normal reflectance of the upper surface of the coated film layer 122 (central portion C and surrounding portion P) for light of a specified wavelength detectable by the device for photographing the alignment pattern AP is different from the normal reflectance of the upper surface of the metal film layer ML2 (gap portion G). For example, the normal reflectance of light of a specified wavelength detectable by the device for photographing the alignment pattern AP on the upper surface of the coated film layer 122 is 30% or more and 50% or less, while the normal reflectance on the upper surface of the metal film layer ML2 is 60% or more. Specifically, the surface roughness of the upper surface of the coated film layer 122, in terms of arithmetic mean roughness, is 0.35 μm or more and 0.6 μm or less, and the surface roughness of the upper surface of the metal film layer ML2, in terms of arithmetic mean roughness, is 0.05 μm or more and less than 0.3 μm. It should be noted that the normal reflectance of the upper surface of the coated film layer 122 before the roughening treatment can be 60% or more.

[0050] Next, as Figure 3G As shown, a first insulating layer 11 is laminated, covering the upper surface and side surfaces of the coated film layer 122 and the metal film layer ML2 exposed from the conductor pattern of the coated film layer 122. For example, insulating resins such as epoxy resin and phenolic resin can be used as the first insulating layer 11. Fluoropolymers, liquid crystal polymers (LCP), fluorinated vinyl resins (PTFE), polyester resins (PE), and modified polyimide resins (MPI) can also be used. The first insulating layer 11 is formed by hot-pressing the resin, which is molded into a film shape.

[0051] After forming the first insulating layer 11, in order to form a through hole 11a in the first insulating layer 11 (refer to...) Figure 3H The alignment pattern AP is used to irradiate the first insulating layer 11 with a laser LL, such as a carbon dioxide laser or a UV laser. The position of the irradiated laser LL in the first insulating layer 11 is determined with reference to the position information obtained from the alignment pattern AP. Specifically, for example, the alignment pattern AP is photographed by a device AC, which is an alignment camera with coaxial illumination. The device AC detects the positive reflection of light of a specified wavelength from the alignment pattern AP that has passed through the first insulating layer 11. The position where the through hole 11a should be formed (the position where the laser LL should be irradiated) is calculated with reference to the position information obtained from the photographed alignment pattern AP.

[0052] As described above, since the upper surface of the coating layer 122 is roughened, the orthographic reflectance of the light detected by the device AC differs between the upper surface of the central portion C and the surrounding portion P and the upper surface of the gap portion G. Therefore, in the captured image of the alignment pattern AP, the brightness of the central portion C and the surrounding portion P has a high contrast with the brightness of the gap portion G. In particular, as described above, when the coating layer 122 has a relatively thin thickness of approximately 3 μm to 6 μm and is formed of the same material as the material constituting the metal film layer ML2, the brightness of the central portion C and the surrounding portion P is unlikely to differ from the brightness of the gap portion G. In such cases, the roughening of the upper surface of the coating layer 122 effectively achieves high brightness contrast. Therefore, when obtaining position information from the captured alignment pattern AP, the boundaries between the gap portion G and the central portion C, and between the gap portion G and the surrounding portion P, are clearly identified, thus enabling high-precision identification of the center position of the alignment pattern AP. It is possible to obtain highly accurate positional information. As a result, the laser LL accurately illuminates the position where the through hole 11a should be formed.

[0053] Although not illustrated, irradiation by lasers such as carbon dioxide lasers is sometimes performed by protecting the upper surface of the first insulating layer 11 with a protective film such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN) film while irradiating with the laser. Furthermore, the first insulating layer 11 can be formed to have a thickness of approximately 7 μm to 15 μm. From the viewpoint of accurately photographing and aligning the pattern AP, it is preferable that the shortest distance from the upper surface of the first conductor layer 12 (the upper surface of the coating layer 122) to the upper surface of the first insulating layer 11 is 10 μm or less.

[0054] like Figure 3H As shown, a through-hole 11a is formed in the first insulating layer 11. The through-hole 11a can be formed with a diameter of 5 μm or more and 15 μm or less on the upper surface of the first insulating layer 11. By irradiating with the laser LL with reference to the high-precision position information described above, the through-hole 11a can be formed relatively accurately at the position where the first via conductor 13 should be formed. The through-hole 11a can be formed such that the depth of the through-hole 11a / the diameter of the through-hole 11a is about 0.5 or more and about 1.5 or less. Here, "depth of the through-hole 11a" refers to the shortest distance between the upper surface of the first conductor layer 12 and the upper surface of the first insulating layer 11, and "diameter of the through-hole 11a" refers to the distance between the two longest points on the outer periphery of the through-hole 11a on the upper surface of the first insulating layer 11 when viewed from above.

[0055] Sometimes, a descaling process is performed after the through-hole 11a is formed. The descaling process is preferably a dry descaling process using plasma gas. The descaling process can also be performed while the surface of the first insulating layer 11 is protected by a protective film such as a PET film.

[0056] Next, as Figure 3I As shown, a first via conductor 13 filling the through-hole 11a and a first conductor layer 12 on the first insulating layer 11 are formed. A metal film layer 121 is formed on the inner wall of the through-hole 11a and on the surface of the first insulating layer 11 by chemical plating or sputtering. Furthermore, if a protective film is provided on the surface of the first insulating layer 11 during the formation of the through-hole 11a and / or during the desmearing process, the protective film can be peeled off before the formation of the metal film layer 121. Next, by electroplating the metal film layer 121 as a power supply layer, a plating film layer 122 is formed inside the opening of the resist layer formed on the metal film layer 121. The interior of the through-hole 11a is completely filled with the electroplated film, forming the first via conductor 13. After removing the resist layer using an alkaline stripping solution, the portion of the metal film layer 121 not covered by the plating film layer 122 is removed by etching. As a result, as... Figure 3IAs shown, a first conductor layer 12 with wiring FW is formed, having a two-layer structure consisting of a metal film layer 121 and a plating film layer 122. The wiring FW can be formed with a minimum wiring width of 2 μm or less and a minimum wiring spacing of 2 μm or less. Furthermore, as shown, the first conductor layer 12, like the first conductor layer 12 formed in contact with the first support substrate SP1, is configured to include an alignment pattern AP in the peripheral region SA.

[0057] Next, as Figure 3J As shown, using and referencing Figure 3I The method for forming the first insulating layer 11, the first conductor layer 12, and the first via conductor 13 described above is the same, forming the desired number of first insulating layers 11 and first conductor layers 12, and the first via conductor 13 penetrating each of the first insulating layers 11. In the formation of the through-hole 11a in the formation of the first via conductor 13, positional information obtained from the alignment pattern AP covered by the insulating layer 11 to which the through-hole 11a is formed is referenced. The step of forming the first laminate portion 10 on the first surface SP1a of the first support substrate SP1 is completed.

[0058] Next, as Figure 3K As shown, a second layer 20 is stacked on the uppermost first insulating layer 11 and first conductor layer 12 in the first layer 10 (see reference). Figure 3N The second insulating layer 21 is located at the bottommost side of the first insulating layer 11 constituting the first laminate portion 10. The thickness of the second insulating layer 21 may differ from the thickness of the first insulating layer 11 constituting the first laminate portion 10. For example, the second insulating layer 21 may be formed to have a thickness of about 20 μm to 30 μm. The second insulating layer 21 may be made of the same insulating resin as the insulating resin constituting the first insulating layer 11. A film 21F formed of resin such as PET is laminated on the second insulating layer 21 and is peelably bonded to the second insulating layer 21.

[0059] Next, as Figure 3L As shown, the first laminate portion 10, having a second insulating layer 21 and a film 21F, is bonded to both sides of the two main surfaces (surfaces perpendicular to the thickness direction) of the second support substrate SP2 via a first support substrate SP1. The main surfaces of the second support substrate SP2 and the second surface SP1b of the first support substrate SP1 are bonded via an adhesive layer ALC made of any adhesive. The second support substrate SP2 may be the same as the core material GS1 of the first support substrate SP1, for example, it may be a glass substrate, a ceramic substrate, or a silicon substrate.

[0060] Next, as Figure 3MAs shown, a second via conductor 23 penetrating the second insulating layer 21 and a second conductor layer 22 in contact with the upper surface of the second insulating layer 21 are formed. A film 21F is peeled off from the second insulating layer 21. Next, for example, a via 21a is formed in the second insulating layer 21 by laser irradiation, and the second via conductor 23 and the second conductor layer 22 on the second insulating layer 21 are formed using a so-called semi-additive method, having a two-layer structure of a metal film layer 221 and a plated film layer 222. The second conductor layer 22 can, for example, be formed to have a thickness of approximately 10 μm to 15 μm.

[0061] In addition, Figure 3M And the following references Figures 3N to 3R The diagram shows a laminate formed on one surface of the second support substrate SP2, omitting illustrations of laminates that could be formed on the opposite surface. However, laminates of the illustrated shape and number are also formed on the opposite surface of the second support substrate SP2. Therefore, in reference... Figures 3M to 3P The process described is designed to prevent warping.

[0062] Next, as Figure 3N As shown, by repeatedly performing the processes of forming the second insulating layer 21, the second conductor layer 22, and the second via conductor 23 described above, the desired number of layers of the second insulating layer 21 and the second conductor layer 22, as well as the second via conductor 23 penetrating each of the second insulating layers 21, are formed. The step of forming the second stacked portion 20 on the first stacked portion 10 is completed. Furthermore, in Figure 3N And the following Figures 3O to 3R The metal films 121 and 221 and the coated films 122 and 222 are not depicted, nor are the conductor layers 12 and 22. Figure 1 Similarly, it is described as a single layer.

[0063] Next, as Figure 3O As shown, on the uppermost second insulating layer 21 and second conductor layer 22 of the second laminated portion 20, the third insulating layer 31, the third conductor layer 32, and the third via conductor 33 penetrating the third insulating layer 31 are formed in the third laminated portion 30 using the same method as that used to form the second insulating layer 21, the second conductor layer 22, and the second via conductor 23. As the insulating resin for forming the third insulating layer 31, a prepreg containing an insulating resin such as epoxy resin or BT resin impregnated with a reinforcing material (core material) made of glass fiber can be used. As shown, a third laminated portion 30 comprising two layers of third insulating layer 31 and two layers of third conductor layer 32 is formed.

[0064] Next, as Figure 3PAs shown, the first to third laminated portions 10, 20, and 30 within the product region MA are separated from the laminated body of the surrounding region SA. For example, a groove V is formed along the periphery of the product region MA, reaching the core material GS1 of the first support substrate SP1. Furthermore, when the first support substrate SP1 contains multiple product regions MA, grooves V are also formed at the boundaries of adjacent product regions MA, dividing the first to third laminated portions 10, 20, and 30 into individual product regions MA.

[0065] Next, as Figure 3Q As shown, the first support substrate SP1 and the second support substrate SP2 are removed from the laminate within the product area MA. When removing the first support substrate SP1, the second metal film layer ML2 of the first support substrate SP1 is peeled off from the adhesive layer AL1. The second metal film layer ML2 adheres strongly to the adhesive layer AL1 in the peripheral area SA, but weakly in the product area MA. Therefore, by lifting the laminate within the product area MA, which is separated from the peripheral area SA, upwards, as shown, the second metal film layer ML2 is peeled off from the adhesive layer AL1. The lower surface of the second metal film layer ML2 under the conductor pad 12p is exposed. Furthermore, in Figure 3Q The illustration is omitted, but the disassembly of the first support substrate SP1 is also performed on the side of the second support substrate SP2 opposite to the side shown in the illustration.

[0066] Next, the second metal film layer ML2 is removed by etching, exposing the lower surface of the conductor pad 12p and the lower surface of the first insulating layer 11. Then, as... Figure 3R As shown, a solder resist layer SR1 is formed by forming photosensitive epoxy resin and polyimide resin layers on the surfaces of the first insulating layer 11 and the first conductor layer 12. An opening SR1a is formed in the solder resist layer SR1 to expose the conductor pad 12p using photolithography. A solder resist layer SR2 is formed by forming photosensitive epoxy resin and polyimide resin layers on the surfaces of the insulating layer 31 and the conductor layer 32. An opening SR2a is formed in the solder resist layer SR2 to expose the conductor pad 32p using photolithography. A conductor bump BP is formed on the conductor pad 12p exposed within the opening SR1a of the solder resist layer SR1. A plating layer including a nickel layer and a tin layer may also be formed on the surface of the conductor bump BP. Figure 3R As shown, wiring substrate 1 is completed.

Claims

1. A method for manufacturing a wiring substrate, comprising the following steps: Prepare a support substrate with a metal film layer formed on its surface; A coating layer containing an alignment pattern is formed on the metal film layer; An insulating layer is formed covering the coated film layer; A through-hole is formed by irradiating the insulating layer with a laser, referring to the position information obtained from the alignment pattern; and A via conductor is formed by filling the through-hole with a conductor. in, The step of forming the coating layer includes the following steps: making the positive reflectance of light of a specified wavelength on the upper surface of the metal film layer different from the positive reflectance of the upper surface of the coating layer.

2. The method for manufacturing a wiring substrate according to claim 1, wherein, The step of forming the coating layer includes the following step: roughening the upper surface of the coating layer.

3. The method for manufacturing a wiring substrate according to claim 2, wherein, The step of roughening the upper surface of the coating layer includes the following steps: roughening the upper surface of the coating layer while the coating layer is filled in the opening of the resist layer formed on the metal film layer.

4. The method for manufacturing a wiring substrate according to claim 2, wherein, The upper surface of the coating layer is roughened such that the positive reflectance of light of the specified wavelength is more than 30% and less than 50%.

5. The method for manufacturing a wiring substrate according to claim 4, wherein, The upper surface of the coating layer is roughened to an arithmetic mean roughness of 0.35 μm or more and 0.6 μm or less.

6. The method for manufacturing a wiring substrate according to claim 4, wherein, The upper surface of the metal film layer is configured such that the positive reflectivity of light of the specified wavelength is 60% or more.

7. The method for manufacturing a wiring substrate according to claim 1, wherein, The position information is obtained by detecting light of the specified wavelength using a device that captures the alignment pattern.

8. The method for manufacturing a wiring substrate according to claim 1, wherein, The metal film and the coated film are formed of the same material.

9. The method for manufacturing a wiring substrate according to claim 1, wherein, The coating layer is formed with a thickness of 3 μm or more and 6 μm or less.

10. The method for manufacturing a wiring substrate according to claim 1, wherein, The through-hole is formed on the upper surface of the insulating layer with a diameter of 5 μm or more and 15 μm or less.

11. The method for manufacturing a wiring substrate according to claim 3, wherein, The step of forming the opening in the resist layer includes the following steps: exposing the resist layer by direct imaging exposure.

12. The method for manufacturing a wiring substrate according to claim 11, wherein, The surface of the support substrate includes one or more rectangular product areas with sides measuring 80 mm or more and 240 mm or less when viewed from above. The coating layer and the insulating layer are formed over one or more product areas.

13. The method for manufacturing a wiring substrate according to claim 1, wherein, The support substrate includes a glass substrate, a ceramic substrate, or a silicon substrate.

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