Electronic equipment and cabinet

Abstract

The invention discloses electronic equipment and a cabinet, and relates to the technical field of electronic equipment, and the electronic equipment comprises a housing which comprises a containing cavity; the cold plate is arranged in the accommodating cavity; the plurality of electronic nodes are respectively arranged on two opposite sides of the cold plate; each electronic node comprises a first circuit board parallel to the cold plate, a processor connected with the first circuit board and at least one memory module, and the memory module is located on the side, close to the cold plate, of the first circuit board; wherein the memory module comprises a second circuit board parallel to the first circuit board, and memory particles and a connector which are connected with the second circuit board, and the memory particles are parallel to the second circuit board and are in contact with the cold plate; according to the invention, the problem that the overall layout of the electronic nodes in the case of the electronic equipment in the prior art cannot enable the liquid cooling technology to fully exert the potential is solved, the direct and effective liquid cooling heat dissipation of each memory module is realized, and the heat dissipation effect of each electronic node is improved.

Description

[0001] This application claims priority to the patent application filed with the China National Intellectual Property Administration on December 31, 2025, with application number 202512050845.2 and entitled "Electronic Equipment and Cabinet". Technical Field

[0002] This application relates to the field of electronic equipment technology, and more particularly to an electronic device and a cabinet. Background Technology

[0003] With the rapid development of the data center and cloud computing industries, the demand for computing power in electronic devices continues to rise. This has prompted electronic device manufacturers to adopt higher-performance processors, which in turn generate more heat. Currently, the widely used air-cooling technology is struggling to cope with the thermal design power (TDP) of processors, which can reach 500W or even 600W. Especially when pursuing high-density deployments, traditional air-cooling methods have significant limitations in terms of heat dissipation efficiency and space utilization.

[0004] While liquid cooling technology can effectively solve the heat dissipation problem of high-power devices, in practical applications, the current overall layout of electronic nodes cannot allow liquid cooling technology to fully realize its potential, which directly affects the computing performance of electronic devices. Summary of the Invention

[0005] This application provides an electronic device and a cabinet to at least solve the problem that the overall layout of electronic nodes in the electronic device chassis in the related art cannot enable liquid cooling technology to fully realize its potential.

[0006] This application provides an electronic device, including: a housing including a receiving cavity; a cold plate disposed within the receiving cavity; a plurality of electronic nodes respectively disposed on opposite sides of the cold plate; each electronic node includes a first circuit board parallel to the cold plate, a processor connected to the first circuit board, and at least one memory module, the memory module being located on the side of the first circuit board closer to the cold plate; wherein, the memory module includes a second circuit board parallel to the first circuit board, a memory chip connected to the second circuit board, and a connector, the memory chip being parallel to the second circuit board and in contact with the cold plate.

[0007] Furthermore, at least two adjacent memory modules form a memory combination, and the connectors of each memory module in the memory combination have different heights; along the first direction, the second circuit board in the memory combination is stacked in a direction away from the first circuit board.

[0008] Furthermore, at least one second circuit board in the memory assembly is positioned close to the cold plate.

[0009] Furthermore, the memory is combined in multiple ways; wherein, along the second direction, the multiple memory combinations are located on the same side or opposite sides of the processor.

[0010] Furthermore, the cold plate includes a cold plate body and a plurality of heat-conducting protrusions spaced apart on the cold plate body; wherein the cold plate body and the heat-conducting protrusions are respectively used to contact different parts of the corresponding electronic nodes.

[0011] Furthermore, the electronic node includes a heat-conducting plate at least partially disposed between two adjacent second circuit boards in the memory assembly, with opposite sides of the heat-conducting plate respectively contacting at least a portion of the memory chips on the corresponding two second circuit boards, and the heat-conducting plate being used to contact a cold plate.

[0012] Furthermore, the electronic device includes a heat dissipation pipe disposed on the side of the heat-conducting plate near the cold plate, with the opposite sides of the heat dissipation pipe contacting the cold plate and the heat-conducting plate, respectively.

[0013] Furthermore, the electronic node also includes a thermal pad, which is disposed between the heat-conducting plate and the second circuit board, with the opposite sides of the thermal pad contacting the heat-conducting plate and the second circuit board, respectively.

[0014] Furthermore, multiple electronic nodes are grouped into multiple node combinations in pairs. Each node combination includes a first electronic node and a second electronic node arranged from front to back along the first direction of the receiving cavity. The first electronic node and the second electronic node have a centrally symmetrical structure about a predetermined center between them.

[0015] Furthermore, the electronic device includes multiple unit combinations spaced apart within the receiving cavity and located at the front end of multiple electronic nodes, with each unit combination corresponding to a different node combination; each unit combination includes an interface unit, a storage unit, and a management unit, which are respectively connected to the corresponding node combination.

[0016] Further, both the first electronic node and the second electronic node include: a right-angle connector, which is disposed on a corresponding first circuit board for plugging into and connecting with a corresponding interface unit; and / or, a processor connector, which is disposed on a corresponding first circuit board and connected to a processor at least through the first circuit board; and / or, a network interface card (NIC) connector, which is disposed on a corresponding first circuit board and connected to the right-angle connector through the first circuit board; in the first electronic node, the NIC connector is connected to the processor connector via a NIC connection cable; and / or, a storage connector, which is disposed on a corresponding first circuit board and connected to a processor at least through the first circuit board; in the first electronic node, the storage connector is connected to a corresponding storage unit via a storage connection cable; and / or, a management connector, which is disposed on a corresponding first circuit board and connected to a processor at least through the first circuit board; in the first electronic node, the management connector is connected to a corresponding management unit via a management connection cable.

[0017] Furthermore, the network card connector of the first electronic node is connected to the processor connector of the second electronic node via a first node connection cable; the storage connector of the second electronic node is connected to the corresponding storage unit via a storage connection cable; and the management connector of the second electronic node is connected to the corresponding management unit via a management connection cable.

[0018] Furthermore, the processor connector of the first electronic node and the processor connector of the second electronic node are connected via a second node connection cable.

[0019] Furthermore, multiple units are arranged in a rectangular array within the cavity and located at the front end of multiple electronic nodes.

[0020] Furthermore, the management unit includes a control motherboard and a management controller and a switching chip mounted on and connected to the control motherboard. The management controller can switch with one of the first electronic node and the second electronic node via the switching chip to exchange low-speed signals that do not require simultaneous access from both nodes.

[0021] Furthermore, both the first electronic node and the second electronic node include a low-speed signal extension chip disposed on the first circuit board; wherein, the management controller exchanges low-speed signals that do not require timely response with the low-speed signal extension chip of the first electronic node and the low-speed signal extension chip of the second electronic node.

[0022] Furthermore, the management controller can directly exchange low-speed signals that require timely response with the first circuit board of the first electronic node and the first circuit board of the second electronic node; the management controller can also directly exchange high-speed signals with the first electronic node and the second electronic node simultaneously.

[0023] Furthermore, when two electronic nodes located on opposite sides of the cold plate need to be connected via connecting cables between the two nodes, the cold plate is provided with clearance through holes for the connecting cables to pass through; and / or, the multiple electronic nodes include at least one of computing nodes, switching nodes, and storage nodes.

[0024] Furthermore, the electronic device includes: a power supply and a power backplane, both disposed within the housing and located at the rear end of multiple electronic nodes, the power supply and the power backplane being connected together; and multiple sets of power cables, the power backplane being connected to the multiple electronic nodes one-to-one through the multiple sets of power cables.

[0025] Furthermore, the height of the shell is 1U, the thickness of the cold plate is greater than or equal to 0.25U and less than or equal to 0.35U, the maximum thickness of each electronic node is less than or equal to 0.35U, and the sum of the thicknesses of one cold plate and two electronic nodes is less than the height of the shell.

[0026] This application also provides a cabinet including the aforementioned electronic equipment.

[0027] This application provides an electronic device comprising: a housing including a receiving cavity; a cold plate disposed within the receiving cavity; and multiple electronic nodes respectively disposed on opposite sides of the cold plate. Each electronic node includes a first circuit board parallel to the cold plate, a processor connected to the first circuit board, and at least one memory module, the memory module being located on the side of the first circuit board closer to the cold plate. The memory module includes a second circuit board parallel to the first circuit board, memory chips connected to the second circuit board, and a connector, the memory chips being parallel to the second circuit board and in contact with the cold plate. Thus, this electronic device, by distributing multiple electronic nodes on opposite sides of the cold plate, with the second circuit board of the memory module of each electronic node parallel to the cold plate and the memory chips parallel to the second circuit board and in contact with the cold plate, utilizes the cold plate as a central heat dissipation element, achieving direct and effective liquid cooling for each memory module. This effectively utilizes both sides of the cold plate, improving the heat dissipation effect for each electronic node and solving the problem in related technologies where the overall layout of electronic nodes in the electronic device chassis cannot fully realize the potential of liquid cooling technology. Attached Figure Description

[0028] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1A simplified layout diagram of the internal cold plate and multiple electronic nodes of an electronic device provided in an embodiment of this application;

[0030] Figure 2 for Figure 1 A partial cross-sectional view of the internal cold plate and electronic nodes of the electronic device shown;

[0031] Figure 3 for Figure 1 A top view of an electronic device showing multiple memory modules arranged on an electronic node;

[0032] Figure 4 for Figure 3 The front view of the electronic node is shown;

[0033] Figure 5 for Figure 1 A top view of an electronic node of the electronic device shown, when multiple connectors are provided;

[0034] Figure 6 for Figure 1 The diagram shows the internal power supply backplane and the connection of multiple electronic nodes of the electronic device.

[0035] Figure 7 for Figure 1 A top view of multiple electronic nodes inside the electronic device shown;

[0036] Figure 8 for Figure 1 A top view of the internal node and unit combinations of the electronic device shown, where they are connected in a certain way;

[0037] Figure 9 for Figure 1 A top view of the internal node and unit combinations of the electronic device shown, where they are connected in another way.

[0038] Figure 10 for Figure 1 A schematic diagram showing the connection between the node combination and the management unit of the unit combination of the electronic device;

[0039] Figure 11 for Figure 1 The diagram shows the connection between the node combination and the interface unit of the unit combination of the electronic device.

[0040] Figure 12 for Figure 1 The front view of the electronic device shown, with multiple units assembled within the housing;

[0041] Figure 13 for Figure 1The diagram shows the connection between two electronic nodes located on opposite sides of the cold plate in the electronic device.

[0042] The above figures include the following reference numerals:

[0043] 10. Shell; 101. Receiving cavity;

[0044] 20. Cold-rolled steel plate; 201. Cold-rolled steel plate body;

[0045] 30. Electronic node; 300. Node assembly; 301. First electronic node; 302. Second electronic node; 303. Heat-conducting plate; 305. Heat-conducting pad;

[0046] 1. First circuit board;

[0047] 2. Processor;

[0048] 3. Memory module; 31. Second circuit board; 32. Memory chip; 33. Connector; 34. Spacing; 35. Memory assembly; 37. Right-angle connector; 38. Processor connector; 39. Network card connector; 310. Storage connector; 311. Management connector; 312. Low-speed signal expansion chip;

[0049] 40. Unit assembly; 401. Interface unit; 402. Storage unit; 403. Management unit; 4031. Control motherboard; 4032. Management controller; 4033. Switching chip;

[0050] 50. Heat pipe; 60. Power supply backplate; 70. Power supply cable. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0052] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "installed," "connected," and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements. The terms "parallel," "perpendicular," and "equal" include the described situation and situations similar to the described situation, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism can be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality can be, for example, a difference between the two equal items being less than or equal to 5% of either one. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0053] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] like Figures 1 to 13 As shown, this application provides an electronic device, including: a housing 10, including a receiving cavity 101; a cold plate 20, disposed within the receiving cavity 101; a plurality of electronic nodes 30, respectively disposed on opposite sides of the cold plate 20; each electronic node 30 includes a first circuit board 1 parallel to the cold plate 20, a processor 2 connected to the first circuit board 1, and at least one memory module 3, the memory module 3 being located on the side of the first circuit board 1 closer to the cold plate 20; wherein, the memory module 3 includes a second circuit board 31 parallel to the first circuit board 1, a memory chip 32 connected to the second circuit board 31, and a connector 33, the memory chip 32 being parallel to the second circuit board 31 and in contact with the cold plate 20.

[0055] In this way, the electronic device of this application sets multiple electronic nodes 30 on opposite sides of the cold plate 20, so that the second circuit board 31 of the memory module 3 of each electronic node 30 is arranged parallel to the cold plate 20, and the memory chip 32 is parallel to the second circuit board 31 and in contact with the cold plate 20. By using the cold plate 20 as a central heat dissipation element, direct and effective liquid cooling heat dissipation of each memory module 3 is achieved, so that both opposite sides of the cold plate 20 are effectively utilized, the heat dissipation effect of each electronic node 30 is improved, and the problem that the overall layout of electronic nodes in the electronic device chassis in related technologies cannot fully realize the potential of liquid cooling technology is solved.

[0056] like Figures 2 to 4 As shown, at least two adjacent memory modules 3 form a memory assembly 35, and the connectors 33 of each memory module 3 in the memory assembly 35 have different heights; along the first direction, the second circuit board 31 in the memory assembly 35 is stacked in a direction away from the first circuit board 1.

[0057] In this configuration, at least one second circuit board 31 of the memory assembly 35 is positioned close to the cold plate 20.

[0058] In this application, the aforementioned memory combination 35 effectively utilizes space resources. Specifically, in two adjacent memory modules 3 of a memory combination 35, a second circuit board 31 is located within the space 34 between the other second circuit board 31 and the first circuit board 1. This enables efficient stacking of multiple memory modules 3 on the first circuit board 1, significantly improving the memory density of an electronic node 30. It not only optimizes the layout on the first circuit board 1 but also allows for minimizing the thickness of the electronic node 30 while ensuring performance. It also ensures good airflow and heat dissipation performance, thereby supporting high-density node configuration of electronic devices such as servers in limited spaces. This provides key hardware support for ultra-high-density layout of electronic devices such as servers, not only improving the computing density of electronic devices such as servers but also enhancing the overall stability and performance of electronic devices such as servers through reasonable planning of memory module arrangement.

[0059] In other embodiments not shown in the figure, the stacking method of memory modules 3 can be further adjusted to adapt to the needs of different electronic devices such as server architectures, achieving a more flexible layout and better heat dissipation.

[0060] like Figure 2As shown, this application uses connectors 33 with two different heights, 2.85mm and 7.5mm, to achieve the above-mentioned stacking arrangement. That is, in two adjacent memory modules 3 of the memory combination 35, one memory module 3 uses a connector 33 with a height of 7.5mm, and the other memory module 3 uses a connector 33 with a height of 2.85mm. The precise alignment of the two memory modules 3 formed by these two types of connectors 33 on the first circuit board 1 ensures that the electronic device can maintain good signal transmission and heat dissipation capabilities even under high-density node configuration, thereby improving the operating efficiency and reliability of the electronic device.

[0061] like Figure 2 As shown, the cold plate 20 includes a cold plate body 201 and a plurality of heat-conducting protrusions spaced apart on the cold plate body 201; wherein the cold plate body 201 and the heat-conducting protrusions are respectively used to contact different parts of the corresponding electronic node 30 to dissipate heat and cool the different parts of the corresponding electronic node 30.

[0062] like Figure 2 As shown, the electronic node 30 includes a heat-conducting plate 303 at least partially disposed between two adjacent second circuit boards 31 in the memory assembly 35. The opposite sides of the heat-conducting plate 303 are in contact with at least a portion of the memory chips 32 on the corresponding two second circuit boards 31, and the heat-conducting plate 303 is used to contact the cold plate 20 to conduct the heat of at least a portion of the memory chips 32 on the corresponding two second circuit boards 31 to the cold plate 20.

[0063] like Figure 2 As shown, the electronic device includes a heat dissipation pipe 50 disposed on the side of the heat-conducting plate 303 near the cold plate 20. The opposite sides of the heat dissipation pipe 50 are in contact with the cold plate 20 and the heat-conducting plate 303, respectively, to transfer heat from the heat-conducting plate 303 to the cold plate 20. The heat dissipation pipe 50 is filled with a two-phase refrigerant, and the two-phase refrigerant does not flow with the refrigerant in the cold plate 20.

[0064] like Figure 2As shown, the electronic node 30 also includes a thermally conductive pad 305, which is disposed between the heat-conducting plate 303 and the second circuit board 31. The opposite sides of the thermally conductive pad 305 contact the heat-conducting plate 303 and the second circuit board 31 respectively, to transfer heat from the second circuit board 31 to the heat-conducting plate 303, and then from the heat-conducting plate 303 to the cold plate 20. In this application, the cold plate 20 includes a cold plate body 201 and multiple thermally conductive protruding channels. A portion of the memory chips 32 of each electronic node 30 directly contacts the cold plate body 201 or the thermally conductive protruding channels, while another portion of the memory chips 32 of each electronic node 30 contacts the heat-conducting plate 303. The second circuit board 31 of each electronic node 30 contacts the heat-conducting plate 303 through the thermally conductive pad 305. This allows the cold plate 20 to make close contact with different heat-generating parts of each electronic node 30, achieving efficient heat transfer. Furthermore, the heat-conducting protrusions on the cold plate body 201 can also be used to directly contact high-power devices such as the processor 2 in the electronic nodes 30, thereby enhancing the structural strength of the cold plate 20 while improving heat dissipation efficiency, ensuring uniform heat distribution and effective heat dissipation. This further increases the contact area between the cold plate 20 and each electronic node 30, making heat dissipation between them faster. A single cold plate 20 can meet the heat dissipation needs of multiple electronic nodes 30, not only improving the overall flexibility of heat dissipation in electronic equipment but also significantly enhancing its thermal management capabilities, effectively controlling the temperature of multiple electronic nodes 30, and ensuring stable operation of the electronic equipment.

[0065] In other embodiments not shown, the shape and size of the heat-conducting protrusion channels can be adjusted according to different electronic components to further optimize heat dissipation performance while maintaining the overall structural strength of the cold plate 20, achieving efficient heat dissipation within a limited space. The memory combination 35 of this application is multiple; wherein, along the second direction, the multiple memory combinations 35 are disposed on the same side or opposite sides of the processor 2.

[0066] Specifically, the width direction of each second circuit board 31 is parallel to the first direction of the processor 2, and the length direction of each second circuit board 31 is parallel to the second direction of the processor 2.

[0067] The first direction of the processor 2 is the width direction of the processor 2, which is the length direction of the first circuit board 1, the length direction of the housing 10, and the length direction of the receiving cavity 101.

[0068] like Figure 3 and Figure 4As shown, in this application, multiple memory modules 35 are respectively arranged on opposite sides of the processor 2 in a first direction. This fully considers the flexibility and heat dissipation requirements of memory configuration in high-density electronic devices such as servers. By arranging multiple memory modules 35 on opposite sides of the processor 2, not only is the area of ​​the first circuit board 1 effectively utilized, but the heat generated by the memory is also concentrated on the cold plate 20. This facilitates efficient heat dissipation through the opposite sides of the integrated cold plate 20, allowing for an increase in the memory capacity of the electronic device while ensuring its computing performance, thus overcoming the contradiction between memory density and space constraints in high-density electronic devices.

[0069] like Figures 2 to 5 As shown, each electronic node 30 includes multiple memory module rows arranged sequentially along a first direction parallel to the processor 2, and each memory module row includes multiple memory combinations 35 arranged sequentially along a second direction parallel to the processor 2.

[0070] The second direction of the processor 2 is the length direction of the processor 2, which is the width direction of the first circuit board 1, the width direction of the housing 10, and the width direction of the receiving cavity 101.

[0071] In this application, this allows for maximized memory configuration within a limited space while maintaining effective communication with the processor 2, improving the data processing capabilities and efficiency of electronic devices such as servers. Thus, by arranging the memory modules in parallel, this application not only optimizes the arrangement of components on the first circuit board 1, enabling a more compact layout of the memory modules 3, but also ensures consistent memory access speed and data transmission, maintaining high performance even in high-density electronic node 30 arrangements. Furthermore, this layout allows for easy expansion of memory capacity by replacing or adding memory modules 3 without major adjustments to the overall structure of the electronic node 30, facilitating maintenance and upgrades of the electronic device.

[0072] like Figures 2 to 5As shown, the processor 2 is located on the side of the first circuit board 1 near the cold plate 20. Each memory module 3 includes multiple memory chips 32, which are respectively disposed on opposite sides of the second circuit board 31. In this application, the processor 2 is located on the side of the first circuit board near the cold plate 20, which makes full use of the heat dissipation performance of the cold plate 20 and ensures that the processor 2 can effectively perform liquid cooling. By placing the processor 2 close to the cold plate, the heat of the processor 2 can be directly and quickly transferred to the cold plate 20, and then efficiently dissipated through the dual-sided heat dissipation capability of the cold plate 20. This not only solves the heat dissipation bottleneck problem in high-density node design, but also achieves the goal of maximizing heat dissipation efficiency in a limited space, thereby supporting a more compact and higher-density server node design, while ensuring the high performance and stability of the server.

[0073] Specifically, the second circuit board 31 of the memory module 3 is attached to the first circuit board 1 in a manner parallel to the first circuit board 1 and the cold plate 20. This not only reduces the overall thickness of each electronic node 30, allowing the electronic nodes 30 to be arranged in a more compact space, but also ensures that a high memory capacity can be maintained even with the ultra-thin electronic node 30 by having memory chips 32 laid out on both sides of the second circuit board 31. The use of connector 33 makes it easy to install the memory module 3 in a flat manner and facilitates maintenance without the need for a complicated wiring process. This improves the serviceability and reliability of the electronic device, and achieves high-density integration of multiple electronic nodes 30 while maintaining good heat dissipation performance and sufficient memory configuration. This not only improves the power density and node density of the electronic device, but also ensures the stability of the electronic device and the efficiency of high-performance computing.

[0074] like Figures 6 to 12 As shown, multiple electronic nodes 30 are grouped into multiple node combinations 300 in pairs. Each node combination 300 includes a first electronic node 301 and a second electronic node 302 arranged from front to back along the first direction of the receiving cavity 101. The first electronic node 301 and the second electronic node 302 have a centrally symmetrical structure about a predetermined center between them.

[0075] In this application, multiple electronic nodes 30 are grouped in pairs to form several node combinations 300. Each node combination includes a first electronic node 301 and a second electronic node 302 arranged from front to back along a first direction of the receiving cavity 101. The first electronic node 301 and the second electronic node 302 form a centrally symmetrical structure about a predetermined center between them, that is, the first electronic node 301 rotates 180 degrees around the predetermined center and coincides with the second electronic node 302. This not only optimizes the layout of the electronic nodes 30, but also achieves better heat dissipation balance through the centrally symmetrical structure, ensuring the uniform distribution of heat inside electronic devices such as servers. In practical applications, this symmetrical layout also helps to simplify the design of the cold plate 20, because the structure of the cold plate 20 can be optimized for the centrally symmetrical characteristics of the node combination 300, improving heat dissipation efficiency while reducing manufacturing costs. In addition, the centrally symmetrical arrangement of the first electronic node 301 and the second electronic node 302 is also beneficial to the setting of connection lines, ensuring the stability and reliability of data communication.

[0076] like Figures 6 to 12 As shown, the electronic device includes multiple unit combinations 40 spaced apart within the receiving cavity 101 and located at the front end of multiple electronic nodes 30. The multiple unit combinations 40 are arranged in a one-to-one correspondence with the multiple node combinations 300. Each unit combination 40 includes an interface unit 401, a storage unit 402, and a management unit 403. The interface unit 401, storage unit 402, and management unit 403 are respectively connected to the corresponding node combination 300.

[0077] In this application, multiple unit combinations 40 are spaced apart within the receiving cavity 101 and located at the front end of multiple electronic nodes 30. The multiple unit combinations 40 are located at the front window of the housing 10 and correspond one-to-one with the multiple node combinations 300. Each unit combination 40 integrates an interface unit 401, a storage unit 402, and a management unit 403. These units are connected to the corresponding node combination 300 to form a complete node support module. This breaks the limitations of traditional server architecture. By modularizing and centralizing the functions of network access, data storage, and node management, the unit combination 40 greatly optimizes the space utilization efficiency within the 1U chassis (i.e., housing 10) of the electronic device and achieves an unprecedented high-density node configuration.

[0078] Specifically, the interface unit 401 provides the necessary network interfaces for each electronic node 30, the storage unit 402 equips each electronic node 30 with a storage hard drive, and the management unit 403 is responsible for monitoring and regulating the working status of each electronic node 30. The efficient interconnection between these units and the electronic nodes 30 not only ensures the normal operation of each electronic node 30 but also simplifies the maintenance process of the electronic equipment, improving the overall reliability and performance. Furthermore, the design of the unit combination 40 allows for flexible adjustment of the electronic node 30 configuration, enabling switching between single-socket and dual-socket nodes to meet the different computing resource needs of users in different scenarios, demonstrating strong adaptability and scalability.

[0079] In other embodiments not shown in the figures, unit assembly 40 may further integrate more functional modules to adapt to more complex usage environments while maintaining the compactness and efficiency of the electronic device.

[0080] like Figures 6 to 12 As shown, both the first electronic node 301 and the second electronic node 302 include: a right-angle connector 37, which is disposed on the corresponding first circuit board 1 for plugging and connecting with the corresponding interface unit 401; a processor connector 38, which is disposed on the corresponding first circuit board 1 and connected to at least the processor 2 through the first circuit board 1; a network card connector 39, which is disposed on the corresponding first circuit board 1 and connected to the right-angle connector 37 through the first circuit board 1; in the first electronic node 301, the network card connector 39 is connected to the processor connector 38 through a network card connection cable; a storage connector 310, which is disposed on the corresponding first circuit board 1 and connected to at least the processor 2 through the first circuit board 1; in the first electronic node 301, the storage connector 310 is connected to the corresponding storage unit 402 through a storage connection cable; and a management connector 311, which is disposed on the corresponding first circuit board 1 and connected to at least the processor 2 through the first circuit board 1; in the first electronic node 301, the management connector 311 is connected to the corresponding management unit 403 through a management connection cable.

[0081] In this application, the first electronic node 301 and the second electronic node 302 are connected to the interface unit 401 via a right-angle connector 37. The processor connector 38 ensures a stable electrical connection between the processor 2 of the electronic node 30 and other connectors. The network card connector 39 is connected to the processor connector 38 via a network card connection cable, so as to connect to the processor 2 via the processor connector 38, realizing signal transmission between the processor 2 and the interface unit 401, enabling the electronic node 30 to access the network. The storage connector 310 is connected to the storage unit 402 via a storage connection cable, providing storage functionality for the node. The management connector 311 is connected to the management unit 403 via a management connection cable, realizing the monitoring and management of the node. Both the storage connector 310 and the management connector 311 are connected to the processor 2 via the first circuit board 1, realizing signal transmission between the processor 2, the storage unit 402, and the management unit 403. In this way, the reasonable layout and interconnection of the above-mentioned connectors not only simplifies the internal structure of the electronic node 30 and improves the efficiency of signal transmission, but also realizes the flexible connection between the electronic node 30 and external devices, enhances the scalability and maintainability of electronic devices, significantly improves the computing density, power density and overall performance of electronic devices such as servers, at the same time, ensures the signal transmission quality between the various electronic nodes 30, reduces the overall power consumption of electronic devices, optimizes the heat dissipation design, and enables electronic devices to achieve greater processing power and higher energy efficiency ratio in a limited space.

[0082] like Figure 8 As shown, the network card connector 39 of the first electronic node 301 and the processor connector 38 of the second electronic node 302 are connected by a first node connection cable; the storage connector 310 of the second electronic node 302 is connected to the corresponding storage unit 402 by a storage connection cable; and the management connector 311 of the second electronic node 302 is connected to the corresponding management unit 403 by a management connection cable.

[0083] In this application, the first electronic node 301 and the second electronic node 302 are connected to the corresponding unit combination 40 via connecting cables. This allows the processor connector 38 of the first electronic node 301 and the processor connector 38 of the second electronic node 302 to connect to the interface unit 401, ensuring the stability of their respective network signals and bandwidth requirements. The connection between the storage connector 310 of the first electronic node 301 and the storage connector 310 of the second electronic node 302 and the corresponding storage unit 402 ensures the reliability of their respective data storage and access speed. Furthermore, the connection between the management connector 311 of the first electronic node 301 and the management connector 311 of the second electronic node 302 and the corresponding management unit 403 enables the monitoring and management of each electronic node 30. This effectively optimizes signal transmission and resource sharing between the two electronic nodes 30 and the corresponding unit combination 40, improving the overall efficiency and management convenience of the electronic equipment. Simultaneously, the unified management of the two electronic nodes 30 by the management unit 403 reduces maintenance costs and enhances the stability and security of the unit combination 40.

[0084] exist Figure 8 In this system, the first electronic node 301 and the second electronic node 302 are two single-path nodes.

[0085] like Figure 9 As shown, the processor connector 38 of the first electronic node 301 and the processor connector 38 of the second electronic node 302 are connected by a second node connection cable.

[0086] In this application, the processor connector 38 between the first electronic node 301 and the second electronic node 302 is interconnected through the second node connection cable. This allows the two electronic nodes 30 of the node combination 300 to communicate and cooperate, which not only optimizes the layout of the electronic nodes 30, but also enhances the coordination and overall performance of electronic devices, thereby improving the scalability and efficiency of electronic devices such as servers.

[0087] exist Figure 9 In this process, the first electronic node 301 and the second electronic node 302 form a dual-path node.

[0088] In the accompanying drawings of this application, solid lines represent wiring connections inside the first circuit board 1, and dashed lines represent cable connections outside the first circuit board 1.

[0089] In other embodiments not shown in the figure, the connection method and management architecture between multiple electronic nodes 30 can also be adjusted through different cable configurations to adapt to more diverse working environments and needs.

[0090] like Figure 12As shown, multiple unit combinations 40 are arranged in a rectangular array within the receiving cavity 101 and located at the front end of multiple electronic nodes 30.

[0091] In this application, multiple unit combinations 40 are arranged in a rectangular array within the housing 101 and located at the front end of multiple electronic nodes 30, i.e., multiple unit combinations 40 are arranged in the front window of the housing 10. This optimizes the space utilization inside electronic devices such as servers. By arranging multiple unit combinations 40 in a rectangular array, not only is the arrangement density of components within the housing 101 effectively increased, but also the forward optimization configuration of multiple electronic nodes 30 is realized. More efficient thermal management and node interconnection of multiple electronic nodes 30 can be achieved in a limited space, thereby improving the computing power and reliability of the entire electronic device such as a server. This helps to simplify the maintenance and operation process of electronic devices such as servers. By uniformly setting multiple unit combinations 40 in the front window of the housing 10, centralized management and rapid maintenance are facilitated, reducing operation and maintenance costs and improving the overall operating efficiency of electronic devices.

[0092] In other embodiments not shown in the figure, this layout of multiple unit combinations 40 can also be flexibly adjusted according to actual needs, for example, by changing the number of rows and columns of the array to adapt to the layout of electronic devices such as servers with different computing densities and heat dissipation requirements.

[0093] Based on the requirements of high-performance electronic devices, the interface unit 401, storage unit 402, and management unit 403 corresponding to each electronic node 30 are essential, and the redundant design of the power supply is also a rigid requirement that cannot be cut. These units and power supplies must be placed on the front and rear windows of the user-operable housing 10. However, the front and rear window space provided by the 1U height and 19-inch width chassis (i.e., housing 10) remains unchanged. As the node density increases exponentially, the pressure on the layout of the front and rear window space will increase exponentially.

[0094] Therefore, this application separates the maintenance of the front window and the rear window of the housing 10. The front window is equipped with multiple unit combinations 40 to meet the needs of each electronic node 30 and facilitate user operation and maintenance. The rear window is only used to house the power supply and the liquid inlet and outlet of the heat dissipation module, and basically does not require user operation and maintenance.

[0095] like Figure 10 As shown, the management unit 403 includes a control motherboard 4031, a management controller 4032 and a switching chip 4033 disposed on and connected to the control motherboard 4031. The management controller 4032 can switch with one of the first electronic node 301 and the second electronic node 302 through the switching chip 4033 to exchange low-speed signals that do not require simultaneous access from both nodes.

[0096] In this application, the management unit 403 includes a control motherboard 4031, a management controller 4032, and a switching chip 4033 located on the control motherboard 4031. The management controller 4032 and the switching chip 4033 are connected. The management controller 4032 is connected to the first circuit board 1 of the first electronic node 301 and the second electronic node 302 through the switching chip 4033, so that communication between the first electronic node 301 and the second electronic node 302 can be switched through the switching chip 4033. This allows for the processing of low-speed signals that do not require simultaneous access from both nodes. This enables a single management unit 403 to effectively monitor and manage two electronic nodes 300 with limited interface resources, optimizing the resource configuration of the management unit 403 and reducing the number of pins required for the management unit 403's interface. The presence of the switching chip 4033 not only simplifies the wiring between the management unit 403 and the electronic nodes 300 but also ensures the flexible transmission of management signals, maintaining good maintainability and stability even in high-density electronic devices such as servers. Furthermore, this management model helps the housing 10 achieve a more compact front window space allocation, thereby supporting the integration of more electronic nodes 30. While increasing the computing density of electronic devices such as servers, it does not sacrifice their management efficiency and performance, providing an efficient and flexible solution for high-density electronic devices such as servers, and ensuring the overall performance and user experience of electronic devices.

[0097] like Figure 10 As shown, both the first electronic node 301 and the second electronic node 302 include a low-speed signal extension chip 312 disposed on the first circuit board 1; wherein, the management controller 4032 exchanges low-speed signals that do not require timely response with the low-speed signal extension chip 312 of the first electronic node 301 and the low-speed signal extension chip 312 of the second electronic node 302.

[0098] In this application, both the first electronic node 301 and the second electronic node 302 include a low-speed signal extension chip 312 disposed on the first circuit board 1. The management controller 4032 is connected to the low-speed signal extension chips 312 of both the first and second electronic nodes 301 to exchange low-speed signals that do not require immediate response. This significantly reduces the number of pins required for low-speed signal transmission between the management controller and each electronic node 30. By using the low-speed signal extension chip 312, effective management of multiple electronic nodes 30 can be achieved with limited interface resources. In actual operation, the management controller 4032 ensures coordinated control of the first and second electronic nodes 301 and 302 through interaction with the low-speed signal extension chip 312, maintaining the stability and efficiency of the electronic equipment even in complex and multi-node environments. In addition, the layout of the signal lines was optimized to avoid the direct doubling of low-speed signals, reducing setup difficulty and cost, while ensuring the quality of signal transmission and the overall performance of electronic equipment.

[0099] like Figure 10 As shown, the management controller 4032 directly and simultaneously exchanges low-speed signals that require timely response with the first circuit board 1 of the first electronic node 301 and the first circuit board 1 of the second electronic node 302; the management controller 4032 directly and simultaneously exchanges high-speed signals with the first electronic node 301 and the second electronic node 302.

[0100] In this application, a highly efficient signal exchange mechanism is established between the management controller 4032 and the first circuit board 1 of the first electronic node 301 and the first circuit board 1 of the second electronic node 302. This allows the management controller 4032 to exchange low-speed and high-speed signals that require timely response with the two nodes, thereby reducing signal transmission delay and improving the overall response speed of the electronic equipment. Specifically, for low-speed and high-speed signals requiring timely response, the management controller 4032 can simultaneously handle the communication between the first electronic node 301 and the second electronic node 302. This not only optimizes data transmission efficiency but also simplifies the interconnection lines between the management controller 4032 and the first and second electronic nodes 301, reducing the complexity of the electronic equipment and the potential failure rate. By intelligently allocating signal priorities and types, even in high-density electronic equipment such as servers, the management controller 4032 can maintain high efficiency and stability, ensuring the coordinated operation of multiple electronic nodes 30 and the normal operation of the electronic equipment.

[0101] Because the electronic device of this application is limited by the interface space of the front window of the housing 10, a management unit 403 is required to manage two electronic nodes 30 at the same time. Therefore, the interface bus of the management unit 403 must be provided to the two electronic nodes 30 respectively.

[0102] First, considering the selection of the corresponding connectors and interface space, the number of pins of the interface of the management unit 403 cannot be doubled. Therefore, a low-speed signal expansion chip 312 is added to the first circuit board 1 of the electronic node 30 to reduce the number of management connection cables between the management unit 403 and the node assembly 300.

[0103] Secondly, the signal rate is adjusted according to the signal rate. Switching high-speed signals is costly because the management controller 4032 directly doubles the high-speed signal and sends it to the two electronic nodes 30. For low-speed signals that do not require simultaneous access by both nodes, the management controller 4032 can switch them at the switching chip 4033 before sending them to the corresponding electronic node 30, in order to prevent insufficient low-speed interface resources of the management controller 4032.

[0104] Finally, based on the real-time nature of the signal, low-speed signals requiring immediate response (i.e., low-delay, fast-response signals) can be directly doubled by the management unit 403 and sent to the two electronic nodes 30 by the management controller 4032. Low-speed signals not requiring immediate response can be sent to the first circuit board 1 by the management controller 4032 through the corresponding low-speed signal extension chip 312 of the electronic node 30 to prevent insufficient connector pins.

[0105] Alternatively, the management controller 4032 can be a BMC or an ILO.

[0106] Among them, BMC stands for Baseboard Management Controller, which is the core component of server hardware management. It is mainly responsible for monitoring and managing the server hardware status (such as temperature, voltage, etc.) and providing remote management functions. ILO stands for Integrated Lights-Out, which has similar functions to BMC. It is used to provide the ability to remotely monitor and manage the server, allowing system administrators to operate without physical contact with the server.

[0107] In other embodiments not shown in the figure, the signal exchange mechanism can be further optimized to adapt to more diverse application scenarios. This includes, but is not limited to, adjusting the signal transmission path, enhancing signal processing capabilities, or improving signal encoding and decoding strategies to meet higher-level computing and management requirements.

[0108] The electronic device of this application includes a heat dissipation module, which includes a cold plate 20 and a water distributor. The water distributor is disposed in the receiving cavity 101 and located at the rear end of a plurality of electronic nodes 30 for connection with the cold plate 20.

[0109] In this application, the heat dissipation module design for electronic devices includes a cold plate 20 and a coolant distributor. The coolant distributor is located within the housing cavity 101 and at the rear end of multiple electronic nodes 30, i.e., the coolant distributor is located at the rear window of the housing 10 and is connected to the cold plate 20. Through the precise steps of the coolant distributor and the efficient heat dissipation of the cold plate 20, precise cooling of multiple electronic nodes 30 is achieved. Specifically, the coolant distributor is responsible for evenly distributing coolant from the outside to the cold plate 20. As a key component of the heat dissipation module, the cold plate 20 allows for the placement of multiple electronic nodes 30 on opposite sides, thereby fully utilizing the contact area of ​​the cold plate 20 and ensuring that each electronic node 30 is effectively cooled. This improves heat dissipation efficiency, avoids localized overheating, and provides a powerful thermal management solution for high-density setups of electronic devices such as servers, ensuring high-performance computing within a limited space while maintaining good heat dissipation performance.

[0110] like Figure 13 As shown, when two electronic nodes 30 located on opposite sides of the cold plate 20 need to be connected by a connection cable between the two nodes, the cold plate 20 is provided with a clearance through hole for the connection cable between the two nodes to pass through; and / or, the multiple electronic nodes 30 include at least one of computing nodes, switching nodes and storage nodes.

[0111] In this application, when signal interconnection between two electronic nodes 30 on opposite sides of the cold plate 20 is required, clearance through holes can be opened on the cold plate 20 to allow the connection cables of the nodes on both sides to pass through the cold plate 20 and be directly connected to the two electronic nodes 30 on opposite sides of the cold plate 20. This simplifies the layout of the connection cables of the nodes on both sides, ensures the optimization of the heat dissipation performance of the cold plate 20, avoids physical interference between the connection cables of the nodes on both sides and the cold plate 20, effectively avoids additional structural complexity and space occupation, improves the flexibility and efficiency of the electronic equipment setup, and ensures the efficient operation of the heat dissipation module.

[0112] Furthermore, the configuration of multiple electronic nodes 30 includes at least one of computing nodes, switching nodes, and storage nodes, indicating that this application supports diverse electronic devices that can be flexibly configured according to different application scenarios to meet the needs of high-performance computing, network switching, and data storage, thereby improving the adaptability and scalability of electronic devices.

[0113] like Figure 6As shown, the electronic device includes: a power supply and a power backplane 60, both of which are disposed within the housing 101 and located at the rear end of multiple electronic nodes 30, and the power supply and the power backplane 60 are connected to each other; multiple sets of power cables 70, and the power backplane 60 is connected to the multiple electronic nodes 30 one by one through the multiple sets of power cables 70.

[0114] In this application, the electronic device includes a power supply and a power backplane 60. Multiple power supplies are housed within the housing 101, located behind multiple electronic nodes 30. Specifically, both the power supplies and the power backplane 60 are situated at the rear window of the housing 10, forming the core of the power module through connection. Furthermore, multiple sets of power cables 70 are introduced, enabling the power backplane 60 to establish a one-to-one power transmission path with each electronic node 30. This achieves efficient centralized management and distribution of power, ensuring stable power supply to each electronic node 30 and enhancing the reliability of the electronic device through redundant power supply design. The combination of the power supplies and the power backplane 60, along with the precise connection of the power cables 70, constitutes a compact yet flexible power supply network, effectively supporting power demands in high-density node environments while simplifying wiring and maintenance.

[0115] Specifically, the power supply is inserted into the receiving cavity 101 through the rear window of the housing 10, and the power supply backplate 60 is connected to the power supply cable 70 through the backplate connector; multiple sets of power supply cables 70 are selected in two lengths to connect to the first electronic node 301 and the second electronic node 302 of each node combination 300 respectively. The longer power supply cable 70 is connected to the first electronic node 301, and the shorter power supply cable 70 is connected to the second electronic node 302; each electronic node 30 corresponds to a set of power supply cables 70, and each set of power supply cables 70 is located on the side of the corresponding electronic node 30 away from the cold plate 20, so as to facilitate disassembly and maintenance.

[0116] In this application, the height of the housing 10 is 1U, and the maximum thickness of each electronic node 30 is less than 0.5U. This achieves an ultra-high density node layout in a chassis (i.e., housing 10) with a height of 1U and a width of 19 inches, while ensuring good heat dissipation, power stability, and scalability, providing users with a high power density and high node density electronic device such as a server.

[0117] In this application, the thickness of the cold plate 20 is greater than or equal to 0.25U and less than or equal to 0.35U, the maximum thickness of each electronic node 30 is less than or equal to 0.35U, and the sum of the thicknesses of one cold plate 20 and two electronic nodes 30 is less than the height of the housing 10. This ensures that multiple electronic nodes 30 can efficiently dissipate heat within a limited space, while maintaining a high-density layout of electronic equipment. By precisely controlling the thickness of the cold plate and nodes, better space utilization can be achieved, enabling electronic equipment such as servers to maintain good ventilation and heat dissipation conditions even at high density.

[0118] Specifically, the overall thickness of each component in the housing 10 of the electronic device in this application is 41.18 mm, and the height of the usable space in the 1U housing 10 is 44.45 mm, which is just right considering tolerance and other factors.

[0119] The calculation method of the total power of the electronic device in this application is shown in Table 1 below, which is approximately 7.3KW. The rear window of the electronic device is equipped with four 3600W power supplies, supporting a redundant design of N+N power supplies. Two power supplies can be removed at will without affecting the power supply.

[0120]

[0121] Current liquid-cooled high-density server architectures, including 2U high chassis, can accommodate four dual-socket nodes. The chassis dimensions are: depth 921mm, width 447mm, height 2U, total power consumption 5.6KW, and total power density 153KW / m³. In contrast, the electronic equipment in this application, including a 1U high chassis, can also accommodate four dual-socket nodes. The chassis dimensions are: depth 1000mm, width 447mm, height 1U, total power consumption 7.3KW, and total power density 367KW / m³.

[0122] Comparison shows that the overall power density of the electronic equipment in the 1U chassis of this application is more than twice that of the current liquid-cooled high-density architecture server with a 2U chassis. Furthermore, the node density of the electronic equipment in the 1U chassis of this application is twice that of the current liquid-cooled high-density architecture server with a 2U chassis. In addition, when the electronic equipment in the 1U chassis of this application accommodates eight single-socket nodes, the node density of the electronic equipment in the 1U chassis of this application is four times that of the current liquid-cooled high-density architecture server with a 2U chassis.

[0123] This application also provides a server rack including the aforementioned electronic equipment. By employing the electronic equipment of this application, the server rack of this application maximizes the integration of electronic nodes within a limited space, while maintaining efficient liquid cooling performance and sufficient memory configuration. This not only optimizes space utilization but also ensures stable operation and high-performance computing of the server rack, providing strong support for high-density, high-efficiency, and high-performance computing environments in data centers.

[0124] The above provides a detailed description of an electronic device and cabinet provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An electronic device, characterized in that, include: The housing (10) includes a receiving cavity (101); A cold plate (20) is disposed within the receiving cavity (101); Multiple electronic nodes (30) are respectively disposed on opposite sides of the cold plate (20); each of the electronic nodes (30) includes a first circuit board (1) parallel to the cold plate (20), a processor (2) connected to the first circuit board (1), and at least one memory module (3), the memory module (3) being located on the side of the first circuit board (1) closer to the cold plate (20); The memory module (3) includes a second circuit board (31) parallel to the first circuit board (1), as well as memory chips (32) and connectors (33) connected to the second circuit board (31).

2. The electronic device according to claim 1, characterized in that, At least two adjacent memory modules (3) form a memory combination (35), and the connectors (33) of each memory module (3) in the memory combination (35) have different heights; along a first direction, the second circuit board (31) in the memory combination (35) is stacked in a direction away from the first circuit board (1).

3. The electronic device according to claim 2, characterized in that, At least one of the second circuit boards (31) in the memory combination (35) is positioned close to the cold plate (20).

4. The electronic device according to claim 2, characterized in that, There are multiple memory combinations (35); wherein, along the second direction, multiple memory combinations (35) are disposed on the same side or opposite sides of the processor (2).

5. The electronic device according to claim 1, characterized in that, The cold plate (20) includes a cold plate body (201) and a plurality of heat-conducting protrusions spaced apart on the cold plate body (201); wherein the cold plate body (201) and the heat-conducting protrusions are respectively used to contact different parts of the corresponding electronic nodes (30).

6. The electronic device according to claim 2, characterized in that, The electronic node (30) includes a heat-conducting plate (303) at least partially disposed between two adjacent second circuit boards (31) in the memory assembly (35), the opposite sides of the heat-conducting plate (303) respectively contacting at least a portion of the memory chips (32) on the corresponding two second circuit boards (31), and the heat-conducting plate (303) is used to contact the cold plate (20).

7. The electronic device according to claim 6, characterized in that, The electronic device includes a heat dissipation pipe (50) disposed on the side of the heat-conducting plate (303) near the cold plate (20), with the opposite sides of the heat dissipation pipe (50) contacting the cold plate (20) and the heat-conducting plate (303) respectively.

8. The electronic device according to claim 6, characterized in that, The electronic node (30) also includes a thermal pad (305) disposed between the heat-conducting plate (303) and the second circuit board (31), with the opposite sides of the thermal pad (305) contacting the heat-conducting plate (303) and the second circuit board (31) respectively.

9. The electronic device according to claim 1, characterized in that, The plurality of electronic nodes (30) are grouped into multiple node combinations (300) in pairs. Each node combination (300) includes a first electronic node (301) and a second electronic node (302) arranged from front to back along a first direction of the receiving cavity (101). The first electronic node (301) and the second electronic node (302) are centrally symmetrical about a predetermined center between them.

10. The electronic device according to claim 9, characterized in that, The electronic device includes multiple unit combinations (40) spaced apart within the receiving cavity (101) and located at the front end of the multiple electronic nodes (30), the multiple unit combinations (40) being arranged one-to-one with the multiple node combinations (300); each of the unit combinations (40) includes an interface unit (401), a storage unit (402) and a management unit (403), the interface unit (401), the storage unit (402) and the management unit (403) being respectively connected to the corresponding node combination (300).

11. The electronic device according to claim 10, characterized in that, Both the first electronic node (301) and the second electronic node (302) include: A right-angle connector (37) is disposed on a corresponding first circuit board (1) for plugging into the interface unit (401); and / or, A processor connector (38) is disposed on a corresponding first circuit board (1) and connected to the processor (2) at least via the first circuit board (1); and / or, A network card connector (39) is provided, wherein the right-angle connector (37) is disposed on the corresponding first circuit board (1) and connected to the right-angle connector (37) via the first circuit board (1); in the first electronic node (301), the network card connector (39) is connected to the processor connector (38) via a network card connection cable; and / or, A storage connector (310), the right-angle connector (37) being disposed on a corresponding first circuit board (1) and connected to at least the processor (2) via the first circuit board (1); in the first electronic node (301), the storage connector (310) being connected to the storage cell (402) via a storage connection cable; and / or, A management connector (311) is provided on the corresponding first circuit board (1) and is connected to the processor (2) at least through the first circuit board (1); in the first electronic node (301), the management connector (311) is connected to the management unit (403) through a management connection cable.

12. The electronic device according to claim 11, characterized in that, The network card connector (39) of the first electronic node (301) and the processor connector (38) of the second electronic node (302) are connected by a first node connection cable; the storage connector (310) of the first electronic node (301) and the processor connector (38) of the second electronic node (302) are connected by a second node connection cable; the management connector (311) of the second electronic node (302) is connected to the management unit (403) by a management connection cable.

13. The electronic device according to claim 11, characterized in that, The processor connector (38) of the first electronic node (301) and the processor connector (38) of the second electronic node (302) are connected by a third node connection cable.

14. The electronic device according to claim 10, characterized in that, The multiple unit combinations (40) are arranged in a rectangular array within the receiving cavity (101) and located at the front end of the multiple electronic nodes (30).

15. The electronic device according to claim 10, characterized in that, The management unit (403) includes a control motherboard (4031) and a management controller (4032) and a switching chip (4033) disposed on and connected to the control motherboard (4031). The management controller (4032) can switch with one of the first electronic node (301) and the second electronic node (302) via the switching chip (4033) to exchange low-speed signals that do not require simultaneous access from both nodes.

16. The electronic device according to claim 15, characterized in that, Both the first electronic node (301) and the second electronic node (302) include a low-speed signal extension chip (312) disposed on the first circuit board (1); wherein, the management controller (4032) exchanges low-speed signals that do not require timely response with the low-speed signal extension chip (312) of the first electronic node (301) and the low-speed signal extension chip (312) of the second electronic node (302).

17. The electronic device according to claim 15, characterized in that, The management controller (4032) directly and simultaneously exchanges low-speed signals that require timely response with the first circuit board (1) of the first electronic node (301) and the first circuit board (1) of the second electronic node (302); the management controller (4032) directly and simultaneously exchanges high-speed signals with the first electronic node (301) and the second electronic node (302).

18. The electronic device according to claim 1, characterized in that, When two electronic nodes (30) respectively located on opposite sides of the cold plate (20) need to be connected via connecting cables from both sides, the cold plate (20) is provided with clearance through holes for the connecting cables from both sides to pass through; and / or, The plurality of electronic nodes (30) include at least one of computing nodes, switching nodes and storage nodes.

19. The electronic device according to claim 1, characterized in that, The electronic device includes: a power supply and a power backplate (60), both of which are disposed in the receiving cavity (101) and located at the rear end of the plurality of electronic nodes (30), the power supply and the power backplate (60) being connected to each other; and a plurality of power cables (70), the power backplate (60) being connected to the plurality of electronic nodes (30) one by one through the plurality of power cables (70).

20. The electronic device according to claim 1, characterized in that, The height of the housing (10) is 1U, the thickness of the cold plate (20) is greater than or equal to 0.25U and less than or equal to 0.35U, the maximum thickness of each of the electronic nodes (30) is less than or equal to 0.35U, and the sum of the thicknesses of one of the cold plates (20) and two of the electronic nodes (30) is less than the height of the housing (10).

21. A server rack, characterized in that, The electronic device included in any one of claims 1 to 20.

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