Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The semiconductor structure comprises a plurality of supporting layers, a first electrode layer, a second electrode layer, a capacitor dielectric layer and a supporting part. The multiple supporting layers are arranged at intervals in the first direction. The first electrode layer extends in a first direction and is in contact with the plurality of support layers. A part of the capacitor dielectric layer is located between the first electrode layer and the second electrode layer. The support portion is located on one side of the plurality of support layers in the first direction and is in contact with the first electrode layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods of manufacturing semiconductor structures, and memory systems. Background Technology

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the requirements for the performance and processes of semiconductor structures such as three-dimensional semiconductor storage devices are becoming increasingly stringent. Summary of the Invention

[0003] This disclosure provides a semiconductor structure. The semiconductor structure includes multiple support layers, a first electrode layer, a second electrode layer, a capacitor dielectric layer, and a support portion. The multiple support layers are spaced apart in a first direction. The first electrode layer extends along the first direction and contacts the multiple support layers. A portion of the capacitor dielectric layer is located between the first electrode layer and the second electrode layer. The support portion is located on one side of the multiple support layers in the first direction and contacts the first electrode layer.

[0004] In one embodiment, at least one end of the support portion in the second direction is warped toward the side opposite to the support layer. The first and second directions intersect.

[0005] In one embodiment, at least one end of the support in the second direction is at a distance greater than the distance between the support portion in contact with the first electrode layer and the adjacent support layer in the first direction.

[0006] In one embodiment, the distance between the portion of the support that contacts the first electrode layer and the adjacent support layer in the first direction is less than 200 nm.

[0007] In one embodiment, the support portion contacts an end of the first electrode layer in a first direction; and / or the support portion contacts a sidewall of the first electrode layer on a plane intersecting the first direction.

[0008] In one embodiment, the distance between adjacent support layers in the first direction is greater than 300 nm.

[0009] In one embodiment, in the first direction, a portion of the second electrode layer is located between the support portion and the support layer, and a portion of the second electrode layer is located between adjacent support layers.

[0010] In one embodiment, the plurality of support layers include a first support layer, a second support layer, and a third support layer. The first support layer extends along a second direction and is less than 200 nm away from the support portion in the first direction. The second support layer is located on one side of the first support layer in the first direction and extends along the second direction, and is more than 300 nm away from the first support layer in the first direction. The third support layer is located on the side of the second support layer opposite to the first support layer and extends along the second direction, and is more than 300 nm away from the second support layer in the first direction. The first and second directions intersect.

[0011] In one embodiment, the support portion and the support layer comprise the same material.

[0012] In one embodiment, the first electrode layer includes a conductive layer. The portion of the conductive layer that contacts the plurality of support layers is continuous in a second direction. The first and second directions intersect.

[0013] In one embodiment, the first electrode layer includes a conductive layer and a dielectric layer. The conductive layer extends along a first direction and contacts a plurality of support layers. The dielectric layer is located on the side of the conductive layer opposite to the support layers and extends along the first direction. The dielectric layer is made of a doped nitride.

[0014] In one embodiment, the semiconductor structure further includes a conductive structure. The conductive structure is located on the side of the second electrode layer opposite to the capacitor dielectric layer. The material of the conductive structure includes a conductive material.

[0015] In one embodiment, the semiconductor structure further includes a transistor and a capacitor contact structure. The capacitor contact structure is located on one side of the transistor. A first electrode layer extends to the capacitor contact structure along a first direction.

[0016] This disclosure also provides a method for manufacturing a semiconductor structure. The method includes: forming a capacitor aperture extending through a mask layer and a stacked structure along a first direction, wherein the mask layer is located on one side of the stacked structure along the first direction; forming a first electrode layer within the capacitor aperture, wherein the first electrode layer extends along the first direction and contacts the mask layer and the stacked structure; forming a support portion located on the side of the mask layer opposite to the stacked structure and in contact with the first electrode layer; and forming a capacitor dielectric layer covering at least a portion of the first electrode layer and a second electrode layer covering at least a portion of the capacitor dielectric layer.

[0017] In one embodiment, forming a capacitor aperture penetrating a mask layer and a stacked structure along a first direction includes: forming a stacked structure comprising a support layer and a sacrificial layer alternately stacked along a first direction, wherein both ends of the stacked structure in the first direction are support layers; forming a mask layer on one side of the stacked structure along the first direction; and forming a capacitor aperture penetrating the mask layer and the stacked structure along the first direction.

[0018] In one embodiment, forming the support portion includes: removing a portion of the mask layer away from the stacked structure along a first direction to form a groove; and forming the support portion within the groove.

[0019] In one embodiment, forming the support portion includes forming the support portion on the side of the mask layer away from the stacked structure, wherein the support portion contacts an end of the first electrode layer in a first direction.

[0020] In one embodiment, forming a capacitor dielectric layer covering at least a portion of a first electrode layer and a second electrode layer covering at least a portion of the capacitor dielectric layer includes: removing the remaining mask layer and sacrificial layer to form a sacrificial gap; and forming a capacitor dielectric layer covering at least a portion of the first electrode layer and a second electrode layer covering at least a portion of the capacitor dielectric layer within the sacrificial gap.

[0021] In one embodiment, removing the remaining mask layer and sacrificial layer to form a sacrificial gap includes: removing a portion of the support portion along a first direction to expose the mask layer; removing the remaining mask layer to expose the support layer; removing a portion of the support layer along the first direction to expose the sacrificial layer; and removing the sacrificial layer to form a sacrificial gap.

[0022] In one embodiment, the method further includes forming a conductive structure. The conductive structure is located on the side of the second electrode layer opposite to the capacitor dielectric layer, and the material of the conductive structure includes a conductive material.

[0023] In one embodiment, the method further includes: forming a transistor; and forming a capacitive contact structure on one side of the transistor. A first electrode layer extends along a first direction to the capacitive contact structure.

[0024] In another aspect, this disclosure provides a storage system including a semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the semiconductor structure to store data. Attached Figure Description

[0025] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0026] Figure 1 This is a partial structural schematic diagram of a semiconductor structure provided according to an exemplary embodiment of the present disclosure;

[0027] Figure 2 This is a partial structural schematic diagram of a semiconductor structure provided according to another exemplary embodiment of the present disclosure;

[0028] Figure 3 This is a partial structural schematic diagram of a semiconductor structure provided according to another exemplary embodiment of the present disclosure;

[0029] Figure 4 This is a partial structural schematic diagram of a semiconductor structure provided according to another exemplary embodiment of the present disclosure;

[0030] Figure 5 This is a partial structural schematic diagram of a semiconductor structure provided according to another exemplary embodiment of the present disclosure;

[0031] Figure 6 This is a flowchart of a method 1000 for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure;

[0032] Figure 7 This is a partial structural schematic diagram of the transistor, capacitor contact structure, stacked structure and mask layer provided according to an exemplary embodiment of the present disclosure;

[0033] Figure 8 This is a partial structural diagram of the capacitor hole formed according to an exemplary embodiment of the present disclosure;

[0034] Figure 9 This is a schematic diagram of the structure after forming the first electrode layer according to an exemplary embodiment of this disclosure;

[0035] Figure 10 This is a schematic diagram of the structure after removing a portion of the first electrode layer located on the mask layer according to an exemplary embodiment of this disclosure;

[0036] Figure 11 This is a schematic diagram of the structure after the groove is formed according to an exemplary embodiment of the present disclosure;

[0037] Figure 12 This is a schematic diagram of the structure after the support portion is formed, according to an exemplary embodiment of this disclosure;

[0038] Figure 13 This is a schematic diagram of the structure after forming a patterned mask layer according to an exemplary embodiment of the present disclosure;

[0039] Figure 14 This is a schematic diagram of the structure after forming the first opening according to an exemplary embodiment of the present disclosure;

[0040] Figure 15 This is a schematic diagram of the structure after removing the hard mask layer and the mask layer according to an exemplary embodiment of this disclosure;

[0041] Figure 16 This is a schematic diagram of the structure after forming the second opening according to an exemplary embodiment of the present disclosure;

[0042] Figure 17 This is a schematic diagram of the structure after removing the second sacrificial layer according to an exemplary embodiment of this disclosure;

[0043] Figure 18 This is a schematic diagram of the structure after forming the third opening and removing the first sacrificial layer according to an exemplary embodiment of this disclosure;

[0044] Figure 19 This is a schematic diagram of the structure after forming a capacitor dielectric layer, a second electrode layer, and a conductive structure according to an exemplary embodiment of the present disclosure;

[0045] Figure 20 This is a partial structural schematic diagram of a semiconductor structure formed according to an exemplary embodiment of the present disclosure;

[0046] Figures 21 to 29 This is a process step diagram for forming a semiconductor structure according to another exemplary embodiment of this disclosure; and

[0047] Figure 30 This is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present disclosure.

[0048] Explanation of reference numerals in the attached figures:

[0049] Z, First direction; X, Second direction; Y, Third direction; D, Stacking direction; L1, L2, L3, L4, h1, h2, H1, H2, H3, H4, Dimensions; 100, Transistor; 110, Gate; 200, Capacitor contact structure; 300, 810 Mask layer; 400, 820, Capacitor via; 500, Groove; 600, 830, Patterned mask layer; 610, 831 Window; 620, Hard mask layer; 630, Other material layers; 700, 840, Sacrificial gap; 710, 841, First opening; 720, 842, Second opening; 730, Third opening; 1100, Stacking structure; 1110, Support layer ; 1120, Sacrificial layer; 1111, First support layer; 1112, Second support layer; 1113, Third support layer; 1121, First sacrificial layer; 1122, Second sacrificial layer; 1210, 2210, 3210, 4210, First electrode layer; 1220, 4220, Capacitor dielectric layer; 1230, 4230, Second electrode layer; 1200, Capacitor; 1211, 2211, 3211, Conductive layer; 2212, 3212, 4211, Dielectric layer; 1300, 2300, Support portion; 1310, 2310, Recessed portion; 1320, 2320, Warped portion; 1400, 4300, Conductive structure. Detailed Implementation

[0050] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way.

[0051] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this disclosure, the first electrode layer discussed herein may also be referred to as the second electrode layer, and the first direction may also be referred to as the second direction, and vice versa.

[0052] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0053] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0054] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplarily" is intended to refer to an example or illustration.

[0055] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0056] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0057] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer can be a region of a homogeneous or non-homogeneous continuous structure, the height of which is less than the height of the continuous structure. For example, a layer can be located at or between any set of horizontal planes on or between the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer can include multiple layers.

[0058] Furthermore, in this disclosure, the use of “connection” or “linkage” may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0059] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0060] It should be noted that the first direction Z, the second direction X, and the third direction Y mentioned below may intersect each other (e.g., perpendicularly). The second direction X and the third direction Y may be two directions that intersect each other (e.g., perpendicularly) on a plane that intersects (e.g., perpendicularly) the first direction Z. The stacking direction D mentioned below may be a direction opposite to the first direction Z.

[0061] Figure 1 This is a partial structural schematic diagram of a semiconductor structure provided according to an exemplary embodiment of the present disclosure.

[0062] The semiconductor structure may include multiple support layers 1110, a first electrode layer 1210, a second electrode layer 1230, a capacitor dielectric layer 1220, and a support portion 1300. The multiple support layers 1110 may be spaced apart along a first direction Z. The first electrode layer 1210 may extend along the first direction Z and may contact the multiple support layers 1110. A portion of the capacitor dielectric layer 1220 may be located between the first electrode layer 1210 and the second electrode layer 1230. The support portion 1300 may be located on one side of the multiple support layers 1110 along the first direction Z and may contact the first electrode layer 1210.

[0063] In an exemplary embodiment of this disclosure, the first electrode layer 1210, the second electrode layer 1230, and the capacitor dielectric layer 1220 can be used to form a capacitor 1200. For example... Figure 1 As shown, the semiconductor structure may further include a transistor 100 and a capacitive contact structure 200 located on one side of the transistor 100. The capacitive contact structure 200 may contact the transistor 100.

[0064] For example, transistor 100 may be a vertical transistor such as a vertical metal-oxide-semiconductor field-effect transistor to facilitate the formation of capacitor 1200 (including a first electrode layer 1210, a second electrode layer 1230, and a capacitor dielectric layer 1220) on one side of transistor 100 along the first direction Z. The material of capacitor contact structure 200 may include one or more of tungsten, molybdenum, copper, aluminum, ruthenium, titanium, titanium nitride, polysilicon, indium tin oxide, metal silicides (e.g., titanium silicide, cobalt silicide, nickel-platinum silicide) or any other suitable conductive material.

[0065] For example, the first electrode layer 1210 may extend along a first direction Z to the capacitor contact structure 200. The first electrode layer 1210 may include a conductive layer 1211, wherein the portion of the conductive layer 1211 that contacts the plurality of support layers 1110 is continuous in a second direction X. For example, the first electrode layer 1210 may be formed by completely filling the conductive layer 1211 within a capacitor hole.

[0066] Exemplarily, the material of the conductive layer 1211 may include at least one of a metal, a metal compound, and a semiconductor material. For example, the material of the conductive layer 1211 may include a compound formed from one or two of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride, etc. Exemplarily, the material of the conductive layer 1211 may be titanium nitride.

[0067] For example, such as Figure 1As shown, the plurality of support layers 1110 may include a first support layer 1111, a second support layer 1112, and a third support layer 1113. The first support layer 1111 may extend along a second direction X. The second support layer 1112 may be located on one side of the first support layer 1111 in a first direction Z and may extend along the second direction X. The third support layer 1113 may be located on the side of the second support layer 1112 opposite to the first support layer 1111 and may extend along the second direction X. The support portion 1300 may be located on the side of the first support layer 1111 opposite to the second support layer 1112 and may extend along the second direction X.

[0068] It should be understood that the limitation on the number of support layers 1110 in this application is merely an example and not an explicit limitation. In actual manufacturing processes, the number of support layers 1110 can be reasonably set according to the required height of the capacitor 1200.

[0069] For example, the distance between adjacent support layers 1110 in the first direction Z can be greater than 300 nm. For instance, the distance between the second support layer 1112 and the third support layer 1113 in the first direction Z can be greater than 300 nm, but can be approximately 510 nm. The distance between the first support layer 1111 and the second support layer 1112 in the first direction Z can be greater than 300 nm, but can be approximately 400 nm. For example, the distance between the first support layer 1111 and the support portion 1300 in the first direction Z can be less than 200 nm.

[0070] For example, such as Figure 1 As shown, the support portion 1300 can contact the sidewall of the first electrode layer 1210 on a plane intersecting the first direction Z (such as the plane formed by the second direction X and the third direction Y). The distance L2 between the portion of the support portion 1300 that contacts the first electrode layer 1210 and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z can be less than 200 nm.

[0071] For example, such as Figure 1 As shown, at least one end of the support portion 1300 in the second direction X (where the first electrode layer 1210 is not provided) may be warped toward the side away from the support layer 1110 (such as the first support layer 1111). For example, the distance L1 between the at least one end of the support portion 1300 in the second direction X (where the first electrode layer 1210 is not provided) and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z may be greater than the distance L2 between the portion of the support portion 1300 that contacts the first electrode layer 1210 and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z.

[0072] For example, such as Figure 1As shown, the support portion 1300 may include a recessed portion 1310 and a warped portion 1320. The recessed portion 1310 may contact the sidewall of the first electrode layer 1210 on a plane intersecting the first direction Z (such as a plane formed by the second direction X and the third direction Y). The warped portion 1320 may be located on at least one side of the recessed portion 1310 in the second direction X (where the first electrode layer 1210 is not disposed) and warped away from the support layer 1110 (such as the first support layer 1111). For example, the recessed portion 1310 may be the central portion of the support portion 1300, and the warped portion 1320 may be the edge portion of the support portion 1300. Exemplarily, the distance L1 between the warped portion 1320 and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z may be greater than the distance L2 between the recessed portion 1310 and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z.

[0073] It should be noted that, Figure 1 The shown example of the support portion 1300 contacting the sidewall of the first electrode layer 1210 in a plane intersecting the first direction Z (such as the plane formed by the second direction X and the third direction Y) is merely an example and not a specific limitation. In actual manufacturing, the support portion 1300 may also contact the end of the first electrode layer 1210 in the first direction Z (not shown), i.e., the support portion 1300 may have a comb-like structure that can cover part of the first electrode layer 1210.

[0074] In this disclosure, by setting the first electrode layer 1210 to contact the support portion 1300 and the plurality of support layers 1110, it is advantageous to ensure that the sum of the dimensions of the support portion 1300 and the plurality of support layers 1110 in the first direction Z is approximately the same as the dimension of the first electrode layer 1210 in the first direction Z. This is beneficial to ensure that, under the premise of a certain degree of difficulty in the forming process, the dimension of the first electrode layer 1210 in the first direction Z is maximized, which in turn is beneficial to increase the dimension of the capacitor 1200 (including the first electrode layer 1210, the second electrode layer 1230 and the capacitor dielectric layer 1220) in the first direction Z, thereby increasing the effective capacitance area of ​​the capacitor 1200.

[0075] For example, the support portion 1300 and the support layer 1110 may comprise the same material. For instance, the materials of the support portion 1300, the first support layer 1111, the second support layer 1112, and the third support layer 1113 may comprise any one or any combination of two or more of silicon nitride, silicon oxynitride, and aluminum oxide. The support portion 1300, the first support layer 1111, the second support layer 1112, and the third support layer 1113 may be doped with at least one of carbon, boron, and phosphorus.

[0076] In this disclosure, the support portion 1300, the first support layer 1111, the second support layer 1112 and the third support layer 1113 can all play a supporting role, which is conducive to improving the mechanical strength of the structure of the capacitor 1200 and reducing the damage to the capacitor 1200 during the forming process (such as grinding).

[0077] For example, such as Figure 1 As shown, in the first direction Z, a portion of the second electrode layer 1230 is located between the support portion 1300 and the support layer 1110, and a portion of the second electrode layer 1230 is located between adjacent support layers 1110. This facilitates the presence of capacitance between the support portion 1300 and the support layer 1110, as well as between adjacent support layers 1110, thereby increasing the size of the capacitor 1200 in the first direction Z and increasing the effective capacitance area of ​​the capacitor 1200.

[0078] Exemplarily, the material of the second electrode layer 1230 may include at least one of a metal, a metal compound, and a semiconductor material. For example, the material of the second electrode layer 1230 may include a compound formed from one or two of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride, etc. Furthermore, the material of the second electrode layer 1230 may also include a stack formed from one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polycrystalline silicon, P-type polycrystalline silicon, or two or more materials from the group consisting of the above materials.

[0079] For example, the capacitor dielectric layer 1220 may be located between the first electrode layer 1210 and the second electrode layer 1230. For example, the capacitor dielectric layer 1220 may cover at least a portion of the first electrode layer 1210, and the second electrode layer 1230 may cover at least a portion of the capacitor dielectric layer 1220.

[0080] Exemplarily, the material of the capacitor dielectric layer 1220 may include a high dielectric constant material. For example, the material of the capacitor dielectric layer 1220 may include, but is not limited to, at least one or a combination of aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconate, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide and / or praseodymium oxide.

[0081] For example, such as Figure 1 As shown, the semiconductor structure may further include a conductive structure 1400. The conductive structure 1400 may be located on the side of the second electrode layer 1230 opposite to the capacitor dielectric layer 1220. Exemplarily, the conductive structure 1400 may cover the second electrode layer 1230. The conductive structure 1400 may have multiple insulating gaps to alleviate structural stress.

[0082] Exemplarily, the material of the conductive structure 1400 may include conductive materials such as doped semiconductor materials. For example, the material of the conductive structure 1400 may include boron-doped germanium silicon. Exemplarily, the conductive structure 1400 may be connected to other conductive structures (not shown) to realize the connection between the capacitor and other conductive structures such as peripheral circuits.

[0083] Figure 2 This is a partial structural schematic diagram of a semiconductor structure provided according to another exemplary embodiment of this disclosure. For the purpose of brevity, Figure 2 The illustrated implementation method and Figure 1 The same content as the embodiments shown will not be repeated here.

[0084] For example, such as Figure 2 As shown, the support portion 2300 can be located on one side of the first electrode layer 1210 in the first direction Z and can contact the end of the first electrode layer 1210 in the first direction Z. The distance L4 between the portion of the support portion 2300 that contacts the first electrode layer 1210 and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z can be less than 200 nm. Since L4 (i.e., the size of the portion of the first electrode layer 1210 that protrudes from the first support layer 1111) is small, the risk of deformation, such as bending, of the portion of the first electrode layer 1210 that protrudes from the first support layer 1111 is small. Therefore, the support portion 2300 can be located on one side of the first electrode layer 1210 in the first direction Z.

[0085] For example, such as Figure 2 As shown, at least one end of the support portion 2300 in the second direction X (where the first electrode layer 1210 is not provided) may be warped toward the side away from the support layer 1110 (such as the first support layer 1111). For example, the distance L3 between the at least one end of the support portion 2300 in the second direction X (where the first electrode layer 1210 is not provided) and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z may be greater than the distance L4 between the portion of the support portion 2300 that contacts the first electrode layer 1210 and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z.

[0086] For example, such as Figure 2As shown, the support portion 2300 may include a recessed portion 2310 and a warped portion 2320. The recessed portion 2310 may be opposite to the first electrode layer 1210 along the first direction Z and may contact the end of the first electrode layer 1210 in the first direction Z. The warped portion 2320 may be located on at least one side of the recessed portion 2310 in the second direction X (where the first electrode layer 1210 is not provided) and warped toward the side away from the support layer 1110 (such as the first support layer 1111). For example, the recessed portion 2310 may be the central portion of the support portion 2300, and the warped portion 2320 may be the edge portion of the support portion 2300. Exemplarily, the distance L3 between the warped portion 2320 and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z may be greater than the distance L4 between the recessed portion 2310 and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z.

[0087] Figure 3 This is a partial structural schematic diagram of a semiconductor structure provided according to another exemplary embodiment of this disclosure. For the purpose of brevity, Figure 3 The illustrated implementation method and Figure 1 The same content as the embodiments shown will not be repeated here.

[0088] For example, such as Figure 3 As shown, the first electrode layer 2210 may extend along the first direction Z and may contact the plurality of support layers 1110. The first electrode layer 2210 may include a conductive layer 2211 and a dielectric layer 2212. The conductive layer 2211 may extend along the first direction Z and contact the plurality of support layers 1110. The dielectric layer 2212 may be located on the side of the conductive layer 2211 opposite to the support layers 1110 and extend along the first direction Z, that is, the conductive layer 2211 may surround the dielectric layer 2212.

[0089] Exemplarily, the material of the conductive layer 2211 may include at least one of a metal, a metal compound, and a semiconductor material. For example, the material of the conductive layer 2211 may include a compound formed from one or two of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride, etc. Exemplarily, the material of the conductive layer 2211 may be titanium nitride.

[0090] For example, the material of dielectric layer 2212 may include a doped nitride. For instance, the material of dielectric layer 2212 may include silicon nitride doped with at least one of carbon, boron, and phosphorus.

[0091] Figure 4 This is a partial structural schematic diagram of a semiconductor structure provided according to another exemplary embodiment of this disclosure. For the purpose of brevity, Figure 4 The illustrated implementation method and Figure 2 The same content as the embodiments shown will not be repeated here.

[0092] For example, such as Figure 4 As shown, the first electrode layer 3210 may extend along the first direction Z and may contact a plurality of support layers 1110. The first electrode layer 3210 may include a conductive layer 3211 and a dielectric layer 3212. The conductive layer 3211 may extend along the first direction Z and contact the plurality of support layers 1110. The dielectric layer 3212 may be located on the side of the conductive layer 3211 opposite to the support layers 1110 and extend along the first direction Z, that is, the conductive layer 3211 may surround the dielectric layer 3212.

[0093] Exemplarily, the material of the conductive layer 3211 may include at least one of a metal, a metal compound, and a semiconductor material. For example, the material of the conductive layer 3211 may include a compound formed from one or two of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride, etc. Exemplarily, the material of the conductive layer 3211 may be titanium nitride.

[0094] By way of example, the material of dielectric layer 3212 may include a doped nitride. For example, the material of dielectric layer 3212 may include silicon nitride doped with at least one of carbon, boron and phosphorus.

[0095] Figure 5 This is a partial structural schematic diagram of a semiconductor structure provided according to another exemplary embodiment of the present disclosure. Exemplarily, the semiconductor structure may include a storage device with storage functionality. For example... Figure 5 As shown, the storage device may include storage cells MC and word lines WL and bit lines BL coupled to the storage cells MC. Exemplarily, the storage device may include at least one of dynamic random access memory (DRAM), phase-change memory (PCM), and ferroelectric random access memory (FRAM). For ease of description, the following description primarily uses DRAM memory as an example.

[0096] The memory cell MC may include DRAM cells and may be arrayed along a second direction X and a third direction Y. Each DRAM cell may include a capacitor 1200 for storing bits of data as positive or negative charges and one or more transistors 100 (aka via transistors) for controlling (e.g., switching and selecting) access to it. Exemplarily, the transistor 100 may be a vertical transistor such as a vertical metal-oxide-semiconductor field-effect transistor 100 (MOSFET) to facilitate the subsequent formation of a capacitor 1200 on one side of the transistor 100 along the first direction Z.

[0097] Word lines WL can be coupled to memory cells MC along a third direction Y to control the switching of vertical transistors 100 in memory cells MC located in a row along the third direction Y. Bit lines BL can be coupled to memory cells MC along a second direction X to send data to and / or receive data from memory cells MC in a column along the second direction X. That is, each word line WL can be coupled to the memory cell MC in the corresponding row and each bit line BL can be coupled to the memory cell MC in the corresponding column.

[0098] For example, the gate 110 of transistor 100 may be connected to word line WL, the drain to bit line BL, and the source to capacitor 1200. The voltage signal on word line WL can control the transistor 100 to turn on or off, thereby reading data information stored in capacitor 1200 through bit line BL, or writing data information into capacitor 1200 for storage through bit line BL.

[0099] Figure 6 This is a flowchart of a method 1000 for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0100] like Figure 6 As shown, a method 1000 for manufacturing a semiconductor structure may include: S1100, forming a capacitor hole penetrating a mask layer and a stacked structure along a first direction, wherein the mask layer is located on one side of the stacked structure in the first direction; S1200, forming a first electrode layer within the capacitor hole, wherein the first electrode layer extends along the first direction and contacts the mask layer and the stacked structure; S1300, forming a support portion located on the side of the mask layer opposite to the stacked structure and in contact with the first electrode layer; and S1400, forming a capacitor dielectric layer covering at least a portion of the first electrode layer and a second electrode layer covering at least a portion of the capacitor dielectric layer. Steps S1100 to S1400 will be described in detail below.

[0101] Figure 7 This is a partial structural schematic diagram of the transistor 100, capacitor contact structure 200, stacked structure 1100 and mask layer 300 provided according to an exemplary embodiment of the present disclosure.

[0102] Exemplarily, a transistor 100 may be formed; and a capacitive contact structure 200 may be formed on one side of the transistor 100. The capacitive contact structure 200 may contact the transistor 100 to facilitate the subsequent formation of a first electrode layer 1210. Figure 9 It can be connected to the transistor 100 through the capacitive contact structure 200.

[0103] For example, transistor 100 may be a vertical transistor such as a vertical metal-oxide-semiconductor field-effect transistor, so as to facilitate the subsequent formation of capacitor 1200 (including a first electrode layer 1210, a second electrode layer 1230 and a capacitor dielectric layer 1220) on one side of transistor 100 along the first direction Z. Figure 19 The material of the capacitive contact structure 200 may include one or more of tungsten, molybdenum, copper, aluminum, ruthenium, titanium, titanium nitride, polysilicon, indium tin oxide, metal silicides (e.g., titanium silicides, cobalt silicides, nickel-platinum silicides) or any other suitable conductive material.

[0104] For example, such as Figure 7 As shown, a stacked structure 1100 comprising a support layer 1110 and a sacrificial layer 1120 alternately stacked along the first direction Z can be formed on one side of the capacitor contact structure 200, wherein the stacking direction D of the stacked structure 1100 may be opposite to the first direction Z. The transistor 100, the capacitor contact structure 200, and the stacked structure 1100 may be sequentially distributed along the first direction Z.

[0105] like Figure 7 As shown, both ends of the stacked structure 1100 in the first direction Z can be support layers 1110, and the number of support layers 1110 can be greater than the number of sacrificial layers 1120. For example, the multiple support layers may include a first support layer 1111, a second support layer 1112, and a third support layer 1113 sequentially distributed along the first direction Z, wherein the first support layer 1111 and the third support layer 1113 may be located at opposite ends of the stacked structure 1100 in the first direction Z. In other words, the first support layer 1111 and the third support layer 1113 may be material layers at opposite ends of the stacked structure 1100. Compared to the first support layer 1111, the third support layer 1113 may be closer to the transistor 100. The multiple sacrificial layers 1120 may include a first sacrificial layer 1121 located between the third support layer 1113 and the second support layer 1112, and a second sacrificial layer 1122 located between the second support layer 1112 and the first support layer 1111.

[0106] It should be understood that the limitation on the number of support layer 1110 and sacrificial layer 1120 in this application is merely an example and not an explicit limitation. In actual processes, the number can be determined according to the subsequently formed capacitor 1200 ( Figure 19 The required height should be reasonably set for the number of support layers 1110 and sacrificial layers 1120.

[0107] For example, the stacked structure 1100 can be formed by alternately stacking the support layer 1110 and the sacrificial layer 1120 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. For example, the stacked structure 1100 can be formed by sequentially stacking the third support layer 1113, the first sacrificial layer 1121, the second support layer 1112, the second sacrificial layer 1122, and the first support layer 1111.

[0108] For example, the distance between adjacent support layers 1110 in the first direction Z can be greater than 300 nm. For instance, the distance between the second support layer 1112 and the third support layer 1113 in the first direction Z can be greater than 300 nm, such as approximately 510 nm. The distance between the first support layer 1111 and the second support layer 1112 in the first direction Z can be greater than 300 nm, such as approximately 400 nm. In other words, the dimensions of both the first sacrificial layer 1121 and the second sacrificial layer 1122 in the first direction Z can be greater than 300 nm.

[0109] For example, the material of the support layer 1110 may include any one or any combination of two or more of silicon nitride, silicon oxynitride, and aluminum oxide. Furthermore, the support layer 1110 may be doped with boron or carbon. The material of the sacrificial layer 1120 may include any one or any combination of two or more of silicon oxide, silicon oxynitride, and polycrystalline silicon. The material of the sacrificial layer 1120 may be different from the material of the support layer 1110 to achieve different etching rates in the same etching process and in the same etchant. For example, in the same etching process and in the same etchant, the etching (e.g., corrosion) rate of the sacrificial layer 1120 may be much greater than the etching rate of the support layer 1110, so that when most of the sacrificial layer 1120 is removed, the support layer 1110 is almost completely retained or only a small portion is removed. For example, the material of the sacrificial layer 1120 may be silicon oxide, and the material of the support layer 1110 may be silicon nitride. Subsequently, a wet etching process can be used to remove the sacrificial layer 1120 while retaining most of the support layer 1110. The etching solution used in the wet etching process may include at least one of hydrofluoric acid solution and hydrofluoric acid ammonia solution.

[0110] For example, such as Figure 7As shown, a mask layer 300 can be formed on one side of the stacked structure 1100 along the first direction Z. Exemplarily, the mask layer 300 can be formed on the first support layer 1111. The dimension h1 of the mask layer 300 in the first direction Z can be large, for example, greater than 100 nm. The mask layer 300 may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. For example, the mask layer 300 may include polycrystalline silicon. Exemplarily, the mask layer 300 can be formed by one or more thin-film deposition processes.

[0111] Figure 8 This is a partial structural schematic diagram of the capacitor hole 400 after its formation according to an exemplary embodiment of the present disclosure. Exemplarily, a capacitor hole 400 can be formed that penetrates the mask layer 300 and the stacked structure 1100 along the first direction Z.

[0112] Exemplarily, a patterned mask (not shown) with an array of windows can be formed on the mask layer 300. The patterned mask is used to mask the etching of the mask layer 300 and the stacked structure 1100 to form capacitor holes 400 corresponding to the windows. The windows may correspond to the capacitor contact structure 200 along a first direction Z, so that the capacitor holes 400 can extend along the first direction Z to the capacitor contact structure 200. Exemplarily, the capacitor holes 400 may have a cylindrical shape extending along the first direction Z. Multiple capacitor holes 400 may be arrayed on a plane formed by a second direction X and a third direction Y.

[0113] For example, the mask layer 300 and the stacked structure 1100 can be etched using a dry etching process, a wet etching process, or a combination of dry etching and wet etching processes to form a capacitor hole 400 that penetrates the mask layer 300 and the stacked structure 1100 along the first direction Z and extends to the capacitor contact structure 200.

[0114] It should be noted that in the etching process to form the capacitor hole 400, a portion of the mask layer 300 is consumed. For example, a portion of the mask layer 300 material near the capacitor hole 400 is consumed, resulting in a reduction in the dimension of the portion of the mask layer 300 near the capacitor hole 400 in the first direction Z. For example, as... Figure 8 As shown, the dimension h1 of the portion of the mask layer 300 facing away from the capacitor hole 400 in the second direction X in the first direction Z (such as at least one end of the mask layer 300 in the second direction X, where no capacitor hole 400 is provided) can be greater than the dimension h2 of the portion of the mask layer 300 in the second direction X that is close to the capacitor hole 400 in the first direction Z.

[0115] Figure 9This is a schematic diagram of the structure after forming the first electrode layer 1210 according to an exemplary embodiment of the present disclosure. Exemplarily, the first electrode layer 1210 may be formed within the capacitor hole 400. The first electrode layer 1210 may extend along a first direction Z and contact the mask layer 300 and the stacked structure 1100. Exemplarily, the first electrode layer 1210 may extend along the first direction Z to the capacitor contact structure 200.

[0116] Exemplarily, a first electrode layer 1210 can be formed on the sidewalls and bottom of the capacitor aperture 400 by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. It should be understood that during the formation of the first electrode layer 1210 on the sidewalls and bottom of the capacitor aperture 400, the first electrode layer 1210 will inevitably also be formed on the mask layer 300. Therefore, as... Figure 10 As shown, a portion of the first electrode layer 1210 located on the mask layer 300 can be removed by chemical mechanical polishing or etching, while retaining the first electrode layer 1210 located on the sidewalls and bottom of the capacitor hole 400.

[0117] In one exemplary embodiment of this application, such as Figure 10 As shown, the first electrode layer 1210 may include a conductive layer 1211, wherein the portion of the conductive layer 1211 that contacts the plurality of support layers 1110 is continuous in the second direction X. For example, the first electrode layer 1210 may be formed by completely filling the conductive layer 1211 within the capacitor hole 400.

[0118] It should be noted that in the actual process, the sacrificial gap 700 is subsequently formed by removing the sacrificial layer 1120 and part of the support layer 1110. Figure 18 During the process, part of the first electrode layer 1210 may be removed. At this time, the first electrode layer 1210 may be part of a cylindrical structure (not shown) and extend along the first direction Z.

[0119] Exemplarily, the material of the conductive layer 1211 may include at least one of a metal, a metal compound, and a semiconductor material. For example, the material of the conductive layer 1211 may include a compound formed from one or two of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride, etc. Exemplarily, the material of the conductive layer 1211 may be titanium nitride.

[0120] In this disclosure, by setting the first electrode layer 1210 to contact the mask layer 300 and the stacked structure 1100, it is beneficial to ensure that the sum of the dimensions of the mask layer 300 and the stacked structure 1100 in the first direction Z, the dimension of the capacitor hole 400 in the first direction Z, and the dimension of the first electrode layer 1210 in the first direction Z are approximately the same. This is beneficial to maximize the dimension of the first electrode layer 1210 in the first direction Z while ensuring that the etching depth of the capacitor hole 400 (i.e., the dimension of the capacitor hole 400 in the first direction Z) is constant. This, in turn, is beneficial to increase the dimension of the subsequently formed capacitor 1200 (including the first electrode layer 1210, the second electrode layer 1230, and the capacitor dielectric layer 1220) in the first direction Z, thereby increasing the effective capacitance area of ​​the capacitor 1200.

[0121] In another exemplary embodiment of this application, reference may be made to Figure 3 The first electrode layer 2210 may include a conductive layer 2211 and a dielectric layer 2212. The conductive layer 2211 may extend along a first direction Z and contact a plurality of support layers 1110. The dielectric layer 2212 may be located on the side of the conductive layer 2211 opposite to the support layers 1110 and extend along the first direction Z, that is, the conductive layer 2211 may surround the dielectric layer 2212.

[0122] For example, the material of dielectric layer 2212 includes doped nitride. The material of dielectric layer 2212 may be different from the materials of mask layer 300 and sacrificial layer 1120 to give a certain etching selectivity among dielectric layer 2212, mask layer 300 and sacrificial layer 1120, so that when mask layer 300 and sacrificial layer 1120 are subsequently removed, dielectric layer 2212 is almost completely retained or a small portion is removed.

[0123] Figure 11 This is a schematic diagram of the structure after forming a groove 500 according to an exemplary embodiment of the present disclosure. Exemplarily, a portion of the mask layer 300 facing away from the stacked structure 1100 can be removed along the first direction Z to form the groove 500. For example, a portion of the mask layer 300 can be removed along the first direction Z on the side of the mask layer 300 facing away from the stacked structure 1100, so that the first electrode layer 1210 protrudes from the mask layer 300 on the side of the mask layer 300 facing away from the stacked structure 1100. Exemplarily, at least one of processes such as dry etching and wet etching can be used to form the groove 500.

[0124] Figure 12This is a schematic diagram of the structure after forming the support portion 1300 according to an exemplary embodiment of the present disclosure. Exemplarily, the support portion 1300 may be formed within the groove 500. Exemplarily, the support portion 1300 covering a portion of the first electrode layer 1210 may be formed on the side of the mask layer 300 opposite to the stacked structure 1100. In other words, the support portion 1300 may be formed on the groove 500 and the mask layer 300. Exemplarily, the support portion 1300 may have a comb-like structure, which may cover a portion of the first electrode layer 1210.

[0125] It should be noted that, as Figure 8 As shown, since the dimension h1 of at least one end of the mask layer 300 in the second direction X (such as the position where the capacitor hole 400 is not provided) in the first direction Z is greater than the dimension h2 of the portion of the mask layer 300 near the capacitor hole 400 in the second direction X, at least one end of the support portion 1300 in the second direction X (such as the end in the second direction X away from the first electrode layer 1210) can be warped toward the side away from the mask layer 300 (or support layer 1110).

[0126] For example, such as Figure 12 As shown, the distance H1 between at least one end of the support portion 1300 in the second direction X (e.g., where the capacitor hole 400 is not provided) and the adjacent support layer (e.g., the first support layer 1111) in the first direction Z can be greater than the distance H2 between the support portion 1300 and the first electrode layer 1210 in the first direction Z and the first support layer 1111. For example, the distance H2 between the support portion 1300 and the first electrode layer 1210 in the first direction Z and the first support layer 1111 can be less than 200 nm.

[0127] For example, such as Figure 12 As shown, the support portion 1300 may include a recessed portion 1310 and a warped portion 1320. The recessed portion 1310 may be opposite to the first electrode layer 1210 along a first direction Z and may extend along a second direction X. The warped portion 1320 may be located on at least one side of the recessed portion 1310 in the second direction X and warped toward the side opposite to the support layer 1110 (such as the first support layer 1111). For example, the recessed portion 1310 may be the central portion of the support portion 1300, and the warped portion 1320 may be the edge portion of the support portion 1300. For example, the distance H3 between the end face of the warped portion 1320 away from the support layer 1110 (such as the first support layer 1111) in the first direction Z and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z can be greater than the distance H4 between the end face of the recessed portion 1310 away from the support layer 1110 (such as the first support layer 1111) in the first direction Z and the adjacent support layer 1110 (such as the first support layer 1111) in the first direction Z.

[0128] Exemplarily, the support portion 1300 and the sacrificial layer 1120 may comprise different materials to achieve different etching rates in the same etching process and etchant. The material of the support portion 1300 may comprise at least one of semiconductor materials and insulating materials. For example, the material of the support portion 1300 may comprise any one or any combination of two or more of silicon nitride, silicon oxynitride, aluminum oxide, polysilicon, etc. Furthermore, the support portion 1300 may be doped with at least one of carbon, boron, and phosphorus. Exemplarily, the material of the support portion 1300 may be, for example, doped silicon nitride. For example, the support portion 1300 may comprise carbon-doped silicon nitride to increase the etching selectivity ratio of the support portion 1300 and the sacrificial layer 1120. In the same etching process and etchant, the etching (e.g., corrosion) rate of the sacrificial layer 1120 may be much greater than the etching rate of the support portion 1300, such that when most of the sacrificial layer 1120 is removed, the support portion 1300 is almost completely retained or only a small portion is removed. Exemplarily, the support portion 1300 and the support layer 1110 may comprise the same material. Exemplarily, the support portion 1300 may be formed by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0129] In this disclosure, the support portion 1300 can subsequently form a sacrificial gap 700 ( Figure 18 In the process of forming the first electrode layer 1210, the support 1300 can play a supporting role, reducing the risk of deformation such as bending. In addition, the formed support 1300 can have a comb-like structure, which is beneficial to improving the mechanical strength and stability of the structure after the formation of the sacrificial gap 700, and thus improving the stability of the final semiconductor structure.

[0130] It should be noted that, Figure 11 and Figure 12 The illustrated embodiment of the support portion 1300 is merely an example and not a specific limitation. In another embodiment of this disclosure, see [reference needed]. Figure 2 or Figure 4 The support portion 2300 may include: Figure 10 A support portion 2300 is formed on the side of the mask layer 300 opposite to the stacked structure 1100, wherein the support portion 2300 contacts the end of the first electrode layer 1210 in the first direction Z. Exemplarily, the portion of the first electrode layer 1210 in the mask layer 300 has a small dimension in the first direction Z, such as less than 200 nm. In the subsequent process of forming the sacrificial gap 700 by removing the mask layer 300, the risk of deformation, such as bending, of the portion of the first electrode layer 1210 in the mask layer 300 is low; therefore, the support portion 2300 can be located on the side of the first electrode layer 1210 in the first direction Z.

[0131] Figure 13This is a schematic diagram of the structure after forming a patterned mask layer 600 according to an exemplary embodiment of the present disclosure. Figure 14 This is a schematic diagram of the structure after forming the first opening 710 according to an exemplary embodiment of the present disclosure. Exemplarily, a patterned mask layer 600 may be formed on the side of the support portion 1300 opposite to the mask layer 300. The patterned mask layer 600 may include an array of windows 610, and the patterned mask layer 600 may subsequently form the first opening 710 in the support portion 1300 to mask out the portion that has been removed.

[0132] Specifically, such as Figure 13 As shown, a hard mask layer 620 (such as a polysilicon hard mask layer) and other material layers 630 (such as photoresist layers and anti-reflective layers) can be formed on the support portion 1300 as material layers for the patterned mask layer 600. Then, a photolithography process can be used to pattern the other material layers 630 (such as photoresist layers) to obtain a patterned mask layer 600 with windows 610, wherein the windows 610 can be located between adjacent first electrode layers 1210 along the first direction Z. Subsequently, the other material layers 630 can be used to mask and etch the hard mask layer 620 and the support portion 1300 to form a first opening 710. Figure 14 As shown, the mask layer 300 can be exposed through the first opening 710. Exemplarily, the first opening 710 can be formed using processes such as photolithography or dry etching. Exemplarily, after the first opening 710 is formed, other material layers 630 can be removed.

[0133] Figure 15 This is a schematic diagram of the structure after removing the hard mask layer 620 and the mask layer 300 according to an exemplary embodiment of this disclosure. Exemplarily, the hard mask layer 620 may include the same material as the mask layer 300, such as polysilicon. The hard mask layer 620 is exposed after removing other material layers 630, and the mask layer 300 is exposed after forming the first opening 710. Exemplarily, the mask layer 300 can be removed via the first opening 710 using a process such as wet etching. It should be understood that the hard mask layer 620 can be removed simultaneously during the process of removing the mask layer 300.

[0134] For example, the thickness of the portion of the support 1300 located on one side of the first electrode layer 1210 in the first direction Z can be relatively large, such as greater than the thickness of the first support layer 1111, the second support layer 1112, or the third support layer 1113. This is because the second opening 720 is formed... Figure 16 ) and the third opening 730 ( Figure 18 In the process of etching, a portion of the support portion 1300 will be removed. Therefore, in order to reduce the risk of the support portion 1300 being etched through during subsequent etching and to ensure sufficient support strength at the support portion 1300, the portion of the support portion 1300 located on one side of the first electrode layer 1210 in the first direction Z may be configured to have a relatively large thickness.

[0135] Figure 16 This is a schematic diagram of the structure after forming the second opening 720 according to an exemplary embodiment of the present disclosure. Figure 17 This is a schematic diagram of the structure after removing the second sacrificial layer 1122 according to an exemplary embodiment of this disclosure. Exemplarily, a portion of the first support layer 1111 can be removed to form a second opening 720, through which the second sacrificial layer 1122 can be exposed. Exemplarily, the second opening 720 can be formed using processes such as photolithography or dry etching, and the second sacrificial layer 1122 can be removed through the second opening 720 using processes such as wet etching.

[0136] Figure 18 This is a schematic diagram of the structure after forming the third opening 730 and removing the first sacrificial layer 1121 according to an exemplary embodiment of this disclosure. Exemplarily, a portion of the second support layer 1112 may be removed to form the third opening 730, wherein the first sacrificial layer 1121 may be exposed through the third opening 730. Exemplarily, the third opening 730 may be formed using processes such as photolithography or dry etching, and the first sacrificial layer 1121 may be removed through the third opening 730 using processes such as wet etching.

[0137] For example, the second opening 720 and the third opening 730 can be opened in a manner similar to that of the first opening 710, and the third opening 730, the second opening 720, and the first opening 710 can be correspondingly arranged along a first direction Z. One second opening 720 and one third opening 730 can simultaneously expose multiple first electrode layers 1210. For example, one second opening 720 and one third opening 730 can expose four first electrode layers 1210.

[0138] It should be noted that during the processes of forming the second opening 720 and the third opening 730, and removing the second sacrificial layer 1122 and the first sacrificial layer 1121, a portion of the first electrode layer 1210 may be removed, making the first electrode layer 1210 part of a cylindrical structure. In other words, one second opening 720 and one third opening 730 may overlap with multiple first electrode layers 1210 simultaneously. For example, one second opening 720 and one third opening 730 may overlap with four first electrode layers 1210.

[0139] For example, such as Figure 18As shown, the space formed by the third opening 730, the second opening 720, the first opening 710, and the removal of the mask layer 300 and the sacrificial layer 1120 (such as the second sacrificial layer 1122 and the first sacrificial layer 1121) can be used to form the sacrificial gap 700. In other words, the sacrificial gap 700 may include the third opening 730, the second opening 720, the first opening 710, and the space formed by removing the mask layer 300 and the sacrificial layer 1120 (such as the second sacrificial layer 1122 and the first sacrificial layer 1121). It should be understood that in the process of forming the sacrificial gap 700, a portion of the first electrode layer 1210 may be removed, making the first electrode layer 1210 part of a cylindrical structure. Furthermore, when the sacrificial layer 1120 and the support layer 1110 are other numbers or more material layers, they can be removed by forming openings and wet etching processes, in a similar manner.

[0140] In this disclosure, some of the support portions 1300 and some of the support layers 1110 (such as the third support layer 1113, some of the second support layer 1112, and some of the first support layer 1111 located below the sacrificial layer 1120) are not removed. The remaining portions of the support layers 1110 and 1300 can provide support during the removal of the sacrificial layer 1120, thereby improving the subsequent formation of the capacitor 1200 (including the first electrode layer 1210, the dielectric layer 1220, and the second electrode layer 1230). Figure 19 The mechanical strength of the structure is improved to reduce damage to capacitor 1200 during subsequent processes (such as grinding).

[0141] Figure 19 This is a schematic diagram of the structure after forming a capacitor dielectric layer 1220, a second electrode layer 1230, and a conductive structure 1400 according to an exemplary embodiment of this disclosure. Exemplarily, a capacitor dielectric layer 1220 covering at least a portion of the first electrode layer 1210 and a second electrode layer 1230 covering at least a portion of the capacitor dielectric layer 1220 can be formed.

[0142] For example, a capacitor dielectric layer 1220 covering at least a portion of the first electrode layer 1210 and a second electrode layer 1230 covering at least a portion of the capacitor dielectric layer 1220 may be formed within the sacrificial gap 700. For instance, the capacitor dielectric layer 1220 may be formed via the sacrificial gap 700 on the exposed sidewalls of the first electrode layer 1210, the support portion 1300, and the support layer 1110, as well as on one side of the support portion 1300 along the first direction Z.

[0143] Exemplarily, the material of the capacitor dielectric layer 1220 may include a high dielectric constant material. For example, the material of the capacitor dielectric layer 1220 may include, but is not limited to, at least one or a combination of aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconate, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide and / or praseodymium oxide.

[0144] For example, such as Figure 19 As shown, a second electrode layer 1230 covering at least a portion of the capacitor dielectric layer 1220 can be formed within the sacrificial gap 700 to facilitate the formation of the capacitor 1200. The capacitor 1200 may include a first electrode layer 1210, a capacitor dielectric layer 1220, and a second electrode layer 1230. For example, the second electrode layer 1230 can be formed via the sacrificial gap 700 on the exposed sidewall of the capacitor dielectric layer 1220 and on one side of the capacitor dielectric layer 1220 along the first direction Z.

[0145] Exemplarily, the material of the second electrode layer 1230 may include at least one of a metal, a metal compound, and a semiconductor material. For example, the material of the second electrode layer 1230 may include a compound formed from one or two of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride, etc. Furthermore, the material of the second electrode layer 1230 may also include a stack formed from one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polycrystalline silicon, P-type polycrystalline silicon, or two or more materials from the group consisting of the above materials.

[0146] For example, such as Figure 19 As shown, a conductive structure 1400 can be formed. The conductive structure 1400 is located on the side of the second electrode layer 1230 away from the capacitor dielectric layer 1220. The material of the conductive structure 1400 includes a conductive material.

[0147] Exemplarily, a conductive structure 1400 may be formed in the remaining space of the sacrificial gap 700 and on one side of the second electrode layer 1230 along the first direction Z, such that the conductive structure 1400 covers the entire second electrode layer 1230. Exemplarily, the conductive structure 1400 may have multiple insulating gaps to alleviate structural stress.

[0148] Exemplarily, the material of the conductive structure 1400 may include conductive materials such as doped semiconductor materials. For example, the material of the conductive structure 1400 may include boron-doped germanium silicon. Exemplarily, the conductive structure 1400 may be connected to other conductive structures (not shown) to enable the connection of the capacitor 1200 to other conductive structures such as peripheral circuits.

[0149] For example, the capacitor dielectric layer 1220, the second electrode layer 1230, and the conductive structure 1400 can be sequentially deposited using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Furthermore, the conductive structure 1400 can also be doped using a doping process.

[0150] Figure 20 This is a partial structural schematic diagram of a semiconductor structure formed according to an exemplary embodiment of the present disclosure.

[0151] For example, the semiconductor structure formed during manufacturing may include a memory device with storage functionality. For instance... Figure 20 As shown, the storage device may include storage cells MC and word lines WL and bit lines BL coupled to the storage cells MC. Exemplarily, the storage device may include at least one of dynamic random access memory (DRAM), phase-change memory (PCM), and ferroelectric random access memory (FRAM). For ease of description, the following description primarily uses DRAM memory as an example.

[0152] The memory cell MC may include DRAM cells and may be arrayed along a second direction X and a third direction Y. Each DRAM cell may include a capacitor 1200 for storing bits of data as positive or negative charges and one or more transistors 100 (also known as via transistors) for controlling (e.g., switching and selecting) access to it. Exemplarily, the transistor 100 may be a vertical transistor such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) to facilitate the subsequent formation of a capacitor 1200 on one side of the transistor 100 along the first direction Z.

[0153] Word lines WL can be coupled to memory cells MC along a third direction Y to control the switching of vertical transistors 100 in memory cells MC located in a row along the third direction Y. Bit lines BL can be coupled to memory cells MC along a second direction X to send data to and / or receive data from memory cells MC in a column along the second direction X. That is, each word line WL can be coupled to the memory cell MC in the corresponding row and each bit line BL can be coupled to the memory cell MC in the corresponding column.

[0154] For example, the gate 110 of transistor 100 may be connected to word line WL, the drain to bit line BL, and the source to capacitor 1200. The voltage signal on word line WL can control the transistor 100 to turn on or off, thereby reading data information stored in capacitor 1200 through bit line BL, or writing data information into capacitor 1200 for storage through bit line BL.

[0155] Figures 21 to 29This is a process step diagram for forming a semiconductor structure according to another exemplary embodiment of this disclosure. For the purpose of brevity, Figures 6 to 20 The illustrated implementation method and Figures 21 to 29 The same content as the embodiments shown will not be repeated here.

[0156] For example, such as Figure 21 As shown, the semiconductor structure may include a transistor 100 extending along a first direction Z and a capacitor contact structure 200 located on one side of the transistor 100, wherein the capacitor contact structure 200 may contact the transistor 100.

[0157] Exemplarily, a stacked structure 1100 may be formed on one side of the capacitive contact structure 200. Exemplarily, the stacked structure 1100 may include alternately stacked support layers 1110 and sacrificial layers 1120. The plurality of support layers may include a first support layer 1111, a second support layer 1112, and a third support layer 1113 sequentially distributed along a first direction Z, wherein the first support layer 1111 and the third support layer 1113 may be located at opposite ends of the stacked structure 1100 along the first direction Z. The plurality of sacrificial layers 1120 may include a first sacrificial layer 1121 located between the third support layer 1113 and the second support layer 1112, and a second sacrificial layer 1122 located between the second support layer 1112 and the first support layer 1111. The transistor 100, the capacitive contact structure 200, and the stacked structure 1100 may be distributed adjacent to each other along the first direction Z.

[0158] For example, such as Figure 21 As shown, a mask layer 810 can be formed on one side of the stacked structure 1100 along the first direction Z; and a capacitor via 820 can be formed along the first direction Z, penetrating the mask layer 810 and the stacked structure 1100. For example, as... Figure 22 As shown, the mask layer 810 can be removed after the capacitor hole 820 is formed.

[0159] For example, such as Figure 23 As shown, a first electrode layer 4210 can be formed on the sidewall of the capacitor hole 820. It should be understood that during the process of forming the first electrode layer 4210 on the sidewall of the capacitor hole 820, the first electrode layer 4210 will inevitably also be formed on the support layer 1110 (such as the first support layer 1111). Therefore, as... Figure 24 As shown, chemical mechanical polishing or etching processes can also be used to remove part of the first electrode layer 4210 located on the first support layer 1111, while retaining the first electrode layer 4210 located on the sidewall of the capacitor hole 820.

[0160] For example, such as Figure 25As shown, a dielectric layer 4211 can be formed in the remaining space of the capacitor hole 820. It should be understood that during the process of forming the dielectric layer 4211 in the remaining space of the capacitor hole 820, a dielectric layer 4211 will inevitably also be formed on the support layer 1110 (such as the first support layer 1111).

[0161] For example, such as Figure 25 As shown, a patterned mask layer 830 can be formed on one side of the support layer 1110 (such as the first support layer 1111) along the first direction Z. The patterned mask layer 830 may include an array of windows 831, and the patterned mask layer 830 can subsequently form a first opening 841 for masking and removing a portion of the first support layer 1111. Figure 26 For example, after the first opening 841 is formed, the patterned mask layer 830 can be removed.

[0162] For example, such as Figure 26 As shown, a portion of the first support layer 1111 can be removed to form a first opening 841, through which the second sacrificial layer 1122 can be exposed. Figure 27 As shown, the second sacrificial layer 1122 can be removed through the first opening 841.

[0163] For example, such as Figure 28 As shown, a portion of the second support layer 1112 can be removed to form a second opening 842, through which the first sacrificial layer 1121 can be exposed. Exemplarily, the second opening 842 can be formed using processes such as photolithography or dry etching, and the first sacrificial layer 1121 can be removed through the second opening 842 using processes such as wet etching. The space formed by the second opening 842, the first opening 841, and the removal of the sacrificial layer 1120 (such as the second sacrificial layer 1122 and the first sacrificial layer 1121) can be used to form a sacrificial gap 840. In other words, the sacrificial gap 840 can include the second opening 842, the first opening 841, and the space formed by removing the sacrificial layer 1120 (such as the second sacrificial layer 1122 and the first sacrificial layer 1121).

[0164] For example, such as Figure 29 As shown, a capacitor 4200 (including the first electrode layer 4210, the capacitor dielectric layer 4220, and the second electrode layer 4230 covering at least a portion of the first electrode layer 4210) can be formed within the sacrificial gap 840.

[0165] For example, such as Figure 29 As shown, a conductive layer 4300 may also be formed on the side of the second electrode layer 4230 away from the capacitor dielectric layer 4220.

[0166] Since the content and structure described above regarding the semiconductor structure are wholly or partially applicable to the method 1000 for manufacturing the semiconductor structure described herein, related or similar content will not be repeated here.

[0167] Although exemplary structures and fabrication methods of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the fabrication methods of the semiconductor structure. Furthermore, the layers and materials described are merely exemplary.

[0168] Figure 30 This is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of this disclosure.

[0169] System 10 can be a mobile phone, desktop computer, laptop, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 12 located therein). Figure 30 As shown, system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more semiconductor structures (such as including 3D memory 14) and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from 3D memory 14.

[0170] The three-dimensional memory 14 may include the semiconductor structure described in any embodiment of this disclosure. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and a host 18 and is configured to control the three-dimensional memory 14. The controller 16 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. For example, the controller 16 may communicate with an external device (e.g., the host 18) according to a specific communication protocol.

[0171] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A semiconductor structure, comprising: Multiple support layers are arranged at intervals in the first direction; A first electrode layer extends along the first direction and contacts the plurality of support layers; Second electrode layer; as well as A capacitor dielectric layer, a portion of which is located between the first electrode layer and the second electrode layer; The semiconductor structure further includes: The support portion is located on one side of the plurality of support layers in the first direction and is in contact with the first electrode layer.

2. The semiconductor structure according to claim 1, wherein, At least one end of the support portion in the second direction is warped toward the side opposite to the support layer; The first direction and the second direction intersect.

3. The semiconductor structure according to claim 2, wherein, The distance between at least one end of the support portion in the second direction and the adjacent support layer in the first direction is greater than the distance between the portion of the support portion that contacts the first electrode layer and the adjacent support layer in the first direction.

4. The semiconductor structure according to claim 3, wherein, The distance between the portion of the support that contacts the first electrode layer and the adjacent support layer in the first direction is less than 200 nm.

5. The semiconductor structure according to claim 4, wherein, The support portion contacts the end of the first electrode layer in the first direction; and / or The support portion contacts the sidewall of the first electrode layer on a plane intersecting the first direction.

6. The semiconductor structure according to any one of claims 1-5, wherein, The distance between adjacent support layers in the first direction is greater than 300 nm.

7. The semiconductor structure according to any one of claims 1-5, wherein, In the first direction, a portion of the second electrode layer is located between the support portion and the support layer, and a portion of the second electrode layer is located between adjacent support layers.

8. The semiconductor structure according to any one of claims 1-5, wherein, The plurality of support layers include: A first support layer extends along a second direction and is less than 200 nm away from the support portion in the first direction; A second support layer is located on one side of the first support layer in the first direction and extends along the second direction, and the distance between the second support layer and the first support layer in the first direction is greater than 300 nm; and The third support layer is located on the side of the second support layer opposite to the first support layer and extends along the second direction, and the distance between the third support layer and the second support layer in the first direction is greater than 300 nm. The first direction and the second direction intersect.

9. The semiconductor structure according to any one of claims 1-5, wherein, The support portion and the support layer are made of the same material.

10. The semiconductor structure according to any one of claims 1-5, wherein, The first electrode layer includes: A conductive layer, wherein the portion of the conductive layer in contact with the plurality of support layers is continuous in a second direction; The first direction and the second direction intersect.

11. The semiconductor structure according to any one of claims 1-5, wherein, The first electrode layer includes: A conductive layer extending along the first direction and in contact with the plurality of support layers; and A dielectric layer is located on the side of the conductive layer opposite to the support layer and extends along the first direction. The material of the dielectric layer includes doped nitrides.

12. The semiconductor structure according to any one of claims 1-5, wherein, The semiconductor structure also includes: A conductive structure is located on the side of the second electrode layer opposite to the capacitor dielectric layer, and the material of the conductive structure includes a conductive material.

13. The semiconductor structure according to any one of claims 1-5, wherein, The semiconductor structure also includes: transistors; and A capacitive contact structure is located on one side of the transistor; The first electrode layer extends along the first direction to the capacitor contact structure.

14. A method for manufacturing a semiconductor structure, comprising: A capacitive aperture is formed that penetrates the mask layer and the stacked structure along a first direction, wherein the mask layer is located on one side of the stacked structure in the first direction; A first electrode layer is formed within the capacitor hole, wherein the first electrode layer extends along the first direction and contacts the mask layer and the stacked structure; A support portion is formed, the support portion being located on the side of the mask layer opposite to the stacked structure and in contact with the first electrode layer; as well as A capacitor dielectric layer covering at least a portion of the first electrode layer and a second electrode layer covering at least a portion of the capacitor dielectric layer are formed.

15. The method according to claim 14, wherein, Forming a capacitor aperture penetrating the mask layer and the stacked structure along a first direction includes: A stacked structure is formed comprising a support layer and a sacrificial layer that are alternately stacked along the first direction, wherein both ends of the stacked structure in the first direction are the support layers; The mask layer is formed on one side of the stacked structure along the first direction; and The capacitor aperture is formed, penetrating the mask layer and the stacked structure along the first direction.

16. The method of claim 14, wherein, The supporting structure includes: Removing a portion of the mask layer away from the stacked structure along the first direction forms a groove; and The support portion is formed within the groove.

17. The method of claim 14, wherein, The formation of the support portion includes: forming the support portion on the side of the mask layer opposite to the stacked structure, wherein the support portion contacts the end of the first electrode layer in the first direction.

18. The method according to claim 15, wherein, Forming a capacitor dielectric layer covering at least a portion of the first electrode layer and a second electrode layer covering at least a portion of the capacitor dielectric layer, comprising: Remove the remaining mask layer and the sacrificial layer to form a sacrificial gap; and A capacitor dielectric layer covering at least a portion of the first electrode layer and a second electrode layer covering at least a portion of the capacitor dielectric layer are formed within the sacrificial gap.

19. The method according to claim 18, wherein, Removing the remaining mask layer and the sacrificial layer to form a sacrificial gap includes: Remove a portion of the support along the first direction to expose the mask layer; Remove the remaining mask layer to expose the support layer; Removing a portion of the support layer along the first direction to expose the sacrificial layer; and The sacrificial layer is removed to form the sacrificial gap.

20. The method according to any one of claims 14-19, wherein, The method further includes: A conductive structure is formed, the conductive structure being located on the side of the second electrode layer opposite to the capacitor dielectric layer, and the material of the conductive structure includes a conductive material.

21. The method according to any one of claims 14-19, wherein, The method further includes: Forming transistors; and A capacitive contact structure is formed on one side of the transistor; The first electrode layer extends along the first direction to the capacitor contact structure.

22. A storage system, comprising: The semiconductor structure as described in any one of claims 1-13; as well as A controller, coupled to the semiconductor structure, is used to control the semiconductor structure to store data.

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