Memory and electronic equipment

Abstract

The invention discloses a memory and electronic equipment. The memory includes a word line, a bit line, and a memory cell including a first transistor and a data storage node, the first transistor including a gate electrode, an active layer, a source electrode, and a drain electrode. The grid electrode is coupled with the word line, the active layer surrounds the grid electrode, the material of the active layer is an oxide semiconductor, the source electrode and the active layer are in Schottky contact, the source electrode is coupled with the bit line, the drain electrode and the active layer are in ohmic contact, and the drain electrode is coupled with the data storage node. The memory helps to reduce the off-state leakage current of the first transistor, helps to improve the on-state saturation current of the first transistor in the charging process of the memory unit, and helps to make the first transistor have a small sub-threshold swing.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory and electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a common semiconductor memory widely used in various consumer electronics products, such as computers, mobile phones, and digital cameras. With technological advancements, to increase the storage capacity per unit area, DRAM architecture design has gradually evolved from two-dimensional (2D) to three-dimensional (3D). In 3D DRAM, multiple memory cells can be stacked vertically; each memory cell typically includes an access transistor and a data storage node coupled to the access transistor. For example, one of the source and drain electrodes of the access transistor is connected to the bit line, the other of the source and drain electrodes is connected to the data storage node, and the gate of the transistor is connected to the word line. The data storage node can be a capacitor, or another transistor (also called a read transistor; in this case, the access transistor is also called a write transistor).

[0003] In some 3D DRAM architectures, the access transistors are designed as channel-all-around (CAA) transistors, using oxide semiconductors such as indium gallium zinc oxide (IGZO) as the channel material. Transistors based on amorphous IGZO typically have lower threshold voltages. The configuration of channel-all-around access transistors in these 3D DRAM architectures still requires improvement. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a memory is provided. The memory includes word lines, bit lines, and memory cells. Each memory cell includes a first transistor and a data storage node. The first transistor includes: a gate coupled to the word lines; an active layer surrounding the gate, wherein the active layer is made of an oxide semiconductor; a source electrode having a Schottky contact with the active layer and coupled to the bit lines; and a drain electrode having an ohmic contact with the active layer and coupled to the data storage node.

[0005] In some embodiments, the difference between the work function of the source electrode and the work function of the active layer is not less than 0.3 eV, and the difference between the work function of the drain electrode and the work function of the active layer is less than 0.2 eV.

[0006] In some embodiments, the active layer is an N-type oxide semiconductor layer, the work function of the source electrode is greater than the work function of the active layer, and the work function of the drain electrode is less than or equal to the work function of the active layer.

[0007] In some embodiments, the active layer is made of indium gallium zinc oxide (IGZO), the source electrode is made of molybdenum nitride (MoN), and the drain electrode is made of titanium nitride (TiN).

[0008] In some embodiments, the first transistor further includes a gate dielectric layer disposed between the gate and the active layer.

[0009] In some embodiments, the gate includes a gate pillar extending in a vertical direction, the active layer includes a first portion surrounding the gate pillar, and the source electrode and the drain electrode are spaced apart in the vertical direction.

[0010] In some embodiments, the active layer further includes a second portion and a third portion connected to the first portion, the second portion being located at the bottom of the gate pillar and coupled to the drain electrode, the source electrode being located above the drain electrode, and the third portion being located on the source electrode.

[0011] In some embodiments, the gate includes a gate pillar extending in a vertical direction, the active layer surrounds the gate pillar, and the source electrode and the drain electrode are arranged at intervals in a horizontal direction.

[0012] In some embodiments, the data storage node includes a capacitor; or, the data storage node includes a second transistor, wherein the drain electrode of the first transistor is coupled to the gate of the second transistor.

[0013] According to a second aspect of the present disclosure, an electronic device is provided, including a processor and a memory provided in any embodiment of the present disclosure. The memory is coupled to the processor.

[0014] In the memory provided in the embodiments of this disclosure, the first transistor is a channel-all-around transistor. The source electrode coupled to the bit line and the active layer are connected by a Schottky contact, and the drain electrode coupled to the data storage node and the active layer are connected by an ohmic contact. This forms an asymmetric contact barrier at the source and drain ends of the channel-all-around transistor, which helps to reduce the off-state leakage current of the first transistor. It also helps to increase the on-state saturation current of the first transistor during the charging process of the memory cell. Furthermore, it helps to make the first transistor have a smaller subthrehold swing. As a result, the performance of the first transistor can better meet the charging and discharging requirements of the memory cell. Attached Figure Description

[0015] Figure 1A This is a schematic diagram of a channel-all-around transistor.

[0016] Figure 1B and Figure 1CThis is a schematic diagram of another type of channel all-around transistor.

[0017] Figure 2A This is a schematic diagram of the structure of a memory cell in a memory provided in some embodiments of this disclosure;

[0018] Figure 2B A schematic diagram of the structure of a memory cell in another memory provided in some embodiments of this disclosure;

[0019] Figure 3A and Figure 3B A schematic diagram of the structure of a memory cell in another memory provided in some embodiments of this disclosure;

[0020] Figure 3C and Figure 3D A schematic diagram illustrating the structure of a memory cell in another memory provided in some embodiments of this disclosure;

[0021] Figure 4A and Figure 4B The IV curves of the first transistor under different source and drain electrode material pairings;

[0022] Figure 5 This is a schematic block diagram of the structure of an electronic device provided in some embodiments of this disclosure. Detailed Implementation

[0023] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0024] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0025] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0026] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0027] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0028] In embodiments of this disclosure, the term "coupling" refers to the operative connection of two (or more) conductive structures to each other. Depending on actual needs, this may include, but is not limited to, the following: 1) two conductive structures are directly electrically connected; 2) two conductive structures are indirectly electrically connected (through other conductive structures); 3) although two conductive structures are not electrically connected (e.g., an insulating layer is provided between them), one of the two conductive structures can control the electrical performance of the other two conductive structures in response to an electrical signal, for example, a gate (or word line) is coupled to an active region (or channel region).

[0029] It should be noted that the technical solutions and technical features described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0030] Figure 1A This is a schematic diagram of a channel-all-around transistor. Figure 1A As shown, transistor Ta includes a gate G, a gate dielectric layer GI, an active layer OXS, a source electrode S, and a drain electrode D. The active layer OXS surrounds the gate G, the gate dielectric layer GI is disposed between the gate G and the active layer OXS, and the source electrode S and drain electrode D are respectively contacted and connected to the active layer OXS. Figure 1A As shown, the gate G extends along the Z direction, and the source electrode S and drain electrode D are arranged at intervals in the Z direction; an interlayer insulating layer (ILD) can be disposed between the source electrode S and the drain electrode D.

[0031] Figure 1B and Figure 1C This is a schematic diagram of another type of channel all-around transistor, in which... Figure 1B This is a top-down view. Figure 1C This is a sectional view taken along the horizontal direction X. For example... Figure 1B and Figure 1CAs shown, transistor Ta includes a gate G, a gate dielectric layer GI, an active layer OXS, a source electrode S, and a drain electrode D. The active layer OXS surrounds the gate G, the gate dielectric layer GI is disposed between the gate G and the active layer OXS, and the source electrode S and drain electrode D are respectively contacted and connected to the active layer OXS. Figure 1B and Figure 1C As shown, the gate G extends along the Z direction, and the source electrode S and drain electrode D are arranged at intervals in the X direction.

[0032] It is understood that in the accompanying drawings of this disclosure, the X and Y directions are intersecting horizontal directions, and the Z direction is a vertical direction perpendicular to the X and Y directions. Typically, the X and Y directions are perpendicular to each other, but this is not a limitation.

[0033] Both Ta and Tb of the aforementioned Channel-All-Around (CAA) transistors can be used as access transistors in memory cells for application in three-dimensional memory architecture designs. It should be noted that the "channel" in "Channel-All-Around" refers to the active layer (also called the channel layer), not the channel region.

[0034] In current applications of channel-all-around transistors (such as the aforementioned transistors Ta and Tb), the source electrode S and drain electrode D are generally considered to be interchangeable. Therefore, during the design and manufacturing process, the source electrode S and drain electrode D are often made of the same conductive material. Alternatively, although the source electrode S and drain electrode D are made of different conductive materials, the materials of the source electrode S and drain electrode D are often arbitrarily selected from a variety of expected conductive materials.

[0035] In their research, the inventors of this application discovered that when the access transistors in the memory use channel-all-around transistors (such as the transistors Ta and Tb mentioned above), since channel-all-around transistors are essentially source-gated transistors (SGTs), the material selection for the source electrode S and drain electrode D of the transistor needs to be carefully designed so that the performance of the transistor better meets the charging and discharging requirements of the memory cell.

[0036] This disclosure provides at least some embodiments of a memory. The memory includes word lines, bit lines, and memory cells. Each memory cell includes a first transistor and a data storage node; the first transistor includes: a gate coupled to the word line; an active layer surrounding the gate, wherein the active layer is made of an oxide semiconductor; a source electrode having a Schottky contact with the active layer and coupled to the bit line; and a drain electrode having an ohmic contact with the active layer and coupled to the data storage node.

[0037] In the memory provided in the embodiments of this disclosure, the first transistor is a channel-all-around transistor. The source electrode coupled to the bit line and the active layer are connected by a Schottky contact, and the drain electrode coupled to the data storage node and the active layer are connected by an ohmic contact. This forms an asymmetric contact barrier at the source and drain ends of the channel-all-around transistor, which helps to reduce the off-state leakage current of the first transistor. It also helps to increase the on-state saturation current of the first transistor during the charging process of the memory cell. Furthermore, it helps to make the first transistor have a smaller subthrehold swing. As a result, the performance of the first transistor can better meet the charging and discharging requirements of the memory cell.

[0038] Figure 2A This is a schematic diagram illustrating the structure of a memory cell in a memory provided for some embodiments of this disclosure. For example, such as... Figure 2A As shown, the memory includes word line WL, bit line BL and memory cell M1; memory cell M1 includes first transistor (i.e. access transistor) T1 and data storage node DSN; first transistor T1 includes gate G1, gate dielectric layer GI1, active layer OXS1, source electrode S1 and drain electrode D1.

[0039] like Figure 2A As shown, the gate G1 is coupled to the word line WL. For example, in some examples, the gate G1 and the word line WL can be integrally formed. For example, as... Figure 2A As shown, the vertical extension of the T-shaped structure indicated by "G1 / WL" can serve as the gate G1, and the horizontal extension of the T-shaped structure can serve as the word line WL. For example, the materials of the gate G1 and the word line WL can be conductive materials, including but not limited to titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicides, etc.

[0040] like Figure 2A As shown, the active layer OXS1 surrounds the gate G1. For example, the material of the active layer OXS1 is an oxide semiconductor, including but not limited to indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), etc.

[0041] like Figure 2A As shown, the gate dielectric layer GI1 is disposed between the gate G1 and the active layer OXS1. For example, the material of the gate dielectric layer GI1 is a dielectric material, including but not limited to silicon oxide, silicon nitride, high-K dielectric materials, etc.; for example, high-K dielectric materials include but are not limited to hafnium oxide (HfO2), zirconium oxide (ZrO2), etc.

[0042] like Figure 2A As shown, the source electrode S1 is in contact with the active layer OXS1 and coupled to the bit line BL. For example, in some examples, the source electrode S1 and the bit line BL can be integrally formed. For example, as... Figure 2A As shown, a portion of the bit line BL can serve as the source electrode S1, but is not limited to this.

[0043] like Figure 2A As shown, the drain electrode D1 is in contact with the active layer OXS1 and coupled to the data storage node DSN.

[0044] like Figure 2A As shown, a data storage node (DSN) can be implemented as a capacitor (CAP). The capacitor CAP can include a first electrode CP1, a second electrode CP2, and a capacitor dielectric layer (CDL) disposed between the first electrode CP1 and the second electrode CP2. Figure 2A As shown, the first electrode CP1 of capacitor CAP is coupled to the drain electrode D1 of first transistor T1. For example, in some examples, the first electrode CP1 and the drain electrode D1 can be integrally formed, but this is not a limitation. It should be noted that in the embodiments of this disclosure, if the first electrode CP1 and the drain electrode D1 are integrally formed, the materials of both need to be determined according to the material selection rules for the drain electrode D1 (see description below).

[0045] For example, the materials of the first electrode CP1 and the second electrode CP2 are conductive materials, including but not limited to titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicides, and doped polycrystalline silicon. For example, the material of the capacitor dielectric layer CDL is a dielectric material, including but not limited to silicon oxide, silicon nitride, and high-k dielectric materials; for example, the material of the capacitor dielectric layer CDL can also be a dielectric material with ferroelectric or antiferroelectric properties, such as ferroelectric hafnium oxide or ferroelectric hafnium zirconium oxide, meaning that the capacitor CAP can be formed as a ferroelectric capacitor. It is understood that... Figure 2A The capacitor CAP shown is exemplary, and the embodiments disclosed herein do not limit the structure of the capacitor CAP.

[0046] For example, such as Figure 2A As shown, the gate G1 may include a gate post extending along the vertical direction Z (i.e., Figure 2A The active layer OXS1 may include a first portion surrounding the gate pillar (i.e., the vertical extension of the T-shaped structure in the middle), and the active layer OXS1 may include a first portion surrounding the gate pillar. Figure 2A (The portion extending vertically along the Z direction in the image), where the source electrode S1 and drain electrode D1 are spaced apart in the vertical Z direction. For example, as... Figure 2A As shown, an interlayer insulating layer ILD1 can be disposed between the source electrode S1 and the drain electrode D1. For example, the material of the interlayer insulating layer ILD1 includes, but is not limited to, silicon oxide, silicon nitride, etc.

[0047] For example, such as Figure 2A As shown, the active layer OXS1 may further include a second part and a third part connected to the first part, the second part (i.e. Figure 2AThe portion extending horizontally along the X direction below the first portion is located at the bottom of the gate pillar and coupled to the drain electrode D1. The source electrode S1 is located above the drain electrode D1. The third portion (i.e. Figure 2A The portion extending horizontally along the X direction above the first part is located above the source electrode S1.

[0048] exist Figure 2A In the illustrated embodiment, the memory may include multiple layers stacked sequentially along the vertical direction Z. Multiple memory cells M1 at the same layer can be formed simultaneously, while memory cells M1 at different layers can be formed layer by layer. In other words, the memory can be implemented as a three-dimensional memory. For example, different layers can be isolated by an interlayer insulating layer ILD2. For example, the material of the interlayer insulating layer ILD2 includes, but is not limited to, silicon oxide, silicon nitride, etc.

[0049] Figure 2B This is a schematic diagram of the structure of a memory cell in another memory provided for some embodiments of this disclosure. Figure 2B The memory cell M2 shown is Figure 2A The main difference in the memory cell M1 shown is that: Figure 2B In the memory cell M2 shown, the data storage node DSN is implemented as the second transistor T2. Figure 2B In the memory cell M2 shown, the first transistor T1 and the second transistor T2 can be referred to as the write transistor T1 and the read transistor T2, respectively. The word line WWL coupled to the gate G1 of the write transistor T1 can be referred to as the write word line WWL, and the bit line WBL coupled to the source electrode S1 of the write transistor T1 can be referred to as the write bit line WBL. Details regarding the structure and material composition of the write transistor T1 can be found in [reference needed]. Figure 2A The description of the first transistor T1 in the illustrated embodiment will not be repeated here.

[0050] like Figure 2B As shown, the read transistor T2 includes a gate G2, a gate dielectric layer GI2, an active layer OXS2, a source electrode S2, and a drain electrode D2. The gate G2 of the read transistor T2 is coupled to the drain electrode D1 of the write transistor T1. For example, in some examples, the gate G2 of the read transistor T2 and the drain electrode D1 of the write transistor T1 can be integrally formed, but this is not a limitation. It should be noted that, in the embodiments of this disclosure, if the gate G2 of the read transistor T2 and the drain electrode D1 of the write transistor T1 are integrally formed, the materials of both need to be determined according to the material selection rules for the drain electrode D1 (see description below).

[0051] For example, the active layer OXS2 is made of oxide semiconductors, including but not limited to indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), and indium zinc oxide (IZO).

[0052] like Figure 2B As shown, the source electrode S2 is in contact with the active layer OXS2 and coupled to the read line RBL. For example, in some examples, the source electrode S2 and the read line RBL are integrally formed. For example, as... Figure 2A As shown, a portion of the read line RBL can serve as the source electrode S2.

[0053] like Figure 2B As shown, the drain electrode D2 is in contact with the active layer OXS2 and coupled to the read word line RWL. For example, in some examples, the drain electrode D2 and the read word line RWL are integrally formed. For example, as... Figure 2A As shown, a portion of the read line RWL can serve as the drain electrode D2.

[0054] refer to Figure 2B The structure of read transistor T2 can be similar to that of write transistor T1. This is understandable. Figure 2B The read transistor T2 shown is exemplary, and the embodiments of this disclosure do not limit the structure of the read transistor T2.

[0055] exist Figure 2B In the illustrated embodiment, the memory may include multiple layers stacked sequentially along the vertical direction Z. Multiple memory cells M2 at the same layer can be formed simultaneously, while memory cells M2 at different layers can be formed layer by layer. In other words, the memory can be implemented as a three-dimensional memory. For example, different layers can be isolated by interlayer insulating layers (not shown in the figure). For example, the material of the interlayer insulating layer includes, but is not limited to, silicon oxide, silicon nitride, etc.

[0056] Figure 3A and Figure 3B This is a schematic diagram illustrating the structure of a memory cell in another memory provided in some embodiments of the present disclosure, wherein, Figure 3A This is a top-down view. Figure 3B This is a sectional view taken along the horizontal direction X. For example... Figure 3A and Figure 3B As shown, the memory includes word line WL, bit line BL and memory cell M3; memory cell M3 includes first transistor (i.e. access transistor) T1 and data storage node DSN; first transistor T1 includes gate G1, gate dielectric layer GI1, active layer OXS1, source electrode S1 and drain electrode D1.

[0057] like Figure 3A and Figure 3B As shown, the gate G1 is coupled to the word line WL. For example, in some examples, the gate G1 and the word line WL are integrally formed. For example, as... Figure 3A and Figure 3BAs shown, a portion of the word line WL can serve as the gate G1, but is not limited to this. For example, the materials of the gate G1 and the word line WL can be conductive materials, including but not limited to titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicides, etc.

[0058] like Figure 3A and Figure 3B As shown, the active layer OXS1 surrounds the gate G1. For example, the material of the active layer OXS1 is an oxide semiconductor, including but not limited to indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), etc.

[0059] like Figure 3A and Figure 3B As shown, the gate dielectric layer GI1 is disposed between the gate G1 and the active layer OXS1. For example, the material of the gate dielectric layer GI1 is a dielectric material, including but not limited to silicon oxide, silicon nitride, high-K dielectric materials, etc.; for example, high-K dielectric materials include but are not limited to hafnium oxide (HfO2), zirconium oxide (ZrO2), etc.

[0060] like Figure 3A and Figure 3B As shown, the source electrode S1 is in contact with the active layer OXS1 and coupled to the bit line BL. For example, in some examples, the source electrode S1 and the bit line BL can be integrally formed. For example, as... Figure 2A As shown, a portion of the bit line BL can serve as the source electrode S1, but is not limited to this.

[0061] like Figure 3A and Figure 3B As shown, the drain electrode D1 is in contact with the active layer OXS1 and coupled to the data storage node DSN.

[0062] like Figure 3A and Figure 3B As shown, the source electrode S1 and the drain electrode D1 are arranged at intervals in the horizontal direction X.

[0063] like Figure 3A and Figure 3B As shown, a data storage node (DSN) can be implemented as a capacitor (CAP). The capacitor CAP can include a first electrode CP1, a second electrode CP2, and a capacitor dielectric layer (CDL) disposed between the first electrode CP1 and the second electrode CP2. Figure 3A and Figure 3B As shown, the first electrode CP1 of capacitor CAP is coupled to the drain electrode D1 of first transistor T1. For example, in some examples, the first electrode CP1 and the drain electrode D1 can be integrally formed, but this is not a limitation. It should be noted that in the embodiments of this disclosure, if the first electrode CP1 and the drain electrode D1 are integrally formed, the materials of both need to be determined according to the material selection rules for the drain electrode D1 (see description below).

[0064] For example, in some examples, such as Figure 3A and Figure 3B As shown, the capacitor dielectric layer CDL surrounds the second electrode CP2, and the first electrode CP1 surrounds the capacitor dielectric layer CDL. Figure 3B The diagram shows multiple memory cells M3 arranged along the vertical direction Z, wherein the multiple memory cells M3 can share the word line WL, the gate dielectric layer GI1, the capacitor dielectric layer CDL, and the second electrode CP2.

[0065] For example, the materials of the first electrode CP1 and the second electrode CP2 are conductive materials, including but not limited to titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicides, and doped polycrystalline silicon. For example, the material of the capacitor dielectric layer CDL is a dielectric material, including but not limited to silicon oxide, silicon nitride, and high-k dielectric materials; for example, the material of the capacitor dielectric layer CDL can also be a dielectric material with ferroelectric or antiferroelectric properties, such as ferroelectric hafnium oxide or ferroelectric hafnium zirconium oxide, meaning that the capacitor CAP can be formed as a ferroelectric capacitor. It is understood that... Figure 3A and Figure 3B The capacitor CAP shown is exemplary, and the embodiments disclosed herein do not limit the structure of the capacitor CAP.

[0066] exist Figure 3A and Figure 3B In the illustrated embodiment, the memory may include multiple layers stacked sequentially along the vertical direction Z, and the memory cells M3 in each layer may be formed synchronously; that is, the memory can be implemented as a three-dimensional memory. It should be noted that, for the sake of simplicity, Figure 3A and Figure 3B Part of the insulation layer has been omitted.

[0067] Figure 3C and Figure 3D This is a schematic diagram illustrating the structure of a memory cell in another type of memory provided in some embodiments of the present disclosure, wherein, Figure 3C This is a top-down view. Figure 3D This is a sectional view taken along the horizontal direction X. Figure 3C and Figure 3D The memory cell M4 shown is Figure 3A and Figure 3B The main difference in the memory cell M3 shown is that: Figure 3C and Figure 3D In the memory cell M4 shown, the data storage node DSN is implemented as the second transistor T2. Figure 3C and Figure 3DIn the memory cell M4 shown, the first transistor T1 and the second transistor T2 can be referred to as the write transistor T1 and the read transistor T2, respectively; the word line WWL coupled to the gate G1 of the write transistor T1 can be referred to as the write word line WWL, and the bit line WBL coupled to the source electrode S1 of the write transistor T1 can be referred to as the write bit line WBL. Details regarding the structure and material composition of the write transistor T1 can be found in [reference needed]. Figure 3A and Figure 3B The description of the first transistor T1 in the illustrated embodiment will not be repeated here.

[0068] like Figure 3C and Figure 3D As shown, the read transistor T2 includes a gate G2, a gate dielectric layer GI2, an active layer OXS2, a gate dielectric layer GI3, a gate G3, a source electrode S2, and a drain electrode D2. That is, the read transistor T2 can be formed as a dual-gate transistor. The gate G2 of the read transistor T2 is coupled to the drain electrode D1 of the write transistor T1. For example, in some examples, the gate G2 of the read transistor T2 and the drain electrode D1 of the write transistor T1 can be integrally formed, but this is not a limitation. It should be noted that in the embodiments of this disclosure, if the gate G2 of the read transistor T2 and the drain electrode D1 of the write transistor T1 are integrally formed, the materials of both need to be determined according to the material selection rules for the drain electrode D1 (see description below).

[0069] For example, the active layer OXS2 is made of oxide semiconductors, including but not limited to indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), and indium zinc oxide (IZO).

[0070] like Figure 3C and Figure 3D As shown, the source electrode S2 is in contact with the active layer OXS2 and coupled to the read line RBL. For example, in some examples, the source electrode S2 and the read line RBL are integrally formed. For example, as... Figure 2A As shown, a portion of the read line RBL can serve as the source electrode S2.

[0071] like Figure 3C and Figure 3D As shown, the drain electrode D2 is in contact with the active layer OXS2. For example, in some examples, the drain electrode D2 is configured to be grounded, but it is not limited to this.

[0072] like Figure 3C and Figure 3D As shown, the gate G3 is coupled to the read word line RWL. For example, in some examples, the gate G3 and the read word line RWL are integrally formed. For example, as... Figure 2A As shown, a portion of the read word line RWL can serve as gate G3.

[0073] For example, in some embodiments, such as Figure 3C and Figure 3D As shown, the gate dielectric layer GI3 surrounds the gate G3, the drain electrode D2 is arranged in parallel with the gate G3, and the active layer OXS2 surrounds the overall structure formed by the gate G3, the gate dielectric layer GI3 and the drain electrode D2. The gate G2 partially surrounds the active layer OXS2, and the gate dielectric layer GI2 is disposed between the gate G2 and the active layer OXS2. Figure 3D The diagram shows multiple memory cells M4 arranged along the vertical direction Z, wherein the multiple memory cells M4 can share the write word line WWL, the gate dielectric layer GI1, the read word line RWL, and the drain electrode D2.

[0074] Understandable, Figure 3C and Figure 3D The read transistor T2 shown is exemplary, and the embodiments of this disclosure do not limit the structure of the read transistor T2.

[0075] exist Figure 3C and Figure 3D In the illustrated embodiment, the memory may include multiple layers stacked sequentially along the vertical direction Z, and the memory cells M4 in each layer may be formed synchronously; that is, the memory can be implemented as a three-dimensional memory. It should be noted that, for the sake of simplicity, Figure 3C and Figure 3D Part of the insulation layer has been omitted.

[0076] The above embodiments of this disclosure ( Figure 2A , Figure 2B , Figure 3A and Figure 3B , Figure 3C and Figure 3D In the memory provided, the source electrode S1 of the first transistor T1 has a Schottky contact with the active layer OXS1, and the drain electrode D1 of the first transistor T2 has an ohmic contact with the active layer OXS1. That is, the materials selected for the source electrode S1 and the drain electrode D1 should meet specific rules. For example, the contact barrier between the source electrode S1 and the active layer OXS1 is higher than the contact barrier between the drain electrode D1 and the active layer OXS1.

[0077] For example, in the embodiments of this disclosure, the active layer OXS1 is substantially uniformly doped, meaning that the source region of the active layer OXS1 in contact with the source electrode S1, the drain region of the active layer OXS1 in contact with the drain electrode D1, and the channel region of the active layer OXS1 located between the source and drain regions have the same doping type, the same dopant ion species, and the same doping concentration. The height of the contact barrier is related to the work function of the two materials in contact. For example, the difference between the work function of the source electrode S1 and the work function of the active layer OXS1 is not less than 0.3 eV (i.e., Schottky contact), and the difference between the work function of the drain electrode D1 and the work function of the active layer OXS1 is less than 0.2 eV (i.e., Ohmic contact). Therefore, the contact barrier between the source electrode S1 and the active layer OXS1 is high, and the contact barrier between the drain electrode D1 and the active layer OXS1 is low. For example, in some examples, the difference between the work function of the source electrode S1 and the work function of the active layer OXS1 is not less than 0.4 eV. For example, in some examples, the difference between the work function of the drain electrode D1 and the work function of the active layer OXS1 is less than or equal to 0.1 eV.

[0078] For example, in some examples, the active layer OXS1 is an N-type oxide semiconductor layer, the work function of the source electrode S1 is greater than the work function of the active layer OXS1, and the work function of the drain electrode D1 is less than or equal to the work function of the active layer OXS1.

[0079] For example, in a specific example, the active layer OXS1 is made of indium gallium zinc oxide (IGZO), the source electrode S1 is made of molybdenum nitride (MoN), and the drain electrode D1 is made of titanium nitride (TiN).

[0080] The inventors of this application, taking N-type indium gallium zinc oxide (work function 4.5 eV) as the active layer OXS1 as an example, simulated the first transistor T1 under different source-drain electrode material pairings and obtained the corresponding IV curves, as shown below. Figure 4A and Figure 4B As shown. It should be noted that, in Figure 4A In the diagram, both the x-axis and y-axis use linear scales; Figure 4B In the diagram, the horizontal axis uses a linear scale, and the vertical axis uses a logarithmic scale.

[0081] exist Figure 4A and Figure 4BIn the diagram, SD_4.6 indicates that the work functions of both the source electrode S1 and the drain electrode D1 are 4.6 eV (4.6 eV corresponds to the material titanium nitride). In this case, the contact between the source electrode S1 and the active layer OXS1 (i.e., the source contact) is an ohmic contact, and the contact between the drain electrode D1 and the active layer OXS1 (i.e., the drain contact) is also an ohmic contact. SD_4.9 indicates that the work functions of both the source electrode S1 and the drain electrode D1 are 4.9 eV (4.9 eV corresponds to the material molybdenum nitride). In this case, both the source and drain contacts are Schottky contacts. S4.9_D4.6 indicates that the work functions of the source electrode S1 and the drain electrode D1 are 4.9 eV and 4.6 eV respectively. In this case, the source contact... The source electrode S1 and drain electrode D1 have work functions of 4.6 eV and 4.9 eV respectively. In this case, the source electrode S1 is an ohmic contact and the drain electrode D1 is an ohmic contact. S4.9_D4.2 indicates that the source electrode S1 and drain electrode D1 have work functions of 4.9 eV and 4.2 eV respectively (4.2 eV corresponds to aluminum). In this case, the source electrode S1 is a Schottky contact and the drain electrode D1 is an ohmic contact. S4.2_D4.9 indicates that the source electrode S1 and drain electrode D1 have work functions of 4.2 eV and 4.9 eV respectively. In this case, the source electrode S1 is an ohmic contact and the drain electrode D1 is a Schottky contact. Figure 4B In the diagram, because the vertical axis uses a logarithmic scale, the IV curves corresponding to the two cases SD_4.6 and S4.6_D4.9 almost overlap; similarly, the IV curves corresponding to the three cases SD_4.9, S4.9_D4.6, and S4.9_D4.2 almost overlap.

[0082] based on Figure 4A and Figure 4B The IV curve shown can be further analyzed to obtain the threshold voltage Vt, on-state saturation current Ion, and subthreshold swing SS of the first transistor T1 under different source-drain electrode material pairing conditions, as shown in the table below.

[0083] Table 1 Performance parameters of the first transistor T1 under different source / drain electrode material pairings

[0084] Vt Ion SS SD_4.6 0.079V 21.78μA 67.60mV / dec SD_4.9 0.389V 17.78μA 73.79mV / dec S4.9_D4.6 0.386V 19.50μA 69.73mV / dec S4.6_D4.9 0.081V 19.66μA 67.46mV / dec S4.9_D4.2 0.383V 21.12μA 68.17mV / dec S4.2_D4.9 -0.328V 21.48μA 68.52mV / dec

[0085] During the simulation, a high voltage of 1V is applied to the drain electrode D1 to simulate the state of the data storage node DSN writing data "1" (a low voltage of 0V corresponds to the state of storing data "0"), and the influence of the interface state is ignored.

[0086] As shown in Table 1, referring to the case of SD_4.6, when both the source and drain contacts are ohmic contacts, the threshold voltage Vt of the first transistor T1 is relatively small (0.079V). Therefore, when there is a slight signal disturbance on the word line, the off-state leakage current of the first transistor T1 is relatively large, which can easily lead to leakage of the memory cell storing the data "1". Similarly, referring to the cases of S4.6_D4.9 and S4.2_D4.9, when the source contact is an ohmic contact and the drain contact is a Schottky contact, the threshold voltage Vt of the first transistor T1 is also relatively small (0.081V) or may even be negative (-0.328V). Therefore, it can also easily lead to leakage of the memory cell storing the data "1".

[0087] Furthermore, as shown in Table 1, referring to the case of SD_4.9, when both the source and drain contacts are Schottky contacts, although the threshold voltage Vt of the first transistor T1 is relatively large (0.389V), its on-state saturation current Ion is relatively small (17.78μA), which will reduce the charging rate of the memory cell.

[0088] In comparison, as shown in Table 1, referring to S4.9_D4.6 and S4.9_D4.2, when the source contact is a Schottky contact and the drain contact is an Ohmic contact, the threshold voltage Vt of the first transistor T1 is larger (0.386V, 0.383V). Therefore, even if there is a slight signal disturbance on the word line, the off-state leakage current of the first transistor T1 is smaller, which can improve the problem of leakage current in the memory cell storing the data "1". On the other hand, during the charging process of the memory cell, the on-state saturation current Ion of the first transistor T1 is larger (19.66μA, 21.48μA), which is beneficial to improving the charging rate of the memory cell. It should be understood that during the charging process of the memory cell, a high voltage (1V for example) is applied to the source electrode S1. At this time, the IV curve of the first transistor T1 should refer to the cases of S4.6_D4.9 and S4.2_D4.9, that is, the on-state saturation current Ion of the first transistor T1 should be 19.66μA and 21.48μA, instead of 19.50μA and 21.12μA. Furthermore, according to Table 1, referring to the cases of S4.9_D4.6 and S4.9_D4.2, compared with other cases, the first transistor T1 still has a smaller subthreshold swing SS.

[0089] It is understood that the materials of the source electrode S2 and drain electrode D2 of the aforementioned second transistor T2 can be selected as needed. For example, the source and drain contacts of the aforementioned second transistor T2 can both be Schottky contacts, but are not limited to this.

[0090] In summary, in the memory provided by the embodiments of this disclosure, the first transistor is a channel-all-around transistor, with a Schottky contact between the source electrode coupled to the bit line and the active layer, and an ohmic contact between the drain electrode coupled to the data storage node and the active layer. This forms an asymmetric contact barrier at the source and drain ends of the channel-all-around transistor, which helps to reduce the off-state leakage current of the first transistor, while also helping to increase the on-state saturation current of the first transistor during the charging process of the memory cell. It also helps to enable the first transistor to have a smaller subthrehold swing. As a result, the performance of the first transistor can better meet the charging and discharging requirements of the memory cell.

[0091] At least some embodiments of this disclosure also provide an electronic device. Figure 5 This is a schematic block diagram illustrating the structure of an electronic device provided in some embodiments of this disclosure. For example... Figure 5 As shown, the electronic device 1 includes a processor 20 and a memory 10 coupled to each other, wherein the memory 10 is the memory provided in any of the foregoing embodiments.

[0092] For example, processor 20 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. Memory 10 may be configured to store data to be processed by processor 20 and / or data processed by the processor.

[0093] For example, electronic device 1 includes, but is not limited to, mobile phones, tablets, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.

[0094] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, It includes word lines, bit lines, and memory cells, wherein the memory cells include a first transistor and a data storage node. The first transistor includes: The gate is coupled to the word line; An active layer surrounding the gate, wherein the active layer is made of an oxide semiconductor. The source electrode has a Schottky contact with the active layer and is coupled to the bit line; The drain electrode has an ohmic contact with the active layer and is coupled to the data storage node.

2. The memory according to claim 1, wherein, The difference between the work function of the source electrode and the work function of the active layer is not less than 0.3 eV, and the difference between the work function of the drain electrode and the work function of the active layer is less than 0.2 eV.

3. The memory according to claim 1, wherein, The active layer is an N-type oxide semiconductor layer, the work function of the source electrode is greater than the work function of the active layer, and the work function of the drain electrode is less than or equal to the work function of the active layer.

4. The memory according to claim 1, characterized in that, The active layer is made of indium gallium zinc oxide (IGZO), the source electrode is made of molybdenum nitride (MoN), and the drain electrode is made of titanium nitride (TiN).

5. The memory according to any one of claims 1-4, characterized in that, The first transistor further includes: A gate dielectric layer is disposed between the gate and the active layer.

6. The memory according to claim 5, characterized in that, The gate includes a gate pillar extending in a vertical direction, the active layer includes a first portion surrounding the gate pillar, and the source electrode and the drain electrode are spaced apart in the vertical direction.

7. The memory according to claim 6, characterized in that, The active layer further includes a second portion and a third portion connected to the first portion. The second portion is located at the bottom of the gate pillar and coupled to the drain electrode. The source electrode is located above the drain electrode, and the third portion is located above the source electrode.

8. The memory according to claim 5, characterized in that, The gate includes a gate pillar extending in a vertical direction, the active layer surrounds the gate pillar, and the source electrode and the drain electrode are arranged at intervals in a horizontal direction.

9. The memory according to any one of claims 1-4, characterized in that, The data storage node includes a capacitor; or, the data storage node includes a second transistor, wherein the drain electrode of the first transistor is coupled to the gate of the second transistor.

10. An electronic device, characterized in that, include: processor; as well as The memory according to any one of claims 1-9, wherein the memory is coupled to the processor.

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